From: Jan Beulich <jbeulich@sourceware.org>
To: bfd-cvs@sourceware.org
Subject: [binutils-gdb] RISC-V: drop leftover match_never() references
Date: Fri, 24 Nov 2023 09:16:12 +0000 (GMT) [thread overview]
Message-ID: <20231124091612.A7C2D3858C2F@sourceware.org> (raw)
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=2ec31e54dff83130fbde8d2f674469078ee203d5
commit 2ec31e54dff83130fbde8d2f674469078ee203d5
Author: Jan Beulich <jbeulich@suse.com>
Date: Fri Nov 24 10:15:59 2023 +0100
RISC-V: drop leftover match_never() references
Commit 27b33966b18e "RISC-V: disallow x0 with certain macro-insns"
wasn't properly re-based over recent opcode table additions.
Diff:
---
opcodes/riscv-opc.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index c9ba4c99284..bf19978e025 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2667,10 +2667,10 @@ const struct riscv_opcode riscv_opcodes[] =
{"th.vmsltu.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VkVm", MATCH_VMSLEUVI, MASK_VMSLEUVI, match_opcode, INSN_ALIAS },
{"th.vmsge.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VkVm", MATCH_VMSGTVI, MASK_VMSGTVI, match_opcode, INSN_ALIAS },
{"th.vmsgeu.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VkVm", MATCH_VMSGTUVI, MASK_VMSGTUVI, match_opcode, INSN_ALIAS },
-{"th.vmsge.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", 0, (int) M_VMSGE, match_never, INSN_MACRO },
-{"th.vmsge.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGE, match_never, INSN_MACRO },
-{"th.vmsgeu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", 1, (int) M_VMSGE, match_never, INSN_MACRO },
-{"th.vmsgeu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,s,VM,VT", 1, (int) M_VMSGE, match_never, INSN_MACRO },
+{"th.vmsge.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", 0, (int) M_VMSGE, NULL, INSN_MACRO },
+{"th.vmsge.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGE, NULL, INSN_MACRO },
+{"th.vmsgeu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", 1, (int) M_VMSGE, NULL, INSN_MACRO },
+{"th.vmsgeu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,s,VM,VT", 1, (int) M_VMSGE, NULL, INSN_MACRO },
{"th.vminu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VMINUVV, MASK_VMINUVV, match_opcode, 0},
{"th.vminu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VMINUVX, MASK_VMINUVX, match_opcode, 0},
{"th.vmin.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VMINVV, MASK_VMINVV, match_opcode, 0},
reply other threads:[~2023-11-24 9:16 UTC|newest]
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