[binutils-gdb] x86: allow 32-bit reg to be used with U{RD,WR}MSR

[binutils-gdb] x86: allow 32-bit reg to be used with U{RD,WR}MSR

[Jan Beulich]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=1f865bae65db9588f6994c02a92355bfb4e3d955

commit 1f865bae65db9588f6994c02a92355bfb4e3d955
Author: Jan Beulich <jbeulich@suse.com>
Date:   Fri Dec 1 08:26:36 2023 +0100

    x86: allow 32-bit reg to be used with U{RD,WR}MSR
    
    ... as MSR index specifier: It is unreasonable to demand that people
    write less readable / understandable code, just because the present
    documentation mentions only Reg64. Whether to also adjust the
    disassembler is a separate question, perhaps indeed more tightly tied
    to what the spec says.

Diff:
---
 gas/testsuite/gas/i386/x86-64-user_msr.s | 8 ++++----
 opcodes/i386-opc.tbl                     | 4 ++--
 opcodes/i386-tbl.h                       | 4 ++--
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/gas/testsuite/gas/i386/x86-64-user_msr.s b/gas/testsuite/gas/i386/x86-64-user_msr.s
index 63bc6c1352c..b3eb7b0ceca 100644
--- a/gas/testsuite/gas/i386/x86-64-user_msr.s
+++ b/gas/testsuite/gas/i386/x86-64-user_msr.s
@@ -5,7 +5,7 @@ _start:
 	urdmsr	%r14, %r12
 	urdmsr	%r14, %rax
 	urdmsr	%rdx, %r12
-	urdmsr	%rdx, %rax
+	urdmsr	%edx, %rax
 	urdmsr	$51515151, %r12
 	urdmsr	$51515151, %rax
 	urdmsr	$0x7f, %r12
@@ -14,7 +14,7 @@ _start:
 	uwrmsr	%r12, %r14
 	uwrmsr	%rax, %r14
 	uwrmsr	%r12, %rdx
-	uwrmsr	%rax, %rdx
+	uwrmsr	%rax, %edx
 	uwrmsr	%r12, $51515151
 	uwrmsr	%rax, $51515151
 	uwrmsr	%r12, $0x7f
@@ -24,7 +24,7 @@ _start:
 	.intel_syntax noprefix
 	urdmsr	r12, r14
 	urdmsr	rax, r14
-	urdmsr	r12, rdx
+	urdmsr	r12, edx
 	urdmsr	rax, rdx
 	urdmsr	r12, 51515151
 	urdmsr	rax, 51515151
@@ -33,7 +33,7 @@ _start:
 	urdmsr	r12, 0x80000000
 	uwrmsr	r14, r12
 	uwrmsr	r14, rax
-	uwrmsr	rdx, r12
+	uwrmsr	edx, r12
 	uwrmsr	rdx, rax
 	uwrmsr	51515151, r12
 	uwrmsr	51515151, rax
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index b170d70d69a..f89c4cb5bcd 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3359,9 +3359,9 @@ eretu, 0xf30f01ca, FRED, NoSuf, {}
 
 // USER_MSR instructions.
 
-urdmsr, 0xf20f38f8, USER_MSR, RegMem|NoSuf|NoRex64, { Reg64, Reg64 }
+urdmsr, 0xf20f38f8, USER_MSR, RegMem|NoSuf|NoRex64, { Reg32|Reg64, Reg64 }
 urdmsr, 0xf2f8/0, USER_MSR, Modrm|Vex128|VexMap7|VexW0|NoSuf, { Imm32, Reg64 }
-uwrmsr, 0xf30f38f8, USER_MSR, Modrm|NoSuf|NoRex64, { Reg64, Reg64 }
+uwrmsr, 0xf30f38f8, USER_MSR, Modrm|NoSuf|NoRex64, { Reg64, Reg32|Reg64 }
 // Immediates want to be first; md_assemble() takes care of swapping operands
 // accordingly.
 uwrmsr, 0xf3f8/0, USER_MSR, Modrm|Vex128|VexMap7|VexW0|NoSuf, { Imm32, Reg64 }
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index e3215358141..eb25f2002e5 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -39638,7 +39638,7 @@ static const insn_template i386_optab[] =
       0 },
     { { 98, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } },
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
-    { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
+    { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
 	  0, 0, 0, 0, 0, 0 } },
       { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
 	  0, 0, 0, 0, 0, 0 } } } },
@@ -39660,7 +39660,7 @@ static const insn_template i386_optab[] =
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
 	  0, 0, 0, 0, 0, 0 } },
-      { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
+      { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
 	  0, 0, 0, 0, 0, 0 } } } },
   { MN_uwrmsr, 0xf8, 2, SPACE_VEXMAP7, 0,
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,