From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1386) id DD4E43858D32; Fri, 5 Jan 2024 08:29:14 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DD4E43858D32 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Jan Beulich To: bfd-cvs@sourceware.org Subject: [binutils-gdb] Arm/doc: separate @code from @item for older makeinfo X-Act-Checkin: binutils-gdb X-Git-Author: Jan Beulich X-Git-Refname: refs/heads/master X-Git-Oldrev: a12915cc7e2a6721678fc4efe7e6a1e9b970512e X-Git-Newrev: 6d548ee95c12fcff446a51beea5c27f0f8df2166 Message-Id: <20240105082914.DD4E43858D32@sourceware.org> Date: Fri, 5 Jan 2024 08:29:14 +0000 (GMT) X-BeenThere: binutils-cvs@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 05 Jan 2024 08:29:15 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D6d548ee95c12= fcff446a51beea5c27f0f8df2166 commit 6d548ee95c12fcff446a51beea5c27f0f8df2166 Author: Jan Beulich Date: Fri Jan 5 09:28:43 2024 +0100 Arm/doc: separate @code from @item for older makeinfo =20 At least 4.12 doesn't like the constructs without a separator. Diff: --- gas/doc/c-arm.texi | 206 ++++++++++++++++++++++++++-----------------------= ---- 1 file changed, 103 insertions(+), 103 deletions(-) diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi index 5a951a88220..0a54073c577 100644 --- a/gas/doc/c-arm.texi +++ b/gas/doc/c-arm.texi @@ -289,199 +289,199 @@ See their availability and meaning below: For @code{armv5te}, @code{armv5texp}, @code{armv5tej}, @code{armv6}, @code= {armv6j}, @code{armv6k}, @code{armv6z}, @code{armv6kz}, @code{armv6zk}, @co= de{armv6t2}, @code{armv6kt2} and @code{armv6zt2}: =20 @itemize @w{} -@item@code{+fp}: Enables VFPv2 instructions. -@item@code{+nofp}: Disables all FPU instrunctions. +@item @code{+fp}: Enables VFPv2 instructions. +@item @code{+nofp}: Disables all FPU instrunctions. @end itemize =20 For @code{armv7}: =20 @itemize @w{} -@item@code{+fp}: Enables VFPv3 instructions with 16 double-word registers. -@item@code{+nofp}: Disables all FPU instructions. +@item @code{+fp}: Enables VFPv3 instructions with 16 double-word registers. +@item @code{+nofp}: Disables all FPU instructions. @end itemize =20 For @code{armv7-a}: =20 @itemize @w{} -@item@code{+fp}: Enables VFPv3 instructions with 16 double-word registers. -@item@code{+vfpv3-d16}: Alias for @code{+fp}. -@item@code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registe= rs. -@item@code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-po= int +@item @code{+fp}: Enables VFPv3 instructions with 16 double-word registers. +@item @code{+vfpv3-d16}: Alias for @code{+fp}. +@item @code{+vfpv3}: Enables VFPv3 instructions with 32 double-word regist= ers. +@item @code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-p= oint conversion instructions and 16 double-word registers. -@item@code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point = conversion +@item @code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point= conversion instructions and 32 double-word registers. -@item@code{+vfpv4-d16}: Enables VFPv4 instructions with 16 double-word reg= isters. -@item@code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registe= rs. -@item@code{+simd}: Enables VFPv3 and NEONv1 instructions with 32 double-wo= rd +@item @code{+vfpv4-d16}: Enables VFPv4 instructions with 16 double-word re= gisters. +@item @code{+vfpv4}: Enables VFPv4 instructions with 32 double-word regist= ers. +@item @code{+simd}: Enables VFPv3 and NEONv1 instructions with 32 double-w= ord registers. -@item@code{+neon}: Alias for @code{+simd}. -@item@code{+neon-vfpv3}: Alias for @code{+simd}. -@item@code{+neon-fp16}: Enables VFPv3, half precision floating-point conve= rsion and +@item @code{+neon}: Alias for @code{+simd}. +@item @code{+neon-vfpv3}: Alias for @code{+simd}. +@item @code{+neon-fp16}: Enables VFPv3, half precision floating-point conv= ersion and NEONv1 instructions with 32 double-word registers. -@item@code{+neon-vfpv4}: Enables VFPv4 and NEONv1 with Fused-MAC instructi= ons and 32 +@item @code{+neon-vfpv4}: Enables VFPv4 and NEONv1 with Fused-MAC instruct= ions and 32 double-word registers. -@item@code{+mp}: Enables Multiprocessing Extensions. -@item@code{+sec}: Enables Security Extensions. -@item@code{+nofp}: Disables all FPU and NEON instructions. -@item@code{+nosimd}: Disables all NEON instructions. +@item @code{+mp}: Enables Multiprocessing Extensions. +@item @code{+sec}: Enables Security Extensions. +@item @code{+nofp}: Disables all FPU and NEON instructions. +@item @code{+nosimd}: Disables all NEON instructions. @end itemize =20 For @code{armv7ve}: =20 @itemize @w{} -@item@code{+fp}: Enables VFPv4 instructions with 16 double-word registers. -@item@code{+vfpv4-d16}: Alias for @code{+fp}. -@item@code{+vfpv3-d16}: Enables VFPv3 instructions with 16 double-word reg= isters. -@item@code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registe= rs. -@item@code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-po= int +@item @code{+fp}: Enables VFPv4 instructions with 16 double-word registers. +@item @code{+vfpv4-d16}: Alias for @code{+fp}. +@item @code{+vfpv3-d16}: Enables VFPv3 instructions with 16 double-word re= gisters. +@item @code{+vfpv3}: Enables VFPv3 instructions with 32 double-word regist= ers. +@item @code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-p= oint conversion instructions and 16 double-word registers. -@item@code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point = conversion +@item @code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point= conversion instructions and 32 double-word registers. -@item@code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registe= rs. -@item@code{+simd}: Enables VFPv4 and NEONv1 with Fused-MAC instructions an= d 32 +@item @code{+vfpv4}: Enables VFPv4 instructions with 32 double-word regist= ers. +@item @code{+simd}: Enables VFPv4 and NEONv1 with Fused-MAC instructions a= nd 32 double-word registers. -@item@code{+neon-vfpv4}: Alias for @code{+simd}. -@item@code{+neon}: Enables VFPv3 and NEONv1 instructions with 32 double-wo= rd +@item @code{+neon-vfpv4}: Alias for @code{+simd}. +@item @code{+neon}: Enables VFPv3 and NEONv1 instructions with 32 double-w= ord registers. -@item@code{+neon-vfpv3}: Alias for @code{+neon}. -@item@code{+neon-fp16}: Enables VFPv3, half precision floating-point conve= rsion and +@item @code{+neon-vfpv3}: Alias for @code{+neon}. +@item @code{+neon-fp16}: Enables VFPv3, half precision floating-point conv= ersion and NEONv1 instructions with 32 double-word registers. double-word registers. -@item@code{+nofp}: Disables all FPU and NEON instructions. -@item@code{+nosimd}: Disables all NEON instructions. +@item @code{+nofp}: Disables all FPU and NEON instructions. +@item @code{+nosimd}: Disables all NEON instructions. @end itemize =20 For @code{armv7-r}: =20 @itemize @w{} -@item@code{+fp.sp}: Enables single-precision only VFPv3 instructions with = 16 +@item @code{+fp.sp}: Enables single-precision only VFPv3 instructions with= 16 double-word registers. -@item@code{+vfpv3xd}: Alias for @code{+fp.sp}. -@item@code{+fp}: Enables VFPv3 instructions with 16 double-word registers. -@item@code{+vfpv3-d16}: Alias for @code{+fp}. -@item@code{+vfpv3xd-fp16}: Enables single-precision only VFPv3 and half +@item @code{+vfpv3xd}: Alias for @code{+fp.sp}. +@item @code{+fp}: Enables VFPv3 instructions with 16 double-word registers. +@item @code{+vfpv3-d16}: Alias for @code{+fp}. +@item @code{+vfpv3xd-fp16}: Enables single-precision only VFPv3 and half floating-point conversion instructions with 16 double-word registers. -@item@code{+vfpv3-d16-fp16}: Enables VFPv3 and half precision floating-poi= nt +@item @code{+vfpv3-d16-fp16}: Enables VFPv3 and half precision floating-po= int conversion instructions with 16 double-word registers. -@item@code{+idiv}: Enables integer division instructions in ARM mode. -@item@code{+nofp}: Disables all FPU instructions. +@item @code{+idiv}: Enables integer division instructions in ARM mode. +@item @code{+nofp}: Disables all FPU instructions. @end itemize =20 For @code{armv7e-m}: =20 @itemize @w{} -@item@code{+fp}: Enables single-precision only VFPv4 instructions with 16 +@item @code{+fp}: Enables single-precision only VFPv4 instructions with 16 double-word registers. -@item@code{+vfpvf4-sp-d16}: Alias for @code{+fp}. -@item@code{+fpv5}: Enables single-precision only VFPv5 instructions with 16 +@item @code{+vfpvf4-sp-d16}: Alias for @code{+fp}. +@item @code{+fpv5}: Enables single-precision only VFPv5 instructions with = 16 double-word registers. -@item@code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registe= rs. -@item@code{+fpv5-d16"}: Alias for @code{+fp.dp}. -@item@code{+nofp}: Disables all FPU instructions. +@item @code{+fp.dp}: Enables VFPv5 instructions with 16 double-word regist= ers. +@item @code{+fpv5-d16"}: Alias for @code{+fp.dp}. +@item @code{+nofp}: Disables all FPU instructions. @end itemize =20 For @code{armv8-m.main}: =20 @itemize @w{} -@item@code{+dsp}: Enables DSP Extension. -@item@code{+fp}: Enables single-precision only VFPv5 instructions with 16 +@item @code{+dsp}: Enables DSP Extension. +@item @code{+fp}: Enables single-precision only VFPv5 instructions with 16 double-word registers. -@item@code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registe= rs. -@item@code{+cdecp0} (CDE extensions for v8-m architecture with coprocessor= 0), -@item@code{+cdecp1} (CDE extensions for v8-m architecture with coprocessor= 1), -@item@code{+cdecp2} (CDE extensions for v8-m architecture with coprocessor= 2), -@item@code{+cdecp3} (CDE extensions for v8-m architecture with coprocessor= 3), -@item@code{+cdecp4} (CDE extensions for v8-m architecture with coprocessor= 4), -@item@code{+cdecp5} (CDE extensions for v8-m architecture with coprocessor= 5), -@item@code{+cdecp6} (CDE extensions for v8-m architecture with coprocessor= 6), -@item@code{+cdecp7} (CDE extensions for v8-m architecture with coprocessor= 7), -@item@code{+nofp}: Disables all FPU instructions. -@item@code{+nodsp}: Disables DSP Extension. +@item @code{+fp.dp}: Enables VFPv5 instructions with 16 double-word regist= ers. +@item @code{+cdecp0} (CDE extensions for v8-m architecture with coprocesso= r 0), +@item @code{+cdecp1} (CDE extensions for v8-m architecture with coprocesso= r 1), +@item @code{+cdecp2} (CDE extensions for v8-m architecture with coprocesso= r 2), +@item @code{+cdecp3} (CDE extensions for v8-m architecture with coprocesso= r 3), +@item @code{+cdecp4} (CDE extensions for v8-m architecture with coprocesso= r 4), +@item @code{+cdecp5} (CDE extensions for v8-m architecture with coprocesso= r 5), +@item @code{+cdecp6} (CDE extensions for v8-m architecture with coprocesso= r 6), +@item @code{+cdecp7} (CDE extensions for v8-m architecture with coprocesso= r 7), +@item @code{+nofp}: Disables all FPU instructions. +@item @code{+nodsp}: Disables DSP Extension. @end itemize =20 For @code{armv8.1-m.main}: =20 @itemize @w{} -@item@code{+dsp}: Enables DSP Extension. -@item@code{+fp}: Enables single and half precision scalar Floating Point E= xtensions +@item @code{+dsp}: Enables DSP Extension. +@item @code{+fp}: Enables single and half precision scalar Floating Point = Extensions for Armv8.1-M Mainline with 16 double-word registers. -@item@code{+fp.dp}: Enables double precision scalar Floating Point Extensi= ons for +@item @code{+fp.dp}: Enables double precision scalar Floating Point Extens= ions for Armv8.1-M Mainline, implies @code{+fp}. -@item@code{+mve}: Enables integer only M-profile Vector Extension for +@item @code{+mve}: Enables integer only M-profile Vector Extension for Armv8.1-M Mainline, implies @code{+dsp}. -@item@code{+mve.fp}: Enables Floating Point M-profile Vector Extension for +@item @code{+mve.fp}: Enables Floating Point M-profile Vector Extension for Armv8.1-M Mainline, implies @code{+mve} and @code{+fp}. -@item@code{+nofp}: Disables all FPU instructions. -@item@code{+nodsp}: Disables DSP Extension. -@item@code{+nomve}: Disables all M-profile Vector Extensions. +@item @code{+nofp}: Disables all FPU instructions. +@item @code{+nodsp}: Disables DSP Extension. +@item @code{+nomve}: Disables all M-profile Vector Extensions. @end itemize =20 For @code{armv8-a}: =20 @itemize @w{} -@item@code{+crc}: Enables CRC32 Extension. -@item@code{+simd}: Enables VFP and NEON for Armv8-A. -@item@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies = @code{+simd}. -@item@code{+sb}: Enables Speculation Barrier Instruction for Armv8-A. -@item@code{+predres}: Enables Execution and Data Prediction Restriction In= struction +@item @code{+crc}: Enables CRC32 Extension. +@item @code{+simd}: Enables VFP and NEON for Armv8-A. +@item @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies= @code{+simd}. +@item @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A. +@item @code{+predres}: Enables Execution and Data Prediction Restriction I= nstruction for Armv8-A. -@item@code{+nofp}: Disables all FPU, NEON and Cryptography Extensions. -@item@code{+nocrypto}: Disables Cryptography Extensions. +@item @code{+nofp}: Disables all FPU, NEON and Cryptography Extensions. +@item @code{+nocrypto}: Disables Cryptography Extensions. @end itemize =20 For @code{armv8.1-a}: =20 @itemize @w{} -@item@code{+simd}: Enables VFP and NEON for Armv8.1-A. -@item@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies = @code{+simd}. -@item@code{+sb}: Enables Speculation Barrier Instruction for Armv8-A. -@item@code{+predres}: Enables Execution and Data Prediction Restriction In= struction +@item @code{+simd}: Enables VFP and NEON for Armv8.1-A. +@item @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies= @code{+simd}. +@item @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A. +@item @code{+predres}: Enables Execution and Data Prediction Restriction I= nstruction for Armv8-A. -@item@code{+nofp}: Disables all FPU, NEON and Cryptography Extensions. -@item@code{+nocrypto}: Disables Cryptography Extensions. +@item @code{+nofp}: Disables all FPU, NEON and Cryptography Extensions. +@item @code{+nocrypto}: Disables Cryptography Extensions. @end itemize =20 For @code{armv8.2-a} and @code{armv8.3-a}: =20 @itemize @w{} -@item@code{+simd}: Enables VFP and NEON for Armv8.1-A. -@item@code{+fp16}: Enables FP16 Extension for Armv8.2-A, implies @code{+si= md}. -@item@code{+fp16fml}: Enables FP16 Floating Point Multiplication Variant E= xtensions +@item @code{+simd}: Enables VFP and NEON for Armv8.1-A. +@item @code{+fp16}: Enables FP16 Extension for Armv8.2-A, implies @code{+s= imd}. +@item @code{+fp16fml}: Enables FP16 Floating Point Multiplication Variant = Extensions for Armv8.2-A, implies @code{+fp16}. -@item@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies = @code{+simd}. -@item@code{+dotprod}: Enables Dot Product Extensions for Armv8.2-A, implie= s @code{+simd}. -@item@code{+sb}: Enables Speculation Barrier Instruction for Armv8-A. -@item@code{+predres}: Enables Execution and Data Prediction Restriction In= struction +@item @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies= @code{+simd}. +@item @code{+dotprod}: Enables Dot Product Extensions for Armv8.2-A, impli= es @code{+simd}. +@item @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A. +@item @code{+predres}: Enables Execution and Data Prediction Restriction I= nstruction for Armv8-A. -@item@code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Ex= tensions. -@item@code{+nocrypto}: Disables Cryptography Extensions. +@item @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product E= xtensions. +@item @code{+nocrypto}: Disables Cryptography Extensions. @end itemize =20 For @code{armv8.4-a}: =20 @itemize @w{} -@item@code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Exte= nsions for +@item @code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Ext= ensions for Armv8.2-A. -@item@code{+fp16}: Enables FP16 Floating Point and Floating Point Multipli= cation +@item @code{+fp16}: Enables FP16 Floating Point and Floating Point Multipl= ication Variant Extensions for Armv8.2-A, implies @code{+simd}. -@item@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies = @code{+simd}. -@item@code{+sb}: Enables Speculation Barrier Instruction for Armv8-A. -@item@code{+predres}: Enables Execution and Data Prediction Restriction In= struction +@item @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies= @code{+simd}. +@item @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A. +@item @code{+predres}: Enables Execution and Data Prediction Restriction I= nstruction for Armv8-A. -@item@code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Ex= tensions. -@item@code{+nocryptp}: Disables Cryptography Extensions. +@item @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product E= xtensions. +@item @code{+nocryptp}: Disables Cryptography Extensions. @end itemize =20 For @code{armv8.5-a}: =20 @itemize @w{} -@item@code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Exte= nsions for +@item @code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Ext= ensions for Armv8.2-A. -@item@code{+fp16}: Enables FP16 Floating Point and Floating Point Multipli= cation +@item @code{+fp16}: Enables FP16 Floating Point and Floating Point Multipl= ication Variant Extensions for Armv8.2-A, implies @code{+simd}. -@item@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies = @code{+simd}. -@item@code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Ex= tensions. -@item@code{+nocryptp}: Disables Cryptography Extensions. +@item @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies= @code{+simd}. +@item @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product E= xtensions. +@item @code{+nocryptp}: Disables Cryptography Extensions. @end itemize =20 @cindex @code{-mfpu=3D} command-line option, ARM