From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1386) id 32CD53846405; Wed, 3 Apr 2024 08:43:19 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 32CD53846405 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1712133799; bh=o4RnPrS1jAvZaTGuW0/PO4k5zIRH2hCKT+U6ysu4VQM=; h=From:To:Subject:Date:From; b=UsevQrBMPxEttfhaH9Z3O9SJC/fMfaxPeBQOGJVPMm0LIeA8jLz8zRI7mw8+GAjqg V3cOFUHjK0pRiM3JNseRsJ2jqn11B2qspiynUo3FQfWdn8dercDlWlrN2XWsLU3zTH vOcA1lNpR5+IK1LD8WCj4xDDzeiIhlnm4sGK0oRo= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Jan Beulich To: binutils-cvs@sourceware.org Subject: [binutils-gdb] Arm64: check tied operand specifier in aarch64-gen X-Act-Checkin: binutils-gdb X-Git-Author: Jan Beulich X-Git-Refname: refs/heads/master X-Git-Oldrev: ef9a6314d8a7c6d29ae448926a736d57a31ee740 X-Git-Newrev: b1c4af2086db25da1acf546b28df5b6fe8198cd6 Message-Id: <20240403084319.32CD53846405@sourceware.org> Date: Wed, 3 Apr 2024 08:43:19 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3Db1c4af2086db= 25da1acf546b28df5b6fe8198cd6 commit b1c4af2086db25da1acf546b28df5b6fe8198cd6 Author: Jan Beulich Date: Wed Apr 3 10:42:44 2024 +0200 Arm64: check tied operand specifier in aarch64-gen =20 Make sure that field actually matches the specified operands. Don't follow existing F_PSEUDO checking in using assertions, though. Print meaningful error messages, thus - while not having a line number available - at least providing some indication of where things are wrong. =20 Fix SVE2.1's extq accordingly, but don't extend the testsuite there: There are further issues with its operands (SVE_Zm_imm4 doesn't look to be correct to use there, as that describes an indexed vector register, while here a separate vector register and immediate operand are to be specified). Diff: --- opcodes/aarch64-gen.c | 37 +++++++++++++++++++++++++++++++++++++ opcodes/aarch64-tbl.h | 2 +- 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/opcodes/aarch64-gen.c b/opcodes/aarch64-gen.c index eab1add0ce2..02dcde1f676 100644 --- a/opcodes/aarch64-gen.c +++ b/opcodes/aarch64-gen.c @@ -129,6 +129,7 @@ read_table (const struct aarch64_opcode* table) const struct aarch64_opcode *ent =3D table; opcode_node **new_ent; unsigned int index =3D initialize_index (table); + unsigned int errors =3D 0; =20 if (!ent->name) return; @@ -140,6 +141,8 @@ read_table (const struct aarch64_opcode* table) =20 do { + bool match =3D false; + /* F_PSEUDO needs to be used together with F_ALIAS to indicate an al= ias opcode is a programmer friendly pseudo instruction available only in the assembly code (thus will not show up in the disassembly). */ @@ -150,12 +153,46 @@ read_table (const struct aarch64_opcode* table) index++; continue; } + + /* Check tied_operand against operands[]. */ + for (unsigned int i =3D 1; i < ARRAY_SIZE (ent->operands); ++i) + { + if (ent->operands[i] =3D=3D AARCH64_OPND_NIL) + break; + + if (ent->operands[i] !=3D ent->operands[0]) + continue; + match =3D true; + + if (i !=3D ent->tied_operand) + { + fprintf (stderr, + "%s (%08x,%08x): operands 1 and %u match, but tied=3D%u\n", + ent->name, ent->opcode, ent->mask, i + 1, ent->tied_operand); + ++errors; + } + } + if (!match && ent->tied_operand + /* SME LDR/STR (array vector) tie together inner immediates only. */ + && ent->iclass !=3D sme_ldr && ent->iclass !=3D sme_str) + { + fprintf (stderr, "%s: no operands match, but tied=3D%u\n", + ent->name, ent->tied_operand); + ++errors; + } + *new_ent =3D new_opcode_node (); (*new_ent)->opcode =3D ent->opcode; (*new_ent)->mask =3D ent->mask; (*new_ent)->index =3D index++; new_ent =3D &((*new_ent)->next); } while ((++ent)->name); + + if (errors) + { + fprintf (stderr, "%u errors, exiting\n", errors); + xexit (3); + } } =20 static inline void diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 5b1c8561ac6..356d303bc1a 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -6425,7 +6425,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =3D SVE2p1_INSNC("fminqv",0x6417a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SV= E_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0), =20 SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index1, 0, OP2 (SVE_Zd, S= VE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0), - SVE2p1_INSN("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE= _Zd, SVE_Zm_imm4), OP_SVE_BBB, 0, 0), + SVE2p1_INSN("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE= _Zd, SVE_Zm_imm4), OP_SVE_BBB, 0, 1), SVE2p1_INSNC("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt, SV= E_Pg3, SVE_ADDR_ZX), OP_SVE_SZS_QD, 0, C_SCAN_MOVPRFX, 0), SVE2p1_INSNC("ld2q",0xa490e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt2, S= VE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), SVE2p1_INSNC("ld3q",0xa510e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt3, S= VE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),