From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7803) id 1EF8C3858C39; Tue, 9 Apr 2024 08:03:18 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1EF8C3858C39 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1712649798; bh=iXHXvr2zj3It/VrnX0k0tszrDjCkEndLVovvG358bJg=; h=From:To:Subject:Date:From; b=H0Qcp+7Mi/5bsdOJAVgNTFL5h9LsqjXwQhVBO6wQnfIPuaWsnyyVFqBwYDbS2xeF0 5tN7KnHPkdx5x37crSao4S128pJt8glk/fbMOrcXsfteVjx67GXTKUpLqfJoTQxVa2 VCipiTlmPwoxuU3VEgpu9nQ4QH8zsvCLt6yG8vGo= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Nelson Chu To: binutils-cvs@sourceware.org Subject: [binutils-gdb] RISC-V: Support Zcmp push/pop instructions. X-Act-Checkin: binutils-gdb X-Git-Author: Jiawei X-Git-Refname: refs/heads/master X-Git-Oldrev: 2bf280a827577eaf26d657af9f5e29dbf77e6ee2 X-Git-Newrev: 9132c8152b899a1683bc886f8ba76bedadb48aa1 Message-Id: <20240409080318.1EF8C3858C39@sourceware.org> Date: Tue, 9 Apr 2024 08:03:18 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D9132c8152b89= 9a1683bc886f8ba76bedadb48aa1 commit 9132c8152b899a1683bc886f8ba76bedadb48aa1 Author: Jiawei Date: Tue Feb 27 11:48:11 2024 +0800 RISC-V: Support Zcmp push/pop instructions. =20 Support zcmp extension push/pop/popret and popret zero instructions. The `reg_list' is a list containing 1 to 13 registers, we can use: "{ra}, {ra, s0}, {ra, s0-s1}, {ra, s0-s2} ... {ra, s0-sN}" to present this feature. =20 Passed gcc/binutils regressions of riscv-gnu-toolchain. =20 Most of work was finished by Sinan Lin. Co-Authored by: Charlie Keaney Co-Authored by: Mary Bennett Co-Authored by: Nandni Jamnadas Co-Authored by: Sinan Lin Co-Authored by: Simon Cook Co-Authored by: Shihua Liao Co-Authored by: Yulong Shi =20 bfd/ChangeLog: =20 * elfxx-riscv.c (riscv_implicit_subset): Imply zca for zcmp. (riscv_supported_std_z_ext): Added zcmp with version 1.0. (riscv_parse_check_conflicts): Zcmp conflicts with d/zcd. (riscv_multi_subset_supports): Handle zcmp. (riscv_multi_subset_supports_ext): Ditto. =20 gas/ChangeLog: =20 * NEWS: Updated. * config/tc-riscv.c (regno_to_reg_list): New function, used to = map register to reg_list number. (reglist_lookup): Called reglist_lookup_internal. Return false= if reg_list number is zero, which is an invalid value. (reglist_lookup_internal): Parse register list, and return the = last register by regno_to_reg_list. (validate_riscv_insn): New operators. (riscv_ip): Ditto. * testsuite/gas/riscv/march-help.l: Updated. * testsuite/gas/riscv/zcmp-push-pop-fail.d: New test. * testsuite/gas/riscv/zcmp-push-pop-fail.l: New test. * testsuite/gas/riscv/zcmp-push-pop-fail.s: New test. * testsuite/gas/riscv/zcmp-push-pop.d: New test. * testsuite/gas/riscv/zcmp-push-pop.s: New test. =20 include/ChangeLog: =20 * opcode/riscv-opc.h (MATCH/MASK_CM_PUSH): New macros for zcmp. (MATCH/MASK_CM_POP): Ditto. (MATCH/MASK_CM_POPRET): Ditto. (MATCH/MASK_CM_POPRETZ): Ditto. (DECLARE_INSN): New declarations for zcmp. * opcode/riscv.h (EXTRACT/ENCODE/VALID_ZCMP_SPIMM): Handle spimm operand for zcmp. (OP_MASK_REG_LIST): Handle operand for zcmp register list. (OP_SH_REG_LIST): Ditto. (ZCMP_SP_ALIGNMENT): New argument, used in riscv_get_sp_base. (X_S0, X_S1, X_S2, X_S10, X_S11): New register numbers. (enum riscv_insn_class): Added INSN_CLASS_ZCMP. (extern riscv_get_sp_base): Added. =20 opcodes/ChangeLog: =20 * riscv-dis.c (print_reg_list): New function, used to get zcmp reg_list field. (riscv_get_spimm): New function, used to get zcmp sp adjustment immediate. (print_insn_args): Handle new operands for zcmp. * riscv-opc.c (riscv_get_sp_base): New function, used by gas and objdump. Get sp base adjustment. (riscv_opcodes): Added zcmp instructions. Diff: --- bfd/elfxx-riscv.c | 13 ++ gas/NEWS | 2 + gas/config/tc-riscv.c | 181 +++++++++++++++++++++++= ++++ gas/testsuite/gas/riscv/march-help.l | 1 + gas/testsuite/gas/riscv/zcmp-push-pop-fail.d | 3 + gas/testsuite/gas/riscv/zcmp-push-pop-fail.l | 9 ++ gas/testsuite/gas/riscv/zcmp-push-pop-fail.s | 13 ++ gas/testsuite/gas/riscv/zcmp-push-pop.d | 154 +++++++++++++++++++++++ gas/testsuite/gas/riscv/zcmp-push-pop.s | 162 ++++++++++++++++++++++++ include/opcode/riscv-opc.h | 14 +++ include/opcode/riscv.h | 18 +++ opcodes/riscv-dis.c | 51 ++++++++ opcodes/riscv-opc.c | 20 +++ 13 files changed, 641 insertions(+) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 28be6651945..b08e44577b8 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1267,6 +1267,7 @@ static struct riscv_implicit_subset riscv_implicit_su= bsets[] =3D {"zcf", "zca", check_implicit_always}, {"zcd", "zca", check_implicit_always}, {"zcb", "zca", check_implicit_always}, + {"zcmp", "zca", check_implicit_always}, {"smaia", "ssaia", check_implicit_always}, {"smcntrpmf", "zicsr", check_implicit_always}, {"smstateen", "ssstateen", check_implicit_always}, @@ -1415,6 +1416,7 @@ static struct riscv_supported_ext riscv_supported_std= _z_ext[] =3D {"zcb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zcf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zcd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zcmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} }; =20 @@ -2056,6 +2058,13 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *r= ps) rps->error_handler (_("rv%d does not support the `q' extension"), xl= en); no_conflict =3D false; } + if (riscv_subset_supports (rps, "zcmp") + && riscv_subset_supports (rps, "zcd")) + { + rps->error_handler + (_("zcmp' is incompatible with `d/zcd' extension")); + no_conflict =3D false; + } if (riscv_lookup_subset (rps->subset_list, "zcf", &subset) && xlen > 32) { @@ -2645,6 +2654,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rp= s, case INSN_CLASS_ZCB_AND_ZMMUL: return (riscv_subset_supports (rps, "zcb") && riscv_subset_supports (rps, "zmmul")); + case INSN_CLASS_ZCMP: + return riscv_subset_supports (rps, "zcmp"); case INSN_CLASS_SVINVAL: return riscv_subset_supports (rps, "svinval"); case INSN_CLASS_H: @@ -2899,6 +2910,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t= *rps, return _("zcb' and `zbb"); case INSN_CLASS_ZCB_AND_ZMMUL: return _("zcb' and `zmmul', or `zcb' and `m"); + case INSN_CLASS_ZCMP: + return "zcmp"; case INSN_CLASS_SVINVAL: return "svinval"; case INSN_CLASS_H: diff --git a/gas/NEWS b/gas/NEWS index 4a7f6dcbb0b..cb58ca8fb8d 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -11,6 +11,8 @@ * Remove support for RISC-V privileged spec 1.9.1, but linker can still recognize it in case of linking old objects. =20 +* Add support for RISC-V Zcmp extension with version 1.0. + * The base register operand in D(X,B) and D(L,B) may be explicitly omitted in assembly on s390. It can now be coded as D(X,) or D(L,) instead of D(= X,0) D(X,%r0), D(L,0), and D(L,%r0). diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 94f0c679bb9..1757ff6e9e2 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1254,6 +1254,158 @@ flt_lookup (float f, const float *array, size_t siz= e, unsigned *regnop) return false; } =20 +/* Map ra and s-register to [4,15], so that we can check if the + reg2 in register list reg1-reg2 or single reg2 is valid or not, + and obtain the corresponding reg_list value. + + ra - 4 + s0 - 5 + s1 - 6 + .... + s10 - 0 (invalid) + s11 - 15. */ + +static int +regno_to_reg_list (unsigned regno) +{ + if (regno =3D=3D X_RA) + return 4; + else if (regno =3D=3D X_S0 || regno =3D=3D X_S1) + return 5 + regno - X_S0; + else if (regno >=3D X_S2 && regno < X_S10) + return 7 + regno - X_S2; + else if (regno =3D=3D X_S11) + return 15; + + /* Invalid symbol. */ + return 0; +} + +/* Parse register list, and return the last register by regno_to_reg_list. + + If ABI register names are used (e.g. ra and s0), the register + list could be "{ra}", "{ra, s0}", "{ra, s0-sN}", where 0 < N < 10 or + N =3D=3D 11. + + If numeric register names are used (e.g. x1 and x8), the register list + could be "{x1}", "{x1,x8}", "{x1,x8-x9}", "{x1,x8-x9,x18}" and + "{x1,x8-x9,x18-xN}", where 19 < N < 25 or N =3D=3D 27. + + The numeric and ABI register names cannot be used at the same time. + + TODO: Report errors for the following cases, + 1. Too many registers in the list. + 2. Cases which return 0. + 3. Illegal formats, for example, {x1,x8-NULL,x18-x24/x18}, {x1-x2,x8}. = */ + +static unsigned +reglist_lookup_internal (char *reglist) +{ + unsigned regno =3D 0; + unsigned reg_list =3D 0; + char *regname[3][2] =3D {{NULL}}; + char *save_tok, *save_subtok; + unsigned i, j; + + char *token =3D strtok_r (reglist, ",", &save_tok); + for (i =3D 0; i < 3 && token !=3D NULL; + token =3D strtok_r (NULL, ",", &save_tok), i++) + { + char *subtoken =3D strtok_r (token, "-", &save_subtok); + for (j =3D 0; j < 2 && subtoken !=3D NULL; + subtoken =3D strtok_r (NULL, "-", &save_subtok), j++) + regname[i][j] =3D subtoken; + } + + bool reg1_numeric =3D false; + for (i =3D 0; i < 3; i++) + { + if (regname[i][0] =3D=3D NULL) + continue; +#define REG_TO_REG_LIST(NAME, NUM, LIST) \ + (reg_lookup (&NAME, RCLASS_GPR, &NUM) && (LIST =3D regno_to_reg_list (NU= M))) +#define REG_NUMERIC(NAME) (NAME[0] =3D=3D 'x') +#define REG_CONFLICT(NAME, REG_NUMERIC) \ + ((NAME[0] =3D=3D 'x' && !REG_NUMERIC) || (NAME[0] !=3D 'x' && REG_NUMERI= C)) + switch (i) + { + case 0: + reg1_numeric =3D REG_NUMERIC (regname[i][0]); + if (!REG_TO_REG_LIST (regname[i][0], regno, reg_list) + || regno !=3D X_RA) + return 0; + break; + case 1: + if (REG_CONFLICT (regname[i][0], reg1_numeric) + /* The second register should be s0 or its numeric names x8. */ + || !REG_TO_REG_LIST (regname[i][0], regno, reg_list) + || regno !=3D X_S0) + return 0; + else if (regname[i][1] =3D=3D NULL) + return reg_list; + + if (REG_CONFLICT (regname[i][1], reg1_numeric) + /* The third register is x9 if the numeric name is used. + Otherwise, it could be any other sN register, where N > 0. */ + || !REG_TO_REG_LIST (regname[i][1], regno, reg_list) + || regno <=3D X_S0 + || (reg1_numeric && regno !=3D X_S1)) + return 0; + break; + case 2: + /* Must use register numeric names. */ + if (!reg1_numeric + || !REG_NUMERIC (regname[i][0]) + /* The fourth register should be s2. */ + || !REG_TO_REG_LIST (regname[i][0], regno, reg_list) + || regno !=3D X_S2) + return 0; + else if (regname[i][1] =3D=3D NULL) + return reg_list; + + if (!reg1_numeric + || !REG_NUMERIC (regname[i][1]) + /* The fifth register could be any other sN register, where N > 1. = */ + || !REG_TO_REG_LIST (regname[i][1], regno, reg_list) + || regno <=3D X_S2) + return 0; + break; + default: + return 0; + } +#undef REG_TO_REG_LIST +#undef REG_NUMERIC +#undef REG_CONFLICT + } + return reg_list; +} + +/* Parse register list. Return false if REG_LIST is zero, which is an + invalid value. */ + +static bool +reglist_lookup (char **s, unsigned *reg_list) +{ + *reg_list =3D 0; + char *reglist =3D strdup (*s); + if (reglist !=3D NULL) + { + char *token =3D strtok (reglist, "}"); + if (token !=3D NULL) + { + *s +=3D strlen (token); + *reg_list =3D reglist_lookup_internal (reglist); + } + else + { + as_bad (_("cannot find `}' for cm.push/cm.pop")); + *reg_list =3D 0; + } + } + free (reglist); + return *reg_list =3D=3D 0 ? false : true; +} + #define USE_BITS(mask,shift) (used_bits |=3D ((insn_t)(mask) << (shift))) #define USE_IMM(n, s) \ (used_bits |=3D ((insn_t)((1ull<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; case 'A': break; /* Macro operand, must be symbol. */ @@ -1450,6 +1604,10 @@ validate_riscv_insn (const struct riscv_opcode *opc,= int length) case 'h': used_bits |=3D ENCODE_ZCB_HALFWORD_UIMM (-1U); break; /* halfword immediate operators, load/store halfword insns. */ case 'b': used_bits |=3D ENCODE_ZCB_BYTE_UIMM (-1U); break; + /* Immediate offset operand for cm.push and cm.pop. */ + case 'p': used_bits |=3D ENCODE_ZCMP_SPIMM (-1U); break; + /* Register list operand for cm.push and cm.pop. */ + case 'r': USE_BITS (OP_MASK_REG_LIST, OP_SH_REG_LIST); break; case 'f': break; default: goto unknown_validate_operand; @@ -3206,6 +3364,8 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expres= sionS *imm_expr, case ')': case '[': case ']': + case '{': + case '}': if (*asarg++ =3D=3D *oparg) continue; break; @@ -3661,6 +3821,27 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expre= ssionS *imm_expr, break; ip->insn_opcode |=3D ENCODE_ZCB_BYTE_UIMM (imm_expr->X_add_number); goto rvc_imm_done; + case 'r': + if (!reglist_lookup (&asarg, ®no)) + break; + INSERT_OPERAND (REG_LIST, *ip, regno); + continue; + case 'p': + if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) + || imm_expr->X_op !=3D O_constant) + break; + /* Convert stack adjustment of cm.push to a positive + offset. */ + if (ip->insn_mo->match =3D=3D MATCH_CM_PUSH) + imm_expr->X_add_number *=3D -1; + /* Subtract base stack adjustment and get spimm. */ + imm_expr->X_add_number -=3D + riscv_get_sp_base (ip->insn_opcode, *riscv_rps_as.xlen); + if (!VALID_ZCMP_SPIMM (imm_expr->X_add_number)) + break; + ip->insn_opcode |=3D + ENCODE_ZCMP_SPIMM (imm_expr->X_add_number); + goto rvc_imm_done; case 'f': /* Operand for matching immediate 255. */ if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) || imm_expr->X_op !=3D O_constant diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv= /march-help.l index 7f92194d10d..e45221e5ed8 100644 --- a/gas/testsuite/gas/riscv/march-help.l +++ b/gas/testsuite/gas/riscv/march-help.l @@ -87,6 +87,7 @@ All available -march extensions for RISC-V: zcb 1.0 zcf 1.0 zcd 1.0 + zcmp 1.0 smaia 1.0 smcntrpmf 1.0 smepmp 1.0 diff --git a/gas/testsuite/gas/riscv/zcmp-push-pop-fail.d b/gas/testsuite/g= as/riscv/zcmp-push-pop-fail.d new file mode 100644 index 00000000000..84ecf263c54 --- /dev/null +++ b/gas/testsuite/gas/riscv/zcmp-push-pop-fail.d @@ -0,0 +1,3 @@ +#as: -march=3Drv64i_zcmp +#source: zcmp-push-pop-fail.s +#error_output: zcmp-push-pop-fail.l diff --git a/gas/testsuite/gas/riscv/zcmp-push-pop-fail.l b/gas/testsuite/g= as/riscv/zcmp-push-pop-fail.l new file mode 100644 index 00000000000..955e495d5bb --- /dev/null +++ b/gas/testsuite/gas/riscv/zcmp-push-pop-fail.l @@ -0,0 +1,9 @@ +.*: Assembler messages: +.*: Error: illegal operands `cm.push \{a0\},-64' +.*: Error: illegal operands `cm.pop \{ra,s1\},-64' +.*: Error: illegal operands `cm.popret \{ra,s2-s3\},-64' +.*: Error: illegal operands `cm.popretz \{ra,s0-s10\},-112' +.*: Error: illegal operands `cm.push \{ra\},0' +.*: Error: illegal operands `cm.pop \{ra,s0\},-80' +.*: Error: illegal operands `cm.popret \{ra,s0-s1\},-15' +.*: Error: illegal operands `cm.popretz \{ra,s0-s11\},-165' diff --git a/gas/testsuite/gas/riscv/zcmp-push-pop-fail.s b/gas/testsuite/g= as/riscv/zcmp-push-pop-fail.s new file mode 100644 index 00000000000..0e8df5800dd --- /dev/null +++ b/gas/testsuite/gas/riscv/zcmp-push-pop-fail.s @@ -0,0 +1,13 @@ +target: + + # reg_list + cm.push {a0}, -64 + cm.pop {ra, s1}, -64 + cm.popret {ra, s2-s3}, -64 + cm.popretz {ra, s0-s10}, -112 + + # spimm + cm.push {ra}, 0 + cm.pop {ra, s0}, -80 + cm.popret {ra, s0-s1}, -15 + cm.popretz {ra, s0-s11}, -165 diff --git a/gas/testsuite/gas/riscv/zcmp-push-pop.d b/gas/testsuite/gas/ri= scv/zcmp-push-pop.d new file mode 100644 index 00000000000..e21295051ec --- /dev/null +++ b/gas/testsuite/gas/riscv/zcmp-push-pop.d @@ -0,0 +1,154 @@ +#as: -march=3Drv64i_zcmp +#source: zcmp-push-pop.s +#objdump: -dr -Mno-aliases + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]*[0-9a-f]+:[ ]+b84e[ ]+cm.push[ ]+\{ra\},-64 +[ ]*[0-9a-f]+:[ ]+b85e[ ]+cm.push[ ]+\{ra,s0\},-64 +[ ]*[0-9a-f]+:[ ]+b86a[ ]+cm.push[ ]+\{ra,s0-s1\},-64 +[ ]*[0-9a-f]+:[ ]+b87a[ ]+cm.push[ ]+\{ra,s0-s2\},-64 +[ ]*[0-9a-f]+:[ ]+b8da[ ]+cm.push[ ]+\{ra,s0-s8\},-112 +[ ]*[0-9a-f]+:[ ]+b8e6[ ]+cm.push[ ]+\{ra,s0-s9\},-112 +[ ]*[0-9a-f]+:[ ]+b8f2[ ]+cm.push[ ]+\{ra,s0-s11\},-112 +[ ]*[0-9a-f]+:[ ]+b84e[ ]+cm.push[ ]+\{ra\},-64 +[ ]*[0-9a-f]+:[ ]+b85e[ ]+cm.push[ ]+\{ra,s0\},-64 +[ ]*[0-9a-f]+:[ ]+b86a[ ]+cm.push[ ]+\{ra,s0-s1\},-64 +[ ]*[0-9a-f]+:[ ]+b87a[ ]+cm.push[ ]+\{ra,s0-s2\},-64 +[ ]*[0-9a-f]+:[ ]+b8da[ ]+cm.push[ ]+\{ra,s0-s8\},-112 +[ ]*[0-9a-f]+:[ ]+b8e6[ ]+cm.push[ ]+\{ra,s0-s9\},-112 +[ ]*[0-9a-f]+:[ ]+b8f2[ ]+cm.push[ ]+\{ra,s0-s11},-112 +[ ]*[0-9a-f]+:[ ]+b842[ ]+cm.push[ ]+\{ra\},-16 +[ ]*[0-9a-f]+:[ ]+b846[ ]+cm.push[ ]+\{ra\},-32 +[ ]*[0-9a-f]+:[ ]+b84e[ ]+cm.push[ ]+\{ra\},-64 +[ ]*[0-9a-f]+:[ ]+b872[ ]+cm.push[ ]+\{ra,s0-s2\},-32 +[ ]*[0-9a-f]+:[ ]+b87a[ ]+cm.push[ ]+\{ra,s0-s2\},-64 +[ ]*[0-9a-f]+:[ ]+b87e[ ]+cm.push[ ]+\{ra,s0-s2\},-80 +[ ]*[0-9a-f]+:[ ]+b882[ ]+cm.push[ ]+\{ra,s0-s3\},-48 +[ ]*[0-9a-f]+:[ ]+b886[ ]+cm.push[ ]+\{ra,s0-s3\},-64 +[ ]*[0-9a-f]+:[ ]+b88e[ ]+cm.push[ ]+\{ra,s0-s3\},-96 +[ ]*[0-9a-f]+:[ ]+b8b2[ ]+cm.push[ ]+\{ra,s0-s6\},-64 +[ ]*[0-9a-f]+:[ ]+b8b6[ ]+cm.push[ ]+\{ra,s0-s6\},-80 +[ ]*[0-9a-f]+:[ ]+b8be[ ]+cm.push[ ]+\{ra,s0-s6\},-112 +[ ]*[0-9a-f]+:[ ]+b8c2[ ]+cm.push[ ]+\{ra,s0-s7\},-80 +[ ]*[0-9a-f]+:[ ]+b8c6[ ]+cm.push[ ]+\{ra,s0-s7\},-96 +[ ]*[0-9a-f]+:[ ]+b8ce[ ]+cm.push[ ]+\{ra,s0-s7\},-128 +[ ]*[0-9a-f]+:[ ]+b8e2[ ]+cm.push[ ]+\{ra,s0-s9\},-96 +[ ]*[0-9a-f]+:[ ]+b8e6[ ]+cm.push[ ]+\{ra,s0-s9\},-112 +[ ]*[0-9a-f]+:[ ]+b8ee[ ]+cm.push[ ]+\{ra,s0-s9\},-144 +[ ]*[0-9a-f]+:[ ]+b8f2[ ]+cm.push[ ]+\{ra,s0-s11\},-112 +[ ]*[0-9a-f]+:[ ]+b8f6[ ]+cm.push[ ]+\{ra,s0-s11\},-128 +[ ]*[0-9a-f]+:[ ]+b8fa[ ]+cm.push[ ]+\{ra,s0-s11\},-144 +[ ]*[0-9a-f]+:[ ]+b8fe[ ]+cm.push[ ]+\{ra,s0-s11\},-160 +[ ]*[0-9a-f]+:[ ]+ba4e[ ]+cm.pop[ ]+\{ra\},64 +[ ]*[0-9a-f]+:[ ]+ba5e[ ]+cm.pop[ ]+\{ra,s0\},64 +[ ]*[0-9a-f]+:[ ]+ba6a[ ]+cm.pop[ ]+\{ra,s0-s1\},64 +[ ]*[0-9a-f]+:[ ]+ba7a[ ]+cm.pop[ ]+\{ra,s0-s2\},64 +[ ]*[0-9a-f]+:[ ]+bada[ ]+cm.pop[ ]+\{ra,s0-s8\},112 +[ ]*[0-9a-f]+:[ ]+bae6[ ]+cm.pop[ ]+\{ra,s0-s9\},112 +[ ]*[0-9a-f]+:[ ]+baf2[ ]+cm.pop[ ]+\{ra,s0-s11\},112 +[ ]*[0-9a-f]+:[ ]+ba4e[ ]+cm.pop[ ]+\{ra\},64 +[ ]*[0-9a-f]+:[ ]+ba5e[ ]+cm.pop[ ]+\{ra,s0\},64 +[ ]*[0-9a-f]+:[ ]+ba6a[ ]+cm.pop[ ]+\{ra,s0-s1\},64 +[ ]*[0-9a-f]+:[ ]+ba7a[ ]+cm.pop[ ]+\{ra,s0-s2\},64 +[ ]*[0-9a-f]+:[ ]+bada[ ]+cm.pop[ ]+\{ra,s0-s8\},112 +[ ]*[0-9a-f]+:[ ]+bae6[ ]+cm.pop[ ]+\{ra,s0-s9\},112 +[ ]*[0-9a-f]+:[ ]+baf2[ ]+cm.pop[ ]+\{ra,s0-s11},112 +[ ]*[0-9a-f]+:[ ]+ba42[ ]+cm.pop[ ]+\{ra\},16 +[ ]*[0-9a-f]+:[ ]+ba46[ ]+cm.pop[ ]+\{ra\},32 +[ ]*[0-9a-f]+:[ ]+ba4e[ ]+cm.pop[ ]+\{ra\},64 +[ ]*[0-9a-f]+:[ ]+ba72[ ]+cm.pop[ ]+\{ra,s0-s2\},32 +[ ]*[0-9a-f]+:[ ]+ba7a[ ]+cm.pop[ ]+\{ra,s0-s2\},64 +[ ]*[0-9a-f]+:[ ]+ba7e[ ]+cm.pop[ ]+\{ra,s0-s2\},80 +[ ]*[0-9a-f]+:[ ]+ba82[ ]+cm.pop[ ]+\{ra,s0-s3\},48 +[ ]*[0-9a-f]+:[ ]+ba86[ ]+cm.pop[ ]+\{ra,s0-s3\},64 +[ ]*[0-9a-f]+:[ ]+ba8e[ ]+cm.pop[ ]+\{ra,s0-s3\},96 +[ ]*[0-9a-f]+:[ ]+bab2[ ]+cm.pop[ ]+\{ra,s0-s6\},64 +[ ]*[0-9a-f]+:[ ]+bab6[ ]+cm.pop[ ]+\{ra,s0-s6\},80 +[ ]*[0-9a-f]+:[ ]+babe[ ]+cm.pop[ ]+\{ra,s0-s6\},112 +[ ]*[0-9a-f]+:[ ]+bac2[ ]+cm.pop[ ]+\{ra,s0-s7\},80 +[ ]*[0-9a-f]+:[ ]+bac6[ ]+cm.pop[ ]+\{ra,s0-s7\},96 +[ ]*[0-9a-f]+:[ ]+bace[ ]+cm.pop[ ]+\{ra,s0-s7\},128 +[ ]*[0-9a-f]+:[ ]+bae2[ ]+cm.pop[ ]+\{ra,s0-s9\},96 +[ ]*[0-9a-f]+:[ ]+bae6[ ]+cm.pop[ ]+\{ra,s0-s9\},112 +[ ]*[0-9a-f]+:[ ]+baee[ ]+cm.pop[ ]+\{ra,s0-s9\},144 +[ ]*[0-9a-f]+:[ ]+baf2[ ]+cm.pop[ ]+\{ra,s0-s11\},112 +[ ]*[0-9a-f]+:[ ]+baf6[ ]+cm.pop[ ]+\{ra,s0-s11\},128 +[ ]*[0-9a-f]+:[ ]+bafa[ ]+cm.pop[ ]+\{ra,s0-s11\},144 +[ ]*[0-9a-f]+:[ ]+bafe[ ]+cm.pop[ ]+\{ra,s0-s11\},160 +[ ]*[0-9a-f]+:[ ]+be4e[ ]+cm.popret[ ]+\{ra\},64 +[ ]*[0-9a-f]+:[ ]+be5e[ ]+cm.popret[ ]+\{ra,s0\},64 +[ ]*[0-9a-f]+:[ ]+be6a[ ]+cm.popret[ ]+\{ra,s0-s1\},64 +[ ]*[0-9a-f]+:[ ]+be7a[ ]+cm.popret[ ]+\{ra,s0-s2\},64 +[ ]*[0-9a-f]+:[ ]+beda[ ]+cm.popret[ ]+\{ra,s0-s8\},112 +[ ]*[0-9a-f]+:[ ]+bee6[ ]+cm.popret[ ]+\{ra,s0-s9\},112 +[ ]*[0-9a-f]+:[ ]+bef2[ ]+cm.popret[ ]+\{ra,s0-s11\},112 +[ ]*[0-9a-f]+:[ ]+be4e[ ]+cm.popret[ ]+\{ra\},64 +[ ]*[0-9a-f]+:[ ]+be5e[ ]+cm.popret[ ]+\{ra,s0\},64 +[ ]*[0-9a-f]+:[ ]+be6a[ ]+cm.popret[ ]+\{ra,s0-s1\},64 +[ ]*[0-9a-f]+:[ ]+be7a[ ]+cm.popret[ ]+\{ra,s0-s2\},64 +[ ]*[0-9a-f]+:[ ]+beda[ ]+cm.popret[ ]+\{ra,s0-s8\},112 +[ ]*[0-9a-f]+:[ ]+bee6[ ]+cm.popret[ ]+\{ra,s0-s9\},112 +[ ]*[0-9a-f]+:[ ]+bef2[ ]+cm.popret[ ]+\{ra,s0-s11},112 +[ ]*[0-9a-f]+:[ ]+be42[ ]+cm.popret[ ]+\{ra\},16 +[ ]*[0-9a-f]+:[ ]+be46[ ]+cm.popret[ ]+\{ra\},32 +[ ]*[0-9a-f]+:[ ]+be4e[ ]+cm.popret[ ]+\{ra\},64 +[ ]*[0-9a-f]+:[ ]+be72[ ]+cm.popret[ ]+\{ra,s0-s2\},32 +[ ]*[0-9a-f]+:[ ]+be7a[ ]+cm.popret[ ]+\{ra,s0-s2\},64 +[ ]*[0-9a-f]+:[ ]+be7e[ ]+cm.popret[ ]+\{ra,s0-s2\},80 +[ ]*[0-9a-f]+:[ ]+be82[ ]+cm.popret[ ]+\{ra,s0-s3\},48 +[ ]*[0-9a-f]+:[ ]+be86[ ]+cm.popret[ ]+\{ra,s0-s3\},64 +[ ]*[0-9a-f]+:[ ]+be8e[ ]+cm.popret[ ]+\{ra,s0-s3\},96 +[ ]*[0-9a-f]+:[ ]+beb2[ ]+cm.popret[ ]+\{ra,s0-s6\},64 +[ ]*[0-9a-f]+:[ ]+beb6[ ]+cm.popret[ ]+\{ra,s0-s6\},80 +[ ]*[0-9a-f]+:[ ]+bebe[ ]+cm.popret[ ]+\{ra,s0-s6\},112 +[ ]*[0-9a-f]+:[ ]+bec2[ ]+cm.popret[ ]+\{ra,s0-s7\},80 +[ ]*[0-9a-f]+:[ ]+bec6[ ]+cm.popret[ ]+\{ra,s0-s7\},96 +[ ]*[0-9a-f]+:[ ]+bece[ ]+cm.popret[ ]+\{ra,s0-s7\},128 +[ ]*[0-9a-f]+:[ ]+bee2[ ]+cm.popret[ ]+\{ra,s0-s9\},96 +[ ]*[0-9a-f]+:[ ]+bee6[ ]+cm.popret[ ]+\{ra,s0-s9\},112 +[ ]*[0-9a-f]+:[ ]+beee[ ]+cm.popret[ ]+\{ra,s0-s9\},144 +[ ]*[0-9a-f]+:[ ]+bef2[ ]+cm.popret[ ]+\{ra,s0-s11\},112 +[ ]*[0-9a-f]+:[ ]+bef6[ ]+cm.popret[ ]+\{ra,s0-s11\},128 +[ ]*[0-9a-f]+:[ ]+befa[ ]+cm.popret[ ]+\{ra,s0-s11\},144 +[ ]*[0-9a-f]+:[ ]+befe[ ]+cm.popret[ ]+\{ra,s0-s11\},160 +[ ]*[0-9a-f]+:[ ]+bc4e[ ]+cm.popretz[ ]+\{ra\},64 +[ ]*[0-9a-f]+:[ ]+bc5e[ ]+cm.popretz[ ]+\{ra,s0\},64 +[ ]*[0-9a-f]+:[ ]+bc6a[ ]+cm.popretz[ ]+\{ra,s0-s1\},64 +[ ]*[0-9a-f]+:[ ]+bc7a[ ]+cm.popretz[ ]+\{ra,s0-s2\},64 +[ ]*[0-9a-f]+:[ ]+bcda[ ]+cm.popretz[ ]+\{ra,s0-s8\},112 +[ ]*[0-9a-f]+:[ ]+bce6[ ]+cm.popretz[ ]+\{ra,s0-s9\},112 +[ ]*[0-9a-f]+:[ ]+bcf2[ ]+cm.popretz[ ]+\{ra,s0-s11\},112 +[ ]*[0-9a-f]+:[ ]+bc4e[ ]+cm.popretz[ ]+\{ra\},64 +[ ]*[0-9a-f]+:[ ]+bc5e[ ]+cm.popretz[ ]+\{ra,s0\},64 +[ ]*[0-9a-f]+:[ ]+bc6a[ ]+cm.popretz[ ]+\{ra,s0-s1\},64 +[ ]*[0-9a-f]+:[ ]+bc7a[ ]+cm.popretz[ ]+\{ra,s0-s2\},64 +[ ]*[0-9a-f]+:[ ]+bcda[ ]+cm.popretz[ ]+\{ra,s0-s8\},112 +[ ]*[0-9a-f]+:[ ]+bce6[ ]+cm.popretz[ ]+\{ra,s0-s9\},112 +[ ]*[0-9a-f]+:[ ]+bcf2[ ]+cm.popretz[ ]+\{ra,s0-s11},112 +[ ]*[0-9a-f]+:[ ]+bc42[ ]+cm.popretz[ ]+\{ra\},16 +[ ]*[0-9a-f]+:[ ]+bc46[ ]+cm.popretz[ ]+\{ra\},32 +[ ]*[0-9a-f]+:[ ]+bc4e[ ]+cm.popretz[ ]+\{ra\},64 +[ ]*[0-9a-f]+:[ ]+bc72[ ]+cm.popretz[ ]+\{ra,s0-s2\},32 +[ ]*[0-9a-f]+:[ ]+bc7a[ ]+cm.popretz[ ]+\{ra,s0-s2\},64 +[ ]*[0-9a-f]+:[ ]+bc7e[ ]+cm.popretz[ ]+\{ra,s0-s2\},80 +[ ]*[0-9a-f]+:[ ]+bc82[ ]+cm.popretz[ ]+\{ra,s0-s3\},48 +[ ]*[0-9a-f]+:[ ]+bc86[ ]+cm.popretz[ ]+\{ra,s0-s3\},64 +[ ]*[0-9a-f]+:[ ]+bc8e[ ]+cm.popretz[ ]+\{ra,s0-s3\},96 +[ ]*[0-9a-f]+:[ ]+bcb2[ ]+cm.popretz[ ]+\{ra,s0-s6\},64 +[ ]*[0-9a-f]+:[ ]+bcb6[ ]+cm.popretz[ ]+\{ra,s0-s6\},80 +[ ]*[0-9a-f]+:[ ]+bcbe[ ]+cm.popretz[ ]+\{ra,s0-s6\},112 +[ ]*[0-9a-f]+:[ ]+bcc2[ ]+cm.popretz[ ]+\{ra,s0-s7\},80 +[ ]*[0-9a-f]+:[ ]+bcc6[ ]+cm.popretz[ ]+\{ra,s0-s7\},96 +[ ]*[0-9a-f]+:[ ]+bcce[ ]+cm.popretz[ ]+\{ra,s0-s7\},128 +[ ]*[0-9a-f]+:[ ]+bce2[ ]+cm.popretz[ ]+\{ra,s0-s9\},96 +[ ]*[0-9a-f]+:[ ]+bce6[ ]+cm.popretz[ ]+\{ra,s0-s9\},112 +[ ]*[0-9a-f]+:[ ]+bcee[ ]+cm.popretz[ ]+\{ra,s0-s9\},144 +[ ]*[0-9a-f]+:[ ]+bcf2[ ]+cm.popretz[ ]+\{ra,s0-s11\},112 +[ ]*[0-9a-f]+:[ ]+bcf6[ ]+cm.popretz[ ]+\{ra,s0-s11\},128 +[ ]*[0-9a-f]+:[ ]+bcfa[ ]+cm.popretz[ ]+\{ra,s0-s11\},144 +[ ]*[0-9a-f]+:[ ]+bcfe[ ]+cm.popretz[ ]+\{ra,s0-s11\},160 diff --git a/gas/testsuite/gas/riscv/zcmp-push-pop.s b/gas/testsuite/gas/ri= scv/zcmp-push-pop.s new file mode 100644 index 00000000000..dc441bc2776 --- /dev/null +++ b/gas/testsuite/gas/riscv/zcmp-push-pop.s @@ -0,0 +1,162 @@ +target: + + # push + # abi names + cm.push {ra}, -64 + cm.push {ra, s0}, -64 + cm.push {ra, s0-s1}, -64 + cm.push {ra, s0-s2}, -64 + cm.push {ra, s0-s8}, -112 + cm.push {ra, s0-s9}, -112 + cm.push {ra, s0-s11}, -112 + # numeric names + cm.push {x1}, -64 + cm.push {x1, x8}, -64 + cm.push {x1, x8-x9}, -64 + cm.push {x1, x8-x9, x18}, -64 + cm.push {x1, x8-x9, x18-x24}, -112 + cm.push {x1, x8-x9, x18-x25}, -112 + cm.push {x1, x8-x9, x18-x27}, -112 + # spimm + cm.push {ra}, -16 + cm.push {ra}, -32 + cm.push {ra}, -64 + cm.push {ra, s0-s2}, -32 + cm.push {ra, s0-s2}, -64 + cm.push {ra, s0-s2}, -80 + cm.push {ra, s0-s3}, -48 + cm.push {ra, s0-s3}, -64 + cm.push {ra, s0-s3}, -96 + cm.push {ra, s0-s6}, -64 + cm.push {ra, s0-s6}, -80 + cm.push {ra, s0-s6}, -112 + cm.push {ra, s0-s7}, -80 + cm.push {ra, s0-s7}, -96 + cm.push {ra, s0-s7}, -128 + cm.push {ra, s0-s9}, -96 + cm.push {ra, s0-s9}, -112 + cm.push {ra, s0-s9}, -144 + cm.push {ra, s0-s11}, -112 + cm.push {ra, s0-s11}, -128 + cm.push {ra, s0-s11}, -144 + cm.push {ra, s0-s11}, -160 + # pop + # abi names + cm.pop {ra}, 64 + cm.pop {ra, s0}, 64 + cm.pop {ra, s0-s1}, 64 + cm.pop {ra, s0-s2}, 64 + cm.pop {ra, s0-s8}, 112 + cm.pop {ra, s0-s9}, 112 + cm.pop {ra, s0-s11}, 112 + # numeric names + cm.pop {x1}, 64 + cm.pop {x1, x8}, 64 + cm.pop {x1, x8-x9}, 64 + cm.pop {x1, x8-x9, x18}, 64 + cm.pop {x1, x8-x9, x18-x24}, 112 + cm.pop {x1, x8-x9, x18-x25}, 112 + cm.pop {x1, x8-x9, x18-x27}, 112 + # spimm + cm.pop {ra}, 16 + cm.pop {ra}, 32 + cm.pop {ra}, 64 + cm.pop {ra, s0-s2}, 32 + cm.pop {ra, s0-s2}, 64 + cm.pop {ra, s0-s2}, 80 + cm.pop {ra, s0-s3}, 48 + cm.pop {ra, s0-s3}, 64 + cm.pop {ra, s0-s3}, 96 + cm.pop {ra, s0-s6}, 64 + cm.pop {ra, s0-s6}, 80 + cm.pop {ra, s0-s6}, 112 + cm.pop {ra, s0-s7}, 80 + cm.pop {ra, s0-s7}, 96 + cm.pop {ra, s0-s7}, 128 + cm.pop {ra, s0-s9}, 96 + cm.pop {ra, s0-s9}, 112 + cm.pop {ra, s0-s9}, 144 + cm.pop {ra, s0-s11}, 112 + cm.pop {ra, s0-s11}, 128 + cm.pop {ra, s0-s11}, 144 + cm.pop {ra, s0-s11}, 160 + # popret + # abi names + cm.popret {ra}, 64 + cm.popret {ra, s0}, 64 + cm.popret {ra, s0-s1}, 64 + cm.popret {ra, s0-s2}, 64 + cm.popret {ra, s0-s8}, 112 + cm.popret {ra, s0-s9}, 112 + cm.popret {ra, s0-s11}, 112 + # numeric names + cm.popret {x1}, 64 + cm.popret {x1, x8}, 64 + cm.popret {x1, x8-x9}, 64 + cm.popret {x1, x8-x9, x18}, 64 + cm.popret {x1, x8-x9, x18-x24}, 112 + cm.popret {x1, x8-x9, x18-x25}, 112 + cm.popret {x1, x8-x9, x18-x27}, 112 + # spimm + cm.popret {ra}, 16 + cm.popret {ra}, 32 + cm.popret {ra}, 64 + cm.popret {ra, s0-s2}, 32 + cm.popret {ra, s0-s2}, 64 + cm.popret {ra, s0-s2}, 80 + cm.popret {ra, s0-s3}, 48 + cm.popret {ra, s0-s3}, 64 + cm.popret {ra, s0-s3}, 96 + cm.popret {ra, s0-s6}, 64 + cm.popret {ra, s0-s6}, 80 + cm.popret {ra, s0-s6}, 112 + cm.popret {ra, s0-s7}, 80 + cm.popret {ra, s0-s7}, 96 + cm.popret {ra, s0-s7}, 128 + cm.popret {ra, s0-s9}, 96 + cm.popret {ra, s0-s9}, 112 + cm.popret {ra, s0-s9}, 144 + cm.popret {ra, s0-s11}, 112 + cm.popret {ra, s0-s11}, 128 + cm.popret {ra, s0-s11}, 144 + cm.popret {ra, s0-s11}, 160 + # popretz + # abi names + cm.popretz {ra}, 64 + cm.popretz {ra, s0}, 64 + cm.popretz {ra, s0-s1}, 64 + cm.popretz {ra, s0-s2}, 64 + cm.popretz {ra, s0-s8}, 112 + cm.popretz {ra, s0-s9}, 112 + cm.popretz {ra, s0-s11}, 112 + # numeric names + cm.popretz {x1}, 64 + cm.popretz {x1, x8}, 64 + cm.popretz {x1, x8-x9}, 64 + cm.popretz {x1, x8-x9, x18}, 64 + cm.popretz {x1, x8-x9, x18-x24}, 112 + cm.popretz {x1, x8-x9, x18-x25}, 112 + cm.popretz {x1, x8-x9, x18-x27}, 112 + # spimm + cm.popretz {ra}, 16 + cm.popretz {ra}, 32 + cm.popretz {ra}, 64 + cm.popretz {ra, s0-s2}, 32 + cm.popretz {ra, s0-s2}, 64 + cm.popretz {ra, s0-s2}, 80 + cm.popretz {ra, s0-s3}, 48 + cm.popretz {ra, s0-s3}, 64 + cm.popretz {ra, s0-s3}, 96 + cm.popretz {ra, s0-s6}, 64 + cm.popretz {ra, s0-s6}, 80 + cm.popretz {ra, s0-s6}, 112 + cm.popretz {ra, s0-s7}, 80 + cm.popretz {ra, s0-s7}, 96 + cm.popretz {ra, s0-s7}, 128 + cm.popretz {ra, s0-s9}, 96 + cm.popretz {ra, s0-s9}, 112 + cm.popretz {ra, s0-s9}, 144 + cm.popretz {ra, s0-s11}, 112 + cm.popretz {ra, s0-s11}, 128 + cm.popretz {ra, s0-s11}, 144 + cm.popretz {ra, s0-s11}, 160 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 1459ef231dd..ae14e14d427 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2271,6 +2271,15 @@ #define MASK_C_NOT 0xfc7f #define MATCH_C_MUL 0x9c41 #define MASK_C_MUL 0xfc63 +/* Zcmp instructions. */ +#define MATCH_CM_PUSH 0xb802 +#define MASK_CM_PUSH 0xff03 +#define MATCH_CM_POP 0xba02 +#define MASK_CM_POP 0xff03 +#define MATCH_CM_POPRET 0xbe02 +#define MASK_CM_POPRET 0xff03 +#define MATCH_CM_POPRETZ 0xbc02 +#define MASK_CM_POPRETZ 0xff03 /* Svinval instruction. */ #define MATCH_SINVAL_VMA 0x16000073 #define MASK_SINVAL_VMA 0xfe007fff @@ -3964,6 +3973,11 @@ DECLARE_INSN(c_lhu, MATCH_C_LHU, MASK_C_LHU) DECLARE_INSN(c_lh, MATCH_C_LH, MASK_C_LH) DECLARE_INSN(c_sb, MATCH_C_SB, MASK_C_SB) DECLARE_INSN(c_sh, MATCH_C_SH, MASK_C_SH) +/* Zcmp instructions. */ +DECLARE_INSN(cm_push, MATCH_CM_PUSH, MASK_CM_PUSH) +DECLARE_INSN(cm_pop, MATCH_CM_POP, MASK_CM_POP) +DECLARE_INSN(cm_popret, MATCH_CM_POPRET, MASK_CM_POPRET) +DECLARE_INSN(cm_popretz, MATCH_CM_POPRETZ, MASK_CM_POPRETZ) /* Vendor-specific (T-Head) XTheadBa instructions. */ DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL) /* Vendor-specific (T-Head) XTheadBb instructions. */ diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 3245873aa6d..d967b78f706 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -112,6 +112,8 @@ static inline unsigned int riscv_insn_length (insn_t in= sn) (RV_X(x, 6, 1) | (RV_X(x, 5, 1) << 1)) #define EXTRACT_ZCB_HALFWORD_UIMM(x) \ (RV_X(x, 5, 1) << 1) +#define EXTRACT_ZCMP_SPIMM(x) \ + (RV_X(x, 2, 2) << 4) /* Vendor-specific (CORE-V) extract macros. */ #define EXTRACT_CV_IS2_UIMM5(x) \ (RV_X(x, 20, 5)) @@ -168,6 +170,8 @@ static inline unsigned int riscv_insn_length (insn_t in= sn) ((RV_X(x, 0, 1) << 6) | (RV_X(x, 1, 1) << 5)) #define ENCODE_ZCB_HALFWORD_UIMM(x) \ (RV_X(x, 1, 1) << 5) +#define ENCODE_ZCMP_SPIMM(x) \ + (RV_X(x, 4, 2) << 2) /* Vendor-specific (CORE-V) encode macros. */ #define ENCODE_CV_IS2_UIMM5(x) \ (RV_X(x, 0, 5) << 20) @@ -200,6 +204,7 @@ static inline unsigned int riscv_insn_length (insn_t in= sn) #define VALID_RVV_VC_IMM(x) (EXTRACT_RVV_VC_IMM(ENCODE_RVV_VC_IMM(x)) =3D= =3D (x)) #define VALID_ZCB_BYTE_UIMM(x) (EXTRACT_ZCB_BYTE_UIMM(ENCODE_ZCB_BYTE_UIMM= (x)) =3D=3D (x)) #define VALID_ZCB_HALFWORD_UIMM(x) (EXTRACT_ZCB_HALFWORD_UIMM(ENCODE_ZCB_H= ALFWORD_UIMM(x)) =3D=3D (x)) +#define VALID_ZCMP_SPIMM(x) (EXTRACT_ZCMP_SPIMM(ENCODE_ZCMP_SPIMM(x)) =3D= =3D (x)) =20 #define RISCV_RTYPE(insn, rd, rs1, rs2) \ ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) <= < OP_SH_RS2)) @@ -337,6 +342,11 @@ static inline unsigned int riscv_insn_length (insn_t i= nsn) #define OP_MASK_XTHEADVTYPE_RES 0xf #define OP_SH_XTHEADVTYPE_RES 7 =20 +/* Zc fields. */ +#define OP_MASK_REG_LIST 0xf +#define OP_SH_REG_LIST 4 +#define ZCMP_SP_ALIGNMENT 16 + #define NVECR 32 #define NVECM 1 =20 @@ -355,6 +365,11 @@ static inline unsigned int riscv_insn_length (insn_t i= nsn) #define X_T0 5 #define X_T1 6 #define X_T2 7 +#define X_S0 8 +#define X_S1 9 +#define X_S2 18 +#define X_S10 26 +#define X_S11 27 #define X_T3 28 =20 #define NGPR 32 @@ -464,6 +479,7 @@ enum riscv_insn_class INSN_CLASS_ZCB_AND_ZBA, INSN_CLASS_ZCB_AND_ZBB, INSN_CLASS_ZCB_AND_ZMMUL, + INSN_CLASS_ZCMP, INSN_CLASS_SVINVAL, INSN_CLASS_ZICBOM, INSN_CLASS_ZICBOP, @@ -613,4 +629,6 @@ extern const float riscv_fli_numval[32]; extern const struct riscv_opcode riscv_opcodes[]; extern const struct riscv_opcode riscv_insn_types[]; =20 +extern unsigned int riscv_get_sp_base (insn_t, unsigned int); + #endif /* _RISCV_H_ */ diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 3019b9a5130..684098d386a 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -215,6 +215,48 @@ maybe_print_address (struct riscv_private_data *pd, in= t base_reg, int offset, pd->print_addr =3D (bfd_vma)(uint32_t)pd->print_addr; } =20 +/* Get Zcmp reg_list field. */ + +static void +print_reg_list (disassemble_info *info, insn_t l) +{ + bool numeric =3D riscv_gpr_names =3D=3D riscv_gpr_names_numeric; + unsigned reg_list =3D (int)EXTRACT_OPERAND (REG_LIST, l); + unsigned r_start =3D numeric ? X_S2 : X_S0; + info->fprintf_func (info->stream, "%s", riscv_gpr_names[X_RA]); + + if (reg_list =3D=3D 5) + info->fprintf_func (info->stream, ",%s", + riscv_gpr_names[X_S0]); + else if (reg_list =3D=3D 6 || (numeric && reg_list > 6)) + info->fprintf_func (info->stream, ",%s-%s", + riscv_gpr_names[X_S0], + riscv_gpr_names[X_S1]); + if (reg_list =3D=3D 15) + info->fprintf_func (info->stream, ",%s-%s", + riscv_gpr_names[r_start], + riscv_gpr_names[X_S11]); + else if (reg_list =3D=3D 7 && numeric) + info->fprintf_func (info->stream, ",%s", + riscv_gpr_names[X_S2]); + else if (reg_list > 6) + info->fprintf_func (info->stream, ",%s-%s", + riscv_gpr_names[r_start], + riscv_gpr_names[reg_list + 11]); +} + +/* Get Zcmp sp adjustment immediate. */ + +static int +riscv_get_spimm (insn_t l) +{ + int spimm =3D riscv_get_sp_base(l, *riscv_rps_dis.xlen); + spimm +=3D EXTRACT_ZCMP_SPIMM (l); + if (((l ^ MATCH_CM_PUSH) & MASK_CM_PUSH) =3D=3D 0) + spimm *=3D -1; + return spimm; +} + /* Print insn arguments for 32/64-bit code. */ =20 static void @@ -420,6 +462,8 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma p= c, disassemble_info *info case ')': case '[': case ']': + case '{': + case '}': print (info->stream, dis_style_text, "%c", *oparg); break; =20 @@ -634,6 +678,13 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma = pc, disassemble_info *info print (info->stream, dis_style_immediate, "%d", (int)EXTRACT_ZCB_HALFWORD_UIMM (l)); break; + case 'r': + print_reg_list (info, l); + break; + case 'p': + print (info->stream, dis_style_immediate, "%d", + riscv_get_spimm (l)); + break; default: goto undefined_modifier; } diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index daa888de8ac..38a4624da7e 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -143,6 +143,20 @@ const float riscv_fli_numval[32] =3D 0x1p+3, 0x1p+4, 0x1p+7, 0x1p+8, 0x1p+15, 0x1p+16, 0x0p+0, 0x0p+0 }; =20 +/* Get sp base adjustment. */ + +unsigned int +riscv_get_sp_base (insn_t opcode, unsigned int xlen) +{ + unsigned reg_size =3D xlen / 8; + unsigned reg_list =3D EXTRACT_BITS (opcode, OP_MASK_REG_LIST, OP_SH_REG_= LIST); + unsigned min_sp_adj =3D (reg_list - 3) * reg_size + + (reg_list =3D=3D 15 ? reg_size : 0); + return (((min_sp_adj / ZCMP_SP_ALIGNMENT) + + (min_sp_adj % ZCMP_SP_ALIGNMENT !=3D 0)) + * ZCMP_SP_ALIGNMENT); +} + #define MASK_RS1 (OP_MASK_RS1 << OP_SH_RS1) #define MASK_RS2 (OP_MASK_RS2 << OP_SH_RS2) #define MASK_RD (OP_MASK_RD << OP_SH_RD) @@ -2068,6 +2082,12 @@ const struct riscv_opcode riscv_opcodes[] =3D {"c.zext.b", 0, INSN_CLASS_ZCB, "Cs", MATCH_C_ZEXT_B, MASK_C_ZEXT_B, ma= tch_opcode, 0 }, {"c.sext.w", 64, INSN_CLASS_ZCB, "d", MATCH_C_ADDIW, MASK_C_ADDIW|MASK_R= VC_IMM, match_rd_nonzero, INSN_ALIAS }, =20 +/* Zcmp instructions. */ +{"cm.push", 0, INSN_CLASS_ZCMP, "{Wcr},Wcp", MATCH_CM_PUSH, MASK_CM_P= USH, match_opcode, 0 }, +{"cm.pop", 0, INSN_CLASS_ZCMP, "{Wcr},Wcp", MATCH_CM_POP, MASK_CM_PO= P, match_opcode, 0 }, +{"cm.popret", 0, INSN_CLASS_ZCMP, "{Wcr},Wcp", MATCH_CM_POPRET, MASK_CM= _POPRET, match_opcode, 0 }, +{"cm.popretz", 0, INSN_CLASS_ZCMP, "{Wcr},Wcp", MATCH_CM_POPRETZ, MASK_C= M_POPRETZ, match_opcode, 0 }, + /* Supervisor instructions. */ {"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_= RS1, match_opcode, INSN_ALIAS }, {"csrwi", 0, INSN_CLASS_ZICSR, "E,Z", MATCH_CSRRWI, MASK_CSRRWI|MAS= K_RD, match_opcode, INSN_ALIAS },