From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7810) id 808AC385842C; Tue, 9 Apr 2024 10:00:54 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 808AC385842C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1712656854; bh=4etBZeUGtZC/lBaoLk13mNCj98eNnN/XFqzD3id0ujw=; h=From:To:Subject:Date:From; b=oz/ItbIHNxrdUF0fNJdoUJpp8P9hY30rGC8+7icEiNEf7Y1Qp9/WNCsuw/nGWHt3Z P9UmSx35JSzaiU8DUEBPjCM6OSqyLx2H3GgL0GBK9/fwvXWKCZ43Z60AU91Sii0LJ0 AZt/AEED6WNOosdZ2yJrzFMOWMaUuun/KmKWNvYQ= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Alex Coplan To: binutils-cvs@sourceware.org Subject: [binutils-gdb] arm: Fix encoding of MVE vqshr[u]n X-Act-Checkin: binutils-gdb X-Git-Author: Alex Coplan X-Git-Refname: refs/heads/master X-Git-Oldrev: f9d6cf2e9f885a1504b459cf437dd9d1931b1168 X-Git-Newrev: b3a561abc3040264aa0c60a8082e2433b0ca38a1 Message-Id: <20240409100054.808AC385842C@sourceware.org> Date: Tue, 9 Apr 2024 10:00:54 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3Db3a561abc304= 0264aa0c60a8082e2433b0ca38a1 commit b3a561abc3040264aa0c60a8082e2433b0ca38a1 Author: Alex Coplan Date: Tue Apr 2 13:42:13 2024 +0100 arm: Fix encoding of MVE vqshr[u]n =20 As it stands, these insns are incorrectly encoded as vqrshr[u]n. Concretely, the problem can be seen as follows: =20 $=C2=A0cat t.s vqrshrnb.s16 q0,q0,#8 vqshrnb.s16 q0,q0,#8 $ gas/as-new t.s -march=3Darmv8.1-m.main+mve -o t.o $ binutils/objdump -d t.o -m armv8.1-m.main =20 t.o: file format elf32-littlearm =20 Disassembly of section .text: =20 00000000 <.text>: 0: ee88 0f41 vqrshrnb.s16 q0, q0, #0 4: ee88 0f41 vqrshrnb.s16 q0, q0, #0 =20 Here we assemble these two instructions to the same opcode. The encoding of the first is the correct, while the encoding of the second is incorrect, and the bottom bit should be clear, see the Armv8-M ARM: https://developer.arm.com/documentation/ddi0553/latest/ =20 There is an additional problem here in that the disassembly of the immediate is incorrect. llvm-objdump shows the correct disassembly here: =20 t.o: file format elf32-littlearm =20 Disassembly of section .text: =20 00000000 <$t>: 0: ee88 0f41 vqrshrnb.s16 q0, q0, #8 4: ee88 0f41 vqrshrnb.s16 q0, q0, #8 =20 Note that we defer adding a test for the correct encoding of these insns until the next patch which fixes the disassembly issue. Diff: --- gas/config/tc-arm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 3bbb75c169a..89c85745adc 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -26621,10 +26621,10 @@ static const struct asm_opcode insns[] =3D mCEF(vshrnb, _vshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn), mCEF(vrshrnt, _vrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn), mCEF(vrshrnb, _vrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn), - mCEF(vqshrnt, _vqrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn), - mCEF(vqshrnb, _vqrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn), - mCEF(vqshrunt, _vqrshrunt, 3, (RMQ, RMQ, I32z), mve_vshrn), - mCEF(vqshrunb, _vqrshrunb, 3, (RMQ, RMQ, I32z), mve_vshrn), + mCEF(vqshrnt, _vqshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn), + mCEF(vqshrnb, _vqshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn), + mCEF(vqshrunt, _vqshrunt, 3, (RMQ, RMQ, I32z), mve_vshrn), + mCEF(vqshrunb, _vqshrunb, 3, (RMQ, RMQ, I32z), mve_vshrn), mCEF(vqrshrnt, _vqrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn), mCEF(vqrshrnb, _vqrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn), mCEF(vqrshrunt, _vqrshrunt, 3, (RMQ, RMQ, I32z), mve_vshrn),