* [binutils-gdb] RISC-V: Add support for Zvfbfmin extension
@ 2024-06-06 8:14 Nelson Chu
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From: Nelson Chu @ 2024-06-06 8:14 UTC (permalink / raw)
To: binutils-cvs
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=d9c14a8744b01b0d3d03a661c732a4d4d5740fbc
commit d9c14a8744b01b0d3d03a661c732a4d4d5740fbc
Author: Xiao Zeng <zengxiao@eswincomputing.com>
Date: Thu Jun 6 15:59:52 2024 +0800
RISC-V: Add support for Zvfbfmin extension
This implements the Zvfbfmin extension, as of version 1.0.
View detailed information in:
<https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zvfbfmin---vector-bf16-converts>
Depending on different usage scenarios, the Zvfbfmin extension may
depend on 'V' or 'Zve32f'. This patch only implements dependencies
in scenario of Embedded Processor. In scenario of Application
Processor, it is necessary to explicitly indicate the dependent
'V' extension.
For relevant information in gcc, please refer to:
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=1ddf65c5fc6ba7cf5826e1c02c569c923a541c09>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Handle Zvfbfmin.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* NEWS: Updated.
* testsuite/gas/riscv/march-help.l: Ditto.
* testsuite/gas/riscv/zvfbfmin.d: New test.
* testsuite/gas/riscv/zvfbfmin.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VFNCVTBF16_F_F_W): Define.
(MASK_VFNCVTBF16_F_F_W): Ditto.
(MATCH_VFWCVTBF16_F_F_V): Ditto.
(MASK_VFWCVTBF16_F_F_V): Ditto.
(DECLARE_INSN): New declarations for Zvfbfmin.
* opcode/riscv.h (enum riscv_insn_class): Add
INSN_CLASS_ZVFBFMIN
opcodes/ChangeLog:
* riscv-opc.c: Add Zvfbfmin instructions.
Diff:
---
bfd/elfxx-riscv.c | 6 ++++++
gas/NEWS | 2 ++
gas/testsuite/gas/riscv/march-help.l | 1 +
gas/testsuite/gas/riscv/zvfbfmin.d | 12 ++++++++++++
gas/testsuite/gas/riscv/zvfbfmin.s | 7 +++++++
include/opcode/riscv-opc.h | 8 ++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 4 ++++
8 files changed, 41 insertions(+)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 1d70139725a..0131ce85477 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1192,6 +1192,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"v", "zve64d", check_implicit_always},
{"v", "zvl128b", check_implicit_always},
{"zabha", "a", check_implicit_always},
+ {"zvfbfmin", "zve32f", check_implicit_always},
{"zvfh", "zvfhmin", check_implicit_always},
{"zvfh", "zfhmin", check_implicit_always},
{"zvfhmin", "zve32f", check_implicit_always},
@@ -1393,6 +1394,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zve64d", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvfbfmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2647,6 +2649,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "zvbb");
case INSN_CLASS_ZVBC:
return riscv_subset_supports (rps, "zvbc");
+ case INSN_CLASS_ZVFBFMIN:
+ return riscv_subset_supports (rps, "zvfbfmin");
case INSN_CLASS_ZVKB:
return riscv_subset_supports (rps, "zvkb");
case INSN_CLASS_ZVKG:
@@ -2917,6 +2921,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("zvbb");
case INSN_CLASS_ZVBC:
return _("zvbc");
+ case INSN_CLASS_ZVFBFMIN:
+ return "zvfbfmin";
case INSN_CLASS_ZVKB:
return _("zvkb");
case INSN_CLASS_ZVKG:
diff --git a/gas/NEWS b/gas/NEWS
index cdf30941894..a668a521772 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -23,6 +23,8 @@
* Add support for RISC-V Zfbfmin extension with version 1.0.
+* Add support for RISC-V Zvfbfmin extension with version 1.0.
+
* The base register operand in D(X,B) and D(L,B) may be explicitly omitted
in assembly on s390. It can now be coded as D(X,) or D(L,) instead of D(X,0)
D(X,%r0), D(L,0), and D(L,%r0).
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index 57c73b3074e..38c70e269bf 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -58,6 +58,7 @@ All available -march extensions for RISC-V:
zve64d 1.0
zvbb 1.0
zvbc 1.0
+ zvfbfmin 1.0
zvfh 1.0
zvfhmin 1.0
zvkb 1.0
diff --git a/gas/testsuite/gas/riscv/zvfbfmin.d b/gas/testsuite/gas/riscv/zvfbfmin.d
new file mode 100644
index 00000000000..ce973812fe1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvfbfmin.d
@@ -0,0 +1,12 @@
+#as: -march=rv64iv_zvfbfmin
+#objdump: -d
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+4a8e9257[ ]+vfncvtbf16.f.f.w[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+488e9257[ ]+vfncvtbf16.f.f.w[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+4a869257[ ]+vfwcvtbf16.f.f.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+48869257[ ]+vfwcvtbf16.f.f.v[ ]+v4,v8,v0.t
diff --git a/gas/testsuite/gas/riscv/zvfbfmin.s b/gas/testsuite/gas/riscv/zvfbfmin.s
new file mode 100644
index 00000000000..9a4493d84d1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvfbfmin.s
@@ -0,0 +1,7 @@
+target:
+ # vfncvtbf16.f.f.w
+ vfncvtbf16.f.f.w v4, v8
+ vfncvtbf16.f.f.w v4, v8, v0.t
+ # vfwcvtbf16.f.f.v
+ vfwcvtbf16.f.f.v v4, v8
+ vfwcvtbf16.f.f.v v4, v8, v0.t
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index ef33aeb1b36..c5270d017b2 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2370,6 +2370,11 @@
#define MASK_FCVT_BF16_S 0xfff0007f
#define MATCH_FCVT_S_BF16 0x40600053
#define MASK_FCVT_S_BF16 0xfff0007f
+/* Zvfbfmin intructions. */
+#define MATCH_VFNCVTBF16_F_F_W 0x480e9057
+#define MASK_VFNCVTBF16_F_F_W 0xfc0ff07f
+#define MATCH_VFWCVTBF16_F_F_V 0x48069057
+#define MASK_VFWCVTBF16_F_F_V 0xfc0ff07f
/* Vendor-specific (CORE-V) Xcvmac instructions. */
#define MATCH_CV_MAC 0x9000302b
#define MASK_CV_MAC 0xfe00707f
@@ -3977,6 +3982,9 @@ DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
/* Zfbfmin instructions. */
DECLARE_INSN(FCVT_BF16_S, MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S)
DECLARE_INSN(FCVT_S_BF16, MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16)
+/* Zvfbfmin instructions. */
+DECLARE_INSN(VFNCVTBF16_F_F_W, MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W)
+DECLARE_INSN(VFWCVTBF16_F_F_V, MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V)
/* Zvbb/Zvkb instructions. */
DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV)
DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index dfb86966b0a..06415634c7f 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -474,6 +474,7 @@ enum riscv_insn_class
INSN_CLASS_ZVEF,
INSN_CLASS_ZVBB,
INSN_CLASS_ZVBC,
+ INSN_CLASS_ZVFBFMIN,
INSN_CLASS_ZVKB,
INSN_CLASS_ZVKG,
INSN_CLASS_ZVKNED,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 1ccf0685b2b..eccd3f6fae1 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2017,6 +2017,10 @@ const struct riscv_opcode riscv_opcodes[] =
{"vmv4r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV4RV, MASK_VMV4RV, match_opcode, 0},
{"vmv8r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV8RV, MASK_VMV8RV, match_opcode, 0},
+/* Zvfbfmin instructions. */
+{"vfncvtbf16.f.f.w", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm", MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W, match_opcode, 0},
+{"vfwcvtbf16.f.f.v", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm", MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V, match_opcode, 0},
+
/* Zvbb/Zvkb instructions. */
{"vandn.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VANDN_VV, MASK_VANDN_VV, match_opcode, 0},
{"vandn.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VANDN_VX, MASK_VANDN_VX, match_opcode, 0},
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