From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1256) id A52BF3858D29; Tue, 11 Jun 2024 08:40:00 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A52BF3858D29 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1718095200; bh=txKEx+yvgm9oZSzRWJCv8vn+ZCV1wh8MRHFGQzfKmdI=; h=From:To:Subject:Date:From; b=x+vxtqos00O0VP40lD8yobzz2im2GZAm+8UllE5mt4mhOGGPsS6wCMvoSG9Jyz7Bk 40lOBZjxaMO4PVIIvKFYiGr0w8UC4WarCfyO0cwhnXM2HDpvdxAZteULXnD7bxS22U GXIiSLYChrg61c9vyoVt0UoIYQ3+se0We3cQY48A= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Maciej W. Rozycki To: binutils-cvs@sourceware.org Subject: [binutils-gdb] MIPS/opcodes: Exclude trap instructions for MIPS Allegrex X-Act-Checkin: binutils-gdb X-Git-Author: David Guillen Fandos X-Git-Refname: refs/heads/master X-Git-Oldrev: b20ab53f81db7eefa0db00d14f06c04527ac324c X-Git-Newrev: 1ded0d12e0ee5399a3c1d8606fd23491e00fc60f Message-Id: <20240611084000.A52BF3858D29@sourceware.org> Date: Tue, 11 Jun 2024 08:40:00 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D1ded0d12e0ee= 5399a3c1d8606fd23491e00fc60f commit 1ded0d12e0ee5399a3c1d8606fd23491e00fc60f Author: David Guillen Fandos Date: Tue Jun 11 09:36:11 2024 +0100 MIPS/opcodes: Exclude trap instructions for MIPS Allegrex =20 These instructions are not supported by the target even though they are part of the MIPS II specification. Diff: --- gas/testsuite/gas/mips/allegrex-removed.d | 3 ++ gas/testsuite/gas/mips/allegrex-removed.l | 13 +++++++ gas/testsuite/gas/mips/allegrex-removed.s | 13 +++++++ gas/testsuite/gas/mips/mips.exp | 1 + opcodes/mips-opc.c | 60 +++++++++++++++------------= ---- 5 files changed, 60 insertions(+), 30 deletions(-) diff --git a/gas/testsuite/gas/mips/allegrex-removed.d b/gas/testsuite/gas/= mips/allegrex-removed.d new file mode 100644 index 00000000000..d94db493719 --- /dev/null +++ b/gas/testsuite/gas/mips/allegrex-removed.d @@ -0,0 +1,3 @@ +#name: MIPS Sony Allegrex CPU removed opcode tests +#as: -march=3Dallegrex -mabi=3D32 +#error_output: allegrex-removed.l diff --git a/gas/testsuite/gas/mips/allegrex-removed.l b/gas/testsuite/gas/= mips/allegrex-removed.l new file mode 100644 index 00000000000..a77d4df2f12 --- /dev/null +++ b/gas/testsuite/gas/mips/allegrex-removed.l @@ -0,0 +1,13 @@ +.*: Assembler messages: +.*:2: Error: opcode not supported on this processor: .* \(.*\) `teqi \$11,= 1024' +.*:3: Error: opcode not supported on this processor: .* \(.*\) `tgei \$11,= 1024' +.*:4: Error: opcode not supported on this processor: .* \(.*\) `tgeiu \$11= ,1024' +.*:5: Error: opcode not supported on this processor: .* \(.*\) `tlti \$11,= 1024' +.*:6: Error: opcode not supported on this processor: .* \(.*\) `tltiu \$11= ,1024' +.*:7: Error: opcode not supported on this processor: .* \(.*\) `tnei \$11,= 1024' +.*:8: Error: opcode not supported on this processor: .* \(.*\) `teq \$1,\$= 2' +.*:9: Error: opcode not supported on this processor: .* \(.*\) `tge \$1,\$= 2' +.*:10: Error: opcode not supported on this processor: .* \(.*\) `tgeu \$1,= \$2' +.*:11: Error: opcode not supported on this processor: .* \(.*\) `tlt \$1,\= $2' +.*:12: Error: opcode not supported on this processor: .* \(.*\) `tltu \$1,= \$2' +.*:13: Error: opcode not supported on this processor: .* \(.*\) `tne \$1,\= $2' diff --git a/gas/testsuite/gas/mips/allegrex-removed.s b/gas/testsuite/gas/= mips/allegrex-removed.s new file mode 100644 index 00000000000..8dac8a1fcaf --- /dev/null +++ b/gas/testsuite/gas/mips/allegrex-removed.s @@ -0,0 +1,13 @@ + .set noreorder + teqi $11,1024 + tgei $11,1024 + tgeiu $11,1024 + tlti $11,1024 + tltiu $11,1024 + tnei $11,1024 + teq $1,$2 + tge $1,$2 + tgeu $1,$2 + tlt $1,$2 + tltu $1,$2 + tne $1,$2 diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.= exp index 2ddbf0c768d..acb7fb8c2a6 100644 --- a/gas/testsuite/gas/mips/mips.exp +++ b/gas/testsuite/gas/mips/mips.exp @@ -1633,6 +1633,7 @@ if { [istarget mips*-*-vxworks*] } { run_list_test "r5900-error-vu0" "-march=3Dr5900" =20 run_dump_test "allegrex" + run_dump_test "allegrex-removed" =20 run_list_test_arches "ext-ill" [mips_arch_list_matching mips64r2] =20 diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index dca5eda47ae..a31a17d4b9a 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -2028,21 +2028,21 @@ const struct mips_opcode mips_builtin_opcodes[] =3D {"synci", "o(b)", 0x041f0000, 0xfc1f0000, RD_2|SM, 0, I33, 0, 0 }, {"syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1, 0, 0 }, {"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1, 0, 0 }, -{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, -{"teq", "s,t", 0x00000034, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 = }, -{"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /= * teqi */ -{"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I2, 0, 0 }, -{"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, -{"tge", "s,t", 0x00000030, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 = }, -{"tge", "s,j", 0x04080000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /= * tgei */ -{"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I2, 0, 0 }, -{"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, -{"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 = }, -{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /= * tgeiu */ -{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I2, 0, 0 }, +{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, +{"teq", "s,t", 0x00000034, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, AL = }, +{"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, AL= }, +{"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }= , /* teqi */ +{"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I2, 0, AL }, +{"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, +{"tge", "s,t", 0x00000030, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, AL = }, +{"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, AL= }, +{"tge", "s,j", 0x04080000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }= , /* tgei */ +{"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I2, 0, AL }, +{"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL = }, +{"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, AL = }, +{"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, AL= }, +{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }= , /* tgeiu */ +{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I2, 0, AL }, {"tlbinv", "", 0x42000003, 0xffffffff, INSN_TLB, 0, I37, TLBINV= , 0 }, {"tlbinvf", "", 0x42000004, 0xffffffff, INSN_TLB, 0, I37, TLBIN= V, 0 }, {"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, 0, I1, 0, 0 }, @@ -2055,21 +2055,21 @@ const struct mips_opcode mips_builtin_opcodes[] =3D {"tlbginvf", "", 0x4200000c, 0xffffffff, INSN_TLB, 0, 0, IVIRT,= 0 }, {"tlbgwr", "", 0x4200000e, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0= }, {"tlbgp", "", 0x42000010, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 = }, -{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, -{"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 = }, -{"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /= * tlti */ -{"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I2, 0, 0 }, -{"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, -{"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 = }, -{"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /= * tltiu */ -{"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I2, 0, 0 }, -{"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, -{"tne", "s,t", 0x00000036, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 = }, -{"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /= * tnei */ -{"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I2, 0, 0 }, +{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, +{"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, AL = }, +{"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, AL= }, +{"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }= , /* tlti */ +{"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I2, 0, AL }, +{"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL = }, +{"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, AL = }, +{"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, AL= }, +{"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }= , /* tltiu */ +{"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I2, 0, AL }, +{"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }, +{"tne", "s,t", 0x00000036, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, AL = }, +{"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, AL= }, +{"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37|AL }= , /* tnei */ +{"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I2, 0, AL }, {"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33,= 0, 0 }, {"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3= _33, 0, 0 }, {"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I2= , 0, SF },