From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1256) id 0C6D43882060; Thu, 13 Jun 2024 13:03:26 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 0C6D43882060 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1718283807; bh=KiZLlVovN1KEtQmIoBfq3+VLSXHWNykhN6s7SHtDd/I=; h=From:To:Subject:Date:From; b=fVvv4VD18aVZCp1vacc07ATo0yQaG1mWskvElcQ6hgz1Sk/xPFwTHq3ZPSjST/ycD e2nWrjIhOf2VOL1B4m7pC8wpTBw/axrYWU6TQ4RMhRQWaTmtjDu+TELDSUq87BZOmB nP37yqundBuEmVyXZ2ackg//+e6nL/VohPpb3A6Y= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Maciej W. Rozycki To: binutils-cvs@sourceware.org Subject: [binutils-gdb] MIPS/opcodes: Rework INSN_* flags into a consistent block X-Act-Checkin: binutils-gdb X-Git-Author: Maciej W. Rozycki X-Git-Refname: refs/heads/master X-Git-Oldrev: 84baa5fe937543578159de698cbb8c5f2e7a57c6 X-Git-Newrev: 888ff82e77d9ab8f04893a68cd6b4f518d6b50d9 Message-Id: <20240613130327.0C6D43882060@sourceware.org> Date: Thu, 13 Jun 2024 13:03:26 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D888ff82e77d9= ab8f04893a68cd6b4f518d6b50d9 commit 888ff82e77d9ab8f04893a68cd6b4f518d6b50d9 Author: Maciej W. Rozycki Date: Thu Jun 13 14:01:54 2024 +0100 MIPS/opcodes: Rework INSN_* flags into a consistent block =20 For historic reasons we have ended up with a random set of discontiguous bit assignments for INSN_* flags within `membership' and `exclusions' members of `mips_opcode'. Some of the bits were previously used for ASE assignments and have been reused in a disorganised fashion since `ase' has been split off as a member on its own. It makes them hard to track and maintain, and to see how many we still have available for future assignments. =20 Therefore reorder the flags using consecutive bits and matching the order used with the switch statement in `cpu_is_member'. Diff: --- include/opcode/mips.h | 53 ++++++++++++++++++++++++-----------------------= ---- 1 file changed, 25 insertions(+), 28 deletions(-) diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 39c20a80123..3ef74eb623a 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -1142,7 +1142,7 @@ mips_opcode_32bit_p (const struct mips_opcode *mo) they were introduced in. INSN_ISA_MASK masks an enumeration that specifies the base ISA level(s). The remainder of a 32-bit word constructed using these macros is a bitmask of the remaining - INSN_* values below. */ + INSN_* values below, as indicated by INSN_CHIP_MASK. */ =20 #define INSN_ISA_MASK 0x0000001ful =20 @@ -1225,48 +1225,45 @@ static const unsigned int mips_isa_table[] =3D { #undef ISAF =20 /* Masks used for Chip specific instructions. */ -#define INSN_CHIP_MASK 0xcfff4f60 - -/* Cavium Networks Octeon instructions. */ -#define INSN_OCTEON 0x00000800 -#define INSN_OCTEONP 0x00000200 -#define INSN_OCTEON2 0x00000100 -#define INSN_OCTEON3 0x00000040 - -/* MIPS R5900 instruction */ -#define INSN_5900 0x00004000 +#define INSN_CHIP_MASK 0x01ffffe0 =20 /* MIPS R4650 instruction. */ -#define INSN_4650 0x00010000 +#define INSN_4650 0x00000020 /* LSI R4010 instruction. */ -#define INSN_4010 0x00020000 +#define INSN_4010 0x00000040 /* NEC VR4100 instruction. */ -#define INSN_4100 0x00040000 +#define INSN_4100 0x00000080 /* Toshiba R3900 instruction. */ -#define INSN_3900 0x00080000 +#define INSN_3900 0x00000100 /* MIPS R10000 instruction. */ -#define INSN_10000 0x00100000 +#define INSN_10000 0x00000200 /* Broadcom SB-1 instruction. */ -#define INSN_SB1 0x00200000 +#define INSN_SB1 0x00000400 /* NEC VR4111/VR4181 instruction. */ -#define INSN_4111 0x00400000 +#define INSN_4111 0x00000800 /* NEC VR4120 instruction. */ -#define INSN_4120 0x00800000 +#define INSN_4120 0x00001000 /* NEC VR5400 instruction. */ -#define INSN_5400 0x01000000 +#define INSN_5400 0x00002000 /* NEC VR5500 instruction. */ -#define INSN_5500 0x02000000 - +#define INSN_5500 0x00004000 +/* MIPS R5900 instruction. */ +#define INSN_5900 0x00008000 /* ST Microelectronics Loongson 2E. */ -#define INSN_LOONGSON_2E 0x40000000 +#define INSN_LOONGSON_2E 0x00010000 /* ST Microelectronics Loongson 2F. */ -#define INSN_LOONGSON_2F 0x80000000 -/* RMI Xlr instruction */ -#define INSN_XLR 0x00000020 +#define INSN_LOONGSON_2F 0x00020000 +/* Cavium Networks Octeon instructions. */ +#define INSN_OCTEON 0x00040000 +#define INSN_OCTEONP 0x00080000 +#define INSN_OCTEON2 0x00100000 +#define INSN_OCTEON3 0x00200000 +/* RMI XLR instruction. */ +#define INSN_XLR 0x00400000 /* Imagination interAptiv MR2. */ -#define INSN_INTERAPTIV_MR2 0x04000000 +#define INSN_INTERAPTIV_MR2 0x00800000 /* Sony PSP Allegrex instruction. */ -#define INSN_ALLEGREX 0x08000000 +#define INSN_ALLEGREX 0x01000000 =20 /* DSP ASE */ #define ASE_DSP 0x00000001