* [binutils-gdb] aarch64: Add SME FP8 multiplication instructions
@ 2024-06-24 15:51 Richard Earnshaw
0 siblings, 0 replies; only message in thread
From: Richard Earnshaw @ 2024-06-24 15:51 UTC (permalink / raw)
To: binutils-cvs
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=a6e529673a95670a9c3046c3681fe6864b2cd05c
commit a6e529673a95670a9c3046c3681fe6864b2cd05c
Author: Andrew Carlotti <andrew.carlotti@arm.com>
Date: Fri Jun 21 19:32:31 2024 +0100
aarch64: Add SME FP8 multiplication instructions
This includes:
- FEAT_SME_F8F32 (+sme-f8f32)
- FEAT_SME_F8F16 (+sme-f8f16)
The FP16 addition/subtraction instructions originally added by
FEAT_SME_F16F16 haven't been added to Binutils yet. They are also
required to be enabled if FEAT_SME_F8F16 is present, so they are
included in this patch.
Diff:
---
gas/config/tc-aarch64.c | 11 +
gas/doc/c-aarch64.texi | 4 +
gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.d | 2 +
gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.l | 87 +
gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.s | 100 +
gas/testsuite/gas/aarch64/fp8-sme-dot2.d | 50 +
gas/testsuite/gas/aarch64/fp8-sme-dot2.s | 47 +
gas/testsuite/gas/aarch64/fp8-sme-dot4.d | 55 +
gas/testsuite/gas/aarch64/fp8-sme-dot4.s | 53 +
gas/testsuite/gas/aarch64/fp8-sme-fmlal-illegal.d | 2 +
gas/testsuite/gas/aarch64/fp8-sme-fmlal-illegal.l | 72 +
gas/testsuite/gas/aarch64/fp8-sme-fmlal-illegal.s | 78 +
gas/testsuite/gas/aarch64/fp8-sme-fmlal.d | 57 +
gas/testsuite/gas/aarch64/fp8-sme-fmlal.s | 56 +
gas/testsuite/gas/aarch64/fp8-sme-fmlall-illegal.d | 2 +
gas/testsuite/gas/aarch64/fp8-sme-fmlall-illegal.l | 72 +
gas/testsuite/gas/aarch64/fp8-sme-fmlall-illegal.s | 78 +
gas/testsuite/gas/aarch64/fp8-sme-fmlall.d | 57 +
gas/testsuite/gas/aarch64/fp8-sme-fmlall.s | 56 +
gas/testsuite/gas/aarch64/fp8-sme-mopa-illegal.d | 2 +
gas/testsuite/gas/aarch64/fp8-sme-mopa-illegal.l | 7 +
gas/testsuite/gas/aarch64/fp8-sme-mopa-illegal.s | 7 +
gas/testsuite/gas/aarch64/fp8-sme-mopa2.d | 15 +
gas/testsuite/gas/aarch64/fp8-sme-mopa2.s | 6 +
gas/testsuite/gas/aarch64/fp8-sme-mopa4.d | 15 +
gas/testsuite/gas/aarch64/fp8-sme-mopa4.s | 6 +
.../gas/aarch64/sme-fp16-addsub-illegal.d | 2 +
.../gas/aarch64/sme-fp16-addsub-illegal.l | 19 +
.../gas/aarch64/sme-fp16-addsub-illegal.s | 24 +
gas/testsuite/gas/aarch64/sme-fp16-addsub.d | 25 +
gas/testsuite/gas/aarch64/sme-fp16-addsub.s | 19 +
gas/testsuite/gas/aarch64/sme2-18-invalid.l | 2 +-
gas/testsuite/gas/aarch64/sme2-9-invalid.l | 6 +-
include/opcode/aarch64.h | 11 +
opcodes/aarch64-asm-2.c | 75 +-
opcodes/aarch64-dis-2.c | 2010 ++++++++++++--------
opcodes/aarch64-opc-2.c | 5 +
opcodes/aarch64-opc.c | 12 +
opcodes/aarch64-opc.h | 3 +
opcodes/aarch64-tbl.h | 74 +
40 files changed, 2444 insertions(+), 840 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 88e0e6e1926..cbae27f2a43 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -6869,10 +6869,14 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SVE_Zn_5_INDEX:
case AARCH64_OPND_SME_Zm_INDEX1:
case AARCH64_OPND_SME_Zm_INDEX2:
+ case AARCH64_OPND_SME_Zm_INDEX2_3:
case AARCH64_OPND_SME_Zm_INDEX3_1:
case AARCH64_OPND_SME_Zm_INDEX3_2:
+ case AARCH64_OPND_SME_Zm_INDEX3_3:
case AARCH64_OPND_SME_Zm_INDEX3_10:
case AARCH64_OPND_SME_Zm_INDEX4_1:
+ case AARCH64_OPND_SME_Zm_INDEX4_2:
+ case AARCH64_OPND_SME_Zm_INDEX4_3:
case AARCH64_OPND_SME_Zm_INDEX4_10:
case AARCH64_OPND_SME_Zn_INDEX1_16:
case AARCH64_OPND_SME_Zn_INDEX2_15:
@@ -8104,6 +8108,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
goto failure;
break;
+ case AARCH64_OPND_SME_ZAda_1b:
case AARCH64_OPND_SME_ZAda_2b:
case AARCH64_OPND_SME_ZAda_3b:
reg = parse_reg_with_qual (&str, REG_TYPE_ZAT, &qualifier, 0);
@@ -10698,6 +10703,10 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
AARCH64_FEATURE (SSVE_FP8FMA)},
{"ssve-fp8dot2", AARCH64_FEATURE (SSVE_FP8DOT2),
AARCH64_FEATURE (SSVE_FP8DOT4)},
+ {"sme-f8f32", AARCH64_FEATURE (SME_F8F32),
+ AARCH64_FEATURES (2, FP8, SME2)},
+ {"sme-f8f16", AARCH64_FEATURE (SME_F8F16),
+ AARCH64_FEATURE (SME_F8F32)},
{NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
};
@@ -10716,6 +10725,8 @@ static const struct aarch64_virtual_dependency_table aarch64_dependencies[] = {
{AARCH64_FEATURE (SSVE_FP8DOT4), AARCH64_FEATURE (FP8DOT4_SVE)},
{AARCH64_FEATURES (2, FP8DOT2, SVE2), AARCH64_FEATURE (FP8DOT2_SVE)},
{AARCH64_FEATURE (SSVE_FP8DOT2), AARCH64_FEATURE (FP8DOT2_SVE)},
+ /* TODO: Add SME_F16F16->SME_F16F16_F8F16 when SME_F16F16 is added. */
+ {AARCH64_FEATURE (SME_F8F16), AARCH64_FEATURE (SME_F16F16_F8F16)},
};
static aarch64_feature_set
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index a73b6c336a7..157c7b2f8a0 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -271,6 +271,10 @@ automatically cause those extensions to be disabled.
@tab Enable the SM3 and SM4 cryptographic extensions.
@item @code{sme} @tab @code{sve2}, @code{bf16}
@tab Enable the Scalable Matrix Extension.
+@item @code{sme-f8f16} @tab @code{sme-f8f32}
+ @tab Enable the SME F8F16 Extension.
+@item @code{sme-f8f32} @tab @code{sme2}, @code{fp8}
+ @tab Enable the SME F8F32 Extension.
@item @code{sme-f64f64} @tab @code{sme}
@tab Enable SME F64F64 Extension.
@item @code{sme-i16i64} @tab @code{sme}
diff --git a/gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.d b/gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.d
new file mode 100644
index 00000000000..58580167f66
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.d
@@ -0,0 +1,2 @@
+#as: -march=armv8-a+sme-f8f16
+#error_output: fp8-sme-dot-illegal.l
diff --git a/gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.l b/gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.l
new file mode 100644
index 00000000000..3444d738cdc
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.l
@@ -0,0 +1,87 @@
+[^:]*: Assembler messages:
+[^:]*:1: Error: z0-z15 expected at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z1\.b},z16\.b\[0\]'
+[^:]*:2: Error: start register out of range at operand 2 -- `fdot za\.s\[w8,0\],{z1\.b-z2\.b},z0\.b\[0\]'
+[^:]*:3: Error: expected a list of 2 registers at operand 2 -- `fdot za\.s\[w8,0,VGx2\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:4: Error: register element index out of range 0 to 3 at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b\[4\]'
+[^:]*:5: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.s\[w8,8\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:6: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w7,0\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:7: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w12,0\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:9: Error: z0-z15 expected at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z3\.b},z16\.b\[0\]'
+[^:]*:10: Error: start register out of range at operand 2 -- `fdot za\.s\[w8,0\],{z2\.b-z5\.b},z0\.b\[0\]'
+[^:]*:11: Error: expected a list of 4 registers at operand 2 -- `fdot za\.s\[w8,0,VGx4\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:12: Error: register element index out of range 0 to 3 at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b\[4\]'
+[^:]*:13: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.s\[w8,8\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:14: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w7,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:15: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w12,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:17: Error: z0-z15 expected at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z1\.b},z16\.b'
+[^:]*:18: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.s\[w8,8\],{z0\.b-z1\.b},z0\.b'
+[^:]*:19: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w7,0\],{z0\.b-z1\.b},z0\.b'
+[^:]*:20: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w12,0\],{z0\.b-z1\.b},z0\.b'
+[^:]*:21: Error: expected a list of 4 registers at operand 2 -- `fdot za\.s\[w8,0,VGx4\],{z0\.b-z1\.b},z0\.b'
+[^:]*:23: Error: z0-z15 expected at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z3\.b},z16\.b'
+[^:]*:24: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.s\[w8,8\],{z0\.b-z3\.b},z0\.b'
+[^:]*:25: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w7,0\],{z0\.b-z3\.b},z0\.b'
+[^:]*:26: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w12,0\],{z0\.b-z3\.b},z0\.b'
+[^:]*:27: Error: expected a list of 2 registers at operand 2 -- `fdot za\.s\[w8,0,VGx2\],{z0\.b-z3\.b},z0\.b'
+[^:]*:29: Error: expected a list of 2 registers at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z1\.b},{z0\.b-z3\.b}'
+[^:]*:30: Error: start register out of range at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z1\.b},{z1\.b-z2\.b}'
+[^:]*:31: Error: start register out of range at operand 2 -- `fdot za\.s\[w8,0\],{z1\.b-z2\.b},{z0\.b-z1\.b}'
+[^:]*:32: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w7,0\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^:]*:33: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.s\[w8,8\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^:]*:35: Error: expected a list of 4 registers at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z3\.b},{z0\.b-z1\.b}'
+[^:]*:36: Error: start register out of range at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z3\.b},{z2\.b-z5\.b}'
+[^:]*:37: Error: start register out of range at operand 2 -- `fdot za\.s\[w8,0\],{z2\.b-z5\.b},{z0\.b-z3\.b}'
+[^:]*:38: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w7,0\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^:]*:39: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.s\[w8,8\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^:]*:41: Error: z0-z15 expected at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z1\.b},z16\.b\[0\]'
+[^:]*:42: Error: start register out of range at operand 2 -- `fdot za\.h\[w8,0\],{z1\.b-z2\.b},z0\.b\[0\]'
+[^:]*:43: Error: expected a list of 2 registers at operand 2 -- `fdot za\.h\[w8,0,VGx2\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:44: Error: register element index out of range 0 to 7 at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z1\.b},z0\.b\[8\]'
+[^:]*:45: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.h\[w8,8\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:46: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w7,0\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:47: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w12,0\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:49: Error: z0-z15 expected at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z3\.b},z16\.b\[0\]'
+[^:]*:50: Error: start register out of range at operand 2 -- `fdot za\.h\[w8,0\],{z2\.b-z5\.b},z0\.b\[0\]'
+[^:]*:51: Error: expected a list of 4 registers at operand 2 -- `fdot za\.h\[w8,0,VGx4\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:52: Error: register element index out of range 0 to 7 at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z3\.b},z0\.b\[8\]'
+[^:]*:53: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.h\[w8,8\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:54: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w7,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:55: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w12,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:57: Error: z0-z15 expected at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z1\.b},z16\.b'
+[^:]*:58: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.h\[w8,8\],{z0\.b-z1\.b},z0\.b'
+[^:]*:59: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w7,0\],{z0\.b-z1\.b},z0\.b'
+[^:]*:60: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w12,0\],{z0\.b-z1\.b},z0\.b'
+[^:]*:61: Error: expected a list of 4 registers at operand 2 -- `fdot za\.h\[w8,0,VGx4\],{z0\.b-z1\.b},z0\.b'
+[^:]*:63: Error: z0-z15 expected at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z3\.b},z16\.b'
+[^:]*:64: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.h\[w8,8\],{z0\.b-z3\.b},z0\.b'
+[^:]*:65: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w7,0\],{z0\.b-z3\.b},z0\.b'
+[^:]*:66: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w12,0\],{z0\.b-z3\.b},z0\.b'
+[^:]*:67: Error: expected a list of 2 registers at operand 2 -- `fdot za\.h\[w8,0,VGx2\],{z0\.b-z3\.b},z0\.b'
+[^:]*:69: Error: expected a list of 2 registers at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z1\.b},{z0\.b-z3\.b}'
+[^:]*:70: Error: start register out of range at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z1\.b},{z1\.b-z2\.b}'
+[^:]*:71: Error: start register out of range at operand 2 -- `fdot za\.h\[w8,0\],{z1\.b-z2\.b},{z0\.b-z1\.b}'
+[^:]*:72: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w7,0\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^:]*:73: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.h\[w8,8\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^:]*:75: Error: expected a list of 4 registers at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z3\.b},{z0\.b-z1\.b}'
+[^:]*:76: Error: start register out of range at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z3\.b},{z2\.b-z5\.b}'
+[^:]*:77: Error: start register out of range at operand 2 -- `fdot za\.h\[w8,0\],{z2\.b-z5\.b},{z0\.b-z3\.b}'
+[^:]*:78: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w7,0\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^:]*:79: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.h\[w8,8\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^:]*:81: Error: expected a selection register in the range w8-w11 at operand 1 -- `fvdot za\.h\[w7,0\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:82: Error: expected a selection register in the range w8-w11 at operand 1 -- `fvdot za\.h\[w12,0\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:83: Error: immediate offset out of range 0 to 7 at operand 1 -- `fvdot za\.h\[w8,8\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:84: Error: start register out of range at operand 2 -- `fvdot za\.h\[w8,0\],{z1\.b-z2\.b},z0\.b\[0\]'
+[^:]*:85: Error: z0-z15 expected at operand 3 -- `fvdot za\.h\[w8,0\],{z0\.b-z1\.b},z16\.b\[0\]'
+[^:]*:86: Error: register element index out of range 0 to 7 at operand 3 -- `fvdot za\.h\[w8,0\],{z0\.b-z1\.b},z0\.b\[8\]'
+[^:]*:88: Error: expected a selection register in the range w8-w11 at operand 1 -- `fvdotb za\.s\[w7,0\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:89: Error: expected a selection register in the range w8-w11 at operand 1 -- `fvdotb za\.s\[w12,0\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:90: Error: immediate offset out of range 0 to 7 at operand 1 -- `fvdotb za\.s\[w8,8\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:91: Error: start register out of range at operand 2 -- `fvdotb za\.s\[w8,0\],{z1\.b-z2\.b},z0\.b\[0\]'
+[^:]*:92: Error: z0-z15 expected at operand 3 -- `fvdotb za\.s\[w8,0\],{z0\.b-z1\.b},z16\.b\[0\]'
+[^:]*:93: Error: register element index out of range 0 to 3 at operand 3 -- `fvdotb za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b\[4\]'
+[^:]*:95: Error: expected a selection register in the range w8-w11 at operand 1 -- `fvdott za\.s\[w7,0\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:96: Error: expected a selection register in the range w8-w11 at operand 1 -- `fvdott za\.s\[w12,0\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:97: Error: immediate offset out of range 0 to 7 at operand 1 -- `fvdott za\.s\[w8,8\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:98: Error: start register out of range at operand 2 -- `fvdott za\.s\[w8,0\],{z1\.b-z2\.b},z0\.b\[0\]'
+[^:]*:99: Error: z0-z15 expected at operand 3 -- `fvdott za\.s\[w8,0\],{z0\.b-z1\.b},z16\.b\[0\]'
+[^:]*:100: Error: register element index out of range 0 to 3 at operand 3 -- `fvdott za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b\[4\]'
diff --git a/gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.s b/gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.s
new file mode 100644
index 00000000000..508bd79e538
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.s
@@ -0,0 +1,100 @@
+fdot za.s[w8, 0], { z0.b-z1.b }, z16.b[0]
+fdot za.s[w8, 0], { z1.b-z2.b }, z0.b[0]
+fdot za.s[w8, 0, VGx2], { z0.b-z3.b }, z0.b[0]
+fdot za.s[w8, 0], { z0.b-z1.b }, z0.b[4]
+fdot za.s[w8, 8], { z0.b-z1.b }, z0.b[0]
+fdot za.s[w7, 0], { z0.b-z1.b }, z0.b[0]
+fdot za.s[w12, 0], { z0.b-z1.b }, z0.b[0]
+
+fdot za.s[w8, 0], { z0.b-z3.b }, z16.b[0]
+fdot za.s[w8, 0], { z2.b-z5.b }, z0.b[0]
+fdot za.s[w8, 0, VGx4], { z0.b-z1.b }, z0.b[0]
+fdot za.s[w8, 0], { z0.b-z3.b }, z0.b[4]
+fdot za.s[w8, 8], { z0.b-z3.b }, z0.b[0]
+fdot za.s[w7, 0], { z0.b-z3.b }, z0.b[0]
+fdot za.s[w12, 0], { z0.b-z3.b }, z0.b[0]
+
+fdot za.s[w8, 0], { z0.b-z1.b }, z16.b
+fdot za.s[w8, 8], { z0.b-z1.b }, z0.b
+fdot za.s[w7, 0], { z0.b-z1.b }, z0.b
+fdot za.s[w12, 0], { z0.b-z1.b }, z0.b
+fdot za.s[w8, 0, VGx4], { z0.b-z1.b }, z0.b
+
+fdot za.s[w8, 0], { z0.b-z3.b }, z16.b
+fdot za.s[w8, 8], { z0.b-z3.b }, z0.b
+fdot za.s[w7, 0], { z0.b-z3.b }, z0.b
+fdot za.s[w12, 0], { z0.b-z3.b }, z0.b
+fdot za.s[w8, 0, VGx2], { z0.b-z3.b }, z0.b
+
+fdot za.s[w8, 0], { z0.b-z1.b }, { z0.b-z3.b}
+fdot za.s[w8, 0], { z0.b-z1.b }, { z1.b-z2.b}
+fdot za.s[w8, 0], { z1.b-z2.b }, { z0.b-z1.b}
+fdot za.s[w7, 0], { z0.b-z1.b }, { z0.b-z1.b}
+fdot za.s[w8, 8], { z0.b-z1.b }, { z0.b-z1.b}
+
+fdot za.s[w8, 0], { z0.b-z3.b }, { z0.b-z1.b}
+fdot za.s[w8, 0], { z0.b-z3.b }, { z2.b-z5.b}
+fdot za.s[w8, 0], { z2.b-z5.b }, { z0.b-z3.b}
+fdot za.s[w7, 0], { z0.b-z3.b }, { z0.b-z3.b}
+fdot za.s[w8, 8], { z0.b-z3.b }, { z0.b-z3.b}
+
+fdot za.h[w8, 0], { z0.b-z1.b }, z16.b[0]
+fdot za.h[w8, 0], { z1.b-z2.b }, z0.b[0]
+fdot za.h[w8, 0, VGx2], { z0.b-z3.b }, z0.b[0]
+fdot za.h[w8, 0], { z0.b-z1.b }, z0.b[8]
+fdot za.h[w8, 8], { z0.b-z1.b }, z0.b[0]
+fdot za.h[w7, 0], { z0.b-z1.b }, z0.b[0]
+fdot za.h[w12, 0], { z0.b-z1.b }, z0.b[0]
+
+fdot za.h[w8, 0], { z0.b-z3.b }, z16.b[0]
+fdot za.h[w8, 0], { z2.b-z5.b }, z0.b[0]
+fdot za.h[w8, 0, VGx4], { z0.b-z1.b }, z0.b[0]
+fdot za.h[w8, 0], { z0.b-z3.b }, z0.b[8]
+fdot za.h[w8, 8], { z0.b-z3.b }, z0.b[0]
+fdot za.h[w7, 0], { z0.b-z3.b }, z0.b[0]
+fdot za.h[w12, 0], { z0.b-z3.b }, z0.b[0]
+
+fdot za.h[w8, 0], { z0.b-z1.b }, z16.b
+fdot za.h[w8, 8], { z0.b-z1.b }, z0.b
+fdot za.h[w7, 0], { z0.b-z1.b }, z0.b
+fdot za.h[w12, 0], { z0.b-z1.b }, z0.b
+fdot za.h[w8, 0, VGx4], { z0.b-z1.b }, z0.b
+
+fdot za.h[w8, 0], { z0.b-z3.b }, z16.b
+fdot za.h[w8, 8], { z0.b-z3.b }, z0.b
+fdot za.h[w7, 0], { z0.b-z3.b }, z0.b
+fdot za.h[w12, 0], { z0.b-z3.b }, z0.b
+fdot za.h[w8, 0, VGx2], { z0.b-z3.b }, z0.b
+
+fdot za.h[w8, 0], { z0.b-z1.b }, { z0.b-z3.b}
+fdot za.h[w8, 0], { z0.b-z1.b }, { z1.b-z2.b}
+fdot za.h[w8, 0], { z1.b-z2.b }, { z0.b-z1.b}
+fdot za.h[w7, 0], { z0.b-z1.b }, { z0.b-z1.b}
+fdot za.h[w8, 8], { z0.b-z1.b }, { z0.b-z1.b}
+
+fdot za.h[w8, 0], { z0.b-z3.b }, { z0.b-z1.b}
+fdot za.h[w8, 0], { z0.b-z3.b }, { z2.b-z5.b}
+fdot za.h[w8, 0], { z2.b-z5.b }, { z0.b-z3.b}
+fdot za.h[w7, 0], { z0.b-z3.b }, { z0.b-z3.b}
+fdot za.h[w8, 8], { z0.b-z3.b }, { z0.b-z3.b}
+
+fvdot za.h[w7, 0], {z0.b-z1.b}, z0.b[0]
+fvdot za.h[w12, 0], {z0.b-z1.b}, z0.b[0]
+fvdot za.h[w8, 8], {z0.b-z1.b}, z0.b[0]
+fvdot za.h[w8, 0], {z1.b-z2.b}, z0.b[0]
+fvdot za.h[w8, 0], {z0.b-z1.b}, z16.b[0]
+fvdot za.h[w8, 0], {z0.b-z1.b}, z0.b[8]
+
+fvdotb za.s[w7, 0], {z0.b-z1.b}, z0.b[0]
+fvdotb za.s[w12, 0], {z0.b-z1.b}, z0.b[0]
+fvdotb za.s[w8, 8], {z0.b-z1.b}, z0.b[0]
+fvdotb za.s[w8, 0], {z1.b-z2.b}, z0.b[0]
+fvdotb za.s[w8, 0], {z0.b-z1.b}, z16.b[0]
+fvdotb za.s[w8, 0], {z0.b-z1.b}, z0.b[4]
+
+fvdott za.s[w7, 0], {z0.b-z1.b}, z0.b[0]
+fvdott za.s[w12, 0], {z0.b-z1.b}, z0.b[0]
+fvdott za.s[w8, 8], {z0.b-z1.b}, z0.b[0]
+fvdott za.s[w8, 0], {z1.b-z2.b}, z0.b[0]
+fvdott za.s[w8, 0], {z0.b-z1.b}, z16.b[0]
+fvdott za.s[w8, 0], {z0.b-z1.b}, z0.b[4]
diff --git a/gas/testsuite/gas/aarch64/fp8-sme-dot2.d b/gas/testsuite/gas/aarch64/fp8-sme-dot2.d
new file mode 100644
index 00000000000..8e78b0c8aa2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sme-dot2.d
@@ -0,0 +1,50 @@
+#as: -march=armv8-a+sme-f8f16
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: c1d00020 fdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1df0020 fdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, z15\.b\[0\]
+ *[0-9a-f]+: c1d003e0 fdot za\.h\[w8, 0, vgx2\], {z30\.b-z31\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1d00820 fdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[4\]
+ *[0-9a-f]+: c1d00c28 fdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[7\]
+ *[0-9a-f]+: c1d00027 fdot za\.h\[w8, 7, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1d06020 fdot za\.h\[w11, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1109040 fdot za\.h\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c11f9040 fdot za\.h\[w8, 0, vgx4\], {z0\.b-z3\.b}, z15\.b\[0\]
+ *[0-9a-f]+: c11093c0 fdot za\.h\[w8, 0, vgx4\], {z28\.b-z31\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1109840 fdot za\.h\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[4\]
+ *[0-9a-f]+: c1109c48 fdot za\.h\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[7\]
+ *[0-9a-f]+: c1109047 fdot za\.h\[w8, 7, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c110f040 fdot za\.h\[w11, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1201008 fdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b
+ *[0-9a-f]+: c12f1008 fdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, z15\.b
+ *[0-9a-f]+: c12013e8 fdot za\.h\[w8, 0, vgx2\], {z31\.b-z0\.b}, z0\.b
+ *[0-9a-f]+: c120100f fdot za\.h\[w8, 7, vgx2\], {z0\.b-z1\.b}, z0\.b
+ *[0-9a-f]+: c1207008 fdot za\.h\[w11, 0, vgx2\], {z0\.b-z1\.b}, z0\.b
+ *[0-9a-f]+: c1301008 fdot za\.h\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b
+ *[0-9a-f]+: c13f1008 fdot za\.h\[w8, 0, vgx4\], {z0\.b-z3\.b}, z15\.b
+ *[0-9a-f]+: c13013e8 fdot za\.h\[w8, 0, vgx4\], {z31\.b-z2\.b}, z0\.b
+ *[0-9a-f]+: c130100f fdot za\.h\[w8, 7, vgx4\], {z0\.b-z3\.b}, z0\.b
+ *[0-9a-f]+: c1307008 fdot za\.h\[w11, 0, vgx4\], {z0\.b-z3\.b}, z0\.b
+ *[0-9a-f]+: c1a01020 fdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
+ *[0-9a-f]+: c1be1020 fdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, {z30\.b-z31\.b}
+ *[0-9a-f]+: c1a013e0 fdot za\.h\[w8, 0, vgx2\], {z30\.b-z31\.b}, {z0\.b-z1\.b}
+ *[0-9a-f]+: c1a01027 fdot za\.h\[w8, 7, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
+ *[0-9a-f]+: c1a07020 fdot za\.h\[w11, 0, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
+ *[0-9a-f]+: c1a11020 fdot za\.h\[w8, 0, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
+ *[0-9a-f]+: c1bd1020 fdot za\.h\[w8, 0, vgx4\], {z0\.b-z3\.b}, {z28\.b-z31\.b}
+ *[0-9a-f]+: c1a113a0 fdot za\.h\[w8, 0, vgx4\], {z28\.b-z31\.b}, {z0\.b-z3\.b}
+ *[0-9a-f]+: c1a11027 fdot za\.h\[w8, 7, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
+ *[0-9a-f]+: c1a17020 fdot za\.h\[w11, 0, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
+ *[0-9a-f]+: c1d01020 fvdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1d07020 fvdot za\.h\[w11, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1d01027 fvdot za\.h\[w8, 7, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1d013e0 fvdot za\.h\[w8, 0, vgx2\], {z30\.b-z31\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1df1020 fvdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, z15\.b\[0\]
+ *[0-9a-f]+: c1d01428 fvdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[3\]
+ *[0-9a-f]+: c1d01c28 fvdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[7\]
diff --git a/gas/testsuite/gas/aarch64/fp8-sme-dot2.s b/gas/testsuite/gas/aarch64/fp8-sme-dot2.s
new file mode 100644
index 00000000000..6da4c3702a1
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sme-dot2.s
@@ -0,0 +1,47 @@
+fdot za.h[w8, 0], { z0.b-z1.b }, z0.b[0]
+fdot za.h[w8, 0], { z0.b - z1.b }, z15.b[0]
+fdot za.h[w8, 0], { z30.b-z31.b }, z0.b[0]
+fdot za.h[w8, 0, VGx2 ], { z0.b-z1.b }, z0.b[4]
+fdot za.h[w8, 0, VGx2 ], { z0.b-z1.b }, z0.b[7]
+fdot za.h[w8, 7], { z0.b-z1.b }, z0.b[0]
+fdot za.h[w11, 0], { z0.b-z1.b }, z0.b[0]
+
+fdot za.h[w8, 0], { z0.b-z3.b }, z0.b[0]
+fdot za.h[w8, 0, VGx4], { z0.b - z3.b }, z15.b[0]
+fdot za.h[w8, 0], { z28.b-z31.b }, z0.b[0]
+fdot za.h[w8, 0], { z0.b-z3.b }, z0.b[4]
+fdot za.h[w8, 0], { z0.b-z3.b }, z0.b[7]
+fdot za.h[w8, 7], { z0.b-z3.b }, z0.b[0]
+fdot za.h[w11, 0], { z0.b-z3.b }, z0.b[0]
+
+fdot za.h[w8, 0], { z0.b-z1.b }, z0.b
+fdot za.h[w8, 0], { z0.b - z1.b }, z15.b
+fdot za.h[w8, 0, VGx2], { z31.b-z0.b }, z0.b
+fdot za.h[w8, 7], { z0.b-z1.b }, z0.b
+fdot za.h[w11, 0], { z0.b-z1.b }, z0.b
+
+fdot za.h[w8, 0], { z0.b-z3.b }, z0.b
+fdot za.h[w8, 0, VGx4], { z0.b - z3.b }, z15.b
+fdot za.h[w8, 0], { z31.b-z2.b }, z0.b
+fdot za.h[w8, 7], { z0.b-z3.b }, z0.b
+fdot za.h[w11, 0], { z0.b-z3.b }, z0.b
+
+fdot za.h[w8, 0], { z0.b-z1.b }, {z0.b-z1.b }
+fdot za.h[w8, 0], { z0.b - z1.b }, {z30.b - z31.b}
+fdot za.h[w8, 0], { z30.b-z31.b }, {z0.b-z1.b}
+fdot za.h[w8, 7], { z0.b-z1.b },{ z0.b-z1.b}
+fdot za.h[w11, 0, VGx2], { z0.b-z1.b }, {z0.b-z1.b}
+
+fdot za.h[w8, 0], { z0.b-z3.b }, {z0.b-z3.b }
+fdot za.h[w8, 0], { z0.b - z3.b }, {z28.b - z31.b}
+fdot za.h[w8, 0], { z28.b-z31.b }, {z0.b-z3.b}
+fdot za.h[w8, 7], { z0.b-z3.b }, {z0.b-z3.b}
+fdot za.h[w11, 0, VGx4], { z0.b-z3.b }, {z0.b-z3.b}
+
+fvdot za.h[w8, 0], {z0.b-z1.b}, z0.b[0]
+fvdot za.h[w11, 0, VGx2], {z0.b-z1.b}, z0.b[0]
+fvdot za.h[w8, 7], { z0.b-z1.b }, z0.b[0]
+fvdot za.h[w8, 0], {z30.b-z31.b}, z0.b[0]
+fvdot za.h[w8, 0], {z0.b-z1.b}, z15.b[0]
+fvdot za.h[w8, 0], {z0.b-z1.b}, z0.b[3]
+fvdot za.h[w8, 0], {z0.b-z1.b}, z0.b[7]
diff --git a/gas/testsuite/gas/aarch64/fp8-sme-dot4.d b/gas/testsuite/gas/aarch64/fp8-sme-dot4.d
new file mode 100644
index 00000000000..d44280ad6cd
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sme-dot4.d
@@ -0,0 +1,55 @@
+#as: -march=armv8-a+sme-f8f32
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: c1500038 fdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c15f0038 fdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z15\.b\[0\]
+ *[0-9a-f]+: c15003f8 fdot za\.s\[w8, 0, vgx2\], {z30\.b-z31\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1500c38 fdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[3\]
+ *[0-9a-f]+: c150003f fdot za\.s\[w8, 7, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1506038 fdot za\.s\[w11, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1508008 fdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c15f8008 fdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z15\.b\[0\]
+ *[0-9a-f]+: c1508388 fdot za\.s\[w8, 0, vgx4\], {z28\.b-z31\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1508c08 fdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[3\]
+ *[0-9a-f]+: c150800f fdot za\.s\[w8, 7, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c150e008 fdot za\.s\[w11, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1201018 fdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b
+ *[0-9a-f]+: c12f1018 fdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z15\.b
+ *[0-9a-f]+: c12013f8 fdot za\.s\[w8, 0, vgx2\], {z31\.b-z0\.b}, z0\.b
+ *[0-9a-f]+: c120101f fdot za\.s\[w8, 7, vgx2\], {z0\.b-z1\.b}, z0\.b
+ *[0-9a-f]+: c1207018 fdot za\.s\[w11, 0, vgx2\], {z0\.b-z1\.b}, z0\.b
+ *[0-9a-f]+: c1301018 fdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b
+ *[0-9a-f]+: c13f1018 fdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z15\.b
+ *[0-9a-f]+: c13013f8 fdot za\.s\[w8, 0, vgx4\], {z31\.b-z2\.b}, z0\.b
+ *[0-9a-f]+: c130101f fdot za\.s\[w8, 7, vgx4\], {z0\.b-z3\.b}, z0\.b
+ *[0-9a-f]+: c1307018 fdot za\.s\[w11, 0, vgx4\], {z0\.b-z3\.b}, z0\.b
+ *[0-9a-f]+: c1a01030 fdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
+ *[0-9a-f]+: c1be1030 fdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, {z30\.b-z31\.b}
+ *[0-9a-f]+: c1a013f0 fdot za\.s\[w8, 0, vgx2\], {z30\.b-z31\.b}, {z0\.b-z1\.b}
+ *[0-9a-f]+: c1a01037 fdot za\.s\[w8, 7, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
+ *[0-9a-f]+: c1a07030 fdot za\.s\[w11, 0, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
+ *[0-9a-f]+: c1a11030 fdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
+ *[0-9a-f]+: c1bd1030 fdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, {z28\.b-z31\.b}
+ *[0-9a-f]+: c1a113b0 fdot za\.s\[w8, 0, vgx4\], {z28\.b-z31\.b}, {z0\.b-z3\.b}
+ *[0-9a-f]+: c1a11037 fdot za\.s\[w8, 7, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
+ *[0-9a-f]+: c1a17030 fdot za\.s\[w11, 0, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
+ *[0-9a-f]+: c1d00800 fvdotb za\.s\[w8, 0, vgx4\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1d06800 fvdotb za\.s\[w11, 0, vgx4\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1d00807 fvdotb za\.s\[w8, 7, vgx4\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1d00bc0 fvdotb za\.s\[w8, 0, vgx4\], {z30\.b-z31\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1df0800 fvdotb za\.s\[w8, 0, vgx4\], {z0\.b-z1\.b}, z15\.b\[0\]
+ *[0-9a-f]+: c1d00808 fvdotb za\.s\[w8, 0, vgx4\], {z0\.b-z1\.b}, z0\.b\[1\]
+ *[0-9a-f]+: c1d00c08 fvdotb za\.s\[w8, 0, vgx4\], {z0\.b-z1\.b}, z0\.b\[3\]
+ *[0-9a-f]+: c1d00810 fvdott za\.s\[w8, 0, vgx4\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1d06810 fvdott za\.s\[w11, 0, vgx4\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1d00817 fvdott za\.s\[w8, 7, vgx4\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1d00bd0 fvdott za\.s\[w8, 0, vgx4\], {z30\.b-z31\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1df0810 fvdott za\.s\[w8, 0, vgx4\], {z0\.b-z1\.b}, z15\.b\[0\]
+ *[0-9a-f]+: c1d00818 fvdott za\.s\[w8, 0, vgx4\], {z0\.b-z1\.b}, z0\.b\[1\]
+ *[0-9a-f]+: c1d00c18 fvdott za\.s\[w8, 0, vgx4\], {z0\.b-z1\.b}, z0\.b\[3\]
diff --git a/gas/testsuite/gas/aarch64/fp8-sme-dot4.s b/gas/testsuite/gas/aarch64/fp8-sme-dot4.s
new file mode 100644
index 00000000000..b405b2610e9
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sme-dot4.s
@@ -0,0 +1,53 @@
+fdot za.s[w8, 0], { z0.b-z1.b }, z0.b[0]
+fdot za.s[w8, 0], { z0.b - z1.b }, z15.b[0]
+fdot za.s[w8, 0], { z30.b-z31.b }, z0.b[0]
+fdot za.s[w8, 0, VGx2 ], { z0.b-z1.b }, z0.b[3]
+fdot za.s[w8, 7], { z0.b-z1.b }, z0.b[0]
+fdot za.s[w11, 0], { z0.b-z1.b }, z0.b[0]
+
+fdot za.s[w8, 0], { z0.b-z3.b }, z0.b[0]
+fdot za.s[w8, 0, VGx4], { z0.b - z3.b }, z15.b[0]
+fdot za.s[w8, 0], { z28.b-z31.b }, z0.b[0]
+fdot za.s[w8, 0], { z0.b-z3.b }, z0.b[3]
+fdot za.s[w8, 7], { z0.b-z3.b }, z0.b[0]
+fdot za.s[w11, 0], { z0.b-z3.b }, z0.b[0]
+
+fdot za.s[w8, 0], { z0.b-z1.b }, z0.b
+fdot za.s[w8, 0], { z0.b - z1.b }, z15.b
+fdot za.s[w8, 0, VGx2], { z31.b-z0.b }, z0.b
+fdot za.s[w8, 7], { z0.b-z1.b }, z0.b
+fdot za.s[w11, 0], { z0.b-z1.b }, z0.b
+
+fdot za.s[w8, 0], { z0.b-z3.b }, z0.b
+fdot za.s[w8, 0, VGx4], { z0.b - z3.b }, z15.b
+fdot za.s[w8, 0], { z31.b-z2.b }, z0.b
+fdot za.s[w8, 7], { z0.b-z3.b }, z0.b
+fdot za.s[w11, 0], { z0.b-z3.b }, z0.b
+
+fdot za.s[w8, 0], { z0.b-z1.b }, {z0.b-z1.b }
+fdot za.s[w8, 0], { z0.b - z1.b }, {z30.b - z31.b}
+fdot za.s[w8, 0], { z30.b-z31.b }, {z0.b-z1.b}
+fdot za.s[w8, 7], { z0.b-z1.b },{ z0.b-z1.b}
+fdot za.s[w11, 0, VGx2], { z0.b-z1.b }, {z0.b-z1.b}
+
+fdot za.s[w8, 0], { z0.b-z3.b }, {z0.b-z3.b }
+fdot za.s[w8, 0], { z0.b - z3.b }, {z28.b - z31.b}
+fdot za.s[w8, 0], { z28.b-z31.b }, {z0.b-z3.b}
+fdot za.s[w8, 7], { z0.b-z3.b }, {z0.b-z3.b}
+fdot za.s[w11, 0, VGx4], { z0.b-z3.b }, {z0.b-z3.b}
+
+fvdotb za.s[w8, 0, VGx4], { z0.b-z1.b }, z0.b[0]
+fvdotb za.s[w11, 0, VGx4], { z0.b-z1.b }, z0.b[0]
+fvdotb za.s[w8, 7, VGx4], { z0.b-z1.b }, z0.b[0]
+fvdotb za.s[w8, 0, VGx4], { z30.b-z31.b }, z0.b[0]
+fvdotb za.s[w8, 0, VGx4], { z0.b-z1.b }, z15.b[0]
+fvdotb za.s[w8, 0, VGx4], { z0.b-z1.b }, z0.b[1]
+fvdotb za.s[w8, 0, VGx4], { z0.b-z1.b }, z0.b[3]
+
+fvdott za.s[w8, 0, VGx4], { z0.b-z1.b }, z0.b[0]
+fvdott za.s[w11, 0, VGx4], { z0.b-z1.b }, z0.b[0]
+fvdott za.s[w8, 7, VGx4], { z0.b-z1.b }, z0.b[0]
+fvdott za.s[w8, 0, VGx4], { z30.b-z31.b }, z0.b[0]
+fvdott za.s[w8, 0, VGx4], { z0.b-z1.b }, z15.b[0]
+fvdott za.s[w8, 0, VGx4], { z0.b-z1.b }, z0.b[1]
+fvdott za.s[w8, 0, VGx4], { z0.b-z1.b }, z0.b[3]
diff --git a/gas/testsuite/gas/aarch64/fp8-sme-fmlal-illegal.d b/gas/testsuite/gas/aarch64/fp8-sme-fmlal-illegal.d
new file mode 100644
index 00000000000..f5293d6d189
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sme-fmlal-illegal.d
@@ -0,0 +1,2 @@
+#as: -march=armv8-a+sme-f8f16
+#error_output: fp8-sme-fmlal-illegal.l
diff --git a/gas/testsuite/gas/aarch64/fp8-sme-fmlal-illegal.l b/gas/testsuite/gas/aarch64/fp8-sme-fmlal-illegal.l
new file mode 100644
index 00000000000..31551f97ee6
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sme-fmlal-illegal.l
@@ -0,0 +1,72 @@
+[^:]*: Assembler messages:
+[^:]*:1: Error: z0-z15 expected at operand 3 -- `fmlal za\.h\[w8,0:1\],z0\.b,z16\.b\[0\]'
+[^:]*:2: Error: unexpected vector group size at operand 1 -- `fmlal za\.h\[w8,0:1,VGx2\],z0\.b,z0\.b\[0\]'
+[^:]*:3: Error: register element index out of range 0 to 15 at operand 3 -- `fmlal za\.h\[w8,0:1\],z0\.b,z0\.b\[16\]'
+[^:]*:4: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],z0\.b,z0\.b\[0\]'
+[^:]*:5: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],z0\.b,z0\.b\[0\]'
+[^:]*:6: Error: immediate offset out of range 0 to 14 at operand 1 -- `fmlal za\.h\[w8,16:17\],z0\.b,z0\.b\[0\]'
+[^:]*:7: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],z0\.b,z0\.b\[0\]'
+[^:]*:8: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0:1\],z0\.b,z0\.b\[0\]'
+[^:]*:9: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0:1\],z0\.b,z0\.b\[0\]'
+[^:]*:11: Error: z0-z15 expected at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z1\.b},z16\.b\[0\]'
+[^:]*:12: Error: start register out of range at operand 2 -- `fmlal za\.h\[w8,0:1\],{z1\.b-z2\.b},z0\.b\[0\]'
+[^:]*:13: Error: expected a list of 2 registers at operand 2 -- `fmlal za\.h\[w8,0:1,VGx2\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:14: Error: register element index out of range 0 to 15 at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z1\.b},z0\.b\[16\]'
+[^:]*:15: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:16: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:17: Error: immediate offset out of range 0 to 6 at operand 1 -- `fmlal za\.h\[w8,8:9\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:18: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:19: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0:1\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:20: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0:1\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:22: Error: z0-z15 expected at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z3\.b},z16\.b\[0\]'
+[^:]*:23: Error: start register out of range at operand 2 -- `fmlal za\.h\[w8,0:1\],{z2\.b-z5\.b},z0\.b\[0\]'
+[^:]*:24: Error: expected a list of 4 registers at operand 2 -- `fmlal za\.h\[w8,0:1,VGx4\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:25: Error: register element index out of range 0 to 15 at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z3\.b},z0\.b\[16\]'
+[^:]*:26: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:27: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:28: Error: immediate offset out of range 0 to 6 at operand 1 -- `fmlal za\.h\[w8,8:9\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:29: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:30: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:31: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:33: Error: z0-z15 expected at operand 3 -- `fmlal za\.h\[w8,0:1\],z0\.b,z16\.b'
+[^:]*:34: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],z0\.b,z0\.b'
+[^:]*:35: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],z0\.b,z0\.b'
+[^:]*:36: Error: immediate offset out of range 0 to 14 at operand 1 -- `fmlal za\.h\[w8,16:17\],z0\.b,z0\.b'
+[^:]*:37: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],z0\.b,z0\.b'
+[^:]*:38: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0\],z0\.b,z0\.b'
+[^:]*:39: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0\],z0\.b,z0\.b'
+[^:]*:40: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0,VGx4\],z0\.b,z0\.b'
+[^:]*:42: Error: z0-z15 expected at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z1\.b},z16\.b'
+[^:]*:43: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],{z0\.b-z1\.b},z0\.b'
+[^:]*:44: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],{z0\.b-z1\.b},z0\.b'
+[^:]*:45: Error: immediate offset out of range 0 to 6 at operand 1 -- `fmlal za\.h\[w8,8:9\],{z0\.b-z1\.b},z0\.b'
+[^:]*:46: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],{z0\.b-z1\.b},z0\.b'
+[^:]*:47: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0:1\],{z0\.b-z1\.b},z0\.b'
+[^:]*:48: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0:1\],{z0\.b-z1\.b},z0\.b'
+[^:]*:49: Error: expected a list of 4 registers at operand 2 -- `fmlal za\.h\[w8,0:1,VGx4\],{z0\.b-z1\.b},z0\.b'
+[^:]*:51: Error: z0-z15 expected at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z3\.b},z16\.b'
+[^:]*:52: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],{z0\.b-z3\.b},z0\.b'
+[^:]*:53: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],{z0\.b-z3\.b},z0\.b'
+[^:]*:54: Error: immediate offset out of range 0 to 6 at operand 1 -- `fmlal za\.h\[w8,8:9\],{z0\.b-z3\.b},z0\.b'
+[^:]*:55: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],{z0\.b-z3\.b},z0\.b'
+[^:]*:56: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0:1\],{z0\.b-z3\.b},z0\.b'
+[^:]*:57: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0:1\],{z0\.b-z3\.b},z0\.b'
+[^:]*:58: Error: expected a list of 2 registers at operand 2 -- `fmlal za\.h\[w8,0:1,VGx2\],{z0\.b-z3\.b},z0\.b'
+[^:]*:60: Error: expected a list of 2 registers at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z1\.b},{z0\.b-z3\.b}'
+[^:]*:61: Error: start register out of range at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z1\.b},{z1\.b-z2\.b}'
+[^:]*:62: Error: start register out of range at operand 2 -- `fmlal za\.h\[w8,0:1\],{z1\.b-z2\.b},{z0\.b-z1\.b}'
+[^:]*:63: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0:1\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^:]*:64: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0:1\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^:]*:65: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^:]*:66: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^:]*:67: Error: immediate offset out of range 0 to 6 at operand 1 -- `fmlal za\.h\[w8,8:9\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^:]*:68: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^:]*:70: Error: expected a list of 4 registers at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z3\.b},{z0\.b-z1\.b}'
+[^:]*:71: Error: start register out of range at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z3\.b},{z2\.b-z5\.b}'
+[^:]*:72: Error: start register out of range at operand 2 -- `fmlal za\.h\[w8,0:1\],{z2\.b-z5\.b},{z0\.b-z3\.b}'
+[^:]*:73: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0:1\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^:]*:74: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0:1\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^:]*:75: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^:]*:76: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^:]*:77: Error: immediate offset out of range 0 to 6 at operand 1 -- `fmlal za\.h\[w8,8:9\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^:]*:78: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
diff --git a/gas/testsuite/gas/aarch64/fp8-sme-fmlal-illegal.s b/gas/testsuite/gas/aarch64/fp8-sme-fmlal-illegal.s
new file mode 100644
index 00000000000..94c4246e098
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sme-fmlal-illegal.s
@@ -0,0 +1,78 @@
+fmlal za.h[w8, 0:1], z0.b, z16.b[0]
+fmlal za.h[w8, 0:1, VGx2], z0.b, z0.b[0]
+fmlal za.h[w8, 0:1], z0.b, z0.b[16]
+fmlal za.h[w8, 0], z0.b, z0.b[0]
+fmlal za.h[w8, 1:2], z0.b, z0.b[0]
+fmlal za.h[w8, 16:17], z0.b, z0.b[0]
+fmlal za.h[w8, 0:3], z0.b, z0.b[0]
+fmlal za.h[w7, 0:1], z0.b, z0.b[0]
+fmlal za.h[w12, 0:1], z0.b, z0.b[0]
+
+fmlal za.h[w8, 0:1], { z0.b-z1.b }, z16.b[0]
+fmlal za.h[w8, 0:1], { z1.b-z2.b }, z0.b[0]
+fmlal za.h[w8, 0:1, VGx2], { z0.b-z3.b }, z0.b[0]
+fmlal za.h[w8, 0:1], { z0.b-z1.b }, z0.b[16]
+fmlal za.h[w8, 0], { z0.b-z1.b }, z0.b[0]
+fmlal za.h[w8, 1:2], { z0.b-z1.b }, z0.b[0]
+fmlal za.h[w8, 8:9], { z0.b-z1.b }, z0.b[0]
+fmlal za.h[w8, 0:3], { z0.b-z1.b }, z0.b[0]
+fmlal za.h[w7, 0:1], { z0.b-z1.b }, z0.b[0]
+fmlal za.h[w12, 0:1], { z0.b-z1.b }, z0.b[0]
+
+fmlal za.h[w8, 0:1], { z0.b-z3.b }, z16.b[0]
+fmlal za.h[w8, 0:1], { z2.b-z5.b }, z0.b[0]
+fmlal za.h[w8, 0:1, VGx4], { z0.b-z1.b }, z0.b[0]
+fmlal za.h[w8, 0:1], { z0.b-z3.b }, z0.b[16]
+fmlal za.h[w8, 0], { z0.b-z3.b }, z0.b[0]
+fmlal za.h[w8, 1:2], { z0.b-z3.b }, z0.b[0]
+fmlal za.h[w8, 8:9], { z0.b-z3.b }, z0.b[0]
+fmlal za.h[w8, 0:3], { z0.b-z3.b }, z0.b[0]
+fmlal za.h[w7, 0], { z0.b-z3.b }, z0.b[0]
+fmlal za.h[w12, 0], { z0.b-z3.b }, z0.b[0]
+
+fmlal za.h[w8, 0:1], z0.b, z16.b
+fmlal za.h[w8, 0], z0.b, z0.b
+fmlal za.h[w8, 1:2], z0.b, z0.b
+fmlal za.h[w8, 16:17], z0.b, z0.b
+fmlal za.h[w8, 0:3], z0.b, z0.b
+fmlal za.h[w7, 0], z0.b, z0.b
+fmlal za.h[w12, 0], z0.b, z0.b
+fmlal za.h[w8, 0, VGx4], z0.b, z0.b
+
+fmlal za.h[w8, 0:1], { z0.b-z1.b }, z16.b
+fmlal za.h[w8, 0], { z0.b-z1.b }, z0.b
+fmlal za.h[w8, 1:2], { z0.b-z1.b }, z0.b
+fmlal za.h[w8, 8:9], { z0.b-z1.b }, z0.b
+fmlal za.h[w8, 0:3], { z0.b-z1.b }, z0.b
+fmlal za.h[w7, 0:1], { z0.b-z1.b }, z0.b
+fmlal za.h[w12, 0:1], { z0.b-z1.b }, z0.b
+fmlal za.h[w8, 0:1, VGx4], { z0.b-z1.b }, z0.b
+
+fmlal za.h[w8, 0:1], { z0.b-z3.b }, z16.b
+fmlal za.h[w8, 0], { z0.b-z3.b }, z0.b
+fmlal za.h[w8, 1:2], { z0.b-z3.b }, z0.b
+fmlal za.h[w8, 8:9], { z0.b-z3.b }, z0.b
+fmlal za.h[w8, 0:3], { z0.b-z3.b }, z0.b
+fmlal za.h[w7, 0:1], { z0.b-z3.b }, z0.b
+fmlal za.h[w12, 0:1], { z0.b-z3.b }, z0.b
+fmlal za.h[w8, 0:1, VGx2], { z0.b-z3.b }, z0.b
+
+fmlal za.h[w8, 0:1], { z0.b-z1.b }, { z0.b-z3.b}
+fmlal za.h[w8, 0:1], { z0.b-z1.b }, { z1.b-z2.b}
+fmlal za.h[w8, 0:1], { z1.b-z2.b }, { z0.b-z1.b}
+fmlal za.h[w7, 0:1], { z0.b-z1.b }, { z0.b-z1.b}
+fmlal za.h[w12, 0:1], { z0.b-z1.b }, { z0.b-z1.b}
+fmlal za.h[w8, 0], { z0.b-z1.b }, { z0.b-z1.b}
+fmlal za.h[w8, 1:2], { z0.b-z1.b }, { z0.b-z1.b}
+fmlal za.h[w8, 8:9], { z0.b-z1.b }, { z0.b-z1.b}
+fmlal za.h[w8, 0:3], { z0.b-z1.b }, { z0.b-z1.b}
+
+fmlal za.h[w8, 0:1], { z0.b-z3.b }, { z0.b-z1.b}
+fmlal za.h[w8, 0:1], { z0.b-z3.b }, { z2.b-z5.b}
+fmlal za.h[w8, 0:1], { z2.b-z5.b }, { z0.b-z3.b}
+fmlal za.h[w7, 0:1], { z0.b-z3.b }, { z0.b-z3.b}
+fmlal za.h[w12, 0:1], { z0.b-z3.b }, { z0.b-z3.b}
+fmlal za.h[w8, 0], { z0.b-z3.b }, { z0.b-z3.b}
+fmlal za.h[w8, 1:2], { z0.b-z3.b }, { z0.b-z3.b}
+fmlal za.h[w8, 8:9], { z0.b-z3.b }, { z0.b-z3.b}
+fmlal za.h[w8, 0:3], { z0.b-z3.b }, { z0.b-z3.b}
diff --git a/gas/testsuite/gas/aarch64/fp8-sme-fmlal.d b/gas/testsuite/gas/aarch64/fp8-sme-fmlal.d
new file mode 100644
index 00000000000..594570205c4
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sme-fmlal.d
@@ -0,0 +1,57 @@
+#as: -march=armv8-a+sme-f8f16
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: c1c00000 fmlal za\.h\[w8, 0:1], z0\.b, z0\.b\[0\]
+ *[0-9a-f]+: c1c06000 fmlal za\.h\[w11, 0:1], z0\.b, z0\.b\[0\]
+ *[0-9a-f]+: c1c00007 fmlal za\.h\[w8, 14:15], z0\.b, z0\.b\[0\]
+ *[0-9a-f]+: c1c003e0 fmlal za\.h\[w8, 0:1], z31\.b, z0\.b\[0\]
+ *[0-9a-f]+: c1cf0000 fmlal za\.h\[w8, 0:1], z0\.b, z15\.b\[0\]
+ *[0-9a-f]+: c1c00408 fmlal za\.h\[w8, 0:1], z0\.b, z0\.b\[3\]
+ *[0-9a-f]+: c1c08c08 fmlal za\.h\[w8, 0:1], z0\.b, z0\.b\[15\]
+ *[0-9a-f]+: c1901030 fmlal za\.h\[w8, 0:1, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1907030 fmlal za\.h\[w11, 0:1, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1901033 fmlal za\.h\[w8, 6:7, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c19013f0 fmlal za\.h\[w8, 0:1, vgx2\], {z30\.b-z31\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c19f1030 fmlal za\.h\[w8, 0:1, vgx2\], {z0\.b-z1\.b}, z15\.b\[0\]
+ *[0-9a-f]+: c1901034 fmlal za\.h\[w8, 0:1, vgx2\], {z0\.b-z1\.b}, z0\.b\[1\]
+ *[0-9a-f]+: c190143c fmlal za\.h\[w8, 0:1, vgx2\], {z0\.b-z1\.b}, z0\.b\[7\]
+ *[0-9a-f]+: c1901c3c fmlal za\.h\[w8, 0:1, vgx2\], {z0\.b-z1\.b}, z0\.b\[15\]
+ *[0-9a-f]+: c1909020 fmlal za\.h\[w8, 0:1, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c190f020 fmlal za\.h\[w11, 0:1, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1909023 fmlal za\.h\[w8, 6:7, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c19093a0 fmlal za\.h\[w8, 0:1, vgx4\], {z28\.b-z31\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c19f9020 fmlal za\.h\[w8, 0:1, vgx4\], {z0\.b-z3\.b}, z15\.b\[0\]
+ *[0-9a-f]+: c1909024 fmlal za\.h\[w8, 0:1, vgx4\], {z0\.b-z3\.b}, z0\.b\[1\]
+ *[0-9a-f]+: c190942c fmlal za\.h\[w8, 0:1, vgx4\], {z0\.b-z3\.b}, z0\.b\[7\]
+ *[0-9a-f]+: c1909c2c fmlal za\.h\[w8, 0:1, vgx4\], {z0\.b-z3\.b}, z0\.b\[15\]
+ *[0-9a-f]+: c1300c00 fmlal za\.h\[w8, 0:1\], z0\.b, z0\.b
+ *[0-9a-f]+: c1306c00 fmlal za\.h\[w11, 0:1\], z0\.b, z0\.b
+ *[0-9a-f]+: c1300c07 fmlal za\.h\[w8, 14:15\], z0\.b, z0\.b
+ *[0-9a-f]+: c1300fe0 fmlal za\.h\[w8, 0:1\], z31\.b, z0\.b
+ *[0-9a-f]+: c13f0c00 fmlal za\.h\[w8, 0:1\], z0\.b, z15\.b
+ *[0-9a-f]+: c1200804 fmlal za\.h\[w8, 0:1, vgx2\], {z0\.b-z1\.b}, z0\.b
+ *[0-9a-f]+: c1206804 fmlal za\.h\[w11, 0:1, vgx2\], {z0\.b-z1\.b}, z0\.b
+ *[0-9a-f]+: c1200807 fmlal za\.h\[w8, 6:7, vgx2\], {z0\.b-z1\.b}, z0\.b
+ *[0-9a-f]+: c1200be4 fmlal za\.h\[w8, 0:1, vgx2\], {z31\.b-z0\.b}, z0\.b
+ *[0-9a-f]+: c12f0804 fmlal za\.h\[w8, 0:1, vgx2\], {z0\.b-z1\.b}, z15\.b
+ *[0-9a-f]+: c1300804 fmlal za\.h\[w8, 0:1, vgx4\], {z0\.b-z3\.b}, z0\.b
+ *[0-9a-f]+: c1306804 fmlal za\.h\[w11, 0:1, vgx4\], {z0\.b-z3\.b}, z0\.b
+ *[0-9a-f]+: c1300807 fmlal za\.h\[w8, 6:7, vgx4\], {z0\.b-z3\.b}, z0\.b
+ *[0-9a-f]+: c1300be4 fmlal za\.h\[w8, 0:1, vgx4\], {z31\.b-z2\.b}, z0\.b
+ *[0-9a-f]+: c13f0804 fmlal za\.h\[w8, 0:1, vgx4\], {z0\.b-z3\.b}, z15\.b
+ *[0-9a-f]+: c1a00820 fmlal za\.h\[w8, 0:1, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
+ *[0-9a-f]+: c1a06820 fmlal za\.h\[w11, 0:1, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
+ *[0-9a-f]+: c1a00823 fmlal za\.h\[w8, 6:7, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
+ *[0-9a-f]+: c1a00be0 fmlal za\.h\[w8, 0:1, vgx2\], {z30\.b-z31\.b}, {z0\.b-z1\.b}
+ *[0-9a-f]+: c1be0820 fmlal za\.h\[w8, 0:1, vgx2\], {z0\.b-z1\.b}, {z30\.b-z31\.b}
+ *[0-9a-f]+: c1a10820 fmlal za\.h\[w8, 0:1, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
+ *[0-9a-f]+: c1a16820 fmlal za\.h\[w11, 0:1, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
+ *[0-9a-f]+: c1a10823 fmlal za\.h\[w8, 6:7, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
+ *[0-9a-f]+: c1a10ba0 fmlal za\.h\[w8, 0:1, vgx4\], {z28\.b-z31\.b}, {z0\.b-z3\.b}
+ *[0-9a-f]+: c1bd0820 fmlal za\.h\[w8, 0:1, vgx4\], {z0\.b-z3\.b}, {z28\.b-z31\.b}
diff --git a/gas/testsuite/gas/aarch64/fp8-sme-fmlal.s b/gas/testsuite/gas/aarch64/fp8-sme-fmlal.s
new file mode 100644
index 00000000000..5455f9e5671
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sme-fmlal.s
@@ -0,0 +1,56 @@
+fmlal za.h[w8, 0:1], z0.b, z0.b[0]
+fmlal za.h[w11, 0:1], z0.b, z0.b[0]
+fmlal za.h[w8, 14:15], z0.b, z0.b[0]
+fmlal za.h[w8, 0:1], z31.b, z0.b[0]
+fmlal za.h[w8, 0:1], z0.b, z15.b[0]
+fmlal za.h[w8, 0:1], z0.b, z0.b[3]
+fmlal za.h[w8, 0:1], z0.b, z0.b[15]
+
+fmlal za.h[w8, 0:1], {z0.b-z1.b }, z0.b[0]
+fmlal za.h[w11, 0:1, VGx2], { z0.b-z1.b}, z0.b[0]
+fmlal za.h[w8, 6:7], {z0.b - z1.b}, z0.b[0]
+fmlal za.h[w8, 0:1], { z30.b-z31.b}, z0.b[0]
+fmlal za.h[w8, 0:1], { z0.b - z1.b}, z15.b[0]
+fmlal za.h[w8, 0:1], { z0.b - z1.b }, z0.b[1]
+fmlal za.h[w8, 0:1], { z0.b - z1.b }, z0.b[7]
+fmlal za.h[w8, 0:1], { z0.b - z1.b }, z0.b[15]
+
+fmlal za.h[w8, 0:1], {z0.b-z3.b }, z0.b[0]
+fmlal za.h[w11, 0:1, VGx4], { z0.b-z3.b}, z0.b[0]
+fmlal za.h[w8, 6:7], {z0.b - z3.b}, z0.b[0]
+fmlal za.h[w8, 0:1], { z28.b-z31.b}, z0.b[0]
+fmlal za.h[w8, 0:1], { z0.b - z3.b}, z15.b[0]
+fmlal za.h[w8, 0:1], { z0.b - z3.b }, z0.b[1]
+fmlal za.h[w8, 0:1], { z0.b - z3.b }, z0.b[7]
+fmlal za.h[w8, 0:1], { z0.b - z3.b }, z0.b[15]
+
+fmlal za.h[w8, 0:1], z0.b, z0.b
+fmlal za.h[w11, 0:1], z0.b, z0.b
+fmlal za.h[w8, 14:15], z0.b, z0.b
+fmlal za.h[w8, 0:1], z31.b, z0.b
+fmlal za.h[w8, 0:1], z0.b, z15.b
+
+fmlal za.h[w8, 0:1], {z0.b -z1.b}, z0.b
+fmlal za.h[w11, 0:1], {z0.b-z1.b}, z0.b
+fmlal za.h[w8, 6:7], { z0.b - z1.b }, z0.b
+fmlal za.h[w8, 0:1, VGx2], {z31.b - z0.b}, z0.b
+fmlal za.h[w8, 0:1], {z0.b - z1.b}, z15.b
+
+fmlal za.h[w8, 0:1], {z0.b -z3.b}, z0.b
+fmlal za.h[w11, 0:1], {z0.b-z3.b}, z0.b
+fmlal za.h[w8, 6:7], { z0.b - z3.b }, z0.b
+fmlal za.h[w8, 0:1, VGx4], {z31.b - z2.b}, z0.b
+fmlal za.h[w8, 0:1], {z0.b - z3.b}, z15.b
+
+fmlal za.h[w8, 0:1], {z0.b -z1.b}, {z0.b-z1.b}
+fmlal za.h[w11, 0:1], {z0.b-z1.b}, {z0.b - z1.b}
+fmlal za.h[w8, 6:7], { z0.b - z1.b }, {z0.b -z1.b}
+fmlal za.h[w8, 0:1, VGx2], {z30.b - z31.b}, {z0.b-z1.b}
+fmlal za.h[w8, 0:1], {z0.b - z1.b}, {z30.b -z31.b}
+
+fmlal za.h[w8, 0:1], {z0.b -z3.b}, {z0.b-z3.b}
+fmlal za.h[w11, 0:1], {z0.b-z3.b}, {z0.b - z3.b}
+fmlal za.h[w8, 6:7], { z0.b - z3.b }, {z0.b-z3.b}
+fmlal za.h[w8, 0:1, VGx4], {z28.b - z31.b}, {z0.b-z3.b}
+fmlal za.h[w8, 0:1], {z0.b - z3.b}, {z28.b-z31.b}
+
diff --git a/gas/testsuite/gas/aarch64/fp8-sme-fmlall-illegal.d b/gas/testsuite/gas/aarch64/fp8-sme-fmlall-illegal.d
new file mode 100644
index 00000000000..b0d20198a64
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sme-fmlall-illegal.d
@@ -0,0 +1,2 @@
+#as: -march=armv8-a+sme-f8f32
+#error_output: fp8-sme-fmlall-illegal.l
diff --git a/gas/testsuite/gas/aarch64/fp8-sme-fmlall-illegal.l b/gas/testsuite/gas/aarch64/fp8-sme-fmlall-illegal.l
new file mode 100644
index 00000000000..12ffda0ad2b
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sme-fmlall-illegal.l
@@ -0,0 +1,72 @@
+[^:]*: Assembler messages:
+[^:]*:1: Error: z0-z15 expected at operand 3 -- `fmlall za\.s\[w8,0:3\],z0\.b,z16\.b\[0\]'
+[^:]*:2: Error: unexpected vector group size at operand 1 -- `fmlall za\.s\[w8,0:3,VGx2\],z0\.b,z0\.b\[0\]'
+[^:]*:3: Error: register element index out of range 0 to 15 at operand 3 -- `fmlall za\.s\[w8,0:3\],z0\.b,z0\.b\[16\]'
+[^:]*:4: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0\],z0\.b,z0\.b\[0\]'
+[^:]*:5: Error: starting offset is not a multiple of 4 at operand 1 -- `fmlall za\.s\[w8,2:5\],z0\.b,z0\.b\[0\]'
+[^:]*:6: Error: immediate offset out of range 0 to 12 at operand 1 -- `fmlall za\.s\[w8,16:19\],z0\.b,z0\.b\[0\]'
+[^:]*:7: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0:1\],z0\.b,z0\.b\[0\]'
+[^:]*:8: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w7,0:3\],z0\.b,z0\.b\[0\]'
+[^:]*:9: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w12,0:3\],z0\.b,z0\.b\[0\]'
+[^:]*:11: Error: z0-z15 expected at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z1\.b},z16\.b\[0\]'
+[^:]*:12: Error: start register out of range at operand 2 -- `fmlall za\.s\[w8,0:3\],{z1\.b-z2\.b},z0\.b\[0\]'
+[^:]*:13: Error: expected a list of 2 registers at operand 2 -- `fmlall za\.s\[w8,0:3,VGx2\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:14: Error: register element index out of range 0 to 15 at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z1\.b},z0\.b\[16\]'
+[^:]*:15: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:16: Error: starting offset is not a multiple of 4 at operand 1 -- `fmlall za\.s\[w8,2:5\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:17: Error: immediate offset out of range 0 to 4 at operand 1 -- `fmlall za\.s\[w8,8:11\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:18: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0:1\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:19: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w7,0:3\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:20: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w12,0:3\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:22: Error: z0-z15 expected at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z3\.b},z16\.b\[0\]'
+[^:]*:23: Error: start register out of range at operand 2 -- `fmlall za\.s\[w8,0:3\],{z2\.b-z5\.b},z0\.b\[0\]'
+[^:]*:24: Error: expected a list of 4 registers at operand 2 -- `fmlall za\.s\[w8,0:3,VGx4\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:25: Error: register element index out of range 0 to 15 at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z3\.b},z0\.b\[16\]'
+[^:]*:26: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:27: Error: starting offset is not a multiple of 4 at operand 1 -- `fmlall za\.s\[w8,2:5\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:28: Error: immediate offset out of range 0 to 4 at operand 1 -- `fmlall za\.s\[w8,8:11\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:29: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0:1\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:30: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w7,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:31: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w12,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:33: Error: z0-z15 expected at operand 3 -- `fmlall za\.s\[w8,0:3\],z0\.b,z16\.b'
+[^:]*:34: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0\],z0\.b,z0\.b'
+[^:]*:35: Error: starting offset is not a multiple of 4 at operand 1 -- `fmlall za\.s\[w8,2:5\],z0\.b,z0\.b'
+[^:]*:36: Error: immediate offset out of range 0 to 12 at operand 1 -- `fmlall za\.s\[w8,16:19\],z0\.b,z0\.b'
+[^:]*:37: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0:1\],z0\.b,z0\.b'
+[^:]*:38: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w7,0\],z0\.b,z0\.b'
+[^:]*:39: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w12,0\],z0\.b,z0\.b'
+[^:]*:40: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0,VGx4\],z0\.b,z0\.b'
+[^:]*:42: Error: z0-z15 expected at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z1\.b},z16\.b'
+[^:]*:43: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b'
+[^:]*:44: Error: starting offset is not a multiple of 4 at operand 1 -- `fmlall za\.s\[w8,2:5\],{z0\.b-z1\.b},z0\.b'
+[^:]*:45: Error: immediate offset out of range 0 to 4 at operand 1 -- `fmlall za\.s\[w8,8:11\],{z0\.b-z1\.b},z0\.b'
+[^:]*:46: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0:1\],{z0\.b-z1\.b},z0\.b'
+[^:]*:47: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w7,0:3\],{z0\.b-z1\.b},z0\.b'
+[^:]*:48: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w12,0:3\],{z0\.b-z1\.b},z0\.b'
+[^:]*:49: Error: expected a list of 4 registers at operand 2 -- `fmlall za\.s\[w8,0:3,VGx4\],{z0\.b-z1\.b},z0\.b'
+[^:]*:51: Error: z0-z15 expected at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z3\.b},z16\.b'
+[^:]*:52: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b'
+[^:]*:53: Error: starting offset is not a multiple of 4 at operand 1 -- `fmlall za\.s\[w8,2:5\],{z0\.b-z3\.b},z0\.b'
+[^:]*:54: Error: immediate offset out of range 0 to 4 at operand 1 -- `fmlall za\.s\[w8,8:11\],{z0\.b-z3\.b},z0\.b'
+[^:]*:55: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0:1\],{z0\.b-z3\.b},z0\.b'
+[^:]*:56: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w7,0:3\],{z0\.b-z3\.b},z0\.b'
+[^:]*:57: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w12,0:3\],{z0\.b-z3\.b},z0\.b'
+[^:]*:58: Error: expected a list of 2 registers at operand 2 -- `fmlall za\.s\[w8,0:3,VGx2\],{z0\.b-z3\.b},z0\.b'
+[^:]*:60: Error: expected a list of 2 registers at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z1\.b},{z0\.b-z3\.b}'
+[^:]*:61: Error: start register out of range at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z1\.b},{z1\.b-z2\.b}'
+[^:]*:62: Error: start register out of range at operand 2 -- `fmlall za\.s\[w8,0:3\],{z1\.b-z2\.b},{z0\.b-z1\.b}'
+[^:]*:63: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w7,0:3\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^:]*:64: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w12,0:3\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^:]*:65: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^:]*:66: Error: starting offset is not a multiple of 4 at operand 1 -- `fmlall za\.s\[w8,2:5\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^:]*:67: Error: immediate offset out of range 0 to 4 at operand 1 -- `fmlall za\.s\[w8,8:11\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^:]*:68: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0:1\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^:]*:70: Error: expected a list of 4 registers at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z3\.b},{z0\.b-z1\.b}'
+[^:]*:71: Error: start register out of range at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z3\.b},{z2\.b-z5\.b}'
+[^:]*:72: Error: start register out of range at operand 2 -- `fmlall za\.s\[w8,0:3\],{z2\.b-z5\.b},{z0\.b-z3\.b}'
+[^:]*:73: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w7,0:3\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^:]*:74: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w12,0:3\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^:]*:75: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^:]*:76: Error: starting offset is not a multiple of 4 at operand 1 -- `fmlall za\.s\[w8,2:5\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^:]*:77: Error: immediate offset out of range 0 to 4 at operand 1 -- `fmlall za\.s\[w8,8:11\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^:]*:78: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0:1\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
diff --git a/gas/testsuite/gas/aarch64/fp8-sme-fmlall-illegal.s b/gas/testsuite/gas/aarch64/fp8-sme-fmlall-illegal.s
new file mode 100644
index 00000000000..9d4f36a5db5
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sme-fmlall-illegal.s
@@ -0,0 +1,78 @@
+fmlall za.s[w8, 0:3], z0.b, z16.b[0]
+fmlall za.s[w8, 0:3, VGx2], z0.b, z0.b[0]
+fmlall za.s[w8, 0:3], z0.b, z0.b[16]
+fmlall za.s[w8, 0], z0.b, z0.b[0]
+fmlall za.s[w8, 2:5], z0.b, z0.b[0]
+fmlall za.s[w8, 16:19], z0.b, z0.b[0]
+fmlall za.s[w8, 0:1], z0.b, z0.b[0]
+fmlall za.s[w7, 0:3], z0.b, z0.b[0]
+fmlall za.s[w12, 0:3], z0.b, z0.b[0]
+
+fmlall za.s[w8, 0:3], { z0.b-z1.b }, z16.b[0]
+fmlall za.s[w8, 0:3], { z1.b-z2.b }, z0.b[0]
+fmlall za.s[w8, 0:3, VGx2], { z0.b-z3.b }, z0.b[0]
+fmlall za.s[w8, 0:3], { z0.b-z1.b }, z0.b[16]
+fmlall za.s[w8, 0], { z0.b-z1.b }, z0.b[0]
+fmlall za.s[w8, 2:5], { z0.b-z1.b }, z0.b[0]
+fmlall za.s[w8, 8:11], { z0.b-z1.b }, z0.b[0]
+fmlall za.s[w8, 0:1], { z0.b-z1.b }, z0.b[0]
+fmlall za.s[w7, 0:3], { z0.b-z1.b }, z0.b[0]
+fmlall za.s[w12, 0:3], { z0.b-z1.b }, z0.b[0]
+
+fmlall za.s[w8, 0:3], { z0.b-z3.b }, z16.b[0]
+fmlall za.s[w8, 0:3], { z2.b-z5.b }, z0.b[0]
+fmlall za.s[w8, 0:3, VGx4], { z0.b-z1.b }, z0.b[0]
+fmlall za.s[w8, 0:3], { z0.b-z3.b }, z0.b[16]
+fmlall za.s[w8, 0], { z0.b-z3.b }, z0.b[0]
+fmlall za.s[w8, 2:5], { z0.b-z3.b }, z0.b[0]
+fmlall za.s[w8, 8:11], { z0.b-z3.b }, z0.b[0]
+fmlall za.s[w8, 0:1], { z0.b-z3.b }, z0.b[0]
+fmlall za.s[w7, 0], { z0.b-z3.b }, z0.b[0]
+fmlall za.s[w12, 0], { z0.b-z3.b }, z0.b[0]
+
+fmlall za.s[w8, 0:3], z0.b, z16.b
+fmlall za.s[w8, 0], z0.b, z0.b
+fmlall za.s[w8, 2:5], z0.b, z0.b
+fmlall za.s[w8, 16:19], z0.b, z0.b
+fmlall za.s[w8, 0:1], z0.b, z0.b
+fmlall za.s[w7, 0], z0.b, z0.b
+fmlall za.s[w12, 0], z0.b, z0.b
+fmlall za.s[w8, 0, VGx4], z0.b, z0.b
+
+fmlall za.s[w8, 0:3], { z0.b-z1.b }, z16.b
+fmlall za.s[w8, 0], { z0.b-z1.b }, z0.b
+fmlall za.s[w8, 2:5], { z0.b-z1.b }, z0.b
+fmlall za.s[w8, 8:11], { z0.b-z1.b }, z0.b
+fmlall za.s[w8, 0:1], { z0.b-z1.b }, z0.b
+fmlall za.s[w7, 0:3], { z0.b-z1.b }, z0.b
+fmlall za.s[w12, 0:3], { z0.b-z1.b }, z0.b
+fmlall za.s[w8, 0:3, VGx4], { z0.b-z1.b }, z0.b
+
+fmlall za.s[w8, 0:3], { z0.b-z3.b }, z16.b
+fmlall za.s[w8, 0], { z0.b-z3.b }, z0.b
+fmlall za.s[w8, 2:5], { z0.b-z3.b }, z0.b
+fmlall za.s[w8, 8:11], { z0.b-z3.b }, z0.b
+fmlall za.s[w8, 0:1], { z0.b-z3.b }, z0.b
+fmlall za.s[w7, 0:3], { z0.b-z3.b }, z0.b
+fmlall za.s[w12, 0:3], { z0.b-z3.b }, z0.b
+fmlall za.s[w8, 0:3, VGx2], { z0.b-z3.b }, z0.b
+
+fmlall za.s[w8, 0:3], { z0.b-z1.b }, { z0.b-z3.b}
+fmlall za.s[w8, 0:3], { z0.b-z1.b }, { z1.b-z2.b}
+fmlall za.s[w8, 0:3], { z1.b-z2.b }, { z0.b-z1.b}
+fmlall za.s[w7, 0:3], { z0.b-z1.b }, { z0.b-z1.b}
+fmlall za.s[w12, 0:3], { z0.b-z1.b }, { z0.b-z1.b}
+fmlall za.s[w8, 0], { z0.b-z1.b }, { z0.b-z1.b}
+fmlall za.s[w8, 2:5], { z0.b-z1.b }, { z0.b-z1.b}
+fmlall za.s[w8, 8:11], { z0.b-z1.b }, { z0.b-z1.b}
+fmlall za.s[w8, 0:1], { z0.b-z1.b }, { z0.b-z1.b}
+
+fmlall za.s[w8, 0:3], { z0.b-z3.b }, { z0.b-z1.b}
+fmlall za.s[w8, 0:3], { z0.b-z3.b }, { z2.b-z5.b}
+fmlall za.s[w8, 0:3], { z2.b-z5.b }, { z0.b-z3.b}
+fmlall za.s[w7, 0:3], { z0.b-z3.b }, { z0.b-z3.b}
+fmlall za.s[w12, 0:3], { z0.b-z3.b }, { z0.b-z3.b}
+fmlall za.s[w8, 0], { z0.b-z3.b }, { z0.b-z3.b}
+fmlall za.s[w8, 2:5], { z0.b-z3.b }, { z0.b-z3.b}
+fmlall za.s[w8, 8:11], { z0.b-z3.b }, { z0.b-z3.b}
+fmlall za.s[w8, 0:1], { z0.b-z3.b }, { z0.b-z3.b}
diff --git a/gas/testsuite/gas/aarch64/fp8-sme-fmlall.d b/gas/testsuite/gas/aarch64/fp8-sme-fmlall.d
new file mode 100644
index 00000000000..a87d1345a90
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sme-fmlall.d
@@ -0,0 +1,57 @@
+#as: -march=armv8-a+sme-f8f32
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: c1400000 fmlall za\.s\[w8, 0:3], z0\.b, z0\.b\[0\]
+ *[0-9a-f]+: c1406000 fmlall za\.s\[w11, 0:3], z0\.b, z0\.b\[0\]
+ *[0-9a-f]+: c1400003 fmlall za\.s\[w8, 12:15], z0\.b, z0\.b\[0\]
+ *[0-9a-f]+: c14003e0 fmlall za\.s\[w8, 0:3], z31\.b, z0\.b\[0\]
+ *[0-9a-f]+: c14f0000 fmlall za\.s\[w8, 0:3], z0\.b, z15\.b\[0\]
+ *[0-9a-f]+: c1400c00 fmlall za\.s\[w8, 0:3], z0\.b, z0\.b\[3\]
+ *[0-9a-f]+: c1409c00 fmlall za\.s\[w8, 0:3], z0\.b, z0\.b\[15\]
+ *[0-9a-f]+: c1900020 fmlall za\.s\[w8, 0:3, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1906020 fmlall za\.s\[w11, 0:3, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1900021 fmlall za\.s\[w8, 4:7, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c19003e0 fmlall za\.s\[w8, 0:3, vgx2\], {z30\.b-z31\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c19f0020 fmlall za\.s\[w8, 0:3, vgx2\], {z0\.b-z1\.b}, z15\.b\[0\]
+ *[0-9a-f]+: c1900022 fmlall za\.s\[w8, 0:3, vgx2\], {z0\.b-z1\.b}, z0\.b\[1\]
+ *[0-9a-f]+: c1900426 fmlall za\.s\[w8, 0:3, vgx2\], {z0\.b-z1\.b}, z0\.b\[7\]
+ *[0-9a-f]+: c1900c26 fmlall za\.s\[w8, 0:3, vgx2\], {z0\.b-z1\.b}, z0\.b\[15\]
+ *[0-9a-f]+: c1108040 fmlall za\.s\[w8, 0:3, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c110e040 fmlall za\.s\[w11, 0:3, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1108041 fmlall za\.s\[w8, 4:7, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c11083c0 fmlall za\.s\[w8, 0:3, vgx4\], {z28\.b-z31\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c11f8040 fmlall za\.s\[w8, 0:3, vgx4\], {z0\.b-z3\.b}, z15\.b\[0\]
+ *[0-9a-f]+: c1108042 fmlall za\.s\[w8, 0:3, vgx4\], {z0\.b-z3\.b}, z0\.b\[1\]
+ *[0-9a-f]+: c1108446 fmlall za\.s\[w8, 0:3, vgx4\], {z0\.b-z3\.b}, z0\.b\[7\]
+ *[0-9a-f]+: c1108c46 fmlall za\.s\[w8, 0:3, vgx4\], {z0\.b-z3\.b}, z0\.b\[15\]
+ *[0-9a-f]+: c1300400 fmlall za\.s\[w8, 0:3\], z0\.b, z0\.b
+ *[0-9a-f]+: c1306400 fmlall za\.s\[w11, 0:3\], z0\.b, z0\.b
+ *[0-9a-f]+: c1300403 fmlall za\.s\[w8, 12:15\], z0\.b, z0\.b
+ *[0-9a-f]+: c13007e0 fmlall za\.s\[w8, 0:3\], z31\.b, z0\.b
+ *[0-9a-f]+: c13f0400 fmlall za\.s\[w8, 0:3\], z0\.b, z15\.b
+ *[0-9a-f]+: c1200002 fmlall za\.s\[w8, 0:3, vgx2\], {z0\.b-z1\.b}, z0\.b
+ *[0-9a-f]+: c1206002 fmlall za\.s\[w11, 0:3, vgx2\], {z0\.b-z1\.b}, z0\.b
+ *[0-9a-f]+: c1200003 fmlall za\.s\[w8, 4:7, vgx2\], {z0\.b-z1\.b}, z0\.b
+ *[0-9a-f]+: c12003e2 fmlall za\.s\[w8, 0:3, vgx2\], {z31\.b-z0\.b}, z0\.b
+ *[0-9a-f]+: c12f0002 fmlall za\.s\[w8, 0:3, vgx2\], {z0\.b-z1\.b}, z15\.b
+ *[0-9a-f]+: c1300002 fmlall za\.s\[w8, 0:3, vgx4\], {z0\.b-z3\.b}, z0\.b
+ *[0-9a-f]+: c1306002 fmlall za\.s\[w11, 0:3, vgx4\], {z0\.b-z3\.b}, z0\.b
+ *[0-9a-f]+: c1300003 fmlall za\.s\[w8, 4:7, vgx4\], {z0\.b-z3\.b}, z0\.b
+ *[0-9a-f]+: c13003e2 fmlall za\.s\[w8, 0:3, vgx4\], {z31\.b-z2\.b}, z0\.b
+ *[0-9a-f]+: c13f0002 fmlall za\.s\[w8, 0:3, vgx4\], {z0\.b-z3\.b}, z15\.b
+ *[0-9a-f]+: c1a00020 fmlall za\.s\[w8, 0:3, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
+ *[0-9a-f]+: c1a06020 fmlall za\.s\[w11, 0:3, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
+ *[0-9a-f]+: c1a00021 fmlall za\.s\[w8, 4:7, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
+ *[0-9a-f]+: c1a003e0 fmlall za\.s\[w8, 0:3, vgx2\], {z30\.b-z31\.b}, {z0\.b-z1\.b}
+ *[0-9a-f]+: c1be0020 fmlall za\.s\[w8, 0:3, vgx2\], {z0\.b-z1\.b}, {z30\.b-z31\.b}
+ *[0-9a-f]+: c1a10020 fmlall za\.s\[w8, 0:3, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
+ *[0-9a-f]+: c1a16020 fmlall za\.s\[w11, 0:3, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
+ *[0-9a-f]+: c1a10021 fmlall za\.s\[w8, 4:7, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
+ *[0-9a-f]+: c1a103a0 fmlall za\.s\[w8, 0:3, vgx4\], {z28\.b-z31\.b}, {z0\.b-z3\.b}
+ *[0-9a-f]+: c1bd0020 fmlall za\.s\[w8, 0:3, vgx4\], {z0\.b-z3\.b}, {z28\.b-z31\.b}
diff --git a/gas/testsuite/gas/aarch64/fp8-sme-fmlall.s b/gas/testsuite/gas/aarch64/fp8-sme-fmlall.s
new file mode 100644
index 00000000000..a0fa3a4f97f
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sme-fmlall.s
@@ -0,0 +1,56 @@
+fmlall za.s[w8, 0:3], z0.b, z0.b[0]
+fmlall za.s[w11, 0:3], z0.b, z0.b[0]
+fmlall za.s[w8, 12:15], z0.b, z0.b[0]
+fmlall za.s[w8, 0:3], z31.b, z0.b[0]
+fmlall za.s[w8, 0:3], z0.b, z15.b[0]
+fmlall za.s[w8, 0:3], z0.b, z0.b[3]
+fmlall za.s[w8, 0:3], z0.b, z0.b[15]
+
+fmlall za.s[w8, 0:3], {z0.b-z1.b }, z0.b[0]
+fmlall za.s[w11, 0:3, VGx2], { z0.b-z1.b}, z0.b[0]
+fmlall za.s[w8, 4:7], {z0.b - z1.b}, z0.b[0]
+fmlall za.s[w8, 0:3], { z30.b-z31.b}, z0.b[0]
+fmlall za.s[w8, 0:3], { z0.b - z1.b}, z15.b[0]
+fmlall za.s[w8, 0:3], { z0.b - z1.b }, z0.b[1]
+fmlall za.s[w8, 0:3], { z0.b - z1.b }, z0.b[7]
+fmlall za.s[w8, 0:3], { z0.b - z1.b }, z0.b[15]
+
+fmlall za.s[w8, 0:3], {z0.b-z3.b }, z0.b[0]
+fmlall za.s[w11, 0:3, VGx4], { z0.b-z3.b}, z0.b[0]
+fmlall za.s[w8, 4:7], {z0.b - z3.b}, z0.b[0]
+fmlall za.s[w8, 0:3], { z28.b-z31.b}, z0.b[0]
+fmlall za.s[w8, 0:3], { z0.b - z3.b}, z15.b[0]
+fmlall za.s[w8, 0:3], { z0.b - z3.b }, z0.b[1]
+fmlall za.s[w8, 0:3], { z0.b - z3.b }, z0.b[7]
+fmlall za.s[w8, 0:3], { z0.b - z3.b }, z0.b[15]
+
+fmlall za.s[w8, 0:3], z0.b, z0.b
+fmlall za.s[w11, 0:3], z0.b, z0.b
+fmlall za.s[w8, 12:15], z0.b, z0.b
+fmlall za.s[w8, 0:3], z31.b, z0.b
+fmlall za.s[w8, 0:3], z0.b, z15.b
+
+fmlall za.s[w8, 0:3], {z0.b -z1.b}, z0.b
+fmlall za.s[w11, 0:3], {z0.b-z1.b}, z0.b
+fmlall za.s[w8, 4:7], { z0.b - z1.b }, z0.b
+fmlall za.s[w8, 0:3, VGx2], {z31.b - z0.b}, z0.b
+fmlall za.s[w8, 0:3], {z0.b - z1.b}, z15.b
+
+fmlall za.s[w8, 0:3], {z0.b -z3.b}, z0.b
+fmlall za.s[w11, 0:3], {z0.b-z3.b}, z0.b
+fmlall za.s[w8, 4:7], { z0.b - z3.b }, z0.b
+fmlall za.s[w8, 0:3, VGx4], {z31.b - z2.b}, z0.b
+fmlall za.s[w8, 0:3], {z0.b - z3.b}, z15.b
+
+fmlall za.s[w8, 0:3], {z0.b -z1.b}, {z0.b-z1.b}
+fmlall za.s[w11, 0:3], {z0.b-z1.b}, {z0.b - z1.b}
+fmlall za.s[w8, 4:7], { z0.b - z1.b }, {z0.b -z1.b}
+fmlall za.s[w8, 0:3, VGx2], {z30.b - z31.b}, {z0.b-z1.b}
+fmlall za.s[w8, 0:3], {z0.b - z1.b}, {z30.b -z31.b}
+
+fmlall za.s[w8, 0:3], {z0.b -z3.b}, {z0.b-z3.b}
+fmlall za.s[w11, 0:3], {z0.b-z3.b}, {z0.b - z3.b}
+fmlall za.s[w8, 4:7], { z0.b - z3.b }, {z0.b-z3.b}
+fmlall za.s[w8, 0:3, VGx4], {z28.b - z31.b}, {z0.b-z3.b}
+fmlall za.s[w8, 0:3], {z0.b - z3.b}, {z28.b-z31.b}
+
diff --git a/gas/testsuite/gas/aarch64/fp8-sme-mopa-illegal.d b/gas/testsuite/gas/aarch64/fp8-sme-mopa-illegal.d
new file mode 100644
index 00000000000..38b71a726d6
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sme-mopa-illegal.d
@@ -0,0 +1,2 @@
+#as: -march=armv8-a+sme-f8f16
+#error_output: fp8-sme-mopa-illegal.l
diff --git a/gas/testsuite/gas/aarch64/fp8-sme-mopa-illegal.l b/gas/testsuite/gas/aarch64/fp8-sme-mopa-illegal.l
new file mode 100644
index 00000000000..47f3765c072
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sme-mopa-illegal.l
@@ -0,0 +1,7 @@
+[^:]*: Assembler messages:
+[^:]*:1: Error: ZA tile number out of range at operand 1 -- `fmopa za2\.h,p0/m,p0/m,z0\.b,z0\.b'
+[^:]*:2: Error: p0-p7 expected at operand 2 -- `fmopa za0\.h,p8/m,p0/m,z0\.b,z0\.b'
+[^:]*:3: Error: p0-p7 expected at operand 3 -- `fmopa za0\.h,p0/m,p8/m,z0\.b,z0\.b'
+[^:]*:5: Error: ZA tile number out of range at operand 1 -- `fmopa za4\.s,p0/m,p0/m,z0\.b,z0\.b'
+[^:]*:6: Error: p0-p7 expected at operand 2 -- `fmopa za0\.s,p8/m,p0/m,z0\.b,z0\.b'
+[^:]*:7: Error: p0-p7 expected at operand 3 -- `fmopa za0\.s,p0/m,p8/m,z0\.b,z0\.b'
diff --git a/gas/testsuite/gas/aarch64/fp8-sme-mopa-illegal.s b/gas/testsuite/gas/aarch64/fp8-sme-mopa-illegal.s
new file mode 100644
index 00000000000..3c0122eb40b
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sme-mopa-illegal.s
@@ -0,0 +1,7 @@
+fmopa za2.h, p0/m, p0/m, z0.b, z0.b
+fmopa za0.h, p8/m, p0/m, z0.b, z0.b
+fmopa za0.h, p0/m, p8/m, z0.b, z0.b
+
+fmopa za4.s, p0/m, p0/m, z0.b, z0.b
+fmopa za0.s, p8/m, p0/m, z0.b, z0.b
+fmopa za0.s, p0/m, p8/m, z0.b, z0.b
diff --git a/gas/testsuite/gas/aarch64/fp8-sme-mopa2.d b/gas/testsuite/gas/aarch64/fp8-sme-mopa2.d
new file mode 100644
index 00000000000..c27ff5b6482
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sme-mopa2.d
@@ -0,0 +1,15 @@
+#as: -march=armv8-a+sme-f8f16
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: 80a00008 fmopa za0\.h, p0/m, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+: 80a00009 fmopa za1\.h, p0/m, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+: 80a01c08 fmopa za0\.h, p7/m, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+: 80a0e008 fmopa za0\.h, p0/m, p7/m, z0\.b, z0\.b
+ *[0-9a-f]+: 80a003e8 fmopa za0\.h, p0/m, p0/m, z31\.b, z0\.b
+ *[0-9a-f]+: 80bf0008 fmopa za0\.h, p0/m, p0/m, z0\.b, z31\.b
diff --git a/gas/testsuite/gas/aarch64/fp8-sme-mopa2.s b/gas/testsuite/gas/aarch64/fp8-sme-mopa2.s
new file mode 100644
index 00000000000..0fa8622cb36
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sme-mopa2.s
@@ -0,0 +1,6 @@
+fmopa za0.h, p0/m, p0/m, z0.b, z0.b
+fmopa za1.h, p0/m, p0/m, z0.b, z0.b
+fmopa za0.h, p7/m, p0/m, z0.b, z0.b
+fmopa za0.h, p0/m, p7/m, z0.b, z0.b
+fmopa za0.h, p0/m, p0/m, z31.b, z0.b
+fmopa za0.h, p0/m, p0/m, z0.b, z31.b
diff --git a/gas/testsuite/gas/aarch64/fp8-sme-mopa4.d b/gas/testsuite/gas/aarch64/fp8-sme-mopa4.d
new file mode 100644
index 00000000000..c7448e6c165
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sme-mopa4.d
@@ -0,0 +1,15 @@
+#as: -march=armv8-a+sme-f8f32
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: 80a00000 fmopa za0\.s, p0/m, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+: 80a00003 fmopa za3\.s, p0/m, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+: 80a01c00 fmopa za0\.s, p7/m, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+: 80a0e000 fmopa za0\.s, p0/m, p7/m, z0\.b, z0\.b
+ *[0-9a-f]+: 80a003e0 fmopa za0\.s, p0/m, p0/m, z31\.b, z0\.b
+ *[0-9a-f]+: 80bf0000 fmopa za0\.s, p0/m, p0/m, z0\.b, z31\.b
diff --git a/gas/testsuite/gas/aarch64/fp8-sme-mopa4.s b/gas/testsuite/gas/aarch64/fp8-sme-mopa4.s
new file mode 100644
index 00000000000..e68c7562b56
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sme-mopa4.s
@@ -0,0 +1,6 @@
+fmopa za0.s, p0/m, p0/m, z0.b, z0.b
+fmopa za3.s, p0/m, p0/m, z0.b, z0.b
+fmopa za0.s, p7/m, p0/m, z0.b, z0.b
+fmopa za0.s, p0/m, p7/m, z0.b, z0.b
+fmopa za0.s, p0/m, p0/m, z31.b, z0.b
+fmopa za0.s, p0/m, p0/m, z0.b, z31.b
diff --git a/gas/testsuite/gas/aarch64/sme-fp16-addsub-illegal.d b/gas/testsuite/gas/aarch64/sme-fp16-addsub-illegal.d
new file mode 100644
index 00000000000..4dcdeb7458d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-fp16-addsub-illegal.d
@@ -0,0 +1,2 @@
+#as: -march=armv8-a+sme-f8f16
+#error_output: sme-fp16-addsub-illegal.l
diff --git a/gas/testsuite/gas/aarch64/sme-fp16-addsub-illegal.l b/gas/testsuite/gas/aarch64/sme-fp16-addsub-illegal.l
new file mode 100644
index 00000000000..b35c7c98b40
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-fp16-addsub-illegal.l
@@ -0,0 +1,19 @@
+[^:]*: Assembler messages:
+[^:]*:1: Error: expected a selection register in the range w8-w11 at operand 1 -- `fadd za\.h\[w7,0\],{z0\.h-z1\.h}'
+[^:]*:2: Error: expected a selection register in the range w8-w11 at operand 1 -- `fadd za\.h\[w12,0\],{z0\.h-z1\.h}'
+[^:]*:3: Error: immediate offset out of range 0 to 7 at operand 1 -- `fadd za\.h\[w8,8\],{z0\.h-z1\.h}'
+[^:]*:4: Error: start register out of range at operand 2 -- `fadd za\.h\[w8,0\],{z1\.h-z2\.h}'
+[^:]*:6: Error: expected a selection register in the range w8-w11 at operand 1 -- `fadd za\.h\[w7,0\],{z0\.h-z3\.h}'
+[^:]*:7: Error: expected a selection register in the range w8-w11 at operand 1 -- `fadd za\.h\[w12,0\],{z0\.h-z3\.h}'
+[^:]*:8: Error: immediate offset out of range 0 to 7 at operand 1 -- `fadd za\.h\[w8,8\],{z0\.h-z3\.h}'
+[^:]*:9: Error: start register out of range at operand 2 -- `fadd za\.h\[w8,0\],{z2\.h-z5\.h}'
+[^:]*:11: Error: missing braces at operand 2 -- `fadd za\.h\[w0,0\],z0\.h'
+[^:]*:13: Error: expected a selection register in the range w8-w11 at operand 1 -- `fsub za\.h\[w7,0\],{z0\.h-z1\.h}'
+[^:]*:14: Error: expected a selection register in the range w8-w11 at operand 1 -- `fsub za\.h\[w12,0\],{z0\.h-z1\.h}'
+[^:]*:15: Error: immediate offset out of range 0 to 7 at operand 1 -- `fsub za\.h\[w8,8\],{z0\.h-z1\.h}'
+[^:]*:16: Error: start register out of range at operand 2 -- `fsub za\.h\[w8,0\],{z1\.h-z2\.h}'
+[^:]*:18: Error: expected a selection register in the range w8-w11 at operand 1 -- `fsub za\.h\[w7,0\],{z0\.h-z3\.h}'
+[^:]*:19: Error: expected a selection register in the range w8-w11 at operand 1 -- `fsub za\.h\[w12,0\],{z0\.h-z3\.h}'
+[^:]*:20: Error: immediate offset out of range 0 to 7 at operand 1 -- `fsub za\.h\[w8,8\],{z0\.h-z3\.h}'
+[^:]*:21: Error: start register out of range at operand 2 -- `fsub za\.h\[w8,0\],{z2\.h-z5\.h}'
+[^:]*:23: Error: missing braces at operand 2 -- `fsub za\.h\[w0,0\],z0\.h'
diff --git a/gas/testsuite/gas/aarch64/sme-fp16-addsub-illegal.s b/gas/testsuite/gas/aarch64/sme-fp16-addsub-illegal.s
new file mode 100644
index 00000000000..02445461202
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-fp16-addsub-illegal.s
@@ -0,0 +1,24 @@
+fadd za.h[w7, 0], {z0.h-z1.h}
+fadd za.h[w12, 0], {z0.h-z1.h}
+fadd za.h[w8, 8], {z0.h-z1.h}
+fadd za.h[w8, 0], {z1.h-z2.h}
+
+fadd za.h[w7, 0], {z0.h-z3.h}
+fadd za.h[w12, 0], {z0.h-z3.h}
+fadd za.h[w8, 8], {z0.h-z3.h}
+fadd za.h[w8, 0], {z2.h-z5.h}
+
+fadd za.h[w0, 0], z0.h
+
+fsub za.h[w7, 0], {z0.h-z1.h}
+fsub za.h[w12, 0], {z0.h-z1.h}
+fsub za.h[w8, 8], {z0.h-z1.h}
+fsub za.h[w8, 0], {z1.h-z2.h}
+
+fsub za.h[w7, 0], {z0.h-z3.h}
+fsub za.h[w12, 0], {z0.h-z3.h}
+fsub za.h[w8, 8], {z0.h-z3.h}
+fsub za.h[w8, 0], {z2.h-z5.h}
+
+fsub za.h[w0, 0], z0.h
+
diff --git a/gas/testsuite/gas/aarch64/sme-fp16-addsub.d b/gas/testsuite/gas/aarch64/sme-fp16-addsub.d
new file mode 100644
index 00000000000..81d8f2ed227
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-fp16-addsub.d
@@ -0,0 +1,25 @@
+#as: -march=armv8-a+sme-f8f16
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: c1a41c00 fadd za\.h\[w8, 0, vgx2\], {z0\.h-z1\.h}
+ *[0-9a-f]+: c1a47c00 fadd za\.h\[w11, 0, vgx2\], {z0\.h-z1\.h}
+ *[0-9a-f]+: c1a41c07 fadd za\.h\[w8, 7, vgx2\], {z0\.h-z1\.h}
+ *[0-9a-f]+: c1a41fc0 fadd za\.h\[w8, 0, vgx2\], {z30\.h-z31\.h}
+ *[0-9a-f]+: c1a51c00 fadd za\.h\[w8, 0, vgx4\], {z0\.h-z3\.h}
+ *[0-9a-f]+: c1a57c00 fadd za\.h\[w11, 0, vgx4\], {z0\.h-z3\.h}
+ *[0-9a-f]+: c1a51c07 fadd za\.h\[w8, 7, vgx4\], {z0\.h-z3\.h}
+ *[0-9a-f]+: c1a51f80 fadd za\.h\[w8, 0, vgx4\], {z28\.h-z31\.h}
+ *[0-9a-f]+: c1a41c08 fsub za\.h\[w8, 0, vgx2\], {z0\.h-z1\.h}
+ *[0-9a-f]+: c1a47c08 fsub za\.h\[w11, 0, vgx2\], {z0\.h-z1\.h}
+ *[0-9a-f]+: c1a41c0f fsub za\.h\[w8, 7, vgx2\], {z0\.h-z1\.h}
+ *[0-9a-f]+: c1a41fc8 fsub za\.h\[w8, 0, vgx2\], {z30\.h-z31\.h}
+ *[0-9a-f]+: c1a51c08 fsub za\.h\[w8, 0, vgx4\], {z0\.h-z3\.h}
+ *[0-9a-f]+: c1a57c08 fsub za\.h\[w11, 0, vgx4\], {z0\.h-z3\.h}
+ *[0-9a-f]+: c1a51c0f fsub za\.h\[w8, 7, vgx4\], {z0\.h-z3\.h}
+ *[0-9a-f]+: c1a51f88 fsub za\.h\[w8, 0, vgx4\], {z28\.h-z31\.h}
diff --git a/gas/testsuite/gas/aarch64/sme-fp16-addsub.s b/gas/testsuite/gas/aarch64/sme-fp16-addsub.s
new file mode 100644
index 00000000000..ae64131b2f1
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-fp16-addsub.s
@@ -0,0 +1,19 @@
+fadd za.h[w8, 0], {z0.h-z1.h}
+fadd za.h[w11, 0], {z0.h-z1.h}
+fadd za.h[w8, 7], {z0.h-z1.h}
+fadd za.h[w8, 0], {z30.h-z31.h}
+
+fadd za.h[w8, 0], {z0.h-z3.h}
+fadd za.h[w11, 0], {z0.h-z3.h}
+fadd za.h[w8, 7], {z0.h-z3.h}
+fadd za.h[w8, 0], {z28.h-z31.h}
+
+fsub za.h[w8, 0], {z0.h-z1.h}
+fsub za.h[w11, 0], {z0.h-z1.h}
+fsub za.h[w8, 7], {z0.h-z1.h}
+fsub za.h[w8, 0], {z30.h-z31.h}
+
+fsub za.h[w8, 0], {z0.h-z3.h}
+fsub za.h[w11, 0], {z0.h-z3.h}
+fsub za.h[w8, 7], {z0.h-z3.h}
+fsub za.h[w8, 0], {z28.h-z31.h}
diff --git a/gas/testsuite/gas/aarch64/sme2-18-invalid.l b/gas/testsuite/gas/aarch64/sme2-18-invalid.l
index 6a1b77a1494..ea824cbcf4c 100644
--- a/gas/testsuite/gas/aarch64/sme2-18-invalid.l
+++ b/gas/testsuite/gas/aarch64/sme2-18-invalid.l
@@ -6,7 +6,7 @@
[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `fvdot za\.h\[w8,0\],{z0\.h-z1\.h},z0\.h'
[^ :]+:[0-9]+: Error: operand mismatch -- `fvdot za\.s\[w8,0\],{z0\.b-z1\.h},z0\.b\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: fvdot za\.s\[w8, 0\], {z0\.h-z1\.h}, z0\.h\[0\]
+[^ :]+:[0-9]+: Info: fvdot za\.h\[w8, 0\], {z0\.b-z1\.b}, z0\.b\[0\]
[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `fvdot za\.s\[w8,0:1\],{z0\.h-z1\.h},z0\.h\[0\]'
[^ :]+:[0-9]+: Error: operand 1 must have a vector group size of 2 -- `fvdot za\.s\[w8,0,vgx4\],{z0\.h-z1\.h},z0\.h\[0\]'
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fvdot za\.s\[w7,0\],{z0\.h-z1\.h},z0\.h\[0\]'
diff --git a/gas/testsuite/gas/aarch64/sme2-9-invalid.l b/gas/testsuite/gas/aarch64/sme2-9-invalid.l
index e181f0b7378..0063e940742 100644
--- a/gas/testsuite/gas/aarch64/sme2-9-invalid.l
+++ b/gas/testsuite/gas/aarch64/sme2-9-invalid.l
@@ -172,8 +172,4 @@
[^ :]+:[0-9]+: Info: fadd za\.s\[w8, 0\], {z0\.s-z1\.s}
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: fadd za\.d\[w8, 0\], {z0\.d-z1\.d}
-[^ :]+:[0-9]+: Error: operand mismatch -- `fadd za\.h\[w8,0\],{z0\.h-z1\.h}'
-[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: fadd za\.s\[w8, 0\], {z0\.s-z1\.s}
-[^ :]+:[0-9]+: Info: other valid variant\(s\):
-[^ :]+:[0-9]+: Info: fadd za\.d\[w8, 0\], {z0\.d-z1\.d}
+[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.h\[w8,0\],{z0\.h-z1\.h}'
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 4168082c7f7..19dadaa18ec 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -254,6 +254,10 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_SSVE_FP8DOT4,
/* SSVE FP8DOT2 instructions. */
AARCH64_FEATURE_SSVE_FP8DOT2,
+ /* SME F8F32 instructions. */
+ AARCH64_FEATURE_SME_F8F32,
+ /* SME F8F16 instructions. */
+ AARCH64_FEATURE_SME_F8F16,
/* Virtual features. These are used to gate instructions that are enabled
by either of two (or more) sets of command line flags. */
@@ -263,6 +267,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_FP8DOT4_SVE,
/* +fp8dot2+sve or +ssve-fp8dot2 */
AARCH64_FEATURE_FP8DOT2_SVE,
+ /* +sme-f16f16 or +sme-f8f16 */
+ AARCH64_FEATURE_SME_F16F16_F8F16,
AARCH64_NUM_FEATURES
};
@@ -795,6 +801,7 @@ enum aarch64_opnd
AARCH64_OPND_SME_Znx4, /* SVE vector register list from [9:7]*4. */
AARCH64_OPND_SME_Ztx2_STRIDED, /* SVE vector register list in [4:0]&23. */
AARCH64_OPND_SME_Ztx4_STRIDED, /* SVE vector register list in [4:0]&19. */
+ AARCH64_OPND_SME_ZAda_1b, /* SME <ZAda>.H, 1-bits. */
AARCH64_OPND_SME_ZAda_2b, /* SME <ZAda>.S, 2-bits. */
AARCH64_OPND_SME_ZAda_3b, /* SME <ZAda>.D, 3-bits. */
AARCH64_OPND_SME_ZA_HV_idx_src, /* SME source ZA tile vector. */
@@ -825,10 +832,14 @@ enum aarch64_opnd
AARCH64_OPND_SME_SHRIMM5, /* size + 5-bit right shift, bits [23:22,20:16]. */
AARCH64_OPND_SME_Zm_INDEX1, /* Zn.T[index], bits [19:16,10]. */
AARCH64_OPND_SME_Zm_INDEX2, /* Zn.T[index], bits [19:16,11:10]. */
+ AARCH64_OPND_SME_Zm_INDEX2_3, /* Zn.T[index], bits [19:16,10,3]. */
AARCH64_OPND_SME_Zm_INDEX3_1, /* Zn.T[index], bits [19:16,10,2:1]. */
AARCH64_OPND_SME_Zm_INDEX3_2, /* Zn.T[index], bits [19:16,11:10,2]. */
+ AARCH64_OPND_SME_Zm_INDEX3_3, /* Zn.T[index], bits [19:16,11:10,3]. */
AARCH64_OPND_SME_Zm_INDEX3_10, /* Zn.T[index], bits [19:16,15,11:10]. */
AARCH64_OPND_SME_Zm_INDEX4_1, /* Zn.T[index], bits [19:16,11:10,2:1]. */
+ AARCH64_OPND_SME_Zm_INDEX4_2, /* Zn.T[index], bits [19:16,11:10,3:2]. */
+ AARCH64_OPND_SME_Zm_INDEX4_3, /* Zn.T[index], bits [19:16,15,11,10,3]. */
AARCH64_OPND_SME_Zm_INDEX4_10, /* Zn.T[index], bits [19:16,15,12:10]. */
AARCH64_OPND_SME_Zn_INDEX1_16, /* Zn[index], bits [9:5] and [16:16]. */
AARCH64_OPND_SME_Zn_INDEX2_15, /* Zn[index], bits [9:5] and [16:15]. */
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 94e8218feda..7578093b938 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -682,16 +682,17 @@ aarch64_insert_operand (const aarch64_operand *self,
case 248:
case 256:
case 257:
- case 264:
+ case 258:
case 265:
case 266:
case 267:
+ case 268:
return aarch64_ins_regno (self, info, code, inst, errors);
case 6:
case 119:
case 120:
- case 299:
- case 302:
+ case 304:
+ case 307:
return aarch64_ins_none (self, info, code, inst, errors);
case 17:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -706,7 +707,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 37:
case 38:
case 39:
- case 304:
+ case 309:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 40:
case 41:
@@ -714,9 +715,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 228:
case 229:
case 232:
- case 268:
case 269:
- case 284:
+ case 270:
case 285:
case 286:
case 287:
@@ -729,6 +729,11 @@ aarch64_insert_operand (const aarch64_operand *self,
case 294:
case 295:
case 296:
+ case 297:
+ case 298:
+ case 299:
+ case 300:
+ case 301:
return aarch64_ins_simple_index (self, info, code, inst, errors);
case 43:
return aarch64_ins_reglist (self, info, code, inst, errors);
@@ -777,14 +782,14 @@ aarch64_insert_operand (const aarch64_operand *self,
case 208:
case 209:
case 210:
- case 270:
- case 297:
- case 298:
- case 300:
- case 301:
+ case 271:
+ case 302:
case 303:
+ case 305:
+ case 306:
case 308:
- case 309:
+ case 313:
+ case 314:
return aarch64_ins_imm (self, info, code, inst, errors);
case 52:
case 53:
@@ -932,7 +937,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 200:
case 201:
case 202:
- case 283:
+ case 284:
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
case 215:
case 216:
@@ -959,10 +964,10 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_sve_index (self, info, code, inst, errors);
case 242:
case 244:
- case 263:
- case 310:
- case 311:
- case 312:
+ case 264:
+ case 315:
+ case 316:
+ case 317:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
case 245:
case 246:
@@ -971,45 +976,45 @@ aarch64_insert_operand (const aarch64_operand *self,
case 251:
case 252:
case 253:
- case 262:
+ case 263:
return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
case 247:
case 254:
case 255:
return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors);
- case 258:
- case 260:
- case 271:
- return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
case 259:
case 261:
- return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
case 272:
+ return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
+ case 260:
+ case 262:
+ return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
case 273:
case 274:
case 275:
case 276:
case 277:
case 278:
- return aarch64_ins_sme_za_array (self, info, code, inst, errors);
case 279:
- return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
+ return aarch64_ins_sme_za_array (self, info, code, inst, errors);
case 280:
- return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
+ return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 281:
- return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+ return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
case 282:
+ return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+ case 283:
return aarch64_ins_plain_shrimm (self, info, code, inst, errors);
- case 305:
- case 306:
- case 307:
+ case 310:
+ case 311:
+ case 312:
return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
- case 313:
- case 314:
- case 315:
- case 316:
+ case 318:
+ case 319:
+ case 320:
+ case 321:
return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
- case 317:
+ case 322:
return aarch64_ins_rcpc3_addr_offset (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index d3274222e4c..d16a43bbdf9 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -1149,21 +1149,43 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 4) & 0x1) == 0)
{
- if (((word >> 30) & 0x1) == 0)
+ if (((word >> 29) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x0x00000101xxxxxxxxxxxxxxxx0xxxx
- sumopa. */
- return 2424;
+ if (((word >> 3) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx000000101xxxxxxxxxxxxxxxx00xxx
+ fmopa. */
+ return 3462;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx000000101xxxxxxxxxxxxxxxx01xxx
+ fmopa. */
+ return 3461;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1x00000101xxxxxxxxxxxxxxxx0xxxx
- st1w. */
- return 2453;
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000101xxxxxxxxxxxxxxxx0xxxx
+ sumopa. */
+ return 2424;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1100000101xxxxxxxxxxxxxxxx0xxxx
+ st1w. */
+ return 2453;
+ }
}
}
else
@@ -1427,13 +1449,13 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 29) & 0x1) == 0)
{
- if (((word >> 3) & 0x1) == 0)
+ if (((word >> 4) & 0x1) == 0)
{
- if (((word >> 4) & 0x1) == 0)
+ if (((word >> 20) & 0x1) == 0)
{
- if (((word >> 20) & 0x1) == 0)
+ if (((word >> 2) & 0x1) == 0)
{
- if (((word >> 2) & 0x1) == 0)
+ if (((word >> 3) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
@@ -1445,54 +1467,109 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xx0000010000xxxxxxxxxxxxxxx001xx
- usmlall. */
- return 2932;
+ xx0000010000xxxxxxxxxxxxxxx010xx
+ smlsll. */
+ return 2743;
}
}
else
{
- if (((word >> 5) & 0x1) == 0)
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010000xxxxxxxxxxxxxxx0x1xx
+ usmlall. */
+ return 2932;
+ }
+ }
+ else
+ {
+ if (((word >> 5) & 0x1) == 0)
+ {
+ if (((word >> 12) & 0x1) == 0)
{
- if (((word >> 15) & 0x1) == 0)
+ if (((word >> 3) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000010001xxxx0xxxxxxxxx000xxx
- smlall. */
- return 2728;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx0xx0xxxxxx000xxx
+ smlall. */
+ return 2728;
+ }
+ else
+ {
+ if (((word >> 6) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx1xx0xxxxx0000xxx
+ smlall. */
+ return 2729;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx1xx0xxxxx1000xxx
+ fmlall. */
+ return 3455;
+ }
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000010001xxxx1xxxxxxxxx000xxx
- smlall. */
- return 2729;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx0xx0xxxxxx001xxx
+ smlsll. */
+ return 2744;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx1xx0xxxxxx001xxx
+ smlsll. */
+ return 2745;
+ }
}
}
else
{
- if (((word >> 15) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000010001xxxx0xxxxxxxxx100xxx
- [...]
[diff truncated at 100000 bytes]
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