From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2098) id 4DFAC38432F1; Tue, 25 Jun 2024 12:39:19 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4DFAC38432F1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1719319159; bh=jD39TnZ0siKQ4Fi6Y880Q5Q4jvfLezQP2/uTPeaux2U=; h=From:To:Subject:Date:From; b=jQWEpKLXgnfuRLacMa+lM7wP2Qr9ib4If/c8EqwVR2jbs6b6I7yjOo7FjTTjKi3oM oxaE2SLY34k029FLEB7ks8D8nfEDrIgbdqrmMuVCIvmJsg95dt9uUQWRML8ImEPUzs ayo4SpKup6FSsUoa09xyF7IEfqg6oB1wQ+V2JnIA= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: SRINATH PARVATHANENI To: binutils-cvs@sourceware.org Subject: [binutils-gdb] aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands. X-Act-Checkin: binutils-gdb X-Git-Author: Srinath Parvathaneni X-Git-Refname: refs/heads/master X-Git-Oldrev: f50b1a3c1f9514efdff6d808b2700eb18ab55630 X-Git-Newrev: 4f2cb9d129f8a5eba81379b70322d013b670045c Message-Id: <20240625123919.4DFAC38432F1@sourceware.org> Date: Tue, 25 Jun 2024 12:39:19 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D4f2cb9d129f8= a5eba81379b70322d013b670045c commit 4f2cb9d129f8a5eba81379b70322d013b670045c Author: Srinath Parvathaneni Date: Tue Jun 25 12:58:27 2024 +0100 aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands. =20 This patch fixes encoding and syntax for sve2p1 instructions ld[1-4]q/s= t[1-4]q as mentioned below, for the issues reported here. https://sourceware.org/pipermail/binutils/2024-February/132408.html =20 1) Previously all the ld[1-4]q/st[1-4]q instructions are wrongly added = as predicated instructions and this issue is fixed in this patch by replac= ing "SVE2p1_INSNC" with "SVE2p1_INSN" macro. 2) Wrong first operand in all the ld[1-4]q/st[1-4]q instructions is fix= ed by replacing "SVE_Zt" with "SVE_ZtxN". 3) Wrong operand qualifiers in ld1q and st1q instructions are also fixe= d in this patch. 4) In ld1q/st1q the index in the second argument is optional and if ind= ex is xzr and is skipped in the assembly, the index field is ignored by= the disassembler. =20 Fixing above mentioned issues helps with following: 1) ld1q and st1q first register operand accepts enclosed figure braces. 2) ld2q, ld3q, ld4q, st2q, st3q, and st4q instructions accepts wrapping sequence of vector registers. =20 For the instructions ld[2-4]q/st[2-4]q, tests for wrapping sequence of = vector registers are added along with short-form of operands for non-wrapping = sequence. =20 I have added test using following logic: ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #0, MUL VL] //raw insn encoding (all ze= roes) ld2q {Z31.Q, Z0.Q}, p0/Z, [x0, #0, MUL VL] // encoding of ld2q {Z0.Q, Z1.Q}, p7/Z, [x0, #0, MUL VL] // encoding of ld2q {Z0.Q, Z1.Q}, p0/Z, [x30, #0, MUL VL] // encoding of ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #-16, MUL VL] // encoding of (low = value) ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #14, MUL VL] // encoding of (high = value) ld2q {Z31.Q, Z0.Q}, p7/Z, [x30, #-16, MUL VL] // encoding of all field= s (all ones) ld2q {Z30.Q, Z31.Q}, p1/Z, [x3, #-2, MUL VL] // random encoding. =20 For all the above form of instructions the hyphenated form is preferred= for disassembly if there are more than two registers in the list, and the r= egister numbers are monotonically increasing in increments of one. Diff: --- gas/config/tc-aarch64.c | 4 +- gas/testsuite/gas/aarch64/illegal-sve2.l | 52 ++++----- gas/testsuite/gas/aarch64/sme-5-illegal.l | 8 +- gas/testsuite/gas/aarch64/sme-6-illegal.l | 8 +- gas/testsuite/gas/aarch64/sve2.d | 76 ++++++------- gas/testsuite/gas/aarch64/sve2p1-1-bad.l | 14 --- gas/testsuite/gas/aarch64/sve2p1-1.d | 14 --- gas/testsuite/gas/aarch64/sve2p1-1.s | 15 --- gas/testsuite/gas/aarch64/sve2p1-4-invalid.d | 3 + gas/testsuite/gas/aarch64/sve2p1-4-invalid.l | 122 +++++++++++++++++++++ gas/testsuite/gas/aarch64/sve2p1-4-invalid.s | 125 +++++++++++++++++++++ gas/testsuite/gas/aarch64/sve2p1-4.d | 152 +++++++++++++++++++++++= +++ gas/testsuite/gas/aarch64/sve2p1-4.s | 155 +++++++++++++++++++++++= ++++ include/opcode/aarch64.h | 4 +- opcodes/aarch64-asm-2.c | 144 ++++++++++++-----------= -- opcodes/aarch64-dis-2.c | 141 ++++++++++++------------ opcodes/aarch64-opc-2.c | 4 +- opcodes/aarch64-opc.c | 78 ++++++++------ opcodes/aarch64-tbl.h | 48 ++++----- 19 files changed, 837 insertions(+), 330 deletions(-) diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 84206e44f1f..ad4dd576174 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -6953,9 +6953,6 @@ parse_operands (char *str, const aarch64_opcode *opco= de) case AARCH64_OPND_SME_Zdnx2: case AARCH64_OPND_SME_Zdnx4: case AARCH64_OPND_SME_Zdnx4_STRIDED: - case AARCH64_OPND_SME_Zt2: - case AARCH64_OPND_SME_Zt3: - case AARCH64_OPND_SME_Zt4: case AARCH64_OPND_SME_Zmx2: case AARCH64_OPND_SME_Zmx4: case AARCH64_OPND_SME_Znx2: @@ -7793,6 +7790,7 @@ parse_operands (char *str, const aarch64_opcode *opco= de) case AARCH64_OPND_SVE_ADDR_RX_LSL1: case AARCH64_OPND_SVE_ADDR_RX_LSL2: case AARCH64_OPND_SVE_ADDR_RX_LSL3: + case AARCH64_OPND_SVE_ADDR_RX_LSL4: /* [, {, lsl #}] but recognizing SVE registers. */ po_misc_or_fail (parse_sve_address (&str, info, &base_qualifier, diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/a= arch64/illegal-sve2.l index 778c40d87a5..dfa05afa8ef 100644 --- a/gas/testsuite/gas/aarch64/illegal-sve2.l +++ b/gas/testsuite/gas/aarch64/illegal-sve2.l @@ -491,7 +491,7 @@ [^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ldn= t1b {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]' [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1b {z0\.d},p0/m,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: ldnt1b {z0\.d}, p0/z, \[z0\.d, xzr\] +[^ :]+:[0-9]+: Info: ldnt1b {z0\.d}, p0/z, \[z0\.d\] [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldn= t1b {z32\.d},p0/z,\[z0\.d\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1b {z0\.d},p8/z,= \[z0\.d\]' [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1b {z0\.d= },p0/z,\[z32\.d\]' @@ -501,14 +501,14 @@ [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1b {z0\= .d},p0/z,\[z0\.d,z0\.d\]' [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1b {z0\.s},p0/z,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: ldnt1b {z0\.s}, p0/z, \[z0\.s, xzr\] +[^ :]+:[0-9]+: Info: ldnt1b {z0\.s}, p0/z, \[z0\.s\] [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1b {z0\.d},p0/z,\[z0\.s\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: ldnt1b {z0\.s}, p0/z, \[z0\.s, xzr\] +[^ :]+:[0-9]+: Info: ldnt1b {z0\.s}, p0/z, \[z0\.s\] [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -= - `ldnt1b {z0\.s,z1\.d},p0/z,\[z0\.s,x0\]' [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1b {z0\.s},p0/m,\[z0\.s\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: ldnt1b {z0\.s}, p0/z, \[z0\.s, xzr\] +[^ :]+:[0-9]+: Info: ldnt1b {z0\.s}, p0/z, \[z0\.s\] [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldn= t1b {z32\.s},p0/z,\[z0\.s\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1b {z0\.s},p8/z,= \[z0\.s\]' [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1b {z0\.s= },p0/z,\[z32\.s\]' @@ -518,7 +518,7 @@ [^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ldn= t1d {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]' [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1d {z0\.d},p0/m,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: ldnt1d {z0\.d}, p0/z, \[z0\.d, xzr\] +[^ :]+:[0-9]+: Info: ldnt1d {z0\.d}, p0/z, \[z0\.d\] [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldn= t1d {z32\.d},p0/z,\[z0\.d\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1d {z0\.d},p8/z,= \[z0\.d\]' [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1d {z0\.d= },p0/z,\[z32\.d\]' @@ -528,17 +528,17 @@ [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1d {z0\= .d},p0/z,\[z0\.d,z0\.d\]' [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1d {z0\.s},p0/z,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: ldnt1d {z0\.d}, p0/z, \[z0\.d, xzr\] +[^ :]+:[0-9]+: Info: ldnt1d {z0\.d}, p0/z, \[z0\.d\] [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1d {z0\.d},p0/z,\[z0\.s\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: ldnt1d {z0\.d}, p0/z, \[z0\.d, xzr\] +[^ :]+:[0-9]+: Info: ldnt1d {z0\.d}, p0/z, \[z0\.d\] [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1d {z0\.d},p0/m,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: ldnt1d {z0\.d}, p0/z, \[z0\.d, xzr\] +[^ :]+:[0-9]+: Info: ldnt1d {z0\.d}, p0/z, \[z0\.d\] [^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ldn= t1h {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]' [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1h {z0\.d},p0/m,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: ldnt1h {z0\.d}, p0/z, \[z0\.d, xzr\] +[^ :]+:[0-9]+: Info: ldnt1h {z0\.d}, p0/z, \[z0\.d\] [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldn= t1h {z32\.d},p0/z,\[z0\.d\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1h {z0\.d},p8/z,= \[z0\.d\]' [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1h {z0\.d= },p0/z,\[z32\.d\]' @@ -548,7 +548,7 @@ [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1h {z0\= .d},p0/z,\[z0\.d,z0\.d\]' [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1h {z0\.s},p0/z,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: ldnt1h {z0\.s}, p0/z, \[z0\.s, xzr\] +[^ :]+:[0-9]+: Info: ldnt1h {z0\.s}, p0/z, \[z0\.s\] [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -= - `ldnt1h {z0\.s,z1\.d},p0/z,\[z0\.s,x0\]' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldn= t1h {z32\.s},p0/z,\[z0\.s\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1h {z0\.s},p8/z,= \[z0\.s\]' @@ -559,9 +559,9 @@ [^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ldn= t1sb {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]' [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1sb {z0\.d},p0/m,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: ldnt1sb {z0\.d}, p0/z, \[z0\.d, xzr\] +[^ :]+:[0-9]+: Info: ldnt1sb {z0\.d}, p0/z, \[z0\.d\] [^ :]+:[0-9]+: Info: other valid variant\(s\): -[^ :]+:[0-9]+: Info: ldnt1sb {z0\.s}, p0/z, \[z0\.s, xzr\] +[^ :]+:[0-9]+: Info: ldnt1sb {z0\.s}, p0/z, \[z0\.s\] [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldn= t1sb {z32\.d},p0/z,\[z0\.d\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1sb {z0\.d},p8/z= ,\[z0\.d\]' [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1sb {z0\.= d},p0/z,\[z32\.d\]' @@ -572,9 +572,9 @@ [^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ldn= t1sh {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]' [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1sh {z0\.d},p0/m,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: ldnt1sh {z0\.d}, p0/z, \[z0\.d, xzr\] +[^ :]+:[0-9]+: Info: ldnt1sh {z0\.d}, p0/z, \[z0\.d\] [^ :]+:[0-9]+: Info: other valid variant\(s\): -[^ :]+:[0-9]+: Info: ldnt1sh {z0\.s}, p0/z, \[z0\.s, xzr\] +[^ :]+:[0-9]+: Info: ldnt1sh {z0\.s}, p0/z, \[z0\.s\] [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldn= t1sh {z32\.d},p0/z,\[z0\.d\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1sh {z0\.d},p8/z= ,\[z0\.d\]' [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1sh {z0\.= d},p0/z,\[z32\.d\]' @@ -585,9 +585,9 @@ [^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ldn= t1sh {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]' [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1sh {z0\.d},p0/m,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: ldnt1sh {z0\.d}, p0/z, \[z0\.d, xzr\] +[^ :]+:[0-9]+: Info: ldnt1sh {z0\.d}, p0/z, \[z0\.d\] [^ :]+:[0-9]+: Info: other valid variant\(s\): -[^ :]+:[0-9]+: Info: ldnt1sh {z0\.s}, p0/z, \[z0\.s, xzr\] +[^ :]+:[0-9]+: Info: ldnt1sh {z0\.s}, p0/z, \[z0\.s\] [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldn= t1sh {z32\.d},p0/z,\[z0\.d\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1sh {z0\.d},p8/z= ,\[z0\.d\]' [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1sh {z0\.= d},p0/z,\[z32\.d\]' @@ -598,7 +598,7 @@ [^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ldn= t1w {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]' [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1w {z0\.d},p0/m,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: ldnt1w {z0\.d}, p0/z, \[z0\.d, xzr\] +[^ :]+:[0-9]+: Info: ldnt1w {z0\.d}, p0/z, \[z0\.d\] [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldn= t1w {z32\.d},p0/z,\[z0\.d\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1w {z0\.d},p8/z,= \[z0\.d\]' [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1w {z0\.d= },p0/z,\[z32\.d\]' @@ -608,7 +608,7 @@ [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1w {z0\= .d},p0/z,\[z0\.d,z0\.d\]' [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1w {z0\.s},p0/z,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: ldnt1w {z0\.s}, p0/z, \[z0\.s, xzr\] +[^ :]+:[0-9]+: Info: ldnt1w {z0\.s}, p0/z, \[z0\.s\] [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -= - `ldnt1w {z0\.s,z1\.d},p0/z,\[z0\.s,x0\]' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldn= t1w {z32\.s},p0/z,\[z0\.s\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1w {z0\.s},p8/z,= \[z0\.s\]' @@ -2219,7 +2219,7 @@ [^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `stn= t1b {z0\.d,z1\.d},p0,\[z0\.d,x0\]' [^ :]+:[0-9]+: Error: operand mismatch -- `stnt1b {z0\.d},p0/m,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: stnt1b {z0\.d}, p0, \[z0\.d, xzr\] +[^ :]+:[0-9]+: Info: stnt1b {z0\.d}, p0, \[z0\.d\] [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `stn= t1b {z32\.d},p0,\[z0\.d\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1b {z0\.d},p8,\[= z0\.d\]' [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1b {z0\.d= },p0,\[z32\.d\]' @@ -2229,7 +2229,7 @@ [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1b {z0\= .d},p0,\[z0\.d,z0\.d\]' [^ :]+:[0-9]+: Error: operand mismatch -- `stnt1b {z0\.s},p0,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: stnt1b {z0\.s}, p0, \[z0\.s, xzr\] +[^ :]+:[0-9]+: Info: stnt1b {z0\.s}, p0, \[z0\.s\] [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -= - `stnt1b {z0\.s,z1\.d},p0,\[z0\.s,x0\]' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `stn= t1b {z32\.s},p0,\[z0\.s\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1b {z0\.s},p8,\[= z0\.s\]' @@ -2240,7 +2240,7 @@ [^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `stn= t1d {z0\.d,z1\.d},p0,\[z0\.d,x0\]' [^ :]+:[0-9]+: Error: operand mismatch -- `stnt1d {z0\.d},p0/m,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: stnt1d {z0\.d}, p0, \[z0\.d, xzr\] +[^ :]+:[0-9]+: Info: stnt1d {z0\.d}, p0, \[z0\.d\] [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `stn= t1d {z32\.d},p0,\[z0\.d\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1d {z0\.d},p8,\[= z0\.d\]' [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1d {z0\.d= },p0,\[z32\.d\]' @@ -2250,11 +2250,11 @@ [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1d {z0\= .d},p0,\[z0\.d,z0\.d\]' [^ :]+:[0-9]+: Error: operand mismatch -- `stnt1d {z0\.s},p0,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: stnt1d {z0\.d}, p0, \[z0\.d, xzr\] +[^ :]+:[0-9]+: Info: stnt1d {z0\.d}, p0, \[z0\.d\] [^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `stn= t1h {z0\.d,z1\.d},p0,\[z0\.d,x0\]' [^ :]+:[0-9]+: Error: operand mismatch -- `stnt1h {z0\.d},p0/m,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: stnt1h {z0\.d}, p0, \[z0\.d, xzr\] +[^ :]+:[0-9]+: Info: stnt1h {z0\.d}, p0, \[z0\.d\] [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `stn= t1h {z32\.d},p0,\[z0\.d\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1h {z0\.d},p8,\[= z0\.d\]' [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1h {z0\.d= },p0,\[z32\.d\]' @@ -2264,7 +2264,7 @@ [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1h {z0\= .d},p0,\[z0\.d,z0\.d\]' [^ :]+:[0-9]+: Error: operand mismatch -- `stnt1h {z0\.s},p0,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: stnt1h {z0\.s}, p0, \[z0\.s, xzr\] +[^ :]+:[0-9]+: Info: stnt1h {z0\.s}, p0, \[z0\.s\] [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -= - `stnt1h {z0\.s,z1\.d},p0,\[z0\.s,x0\]' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `stn= t1h {z32\.s},p0,\[z0\.s\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1h {z0\.s},p8,\[= z0\.s\]' @@ -2275,7 +2275,7 @@ [^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `stn= t1w {z0\.d,z1\.d},p0,\[z0\.d,x0\]' [^ :]+:[0-9]+: Error: operand mismatch -- `stnt1w {z0\.d},p0/m,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: stnt1w {z0\.d}, p0, \[z0\.d, xzr\] +[^ :]+:[0-9]+: Info: stnt1w {z0\.d}, p0, \[z0\.d\] [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `stn= t1w {z32\.d},p0,\[z0\.d\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1w {z0\.d},p8,\[= z0\.d\]' [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1w {z0\.d= },p0,\[z32\.d\]' @@ -2285,7 +2285,7 @@ [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1w {z0\= .d},p0,\[z0\.d,z0\.d\]' [^ :]+:[0-9]+: Error: operand mismatch -- `stnt1w {z0\.s},p0,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: stnt1w {z0\.s}, p0, \[z0\.s, xzr\] +[^ :]+:[0-9]+: Info: stnt1w {z0\.s}, p0, \[z0\.s\] [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -= - `stnt1w {z0\.s,z1\.d},p0,\[z0\.s,x0\]' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `stn= t1w {z32\.s},p0,\[z0\.s\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1w {z0\.s},p8,\[= z0\.s\]' diff --git a/gas/testsuite/gas/aarch64/sme-5-illegal.l b/gas/testsuite/gas/= aarch64/sme-5-illegal.l index c4bfc1f8b5a..b0736e0fcd6 100644 --- a/gas/testsuite/gas/aarch64/sme-5-illegal.l +++ b/gas/testsuite/gas/aarch64/sme-5-illegal.l @@ -35,10 +35,10 @@ [^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- = `ld1d {za7h.d\[w15,2\]},p7/z,\[sp\]' [^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- = `ld1d {za7v.d\[w15,2\]},p7/z,\[x0,x17,lsl#3\]' [^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- = `ld1d {za7h.d\[w15,2\]},p7/z,\[sp,x17,lsl#3\]' -[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `ld1q {za16v= .q\[w12\]},p0/z,\[x0\]' -[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `ld1q {za16h= .q\[w12\]},p0/z,\[sp\]' -[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `ld1q {za16v= .q\[w12\]},p0/z,\[x0,x0,lsl#4\]' -[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `ld1q {za16h= .q\[w12\]},p0/z,\[sp,x0,lsl#4\]' +[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at o= perand 1 -- `ld1q {za16v.q\[w12\]},p0/z,\[x0\]' +[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at o= perand 1 -- `ld1q {za16h.q\[w12\]},p0/z,\[sp\]' +[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at o= perand 1 -- `ld1q {za16v.q\[w12\]},p0/z,\[x0,x0,lsl#4\]' +[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at o= perand 1 -- `ld1q {za16h.q\[w12\]},p0/z,\[sp,x0,lsl#4\]' [^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `ld1q {za1= 5v.q\[w15,1\]},p7/z,\[x17\]' [^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `ld1q {za1= 5h.q\[w15,1\]},p7/z,\[sp\]' [^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `ld1q {za1= 5v.q\[w15,1\]},p7/z,\[x0,x17,lsl#4\]' diff --git a/gas/testsuite/gas/aarch64/sme-6-illegal.l b/gas/testsuite/gas/= aarch64/sme-6-illegal.l index b98b76faaed..10c2a51204b 100644 --- a/gas/testsuite/gas/aarch64/sme-6-illegal.l +++ b/gas/testsuite/gas/aarch64/sme-6-illegal.l @@ -35,10 +35,10 @@ [^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- = `st1d {za7h.d\[w15,2\]},p7,\[sp\]' [^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- = `st1d {za7v.d\[w15,2\]},p7,\[x0,x17,lsl#3\]' [^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- = `st1d {za7h.d\[w15,2\]},p7,\[sp,x17,lsl#3\]' -[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `st1q {za16v= .q\[w12\]},p0,\[x0\]' -[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `st1q {za16h= .q\[w12\]},p0,\[sp\]' -[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `st1q {za16v= .q\[w12\]},p0,\[x0,x0,lsl#4\]' -[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `st1q {za16h= .q\[w12\]},p0,\[sp,x0,lsl#4\]' +[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at o= perand 1 -- `st1q {za16v.q\[w12\]},p0,\[x0\]' +[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at o= perand 1 -- `st1q {za16h.q\[w12\]},p0,\[sp\]' +[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at o= perand 1 -- `st1q {za16v.q\[w12\]},p0,\[x0,x0,lsl#4\]' +[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at o= perand 1 -- `st1q {za16h.q\[w12\]},p0,\[sp,x0,lsl#4\]' [^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `st1q {za1= 5v.q\[w15,1\]},p7,\[x17\]' [^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `st1q {za1= 5h.q\[w15,1\]},p7,\[sp\]' [^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `st1q {za1= 5v.q\[w15,1\]},p7,\[x0,x17,lsl#4\]' diff --git a/gas/testsuite/gas/aarch64/sve2.d b/gas/testsuite/gas/aarch64/s= ve2.d index 6c0d94203cb..e9a5bcd7120 100644 --- a/gas/testsuite/gas/aarch64/sve2.d +++ b/gas/testsuite/gas/aarch64/sve2.d @@ -181,50 +181,50 @@ Disassembly of section \.text: *[0-9a-f]+: 4520a000 histseg z0\.b, z0\.b, z0\.b *[0-9a-f]+: c41bd6b1 ldnt1b {z17\.d}, p5/z, \[z21\.d, x27\] *[0-9a-f]+: c400c000 ldnt1b {z0\.d}, p0/z, \[z0\.d, x0\] - *[0-9a-f]+: c41fc000 ldnt1b {z0\.d}, p0/z, \[z0\.d, xzr\] - *[0-9a-f]+: c41fc000 ldnt1b {z0\.d}, p0/z, \[z0\.d, xzr\] + *[0-9a-f]+: c41fc000 ldnt1b {z0\.d}, p0/z, \[z0\.d\] + *[0-9a-f]+: c41fc000 ldnt1b {z0\.d}, p0/z, \[z0\.d\] *[0-9a-f]+: 841bb6b1 ldnt1b {z17\.s}, p5/z, \[z21\.s, x27\] *[0-9a-f]+: 8400a000 ldnt1b {z0\.s}, p0/z, \[z0\.s, x0\] - *[0-9a-f]+: 841fa000 ldnt1b {z0\.s}, p0/z, \[z0\.s, xzr\] - *[0-9a-f]+: 841fa000 ldnt1b {z0\.s}, p0/z, \[z0\.s, xzr\] + *[0-9a-f]+: 841fa000 ldnt1b {z0\.s}, p0/z, \[z0\.s\] + *[0-9a-f]+: 841fa000 ldnt1b {z0\.s}, p0/z, \[z0\.s\] *[0-9a-f]+: c59bd6b1 ldnt1d {z17\.d}, p5/z, \[z21\.d, x27\] *[0-9a-f]+: c580c000 ldnt1d {z0\.d}, p0/z, \[z0\.d, x0\] - *[0-9a-f]+: c59fc000 ldnt1d {z0\.d}, p0/z, \[z0\.d, xzr\] - *[0-9a-f]+: c59fc000 ldnt1d {z0\.d}, p0/z, \[z0\.d, xzr\] + *[0-9a-f]+: c59fc000 ldnt1d {z0\.d}, p0/z, \[z0\.d\] + *[0-9a-f]+: c59fc000 ldnt1d {z0\.d}, p0/z, \[z0\.d\] *[0-9a-f]+: c49bd6b1 ldnt1h {z17\.d}, p5/z, \[z21\.d, x27\] *[0-9a-f]+: c480c000 ldnt1h {z0\.d}, p0/z, \[z0\.d, x0\] - *[0-9a-f]+: c49fc000 ldnt1h {z0\.d}, p0/z, \[z0\.d, xzr\] - *[0-9a-f]+: c49fc000 ldnt1h {z0\.d}, p0/z, \[z0\.d, xzr\] + *[0-9a-f]+: c49fc000 ldnt1h {z0\.d}, p0/z, \[z0\.d\] + *[0-9a-f]+: c49fc000 ldnt1h {z0\.d}, p0/z, \[z0\.d\] *[0-9a-f]+: 849bb6b1 ldnt1h {z17\.s}, p5/z, \[z21\.s, x27\] *[0-9a-f]+: 8480a000 ldnt1h {z0\.s}, p0/z, \[z0\.s, x0\] - *[0-9a-f]+: 849fa000 ldnt1h {z0\.s}, p0/z, \[z0\.s, xzr\] - *[0-9a-f]+: 849fa000 ldnt1h {z0\.s}, p0/z, \[z0\.s, xzr\] + *[0-9a-f]+: 849fa000 ldnt1h {z0\.s}, p0/z, \[z0\.s\] + *[0-9a-f]+: 849fa000 ldnt1h {z0\.s}, p0/z, \[z0\.s\] *[0-9a-f]+: 841b96b1 ldnt1sb {z17\.s}, p5/z, \[z21\.s, x27\] *[0-9a-f]+: 84008000 ldnt1sb {z0\.s}, p0/z, \[z0\.s, x0\] - *[0-9a-f]+: 841f8000 ldnt1sb {z0\.s}, p0/z, \[z0\.s, xzr\] - *[0-9a-f]+: 841f8000 ldnt1sb {z0\.s}, p0/z, \[z0\.s, xzr\] + *[0-9a-f]+: 841f8000 ldnt1sb {z0\.s}, p0/z, \[z0\.s\] + *[0-9a-f]+: 841f8000 ldnt1sb {z0\.s}, p0/z, \[z0\.s\] *[0-9a-f]+: c4008000 ldnt1sb {z0\.d}, p0/z, \[z0\.d, x0\] - *[0-9a-f]+: c41f8000 ldnt1sb {z0\.d}, p0/z, \[z0\.d, xzr\] - *[0-9a-f]+: c41f8000 ldnt1sb {z0\.d}, p0/z, \[z0\.d, xzr\] + *[0-9a-f]+: c41f8000 ldnt1sb {z0\.d}, p0/z, \[z0\.d\] + *[0-9a-f]+: c41f8000 ldnt1sb {z0\.d}, p0/z, \[z0\.d\] *[0-9a-f]+: 849b96b1 ldnt1sh {z17\.s}, p5/z, \[z21\.s, x27\] *[0-9a-f]+: 84808000 ldnt1sh {z0\.s}, p0/z, \[z0\.s, x0\] - *[0-9a-f]+: 849f8000 ldnt1sh {z0\.s}, p0/z, \[z0\.s, xzr\] - *[0-9a-f]+: 849f8000 ldnt1sh {z0\.s}, p0/z, \[z0\.s, xzr\] + *[0-9a-f]+: 849f8000 ldnt1sh {z0\.s}, p0/z, \[z0\.s\] + *[0-9a-f]+: 849f8000 ldnt1sh {z0\.s}, p0/z, \[z0\.s\] *[0-9a-f]+: c4808000 ldnt1sh {z0\.d}, p0/z, \[z0\.d, x0\] - *[0-9a-f]+: c49f8000 ldnt1sh {z0\.d}, p0/z, \[z0\.d, xzr\] - *[0-9a-f]+: c49f8000 ldnt1sh {z0\.d}, p0/z, \[z0\.d, xzr\] + *[0-9a-f]+: c49f8000 ldnt1sh {z0\.d}, p0/z, \[z0\.d\] + *[0-9a-f]+: c49f8000 ldnt1sh {z0\.d}, p0/z, \[z0\.d\] *[0-9a-f]+: c51b96b1 ldnt1sw {z17\.d}, p5/z, \[z21\.d, x27\] *[0-9a-f]+: c5008000 ldnt1sw {z0\.d}, p0/z, \[z0\.d, x0\] - *[0-9a-f]+: c51f8000 ldnt1sw {z0\.d}, p0/z, \[z0\.d, xzr\] - *[0-9a-f]+: c51f8000 ldnt1sw {z0\.d}, p0/z, \[z0\.d, xzr\] + *[0-9a-f]+: c51f8000 ldnt1sw {z0\.d}, p0/z, \[z0\.d\] + *[0-9a-f]+: c51f8000 ldnt1sw {z0\.d}, p0/z, \[z0\.d\] *[0-9a-f]+: 851bb6b1 ldnt1w {z17\.s}, p5/z, \[z21\.s, x27\] *[0-9a-f]+: 8500a000 ldnt1w {z0\.s}, p0/z, \[z0\.s, x0\] - *[0-9a-f]+: 851fa000 ldnt1w {z0\.s}, p0/z, \[z0\.s, xzr\] - *[0-9a-f]+: 851fa000 ldnt1w {z0\.s}, p0/z, \[z0\.s, xzr\] + *[0-9a-f]+: 851fa000 ldnt1w {z0\.s}, p0/z, \[z0\.s\] + *[0-9a-f]+: 851fa000 ldnt1w {z0\.s}, p0/z, \[z0\.s\] *[0-9a-f]+: c51bd6b1 ldnt1w {z17\.d}, p5/z, \[z21\.d, x27\] *[0-9a-f]+: c500c000 ldnt1w {z0\.d}, p0/z, \[z0\.d, x0\] - *[0-9a-f]+: c51fc000 ldnt1w {z0\.d}, p0/z, \[z0\.d, xzr\] - *[0-9a-f]+: c51fc000 ldnt1w {z0\.d}, p0/z, \[z0\.d, xzr\] + *[0-9a-f]+: c51fc000 ldnt1w {z0\.d}, p0/z, \[z0\.d\] + *[0-9a-f]+: c51fc000 ldnt1w {z0\.d}, p0/z, \[z0\.d\] *[0-9a-f]+: 45359629 match p9\.b, p5/z, z17\.b, z21\.b *[0-9a-f]+: 45358220 match p0\.b, p0/z, z17\.b, z21\.b *[0-9a-f]+: 45208000 match p0\.b, p0/z, z0\.b, z0\.b @@ -876,32 +876,32 @@ Disassembly of section \.text: *[0-9a-f]+: 45c05400 ssubwt z0\.d, z0\.d, z0\.s *[0-9a-f]+: e45b36b1 stnt1b {z17\.s}, p5, \[z21\.s, x27\] *[0-9a-f]+: e4402000 stnt1b {z0\.s}, p0, \[z0\.s, x0\] - *[0-9a-f]+: e45f2000 stnt1b {z0\.s}, p0, \[z0\.s, xzr\] - *[0-9a-f]+: e45f2000 stnt1b {z0\.s}, p0, \[z0\.s, xzr\] + *[0-9a-f]+: e45f2000 stnt1b {z0\.s}, p0, \[z0\.s\] + *[0-9a-f]+: e45f2000 stnt1b {z0\.s}, p0, \[z0\.s\] *[0-9a-f]+: e41b36b1 stnt1b {z17\.d}, p5, \[z21\.d, x27\] *[0-9a-f]+: e4002000 stnt1b {z0\.d}, p0, \[z0\.d, x0\] - *[0-9a-f]+: e41f2000 stnt1b {z0\.d}, p0, \[z0\.d, xzr\] - *[0-9a-f]+: e41f2000 stnt1b {z0\.d}, p0, \[z0\.d, xzr\] + *[0-9a-f]+: e41f2000 stnt1b {z0\.d}, p0, \[z0\.d\] + *[0-9a-f]+: e41f2000 stnt1b {z0\.d}, p0, \[z0\.d\] *[0-9a-f]+: e59b36b1 stnt1d {z17\.d}, p5, \[z21\.d, x27\] *[0-9a-f]+: e5802000 stnt1d {z0\.d}, p0, \[z0\.d, x0\] - *[0-9a-f]+: e59f2000 stnt1d {z0\.d}, p0, \[z0\.d, xzr\] - *[0-9a-f]+: e59f2000 stnt1d {z0\.d}, p0, \[z0\.d, xzr\] + *[0-9a-f]+: e59f2000 stnt1d {z0\.d}, p0, \[z0\.d\] + *[0-9a-f]+: e59f2000 stnt1d {z0\.d}, p0, \[z0\.d\] *[0-9a-f]+: e4db36b1 stnt1h {z17\.s}, p5, \[z21\.s, x27\] *[0-9a-f]+: e4c02000 stnt1h {z0\.s}, p0, \[z0\.s, x0\] - *[0-9a-f]+: e4df2000 stnt1h {z0\.s}, p0, \[z0\.s, xzr\] - *[0-9a-f]+: e4df2000 stnt1h {z0\.s}, p0, \[z0\.s, xzr\] + *[0-9a-f]+: e4df2000 stnt1h {z0\.s}, p0, \[z0\.s\] + *[0-9a-f]+: e4df2000 stnt1h {z0\.s}, p0, \[z0\.s\] *[0-9a-f]+: e49b36b1 stnt1h {z17\.d}, p5, \[z21\.d, x27\] *[0-9a-f]+: e4802000 stnt1h {z0\.d}, p0, \[z0\.d, x0\] - *[0-9a-f]+: e49f2000 stnt1h {z0\.d}, p0, \[z0\.d, xzr\] - *[0-9a-f]+: e49f2000 stnt1h {z0\.d}, p0, \[z0\.d, xzr\] + *[0-9a-f]+: e49f2000 stnt1h {z0\.d}, p0, \[z0\.d\] + *[0-9a-f]+: e49f2000 stnt1h {z0\.d}, p0, \[z0\.d\] *[0-9a-f]+: e55b36b1 stnt1w {z17\.s}, p5, \[z21\.s, x27\] *[0-9a-f]+: e5402000 stnt1w {z0\.s}, p0, \[z0\.s, x0\] - *[0-9a-f]+: e55f2000 stnt1w {z0\.s}, p0, \[z0\.s, xzr\] - *[0-9a-f]+: e55f2000 stnt1w {z0\.s}, p0, \[z0\.s, xzr\] + *[0-9a-f]+: e55f2000 stnt1w {z0\.s}, p0, \[z0\.s\] + *[0-9a-f]+: e55f2000 stnt1w {z0\.s}, p0, \[z0\.s\] *[0-9a-f]+: e51b36b1 stnt1w {z17\.d}, p5, \[z21\.d, x27\] *[0-9a-f]+: e5002000 stnt1w {z0\.d}, p0, \[z0\.d, x0\] - *[0-9a-f]+: e51f2000 stnt1w {z0\.d}, p0, \[z0\.d, xzr\] - *[0-9a-f]+: e51f2000 stnt1w {z0\.d}, p0, \[z0\.d, xzr\] + *[0-9a-f]+: e51f2000 stnt1w {z0\.d}, p0, \[z0\.d\] + *[0-9a-f]+: e51f2000 stnt1w {z0\.d}, p0, \[z0\.d\] *[0-9a-f]+: 457b72b1 subhnb z17\.b, z21\.h, z27\.h *[0-9a-f]+: 45607000 subhnb z0\.b, z0\.h, z0\.h *[0-9a-f]+: 45a07000 subhnb z0\.h, z0\.s, z0\.s diff --git a/gas/testsuite/gas/aarch64/sve2p1-1-bad.l b/gas/testsuite/gas/a= arch64/sve2p1-1-bad.l index 90c54fdc901..888504de74e 100644 --- a/gas/testsuite/gas/aarch64/sve2p1-1-bad.l +++ b/gas/testsuite/gas/aarch64/sve2p1-1-bad.l @@ -80,17 +80,3 @@ .*: Error: selected processor does not support `fminqv v4.2d,p3,z2.d' .*: Error: selected processor does not support `fminqv v8.2d,p4,z1.d' .*: Error: selected processor does not support `fminqv v16.4s,p7,z0.s' -.*: Error: selected processor does not support `ld1q Z0.Q,p4/Z,\[Z16.D,x0\= ]' -.*: Error: selected processor does not support `ld2q {Z0.Q,Z1.Q},p4/Z,\[x0= ,#-4,MUL VL\]' -.*: Error: selected processor does not support `ld3q .* -.*: Error: selected processor does not support `ld4q .* -.*: Error: selected processor does not support `ld2q {Z0.Q,Z1.Q},p4/Z,\[x0= ,x2,lsl#4\]' -.*: Error: selected processor does not support `ld3q {Z0.Q,Z1.Q,Z2.Q},p4/Z= ,\[x0,x4,lsl#4\]' -.*: Error: selected processor does not support `ld4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q}= ,p4/Z,\[x0,x6,lsl#4\]' -.*: Error: selected processor does not support `st1q Z0.Q,p4,\[Z16.D,x0\]' -.*: Error: selected processor does not support `st2q {Z0.Q,Z1.Q},p4,\[x0,#= -4,MUL VL\]' -.*: Error: selected processor does not support `st3q .* -.*: Error: selected processor does not support `st4q .* -.*: Error: selected processor does not support `st2q {Z0.Q,Z1.Q},p4,\[x0,x= 2,lsl#4\]' -.*: Error: selected processor does not support `st3q {Z0.Q,Z1.Q,Z2.Q},p4,\= [x0,x4,lsl#4\]' -.*: Error: selected processor does not support `st4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q}= ,p4,\[x0,x6,lsl#4\]' diff --git a/gas/testsuite/gas/aarch64/sve2p1-1.d b/gas/testsuite/gas/aarch= 64/sve2p1-1.d index 8635d334442..da57edf7e81 100644 --- a/gas/testsuite/gas/aarch64/sve2p1-1.d +++ b/gas/testsuite/gas/aarch64/sve2p1-1.d @@ -89,17 +89,3 @@ .*: 64d7ac44 fminqv v4.2d, p3, z2.d .*: 64d7b028 fminqv v8.2d, p4, z1.d .*: 6497bc10 fminqv v16.4s, p7, z0.s -.*: c400b200 ld1q z0.q, p4/z, \[z16.d, x0\] -.*: a49ef000 ld2q {z0.q, z1.q}, p4/z, \[x0, #-4, mul vl\] -.*: a51ef000 ld3q {z0.q, z1.q, z2.q}, p4/z, \[x0, #-6, mul vl\] -.*: a59ef000 ld4q {z0.q, z1.q, z2.q, z3.q}, p4/z, \[x0, #-8, mul vl\] -.*: a4a29000 ld2q {z0.q, z1.q}, p4/z, \[x0, x2, lsl #4\] -.*: a5249000 ld3q {z0.q, z1.q, z2.q}, p4/z, \[x0, x4, lsl #4\] -.*: a5a69000 ld4q {z0.q, z1.q, z2.q, z3.q}, p4/z, \[x0, x6, lsl #4\] -.*: e4203200 st1q z0.q, p4, \[z16.d, x0\] -.*: e44e1000 st2q {z0.q, z1.q}, p4, \[x0, #-4, mul vl\] -.*: e48e1000 st3q {z0.q, z1.q, z2.q}, p4, \[x0, #-6, mul vl\] -.*: e4ce1000 st4q {z0.q, z1.q, z2.q, z3.q}, p4, \[x0, #-8, mul vl\] -.*: e4621000 st2q {z0.q, z1.q}, p4, \[x0, x2, lsl #4\] -.*: e4a41000 st3q {z0.q, z1.q, z2.q}, p4, \[x0, x4, lsl #4\] -.*: e4e61000 st4q {z0.q, z1.q, z2.q, z3.q}, p4, \[x0, x6, lsl #4\] diff --git a/gas/testsuite/gas/aarch64/sve2p1-1.s b/gas/testsuite/gas/aarch= 64/sve2p1-1.s index 0e33c603361..718ebccbf75 100644 --- a/gas/testsuite/gas/aarch64/sve2p1-1.s +++ b/gas/testsuite/gas/aarch64/sve2p1-1.s @@ -90,18 +90,3 @@ fminqv v2.4s, p2, z4.s fminqv v4.2d, p3, z2.d fminqv v8.2d, p4, z1.d fminqv v16.4s, p7, z0.s -ld1q Z0.Q, p4/Z, [Z16.D, x0] -ld2q {Z0.Q, Z1.Q}, p4/Z, [x0, #-4, MUL VL] -ld3q {Z0.Q, Z1.Q, Z2.Q}, p4/Z, [x0, #-6, MUL VL] -ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4/Z, [x0, #-8, MUL VL] -ld2q {Z0.Q, Z1.Q}, p4/Z, [x0, x2, lsl #4] -ld3q {Z0.Q, Z1.Q, Z2.Q}, p4/Z, [x0, x4, lsl #4] -ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4/Z, [x0, x6, lsl #4] - -st1q Z0.Q, p4, [Z16.D, x0] -st2q {Z0.Q, Z1.Q}, p4, [x0, #-4, MUL VL] -st3q {Z0.Q, Z1.Q, Z2.Q}, p4, [x0, #-6, MUL VL] -st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4, [x0, #-8, MUL VL] -st2q {Z0.Q, Z1.Q}, p4, [x0, x2, lsl #4] -st3q {Z0.Q, Z1.Q, Z2.Q}, p4, [x0, x4, lsl #4] -st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4, [x0, x6, lsl #4] diff --git a/gas/testsuite/gas/aarch64/sve2p1-4-invalid.d b/gas/testsuite/g= as/aarch64/sve2p1-4-invalid.d new file mode 100644 index 00000000000..2363a12484d --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve2p1-4-invalid.d @@ -0,0 +1,3 @@ +#name: Test of illegal SVE2.1 ld[1-4]q/st[1-4]q instructions. +#as: -march=3Darmv9.4-a +#error_output: sve2p1-4-invalid.l diff --git a/gas/testsuite/gas/aarch64/sve2p1-4-invalid.l b/gas/testsuite/g= as/aarch64/sve2p1-4-invalid.l new file mode 100644 index 00000000000..c903664b698 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve2p1-4-invalid.l @@ -0,0 +1,122 @@ +.*: Assembler messages: +.*: Error: p0-p7 expected at operand 2 -- `ld1q {Z0.Q},P8/Z,\[Z0.D,x0\]' +.*: Error: invalid base register at operand 3 -- `ld1q {Z0.Q},P0/Z,\[Z31.Q= ,x0\]' +.*: Error: invalid addressing mode at operand 3 -- `ld1q {Z0.Q},P0/Z,\[Z0.= D,x31\]' +.*: Error: operand mismatch -- `ld1q {Z31.D},P7/Z,\[Z31.D,x30\]' +.*: Info: did you mean this\? +.*: Info: ld1q {z31.q}, p7/z, \[z31.d, x30\] +.*: Error: invalid offset register at operand 3 -- `ld1q Z0.Q,P0/Z,\[Z0.D,= sp\]' +.*: Error: operand mismatch -- `ld1q Z0.Q,P0/Z,\[Z0.S,x15\]' +.*: Info: did you mean this\? +.*: Info: ld1q {z0.q}, p0/z, \[z0.d, x15\] +.*: Error: invalid use of 32-bit register offset at operand 3 -- `ld1q Z0.= Q,P0/Z,\[Z0.D,w10\]' +.*: Error: the register list must have a stride of 1 at operand 1 -- `ld2q= {Z0.Q,Z2.Q},p0/Z,\[x0,#-2,MUL VL\]' +.*: Error: invalid register list at operand 1 -- `ld2q {Z31.Q,Z31.Q},p0/Z,= \[x0,#-2,MUL VL\]' +.*: Error: p0-p7 expected at operand 2 -- `ld2q {Z0.Q,Z1.Q},p8/Z,\[x0,#-2,= MUL VL\]' +.*: Error: invalid base register at operand 3 -- `ld2q {Z0.Q,Z1.Q},p0/Z,\[= x31,#-2,MUL VL\]' +.*: Error: immediate value must be a multiple of 2 at operand 3 -- `ld2q {= Z30.Q,Z31.Q},p7/Z,\[x30,#-3,MUL VL\]' +.*: Error: invalid base register at operand 3 -- `ld2q {Z0.Q,Z1.Q},p0/Z,\[= x31,#-20,MUL VL\]' +.*: Error: invalid base register at operand 3 -- `ld2q {Z0.Q,Z1.Q},p0/Z,\[= xzr,#-20,MUL VL\]' +.*: Error: invalid register list at operand 1 -- `ld3q {Z0.Q,Z1.Q,Z3.Q},p0= /Z,\[x0,#-3,MUL VL\]' +.*: Error: operand mismatch -- `ld3q {Z29.Q,Z30.Q,Z31.Q},p8/M,\[x0,#-3,MUL= VL\]' +.*: Info: did you mean this\? +.*: Info: ld3q {z29.q-z31.q}, p8/z, \[x0, #-3, mul vl\] +.*: Error: immediate value must be a multiple of 3 at operand 3 -- `ld3q {= Z0.Q,Z1.Q,Z2.Q},p7/Z,\[x0,#-2,MUL VL\]' +.*: Error: invalid base register at operand 3 -- `ld3q {Z0.Q,Z1.Q,Z2.Q},p0= /Z,\[x31,#-3,MUL VL\]' +.*: Error: type mismatch in vector register list at operand 1 -- `ld3q {Z2= 9.Q,Z30.Q,Z31.D},p7/Z,\[x30,#-3,MUL VL\]' +.*: Error: type mismatch in vector register list at operand 1 -- `ld3q {Z2= 9.Q,Z30.Q,Z31.D},p7/Z,\[x30,#-30,MUL VL\]' +.*: Error: type mismatch in vector register list at operand 1 -- `ld3q {Z2= 9.Q,Z30.Q,Z31.D},p7/Z,\[xzr,#-30,MUL VL\]' +.*: Error: expected a list of 4 registers at operand 1 -- `ld4q {Z0.Q,Z1.Q= ,Z2.Q},p0/Z,\[x0,#-4,MUL VL\]' +.*: Error: p0-p7 expected at operand 2 -- `ld4q {Z28.Q,Z29.Q,Z30.Q,Z31.Q},= p9/Z,\[x0,#-4,MUL VL\]' +.*: Error: immediate value must be a multiple of 4 at operand 3 -- `ld4q {= Z0.Q,Z1.Q,Z2.Q,Z3.Q},p7/Z,\[x0,#-3,MUL VL\]' +.*: Error: invalid base register at operand 3 -- `ld4q {Z0.Q,Z1.Q,Z2.Q,Z3.= Q},p0/Z,\[x31,#-4,MUL VL\]' +.*: Error: type mismatch in vector register list at operand 1 -- `ld4q {Z2= 8.Q,Z29.Q,Z30.D,Z31.Q},p7/Z,\[x30,#-4,MUL VL\]' +.*: Error: type mismatch in vector register list at operand 1 -- `ld4q {Z2= 8.Q,Z29.Q,Z30.D,Z31.Q},p7/Z,\[x30,#-100,MUL VL\]' +.*: Error: type mismatch in vector register list at operand 1 -- `ld4q {Z2= 8.Q,Z29.Q,Z30.D,Z31.Q},p7/Z,\[xzr,#-100,MUL VL\]' +.*: Error: invalid addressing mode at operand 3 -- `ld2q {Z0.Q,Z1.Q},p0/Z,= \[x0,x0,LSL#3\]' +.*: Error: invalid addressing mode at operand 3 -- `ld2q {Z0.Q,Z1.Q},p0/Z,= \[sp,x0,LSL#3\]' +.*: Error: invalid offset register at operand 3 -- `ld2q {Z0.Q,Z1.Q},p0/Z,= \[x0,sp,LSL#3\]' +.*: Error: invalid register list at operand 1 -- `ld2q {Z31.Q,Z31.Q},p0/Z,= \[x0,x0,LSL#4\]' +.*: Error: index register xzr is not allowed at operand 3 -- `ld2q {Z31.Q,= Z0.Q},p0/Z,\[x0,xzr,LSL#2\]' +.*: Error: p0-p7 expected at operand 2 -- `ld2q {Z0.Q,Z1.Q},p8/Z,\[x0,x0,L= SL#4\]' +.*: Error: invalid base register at operand 3 -- `ld2q {Z0.Q,Z1.Q},p0/Z,\[= x31,x0,LSL#4\]' +.*: Error: only 'MUL VL' is permitted at operand 3 -- `ld2q {Z0.Q,Z1.Q},p0= /Z,\[x0,x31,LSL#4\]' +.*: Error: invalid base register at operand 3 -- `ld2q {Z30.Q,Z31.Q},p7/Z,= \[x31,x31,LSL#4\]' +.*: Error: shift expression expected at operand 3 -- `ld3q {Z0.Q,Z1.Q,Z2.Q= },p0/Z,\[x0,x0,#4\]' +.*: Error: shift expression expected at operand 3 -- `ld3q {Z0.Q,Z1.Q,Z2.Q= },p0/Z,\[sp,x0,#4\]' +.*: Error: invalid offset register at operand 3 -- `ld3q {Z0.Q,Z1.Q,Z2.Q},= p0/Z,\[x0,sp,#4\]' +.*: Error: invalid addressing mode at operand 3 -- `ld3q {Z29.Q,Z30.Q,Z31.= Q},p0/Z,\[x0,x0,LSL#2\]' +.*: Error: index register xzr is not allowed at operand 3 -- `ld3q {Z29.Q,= Z30.Q,Z31.Q},p0/Z,\[x0,xzr,LSL#3\]' +.*: Error: operand mismatch -- `ld3q {Z0.Q,Z1.Q,Z2.Q},p7/M,\[x0,x0,LSL#4\]' +.*: Info: did you mean this\? +.*: Info: ld3q {z0.q-z2.q}, p7/z, \[x0, x0, lsl #4\] +.*: Error: p0-p7 expected at operand 2 -- `ld3q {Z0.Q,Z1.Q,Z2.Q},p8/Z,\[x3= 0,x0,LSL#4\]' +.*: Error: invalid register list at operand 1 -- `ld3q {Z4.Q,Z1.Q,Z2.Q},p0= /Z,\[x31,x30,LSL#4\]' +.*: Error: type mismatch in vector register list at operand 1 -- `ld3q {Z2= 9.D,Z30.Q,Z31.Q},p7/Z,\[x31,x30,LSL#4\]' +.*: Error: invalid register list at operand 1 -- `ld4q {Z1.Q,Z1.Q,Z2.Q,Z3.= Q},p0/Z,\[x0,x0,LSL#4\]' +.*: Error: invalid register list at operand 1 -- `ld4q {Z1.Q,Z1.Q,Z2.Q,Z3.= Q},p0/Z,\[sp,x0,LSL#4\]' +.*: Error: invalid register list at operand 1 -- `ld4q {Z1.Q,Z1.Q,Z2.Q,Z3.= Q},p0/Z,\[x0,sp,LSL#4\]' +.*: Error: invalid register list at operand 1 -- `ld4q {Z30.Q,Z29.Q,Z30.Q,= Z31.Q},p8/Z,\[x0,x0,LSL#4\]' +.*: Error: index register xzr is not allowed at operand 3 -- `ld4q {Z28.Q,= Z29.Q,Z30.Q,Z31.Q},p7/Z,\[x0,xzr,LSL#4\]' +.*: Error: invalid addressing mode at operand 3 -- `ld4q {Z0.Q,Z1.Q,Z2.Q,Z= 3.Q},p7/Z,\[x0,x0,LSL#2\]' +.*: Error: invalid base register at operand 3 -- `ld4q {Z0.Q,Z1.Q,Z2.Q,Z3.= Q},p0/Z,\[x31,x0,LSL#4\]' +.*: Error: type mismatch in vector register list at operand 1 -- `ld4q {Z0= .Q,Z1.Q,Z2.D,Z3.Q},p0/Z,\[x1,x30,LSL#4\]' +.*: Error: invalid register list at operand 1 -- `ld4q {Z2.Q,Z29.Q,Z30.Q,Z= 31.Q},p7/Z,\[x30,x30,LSL#4\]' +.*: Error: p0-p7 expected at operand 2 -- `st1q {Z0.Q},P8,\[Z0.D,x0\]' +.*: Error: invalid base register at operand 3 -- `st1q {Z0.Q},P0,\[Z31.Q,x= 0\]' +.*: Error: invalid addressing mode at operand 3 -- `st1q {Z0.Q},P0,\[Z0.D,= x31\]' +.*: Error: operand mismatch -- `st1q {Z31.D},P7,\[Z31.D,x30\]' +.*: Info: did you mean this\? +.*: Info: st1q {z31.q}, p7, \[z31.d, x30\] +.*: Error: invalid offset register at operand 3 -- `st1q Z0.Q,P0,\[Z0.D,sp= \]' +.*: Error: operand mismatch -- `st1q Z0.Q,P0,\[Z0.S,x15\]' +.*: Info: did you mean this\? +.*: Info: st1q {z0.q}, p0, \[z0.d, x15\] +.*: Error: invalid use of 32-bit register offset at operand 3 -- `st1q Z0.= Q,P0,\[Z0.D,w10\]' +.*: Error: the register list must have a stride of 1 at operand 1 -- `st2q= {Z0.Q,Z2.Q},p0,\[x0,#-2,MUL VL\]' +.*: Error: invalid register list at operand 1 -- `st2q {Z31.Q,Z31.Q},p0,\[= x0,#-2,MUL VL\]' +.*: Error: p0-p7 expected at operand 2 -- `st2q {Z0.Q,Z1.Q},p8,\[x0,#-2,MU= L VL\]' +.*: Error: invalid base register at operand 3 -- `st2q {Z0.Q,Z1.Q},p0,\[x3= 1,#-2,MUL VL\]' +.*: Error: immediate value must be a multiple of 2 at operand 3 -- `st2q {= Z30.Q,Z31.Q},p7,\[x30,#-3,MUL VL\]' +.*: Error: invalid base register at operand 3 -- `st2q {Z0.Q,Z1.Q},p0,\[x3= 1,#-20,MUL VL\]' +.*: Error: invalid base register at operand 3 -- `st2q {Z0.Q,Z1.Q},p0,\[xz= r,#-20,MUL VL\]' +.*: Error: invalid register list at operand 1 -- `st3q {Z0.Q,Z1.Q,Z3.Q},p0= ,\[x0,#-3,MUL VL\]' +.*: Error: p0-p7 expected at operand 2 -- `st3q {Z29.Q,Z30.Q,Z31.Q},p8,\[x= 0,#-3,MUL VL\]' +.*: Error: immediate value must be a multiple of 3 at operand 3 -- `st3q {= Z0.Q,Z1.Q,Z2.Q},p7,\[x0,#-2,MUL VL\]' +.*: Error: invalid base register at operand 3 -- `st3q {Z0.Q,Z1.Q,Z2.Q},p0= ,\[x31,#-3,MUL VL\]' +.*: Error: type mismatch in vector register list at operand 1 -- `st3q {Z2= 9.Q,Z30.Q,Z31.D},p7,\[x30,#-3,MUL VL\]' +.*: Error: type mismatch in vector register list at operand 1 -- `st3q {Z2= 9.Q,Z30.Q,Z31.D},p7,\[x30,#-30,MUL VL\]' +.*: Error: type mismatch in vector register list at operand 1 -- `st3q {Z2= 9.Q,Z30.Q,Z31.D},p7,\[xzr,#-30,MUL VL\]' +.*: Error: expected a list of 4 registers at operand 1 -- `st4q {Z0.Q,Z1.Q= ,Z2.Q},p0,\[x0,#-4,MUL VL\]' +.*: Error: p0-p7 expected at operand 2 -- `st4q {Z28.Q,Z29.Q,Z30.Q,Z31.Q},= p9,\[x0,#-4,MUL VL\]' +.*: Error: immediate value must be a multiple of 4 at operand 3 -- `st4q {= Z0.Q,Z1.Q,Z2.Q,Z3.Q},p7,\[x0,#-3,MUL VL\]' +.*: Error: invalid base register at operand 3 -- `st4q {Z0.Q,Z1.Q,Z2.Q,Z3.= Q},p0,\[x31,#-4,MUL VL\]' +.*: Error: type mismatch in vector register list at operand 1 -- `st4q {Z2= 8.Q,Z29.Q,Z30.D,Z31.Q},p7,\[x30,#-4,MUL VL\]' +.*: Error: type mismatch in vector register list at operand 1 -- `st4q {Z2= 8.Q,Z29.Q,Z30.D,Z31.Q},p7,\[x30,#-100,MUL VL\]' +.*: Error: type mismatch in vector register list at operand 1 -- `st4q {Z2= 8.Q,Z29.Q,Z30.D,Z31.Q},p7,\[xzr,#-100,MUL VL\]' +.*: Error: invalid addressing mode at operand 3 -- `st2q {Z0.Q,Z1.Q},p0,\[= x0,x0,LSL#3\]' +.*: Error: invalid addressing mode at operand 3 -- `st2q {Z0.Q,Z1.Q},p0,\[= sp,x0,LSL#3\]' +.*: Error: invalid offset register at operand 3 -- `st2q {Z0.Q,Z1.Q},p0,\[= x0,sp,LSL#3\]' +.*: Error: invalid register list at operand 1 -- `st2q {Z31.Q,Z31.Q},p0,\[= x0,x0,LSL#4\]' +.*: Error: index register xzr is not allowed at operand 3 -- `st2q {Z30.Q,= Z31.Q},p0,\[x0,xzr,LSL#2\]' +.*: Error: p0-p7 expected at operand 2 -- `st2q {Z0.Q,Z1.Q},p8,\[x0,x0,LSL= #4\]' +.*: Error: invalid base register at operand 3 -- `st2q {Z0.Q,Z1.Q},p0,\[x3= 1,x0,LSL#4\]' +.*: Error: only 'MUL VL' is permitted at operand 3 -- `st2q {Z0.Q,Z1.Q},p0= ,\[x0,x31,LSL#4\]' +.*: Error: invalid base register at operand 3 -- `st2q {Z30.Q,Z31.Q},p7,\[= x31,x31,LSL#4\]' +.*: Error: shift expression expected at operand 3 -- `st3q {Z0.Q,Z1.Q,Z2.Q= },p0,\[x0,x0,#4\]' +.*: Error: shift expression expected at operand 3 -- `st3q {Z0.Q,Z1.Q,Z2.Q= },p0,\[sp,x0,#4\]' +.*: Error: invalid offset register at operand 3 -- `st3q {Z0.Q,Z1.Q,Z2.Q},= p0,\[x0,sp,#4\]' +.*: Error: invalid addressing mode at operand 3 -- `st3q {Z29.Q,Z30.Q,Z31.= Q},p0,\[x0,x0,LSL#2\]' +.*: Error: index register xzr is not allowed at operand 3 -- `st3q {Z29.Q,= Z30.Q,Z31.Q},p0,\[x0,xzr,LSL#3\]' +.*: Error: p0-p7 expected at operand 2 -- `st3q {Z0.Q,Z1.Q,Z2.Q},p8,\[x30,= x0,LSL#4\]' +.*: Error: invalid register list at operand 1 -- `st3q {Z4.Q,Z1.Q,Z2.Q},p0= ,\[x31,x30,LSL#4\]' +.*: Error: type mismatch in vector register list at operand 1 -- `st3q {Z2= 9.D,Z30.Q,Z31.Q},p7,\[x31,x30,LSL#4\]' +.*: Error: invalid register list at operand 1 -- `st4q {Z1.Q,Z1.Q,Z2.Q,Z3.= Q},p0,\[x0,x0,LSL#4\]' +.*: Error: invalid register list at operand 1 -- `st4q {Z1.Q,Z1.Q,Z2.Q,Z3.= Q},p0,\[sp,x0,LSL#4\]' +.*: Error: invalid register list at operand 1 -- `st4q {Z1.Q,Z1.Q,Z2.Q,Z3.= Q},p0,\[x0,sp,LSL#4\]' +.*: Error: invalid register list at operand 1 -- `st4q {Z30.Q,Z29.Q,Z30.Q,= Z31.Q},p8,\[x0,x0,LSL#4\]' +.*: Error: index register xzr is not allowed at operand 3 -- `st4q {Z28.Q,= Z29.Q,Z30.Q,Z31.Q},p7,\[x0,xzr,LSL#4\]' +.*: Error: invalid addressing mode at operand 3 -- `st4q {Z0.Q,Z1.Q,Z2.Q,Z= 3.Q},p7,\[x0,x0,LSL#2\]' +.*: Error: invalid base register at operand 3 -- `st4q {Z0.Q,Z1.Q,Z2.Q,Z3.= Q},p0,\[x31,x0,LSL#4\]' +.*: Error: type mismatch in vector register list at operand 1 -- `st4q {Z0= .Q,Z1.Q,Z2.D,Z3.Q},p0,\[x1,x30,LSL#4\]' +.*: Error: invalid register list at operand 1 -- `st4q {Z2.Q,Z29.Q,Z30.Q,Z= 31.Q},p7,\[x30,x30,LSL#4\]' diff --git a/gas/testsuite/gas/aarch64/sve2p1-4-invalid.s b/gas/testsuite/g= as/aarch64/sve2p1-4-invalid.s new file mode 100644 index 00000000000..789209f2eda --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve2p1-4-invalid.s @@ -0,0 +1,125 @@ +ld1q Z0.Q , P0/Z, [Z0.D, x0] +ld1q { Z0.Q }, P8/Z, [Z0.D, x0] +ld1q { Z0.Q }, P0/Z, [Z31.Q, x0] +ld1q { Z0.Q }, P0/Z, [Z0.D, x31] +ld1q { Z31.D }, P7/Z, [Z31.D, x30] +ld1q Z0.Q , P0/Z, [Z0.D, sp] +ld1q Z0.Q , P0/Z, [Z0.S, x15] +ld1q Z0.Q , P0/Z, [Z0.D, w10] + +ld2q {Z0.Q, Z2.Q}, p0/Z, [x0, #-2, MUL VL] +ld2q {Z31.Q, Z31.Q}, p0/Z, [x0, #-2, MUL VL] +ld2q {Z0.Q, Z1.Q}, p8/Z, [x0, #-2, MUL VL] +ld2q {Z0.Q, Z1.Q}, p0/Z, [x31, #-2, MUL VL] +ld2q {Z30.Q, Z31.Q}, p7/Z, [x30, #-3, MUL VL] +ld2q {Z0.Q, Z1.Q}, p0/Z, [x31, #-20, MUL VL] +ld2q {Z0.Q, Z1.Q}, p0/Z, [xzr, #-20, MUL VL] + +ld3q {Z0.Q, Z1.Q, Z3.Q}, p0/Z, [x0, #-3, MUL VL] +ld3q {Z29.Q, Z30.Q, Z31.Q}, p8/M, [x0, #-3, MUL VL] +ld3q {Z0.Q, Z1.Q, Z2.Q}, p7/Z, [x0, #-2, MUL VL] +ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x31, #-3, MUL VL] +ld3q {Z29.Q, Z30.Q, Z31.D}, p7/Z, [x30, #-3, MUL VL] +ld3q {Z29.Q, Z30.Q, Z31.D}, p7/Z, [x30, #-30, MUL VL] +ld3q {Z29.Q, Z30.Q, Z31.D}, p7/Z, [xzr, #-30, MUL VL] + +ld4q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0, #-4, MUL VL] +ld4q {Z28.Q, Z29.Q, Z30.Q,Z31.Q}, p9/Z, [x0, #-4, MUL VL] +ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p7/Z, [x0, #-3, MUL VL] +ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x31, #-4, MUL VL] +ld4q {Z28.Q, Z29.Q, Z30.D, Z31.Q}, p7/Z, [x30, #-4, MUL VL] +ld4q {Z28.Q, Z29.Q, Z30.D, Z31.Q}, p7/Z, [x30, #-100, MUL VL] +ld4q {Z28.Q, Z29.Q, Z30.D, Z31.Q}, p7/Z, [xzr, #-100, MUL VL] + +ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, x0, LSL #3] +ld2q {Z0.Q, Z1.Q}, p0/Z, [sp, x0, LSL #3] +ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, sp, LSL #3] +ld2q {Z31.Q, Z31.Q}, p0/Z, [x0, x0, LSL #4] +ld2q {Z31.Q, Z0.Q}, p0/Z, [x0, xzr, LSL #2] +ld2q {Z0.Q, Z1.Q}, p8/Z, [x0, x0, LSL #4] +ld2q {Z0.Q, Z1.Q}, p0/Z, [x31, x0, LSL #4] +ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, x31, LSL #4] +ld2q {Z30.Q, Z31.Q}, p7/Z, [x31, x31, LSL #4] + +ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0, x0, #4] +ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [sp, x0, #4] +ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0, sp, #4] +ld3q {Z29.Q, Z30.Q, Z31.Q}, p0/Z, [x0, x0, LSL #2] +ld3q {Z29.Q, Z30.Q, Z31.Q}, p0/Z, [x0, xzr, LSL #3] +ld3q {Z0.Q, Z1.Q, Z2.Q}, p7/M, [x0, x0, LSL #4] +ld3q {Z0.Q, Z1.Q, Z2.Q}, p8/Z, [x30, x0, LSL #4] +ld3q {Z4.Q, Z1.Q, Z2.Q}, p0/Z, [x31, x30, LSL #4] +ld3q {Z29.D, Z30.Q, Z31.Q}, p7/Z, [x31, x30, LSL #4] + +ld4q {Z1.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x0, x0, LSL #4] +ld4q {Z1.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [sp, x0, LSL #4] +ld4q {Z1.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x0, sp, LSL #4] +ld4q {Z30.Q, Z29.Q, Z30.Q,Z31.Q}, p8/Z, [x0, x0, LSL #4] +ld4q {Z28.Q, Z29.Q, Z30.Q,Z31.Q}, p7/Z, [x0, xzr, LSL #4] +ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p7/Z, [x0, x0, LSL #2] +ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x31, x0, LSL #4] +ld4q {Z0.Q, Z1.Q, Z2.D, Z3.Q}, p0/Z, [x1, x30, LSL #4] +ld4q {Z2.Q, Z29.Q, Z30.Q, Z31.Q}, p7/Z, [x30, x30, LSL #4] + +st1q Z0.Q , P0, [Z0.D, x0] +st1q { Z0.Q }, P8, [Z0.D, x0] +st1q { Z0.Q }, P0, [Z31.Q, x0] +st1q { Z0.Q }, P0, [Z0.D, x31] +st1q { Z31.D }, P7, [Z31.D, x30] +st1q Z0.Q , P0, [Z0.D, sp] +st1q Z0.Q , P0, [Z0.S, x15] +st1q Z0.Q , P0, [Z0.D, w10] + +st2q {Z0.Q, Z2.Q}, p0, [x0, #-2, MUL VL] +st2q {Z31.Q, Z31.Q}, p0, [x0, #-2, MUL VL] +st2q {Z0.Q, Z1.Q}, p8, [x0, #-2, MUL VL] +st2q {Z0.Q, Z1.Q}, p0, [x31, #-2, MUL VL] +st2q {Z30.Q, Z31.Q}, p7, [x30, #-3, MUL VL] +st2q {Z0.Q, Z1.Q}, p0, [x31, #-20, MUL VL] +st2q {Z0.Q, Z1.Q}, p0, [xzr, #-20, MUL VL] + +st3q {Z0.Q, Z1.Q, Z3.Q}, p0, [x0, #-3, MUL VL] +st3q {Z29.Q, Z30.Q, Z31.Q}, p8, [x0, #-3, MUL VL] +st3q {Z0.Q, Z1.Q, Z2.Q}, p7, [x0, #-2, MUL VL] +st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x31, #-3, MUL VL] +st3q {Z29.Q, Z30.Q, Z31.D}, p7, [x30, #-3, MUL VL] +st3q {Z29.Q, Z30.Q, Z31.D}, p7, [x30, #-30, MUL VL] +st3q {Z29.Q, Z30.Q, Z31.D}, p7, [xzr, #-30, MUL VL] + +st4q {Z0.Q, Z1.Q, Z2.Q}, p0, [x0, #-4, MUL VL] +st4q {Z28.Q, Z29.Q, Z30.Q,Z31.Q}, p9, [x0, #-4, MUL VL] +st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p7, [x0, #-3, MUL VL] +st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x31, #-4, MUL VL] +st4q {Z28.Q, Z29.Q, Z30.D, Z31.Q}, p7, [x30, #-4, MUL VL] +st4q {Z28.Q, Z29.Q, Z30.D, Z31.Q}, p7, [x30, #-100, MUL VL] +st4q {Z28.Q, Z29.Q, Z30.D, Z31.Q}, p7, [xzr, #-100, MUL VL] + +st2q {Z0.Q, Z1.Q}, p0, [x0, x0, LSL #3] +st2q {Z0.Q, Z1.Q}, p0, [sp, x0, LSL #3] +st2q {Z0.Q, Z1.Q}, p0, [x0, sp, LSL #3] +st2q {Z31.Q, Z31.Q}, p0, [x0, x0, LSL #4] +st2q {Z30.Q, Z31.Q}, p0, [x0, xzr, LSL #2] +st2q {Z0.Q, Z1.Q}, p8, [x0, x0, LSL #4] +st2q {Z0.Q, Z1.Q}, p0, [x31, x0, LSL #4] +st2q {Z0.Q, Z1.Q}, p0, [x0, x31, LSL #4] +st2q {Z30.Q, Z31.Q}, p7, [x31, x31, LSL #4] + +st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x0, x0, #4] +st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [sp, x0, #4] +st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x0, sp, #4] +st3q {Z29.Q, Z30.Q, Z31.Q}, p0, [x0, x0, LSL #2] +st3q {Z29.Q, Z30.Q, Z31.Q}, p0, [x0, xzr, LSL #3] +st3q {Z0.Q, Z1.Q, Z2.Q}, p7, [x0, x0, LSL #4] +st3q {Z0.Q, Z1.Q, Z2.Q}, p8, [x30, x0, LSL #4] +st3q {Z4.Q, Z1.Q, Z2.Q}, p0, [x31, x30, LSL #4] +st3q {Z29.D, Z30.Q, Z31.Q}, p7, [x31, x30, LSL #4] + +st4q {Z1.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x0, x0, LSL #4] +st4q {Z1.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [sp, x0, LSL #4] +st4q {Z1.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x0, sp, LSL #4] +st4q {Z30.Q, Z29.Q, Z30.Q,Z31.Q}, p8, [x0, x0, LSL #4] +st4q {Z28.Q, Z29.Q, Z30.Q,Z31.Q}, p7, [x0, xzr, LSL #4] +st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p7, [x0, x0, LSL #2] +st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x31, x0, LSL #4] +st4q {Z0.Q, Z1.Q, Z2.D, Z3.Q}, p0, [x1, x30, LSL #4] +st4q {Z2.Q, Z29.Q, Z30.Q, Z31.Q}, p7, [x30, x30, LSL #4] diff --git a/gas/testsuite/gas/aarch64/sve2p1-4.d b/gas/testsuite/gas/aarch= 64/sve2p1-4.d new file mode 100644 index 00000000000..390c63d8acf --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve2p1-4.d @@ -0,0 +1,152 @@ +#name: Test of SVE2.1 ld[1-4]q/st[1-4]q instructions. +#as: -march=3Darmv9.4-a +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +.*: c400a000 ld1q {z0.q}, p0/z, \[z0.d, x0\] +.*: c400a01f ld1q {z31.q}, p0/z, \[z0.d, x0\] +.*: c400bc00 ld1q {z0.q}, p7/z, \[z0.d, x0\] +.*: c400a3e0 ld1q {z0.q}, p0/z, \[z31.d, x0\] +.*: c41ea000 ld1q {z0.q}, p0/z, \[z0.d, x30\] +.*: c41fa000 ld1q {z0.q}, p0/z, \[z0.d\] +.*: c41fa000 ld1q {z0.q}, p0/z, \[z0.d\] +.*: c41ebfff ld1q {z31.q}, p7/z, \[z31.d, x30\] +.*: c404acef ld1q {z15.q}, p3/z, \[z7.d, x4\] +.*: a490e000 ld2q {z0.q-z1.q}, p0/z, \[x0\] +.*: a490e01f ld2q {z31.q-z0.q}, p0/z, \[x0\] +.*: a490fc00 ld2q {z0.q-z1.q}, p7/z, \[x0\] +.*: a490e3c0 ld2q {z0.q-z1.q}, p0/z, \[x30\] +.*: a490e3c0 ld2q {z0.q-z1.q}, p0/z, \[x30\] +.*: a498e000 ld2q {z0.q-z1.q}, p0/z, \[x0, #-16, mul vl\] +.*: a497e000 ld2q {z0.q-z1.q}, p0/z, \[x0, #14, mul vl\] +.*: a498ffdf ld2q {z31.q-z0.q}, p7/z, \[x30, #-16, mul vl\] +.*: a49be7e1 ld2q {z1.q-z2.q}, p1/z, \[sp, #-10, mul vl\] +.*: a49fe47e ld2q {z30.q-z31.q}, p1/z, \[x3, #-2, mul vl\] +.*: a510e000 ld3q {z0.q-z2.q}, p0/z, \[x0\] +.*: a510e01f ld3q {z31.q-z1.q}, p0/z, \[x0\] +.*: a510fc00 ld3q {z0.q-z2.q}, p7/z, \[x0\] +.*: a510e3c0 ld3q {z0.q-z2.q}, p0/z, \[x30\] +.*: a510e3c0 ld3q {z0.q-z2.q}, p0/z, \[x30\] +.*: a518e000 ld3q {z0.q-z2.q}, p0/z, \[x0, #-24, mul vl\] +.*: a517e000 ld3q {z0.q-z2.q}, p0/z, \[x0, #21, mul vl\] +.*: a518ffdf ld3q {z31.q-z1.q}, p7/z, \[x30, #-24, mul vl\] +.*: a51fffdd ld3q {z29.q-z31.q}, p7/z, \[x30, #-3, mul vl\] +.*: a51fffdd ld3q {z29.q-z31.q}, p7/z, \[x30, #-3, mul vl\] +.*: a51ce7e1 ld3q {z1.q-z3.q}, p1/z, \[sp, #-12, mul vl\] +.*: a51fffdd ld3q {z29.q-z31.q}, p7/z, \[x30, #-3, mul vl\] +.*: a590e000 ld4q {z0.q-z3.q}, p0/z, \[x0\] +.*: a590e01f ld4q {z31.q-z2.q}, p0/z, \[x0\] +.*: a590fc00 ld4q {z0.q-z3.q}, p7/z, \[x0\] +.*: a590e3c0 ld4q {z0.q-z3.q}, p0/z, \[x30\] +.*: a590e3c0 ld4q {z0.q-z3.q}, p0/z, \[x30\] +.*: a598e000 ld4q {z0.q-z3.q}, p0/z, \[x0, #-32, mul vl\] +.*: a597e000 ld4q {z0.q-z3.q}, p0/z, \[x0, #28, mul vl\] +.*: a598ffdf ld4q {z31.q-z2.q}, p7/z, \[x30, #-32, mul vl\] +.*: a59fffdc ld4q {z28.q-z31.q}, p7/z, \[x30, #-4, mul vl\] +.*: a59fffdc ld4q {z28.q-z31.q}, p7/z, \[x30, #-4, mul vl\] +.*: a59cf3e1 ld4q {z1.q-z4.q}, p4/z, \[sp, #-16, mul vl\] +.*: a59fffdc ld4q {z28.q-z31.q}, p7/z, \[x30, #-4, mul vl\] +.*: a4a08000 ld2q {z0.q-z1.q}, p0/z, \[x0, x0, lsl #4\] +.*: a4a0801f ld2q {z31.q-z0.q}, p0/z, \[x0, x0, lsl #4\] +.*: a4a09c00 ld2q {z0.q-z1.q}, p7/z, \[x0, x0, lsl #4\] +.*: a4a083c0 ld2q {z0.q-z1.q}, p0/z, \[x30, x0, lsl #4\] +.*: a4bd8000 ld2q {z0.q-z1.q}, p0/z, \[x0, x29, lsl #4\] +.*: a4bd9fdf ld2q {z31.q-z0.q}, p7/z, \[x30, x29, lsl #4\] +.*: a4b4914f ld2q {z15.q-z16.q}, p4/z, \[x10, x20, lsl #4\] +.*: a4b48ff4 ld2q {z20.q-z21.q}, p3/z, \[sp, x20, lsl #4\] +.*: a5208000 ld3q {z0.q-z2.q}, p0/z, \[x0, x0, lsl #4\] +.*: a520801f ld3q {z31.q-z1.q}, p0/z, \[x0, x0, lsl #4\] +.*: a5209c00 ld3q {z0.q-z2.q}, p7/z, \[x0, x0, lsl #4\] +.*: a52083c0 ld3q {z0.q-z2.q}, p0/z, \[x30, x0, lsl #4\] +.*: a53d8000 ld3q {z0.q-z2.q}, p0/z, \[x0, x29, lsl #4\] +.*: a53d9fdf ld3q {z31.q-z1.q}, p7/z, \[x30, x29, lsl #4\] +.*: a534894a ld3q {z10.q-z12.q}, p2/z, \[x10, x20, lsl #4\] +.*: a534894a ld3q {z10.q-z12.q}, p2/z, \[x10, x20, lsl #4\] +.*: a534894a ld3q {z10.q-z12.q}, p2/z, \[x10, x20, lsl #4\] +.*: a53497ef ld3q {z15.q-z17.q}, p5/z, \[sp, x20, lsl #4\] +.*: a5a08000 ld4q {z0.q-z3.q}, p0/z, \[x0, x0, lsl #4\] +.*: a5a0801f ld4q {z31.q-z2.q}, p0/z, \[x0, x0, lsl #4\] +.*: a5a09c00 ld4q {z0.q-z3.q}, p7/z, \[x0, x0, lsl #4\] +.*: a5a083c0 ld4q {z0.q-z3.q}, p0/z, \[x30, x0, lsl #4\] +.*: a5bd8000 ld4q {z0.q-z3.q}, p0/z, \[x0, x29, lsl #4\] +.*: a5bd9fdf ld4q {z31.q-z2.q}, p7/z, \[x30, x29, lsl #4\] +.*: a5a4886a ld4q {z10.q-z13.q}, p2/z, \[x3, x4, lsl #4\] +.*: a5a4886a ld4q {z10.q-z13.q}, p2/z, \[x3, x4, lsl #4\] +.*: a5a4886a ld4q {z10.q-z13.q}, p2/z, \[x3, x4, lsl #4\] +.*: a5a48bea ld4q {z10.q-z13.q}, p2/z, \[sp, x4, lsl #4\] +.*: e4202000 st1q {z0.q}, p0, \[z0.d, x0\] +.*: e420201f st1q {z31.q}, p0, \[z0.d, x0\] +.*: e4203c00 st1q {z0.q}, p7, \[z0.d, x0\] +.*: e42023e0 st1q {z0.q}, p0, \[z31.d, x0\] +.*: e43e2000 st1q {z0.q}, p0, \[z0.d, x30\] +.*: e43f2000 st1q {z0.q}, p0, \[z0.d\] +.*: e43f2000 st1q {z0.q}, p0, \[z0.d\] +.*: e43e3fff st1q {z31.q}, p7, \[z31.d, x30\] +.*: e4242cef st1q {z15.q}, p3, \[z7.d, x4\] +.*: e4400000 st2q {z0.q-z1.q}, p0, \[x0\] +.*: e440001f st2q {z31.q-z0.q}, p0, \[x0\] +.*: e4401c00 st2q {z0.q-z1.q}, p7, \[x0\] +.*: e44003c0 st2q {z0.q-z1.q}, p0, \[x30\] +.*: e44003c0 st2q {z0.q-z1.q}, p0, \[x30\] +.*: e4480000 st2q {z0.q-z1.q}, p0, \[x0, #-16, mul vl\] +.*: e4470000 st2q {z0.q-z1.q}, p0, \[x0, #14, mul vl\] +.*: e4481fdf st2q {z31.q-z0.q}, p7, \[x30, #-16, mul vl\] +.*: e44b07e1 st2q {z1.q-z2.q}, p1, \[sp, #-10, mul vl\] +.*: e44f047e st2q {z30.q-z31.q}, p1, \[x3, #-2, mul vl\] +.*: e4800000 st3q {z0.q-z2.q}, p0, \[x0\] +.*: e480001f st3q {z31.q-z1.q}, p0, \[x0\] +.*: e4801c00 st3q {z0.q-z2.q}, p7, \[x0\] +.*: e48003c0 st3q {z0.q-z2.q}, p0, \[x30\] +.*: e48003c0 st3q {z0.q-z2.q}, p0, \[x30\] +.*: e4880000 st3q {z0.q-z2.q}, p0, \[x0, #-24, mul vl\] +.*: e4870000 st3q {z0.q-z2.q}, p0, \[x0, #21, mul vl\] +.*: e4881fdf st3q {z31.q-z1.q}, p7, \[x30, #-24, mul vl\] +.*: e48f1fdd st3q {z29.q-z31.q}, p7, \[x30, #-3, mul vl\] +.*: e48f1fdd st3q {z29.q-z31.q}, p7, \[x30, #-3, mul vl\] +.*: e48c07e1 st3q {z1.q-z3.q}, p1, \[sp, #-12, mul vl\] +.*: e48f1fdd st3q {z29.q-z31.q}, p7, \[x30, #-3, mul vl\] +.*: e4c00000 st4q {z0.q-z3.q}, p0, \[x0\] +.*: e4c0001f st4q {z31.q-z2.q}, p0, \[x0\] +.*: e4c01c00 st4q {z0.q-z3.q}, p7, \[x0\] +.*: e4c003c0 st4q {z0.q-z3.q}, p0, \[x30\] +.*: e4c003c0 st4q {z0.q-z3.q}, p0, \[x30\] +.*: e4c80000 st4q {z0.q-z3.q}, p0, \[x0, #-32, mul vl\] +.*: e4c70000 st4q {z0.q-z3.q}, p0, \[x0, #28, mul vl\] +.*: e4c81fdf st4q {z31.q-z2.q}, p7, \[x30, #-32, mul vl\] +.*: e4cf1fdc st4q {z28.q-z31.q}, p7, \[x30, #-4, mul vl\] +.*: e4cf1fdc st4q {z28.q-z31.q}, p7, \[x30, #-4, mul vl\] +.*: e4cc13e1 st4q {z1.q-z4.q}, p4, \[sp, #-16, mul vl\] +.*: e4cf1fdc st4q {z28.q-z31.q}, p7, \[x30, #-4, mul vl\] +.*: e4600000 st2q {z0.q-z1.q}, p0, \[x0, x0, lsl #4\] +.*: e460001f st2q {z31.q-z0.q}, p0, \[x0, x0, lsl #4\] +.*: e4601c00 st2q {z0.q-z1.q}, p7, \[x0, x0, lsl #4\] +.*: e46003c0 st2q {z0.q-z1.q}, p0, \[x30, x0, lsl #4\] +.*: e47d0000 st2q {z0.q-z1.q}, p0, \[x0, x29, lsl #4\] +.*: e47d1fdf st2q {z31.q-z0.q}, p7, \[x30, x29, lsl #4\] +.*: e474114f st2q {z15.q-z16.q}, p4, \[x10, x20, lsl #4\] +.*: e4740ff4 st2q {z20.q-z21.q}, p3, \[sp, x20, lsl #4\] +.*: e4a00000 st3q {z0.q-z2.q}, p0, \[x0, x0, lsl #4\] +.*: e4a0001f st3q {z31.q-z1.q}, p0, \[x0, x0, lsl #4\] +.*: e4a01c00 st3q {z0.q-z2.q}, p7, \[x0, x0, lsl #4\] +.*: e4a003c0 st3q {z0.q-z2.q}, p0, \[x30, x0, lsl #4\] +.*: e4bd0000 st3q {z0.q-z2.q}, p0, \[x0, x29, lsl #4\] +.*: e4bd1fdf st3q {z31.q-z1.q}, p7, \[x30, x29, lsl #4\] +.*: e4b4094a st3q {z10.q-z12.q}, p2, \[x10, x20, lsl #4\] +.*: e4b4094a st3q {z10.q-z12.q}, p2, \[x10, x20, lsl #4\] +.*: e4b4094a st3q {z10.q-z12.q}, p2, \[x10, x20, lsl #4\] +.*: e4b417ef st3q {z15.q-z17.q}, p5, \[sp, x20, lsl #4\] +.*: e4e00000 st4q {z0.q-z3.q}, p0, \[x0, x0, lsl #4\] +.*: e4e0001f st4q {z31.q-z2.q}, p0, \[x0, x0, lsl #4\] +.*: e4e01c00 st4q {z0.q-z3.q}, p7, \[x0, x0, lsl #4\] +.*: e4e003c0 st4q {z0.q-z3.q}, p0, \[x30, x0, lsl #4\] +.*: e4fd0000 st4q {z0.q-z3.q}, p0, \[x0, x29, lsl #4\] +.*: e4fd1fdf st4q {z31.q-z2.q}, p7, \[x30, x29, lsl #4\] +.*: e4e4086a st4q {z10.q-z13.q}, p2, \[x3, x4, lsl #4\] +.*: e4e4086a st4q {z10.q-z13.q}, p2, \[x3, x4, lsl #4\] +.*: e4e4086a st4q {z10.q-z13.q}, p2, \[x3, x4, lsl #4\] +.*: e4e40bea st4q {z10.q-z13.q}, p2, \[sp, x4, lsl #4\] diff --git a/gas/testsuite/gas/aarch64/sve2p1-4.s b/gas/testsuite/gas/aarch= 64/sve2p1-4.s new file mode 100644 index 00000000000..70d5044bcaa --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve2p1-4.s @@ -0,0 +1,155 @@ +ld1q { Z0.Q }, P0/Z, [Z0.D, x0] +ld1q { Z31.Q }, P0/Z, [Z0.D, x0] +ld1q { Z0.Q }, P7/Z, [Z0.D, x0] +ld1q { Z0.Q }, P0/Z, [Z31.D, x0] +ld1q { Z0.Q }, P0/Z, [Z0.D, x30] +ld1q { Z0.Q }, P0/Z, [Z0.D, xzr] +ld1q { Z0.Q }, P0/Z, [Z0.D] +ld1q { Z31.Q }, P7/Z, [Z31.D, x30] +ld1q { Z15.Q }, P3/Z, [Z7.D, x4] + +ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #0, MUL VL] +ld2q {Z31.Q, Z0.Q}, p0/Z, [x0, #0, MUL VL] +ld2q {Z0.Q, Z1.Q}, p7/Z, [x0, #0, MUL VL] +ld2q {Z0.Q, Z1.Q}, p0/Z, [x30, #0, MUL VL] +ld2q {Z0.Q, Z1.Q}, p0/Z, [x30] +ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #-16, MUL VL] +ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #14, MUL VL] +ld2q {Z31.Q, Z0.Q}, p7/Z, [x30, #-16, MUL VL] +ld2q {Z1.Q, Z2.Q}, p1/Z, [sp, #-10, MUL VL] +ld2q {Z30.Q, Z31.Q}, p1/Z, [x3, #-2, MUL VL] + +ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0, #0, MUL VL] +ld3q {Z31.Q, Z0.Q, Z1.Q}, p0/Z, [x0, #0, MUL VL] +ld3q {Z0.Q, Z1.Q, Z2.Q}, p7/Z, [x0, #0, MUL VL] +ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x30, #0, MUL VL] +ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x30] +ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0, #-24, MUL VL] +ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0, #21, MUL VL] +ld3q {Z31.Q, Z0.Q, Z1.Q}, p7/Z, [x30, #-24, MUL VL] +ld3q {Z29.Q, Z30.Q, Z31.Q}, p7/Z, [x30, #-3, MUL VL] +ld3q {Z29.Q - Z30.Q - Z31.Q}, p7/Z, [x30, #-3, MUL VL] +ld3q {Z1.Q, Z2.Q, z3.Q}, p1/Z, [sp, #-12, MUL VL] +ld3q {Z29.Q - Z31.Q}, p7/Z, [x30, #-3, MUL VL] + +ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x0, #0, MUL VL] +ld4q {Z31.Q, Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0, #0, MUL VL] +ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p7/Z, [x0, #0, MUL VL] +ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x30, #0, MUL VL] +ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x30] +ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x0, #-32, MUL VL] +ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x0, #28, MUL VL] +ld4q {Z31.Q, Z0.Q, Z1.Q, Z2.Q}, p7/Z, [x30, #-32, MUL VL] +ld4q {Z28.Q, Z29.Q, Z30.Q, Z31.Q}, p7/Z, [x30, #-4, MUL VL] +ld4q {Z28.Q - Z29.Q - Z30.Q - Z31.Q}, p7/Z, [x30, #-4, MUL VL] +ld4q {Z1.Q, Z2.Q, z3.Q, Z4.Q}, p4/Z, [sp, #-16, MUL VL] +ld4q {Z28.Q - Z31.Q}, p7/Z, [x30, #-4, MUL VL] + +ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, x0, LSL #4] +ld2q {Z31.Q, Z0.Q}, p0/Z, [x0, x0, LSL #4] +ld2q {Z0.Q, Z1.Q}, p7/Z, [x0, x0, LSL #4] +ld2q {Z0.Q, Z1.Q}, p0/Z, [x30, x0, LSL #4] +ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, x29, LSL #4] +ld2q {Z31.Q, Z0.Q}, p7/Z, [x30, x29, LSL #4] +ld2q {Z15.Q, Z16.Q}, p4/Z, [x10, x20, LSL #4] +ld2q {Z20.Q, Z21.Q}, p3/Z, [sp, x20, LSL #4] + +ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0, x0, LSL #4] +ld3q {Z31.Q, Z0.Q, Z1.Q}, p0/Z, [x0, x0, LSL #4] +ld3q {Z0.Q, Z1.Q, Z2.Q}, p7/Z, [x0, x0, LSL #4] +ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x30, x0, LSL #4] +ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0, x29, LSL #4] +ld3q {Z31.Q, Z0.Q, Z1.Q}, p7/Z, [x30, x29, LSL #4] +ld3q {Z10.Q, Z11.Q, Z12.Q}, p2/Z, [x10, x20, LSL #4] +ld3q {Z10.Q - Z11.Q - Z12.Q}, p2/Z, [x10, x20, LSL #4] +ld3q {Z10.Q - Z12.Q}, p2/Z, [x10, x20, LSL #4] +ld3q {Z15.Q - Z17.Q}, p5/Z, [sp, x20, LSL #4] + +ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x0, x0, LSL #4] +ld4q {Z31.Q, Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0, x0, LSL #4] +ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p7/Z, [x0, x0, LSL #4] +ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x30, x0, LSL #4] +ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x0, x29, LSL #4] +ld4q {Z31.Q, Z0.Q, Z1.Q, Z2.Q}, p7/Z, [x30, x29, LSL #4] +ld4q {Z10.Q, Z11.Q, Z12.Q, Z13.Q}, p2/Z, [x3, x4, LSL #4] +ld4q {Z10.Q - Z11.Q - Z12.Q - Z13.Q}, p2/Z, [x3, x4, LSL #4] +ld4q {Z10.Q - Z13.Q}, p2/Z, [x3, x4, LSL #4] +ld4q {Z10.Q, Z11.Q, Z12.Q, Z13.Q}, p2/Z, [sp, x4, LSL #4] + +st1q { Z0.Q }, P0, [Z0.D, x0] +st1q { Z31.Q }, P0, [Z0.D, x0] +st1q { Z0.Q }, P7, [Z0.D, x0] +st1q { Z0.Q }, P0, [Z31.D, x0] +st1q { Z0.Q }, P0, [Z0.D, x30] +st1q { Z0.Q }, P0, [Z0.D, xzr] +st1q { Z0.Q }, P0, [Z0.D] +st1q { Z31.Q }, P7, [Z31.D, x30] +st1q { Z15.Q }, P3, [Z7.D, x4] + +st2q {Z0.Q, Z1.Q}, p0, [x0, #0, MUL VL] +st2q {Z31.Q, Z0.Q}, p0, [x0, #0, MUL VL] +st2q {Z0.Q, Z1.Q}, p7, [x0, #0, MUL VL] +st2q {Z0.Q, Z1.Q}, p0, [x30, #0, MUL VL] +st2q {Z0.Q, Z1.Q}, p0, [x30] +st2q {Z0.Q, Z1.Q}, p0, [x0, #-16, MUL VL] +st2q {Z0.Q, Z1.Q}, p0, [x0, #14, MUL VL] +st2q {Z31.Q, Z0.Q}, p7, [x30, #-16, MUL VL] +st2q {Z1.Q, Z2.Q}, p1, [sp, #-10, MUL VL] +st2q {Z30.Q, Z31.Q}, p1, [x3, #-2, MUL VL] + +st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x0, #0, MUL VL] +st3q {Z31.Q, Z0.Q, Z1.Q}, p0, [x0, #0, MUL VL] +st3q {Z0.Q, Z1.Q, Z2.Q}, p7, [x0, #0, MUL VL] +st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x30, #0, MUL VL] +st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x30] +st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x0, #-24, MUL VL] +st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x0, #21, MUL VL] +st3q {Z31.Q, Z0.Q, Z1.Q}, p7, [x30, #-24, MUL VL] +st3q {Z29.Q, Z30.Q, Z31.Q}, p7, [x30, #-3, MUL VL] +st3q {Z29.Q - Z30.Q - Z31.Q}, p7, [x30, #-3, MUL VL] +st3q {Z1.Q, Z2.Q, z3.Q}, p1, [sp, #-12, MUL VL] +st3q {Z29.Q - Z31.Q}, p7, [x30, #-3, MUL VL] + +st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x0, #0, MUL VL] +st4q {Z31.Q, Z0.Q, Z1.Q, Z2.Q}, p0, [x0, #0, MUL VL] +st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p7, [x0, #0, MUL VL] +st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x30, #0, MUL VL] +st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x30] +st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x0, #-32, MUL VL] +st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x0, #28, MUL VL] +st4q {Z31.Q, Z0.Q, Z1.Q, Z2.Q}, p7, [x30, #-32, MUL VL] +st4q {Z28.Q, Z29.Q, Z30.Q, Z31.Q}, p7, [x30, #-4, MUL VL] +st4q {Z28.Q - Z29.Q - Z30.Q - Z31.Q}, p7, [x30, #-4, MUL VL] +st4q {Z1.Q, Z2.Q, z3.Q, Z4.Q}, p4, [sp, #-16, MUL VL] +st4q {Z28.Q - Z31.Q}, p7, [x30, #-4, MUL VL] + +st2q {Z0.Q, Z1.Q}, p0, [x0, x0, LSL #4] +st2q {Z31.Q, Z0.Q}, p0, [x0, x0, LSL #4] +st2q {Z0.Q, Z1.Q}, p7, [x0, x0, LSL #4] +st2q {Z0.Q, Z1.Q}, p0, [x30, x0, LSL #4] +st2q {Z0.Q, Z1.Q}, p0, [x0, x29, LSL #4] +st2q {Z31.Q, Z0.Q}, p7, [x30, x29, LSL #4] +st2q {Z15.Q, Z16.Q}, p4, [x10, x20, LSL #4] +st2q {Z20.Q, Z21.Q}, p3, [sp, x20, LSL #4] + +st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x0, x0, LSL #4] +st3q {Z31.Q, Z0.Q, Z1.Q}, p0, [x0, x0, LSL #4] +st3q {Z0.Q, Z1.Q, Z2.Q}, p7, [x0, x0, LSL #4] +st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x30, x0, LSL #4] +st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x0, x29, LSL #4] +st3q {Z31.Q, Z0.Q, Z1.Q}, p7, [x30, x29, LSL #4] +st3q {Z10.Q, Z11.Q, Z12.Q}, p2, [x10, x20, LSL #4] +st3q {Z10.Q - Z11.Q - Z12.Q}, p2, [x10, x20, LSL #4] +st3q {Z10.Q - Z12.Q}, p2, [x10, x20, LSL #4] +st3q {Z15.Q - Z17.Q}, p5, [sp, x20, LSL #4] + +st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x0, x0, LSL #4] +st4q {Z31.Q, Z0.Q, Z1.Q, Z2.Q}, p0, [x0, x0, LSL #4] +st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p7, [x0, x0, LSL #4] +st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x30, x0, LSL #4] +st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x0, x29, LSL #4] +st4q {Z31.Q, Z0.Q, Z1.Q, Z2.Q}, p7, [x30, x29, LSL #4] +st4q {Z10.Q, Z11.Q, Z12.Q, Z13.Q}, p2, [x3, x4, LSL #4] +st4q {Z10.Q - Z11.Q - Z12.Q - Z13.Q}, p2, [x3, x4, LSL #4] +st4q {Z10.Q - Z13.Q}, p2, [x3, x4, LSL #4] +st4q {Z10.Q, Z11.Q, Z12.Q, Z13.Q}, p2, [sp, x4, LSL #4] diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index a178e8c6e4c..61758c96285 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -686,6 +686,7 @@ enum aarch64_opnd AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [, , LSL #1]. */ AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [, , LSL #2]. */ AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [, , LSL #3]. */ + AARCH64_OPND_SVE_ADDR_RX_LSL4, /* SVE [, , LSL #4]. */ AARCH64_OPND_SVE_ADDR_ZX, /* SVE [Zn.{, }]. */ AARCH64_OPND_SVE_ADDR_RZ, /* SVE [, Zm.D]. */ AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [, Zm.D, LSL #1]. */ @@ -861,9 +862,6 @@ enum aarch64_opnd AARCH64_OPND_MOPS_WB_Rn, /* Rn!, in bits [5, 9]. */ AARCH64_OPND_CSSC_SIMM8, /* CSSC signed 8-bit immediate. */ AARCH64_OPND_CSSC_UIMM8, /* CSSC unsigned 8-bit immediate. */ - AARCH64_OPND_SME_Zt2, /* Qobule SVE vector register list. */ - AARCH64_OPND_SME_Zt3, /* Trible SVE vector register list. */ - AARCH64_OPND_SME_Zt4, /* Quad SVE vector register list. */ AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND, /* []{, #}. */ AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB, /* [] or [, #]= !. */ AARCH64_OPND_RCPC3_ADDR_POSTIND, /* [], #. */ diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index 5eb21c24251..00d10f1e151 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -654,7 +654,6 @@ aarch64_insert_operand (const aarch64_operand *self, case 123: case 124: case 125: - case 183: case 184: case 185: case 186: @@ -668,31 +667,32 @@ aarch64_insert_operand (const aarch64_operand *self, case 194: case 195: case 196: - case 212: + case 197: case 213: case 214: case 215: - case 224: + case 216: case 225: case 226: case 227: case 228: - case 239: - case 243: - case 248: - case 256: + case 229: + case 240: + case 244: + case 249: case 257: case 258: - case 265: + case 259: case 266: case 267: case 268: + case 269: return aarch64_ins_regno (self, info, code, inst, errors); case 6: case 119: case 120: - case 304: - case 307: + case 305: + case 308: return aarch64_ins_none (self, info, code, inst, errors); case 17: return aarch64_ins_reg_extended (self, info, code, inst, errors); @@ -707,17 +707,16 @@ aarch64_insert_operand (const aarch64_operand *self, case 37: case 38: case 39: - case 309: + case 310: return aarch64_ins_reglane (self, info, code, inst, errors); case 40: case 41: case 42: - case 229: case 230: - case 233: - case 269: + case 231: + case 234: case 270: - case 285: + case 271: case 286: case 287: case 288: @@ -734,6 +733,7 @@ aarch64_insert_operand (const aarch64_operand *self, case 299: case 300: case 301: + case 302: return aarch64_ins_simple_index (self, info, code, inst, errors); case 43: return aarch64_ins_reglist (self, info, code, inst, errors); @@ -772,9 +772,8 @@ aarch64_insert_operand (const aarch64_operand *self, case 92: case 118: case 122: - case 180: - case 182: - case 203: + case 181: + case 183: case 204: case 205: case 206: @@ -783,14 +782,15 @@ aarch64_insert_operand (const aarch64_operand *self, case 209: case 210: case 211: - case 271: - case 302: + case 212: + case 272: case 303: - case 305: + case 304: case 306: - case 308: - case 313: + case 307: + case 309: case 314: + case 315: return aarch64_ins_imm (self, info, code, inst, errors); case 52: case 53: @@ -800,10 +800,10 @@ aarch64_insert_operand (const aarch64_operand *self, case 56: return aarch64_ins_advsimd_imm_modified (self, info, code, inst, err= ors); case 60: - case 170: + case 171: return aarch64_ins_fpimm (self, info, code, inst, errors); case 78: - case 178: + case 179: return aarch64_ins_limm (self, info, code, inst, errors); case 79: return aarch64_ins_aimm (self, info, code, inst, errors); @@ -813,11 +813,11 @@ aarch64_insert_operand (const aarch64_operand *self, return aarch64_ins_fbits (self, info, code, inst, errors); case 83: case 84: - case 175: + case 176: return aarch64_ins_imm_rotate2 (self, info, code, inst, errors); case 85: - case 174: - case 176: + case 175: + case 177: return aarch64_ins_imm_rotate1 (self, info, code, inst, errors); case 86: case 87: @@ -894,8 +894,8 @@ aarch64_insert_operand (const aarch64_operand *self, case 150: case 151: case 152: - return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors); case 153: + return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors); case 154: case 155: case 156: @@ -903,117 +903,115 @@ aarch64_insert_operand (const aarch64_operand *self, case 158: case 159: case 160: - return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors); case 161: + return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors); case 162: case 163: case 164: - return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors); case 165: - return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors); + return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors); case 166: - return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors); + return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors); case 167: - return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors); + return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors); case 168: - return aarch64_ins_sve_aimm (self, info, code, inst, errors); + return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors); case 169: + return aarch64_ins_sve_aimm (self, info, code, inst, errors); + case 170: return aarch64_ins_sve_asimm (self, info, code, inst, errors); - case 171: - return aarch64_ins_sve_float_half_one (self, info, code, inst, error= s); case 172: - return aarch64_ins_sve_float_half_two (self, info, code, inst, error= s); + return aarch64_ins_sve_float_half_one (self, info, code, inst, error= s); case 173: + return aarch64_ins_sve_float_half_two (self, info, code, inst, error= s); + case 174: return aarch64_ins_sve_float_zero_one (self, info, code, inst, error= s); - case 177: + case 178: return aarch64_ins_inv_limm (self, info, code, inst, errors); - case 179: + case 180: return aarch64_ins_sve_limm_mov (self, info, code, inst, errors); - case 181: + case 182: return aarch64_ins_sve_scale (self, info, code, inst, errors); - case 197: case 198: case 199: - return aarch64_ins_sve_shlimm (self, info, code, inst, errors); case 200: + return aarch64_ins_sve_shlimm (self, info, code, inst, errors); case 201: case 202: - case 284: + case 203: + case 285: return aarch64_ins_sve_shrimm (self, info, code, inst, errors); - case 216: case 217: case 218: case 219: - return aarch64_ins_sme_za_vrs1 (self, info, code, inst, errors); case 220: + return aarch64_ins_sme_za_vrs1 (self, info, code, inst, errors); case 221: case 222: case 223: + case 224: return aarch64_ins_sme_za_vrs2 (self, info, code, inst, errors); - case 231: case 232: - case 234: + case 233: case 235: case 236: case 237: case 238: + case 239: return aarch64_ins_sve_quad_index (self, info, code, inst, errors); - case 240: case 241: - return aarch64_ins_sve_index (self, info, code, inst, errors); case 242: - case 244: - case 264: - case 315: - case 316: - case 317: - return aarch64_ins_sve_reglist (self, info, code, inst, errors); + return aarch64_ins_sve_index (self, info, code, inst, errors); + case 243: case 245: + case 265: + return aarch64_ins_sve_reglist (self, info, code, inst, errors); case 246: - case 249: + case 247: case 250: case 251: case 252: case 253: - case 263: - return aarch64_ins_sve_aligned_reglist (self, info, code, inst, erro= rs); - case 247: case 254: + case 264: + return aarch64_ins_sve_aligned_reglist (self, info, code, inst, erro= rs); + case 248: case 255: + case 256: return aarch64_ins_sve_strided_reglist (self, info, code, inst, erro= rs); - case 259: - case 261: - case 272: - return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors); case 260: case 262: - return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, er= rors); case 273: + return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors); + case 261: + case 263: + return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, er= rors); case 274: case 275: case 276: case 277: case 278: case 279: - return aarch64_ins_sme_za_array (self, info, code, inst, errors); case 280: - return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors= ); + return aarch64_ins_sme_za_array (self, info, code, inst, errors); case 281: - return aarch64_ins_sme_sm_za (self, info, code, inst, errors); + return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors= ); case 282: - return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, = errors); + return aarch64_ins_sme_sm_za (self, info, code, inst, errors); case 283: + return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, = errors); + case 284: return aarch64_ins_plain_shrimm (self, info, code, inst, errors); - case 310: case 311: case 312: + case 313: return aarch64_ins_x0_to_x30 (self, info, code, inst, errors); + case 316: + case 317: case 318: case 319: - case 320: - case 321: return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, er= rors); - case 322: + case 320: return aarch64_ins_rcpc3_addr_offset (self, info, code, inst, errors= ); default: assert (0); abort (); } diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index 09527281178..95342ce0c0b 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -34443,7 +34443,6 @@ aarch64_extract_operand (const aarch64_operand *sel= f, case 123: case 124: case 125: - case 183: case 184: case 185: case 186: @@ -34457,31 +34456,32 @@ aarch64_extract_operand (const aarch64_operand *s= elf, case 194: case 195: case 196: - case 212: + case 197: case 213: case 214: case 215: - case 224: + case 216: case 225: case 226: case 227: case 228: - case 239: - case 243: - case 248: - case 256: + case 229: + case 240: + case 244: + case 249: case 257: case 258: - case 265: + case 259: case 266: case 267: case 268: + case 269: return aarch64_ext_regno (self, info, code, inst, errors); case 6: case 119: case 120: - case 304: - case 307: + case 305: + case 308: return aarch64_ext_none (self, info, code, inst, errors); case 11: return aarch64_ext_regrt_sysins (self, info, code, inst, errors); @@ -34501,17 +34501,16 @@ aarch64_extract_operand (const aarch64_operand *s= elf, case 37: case 38: case 39: - case 309: + case 310: return aarch64_ext_reglane (self, info, code, inst, errors); case 40: case 41: case 42: - case 229: case 230: - case 233: - case 269: + case 231: + case 234: case 270: - case 285: + case 271: case 286: case 287: case 288: @@ -34528,6 +34527,7 @@ aarch64_extract_operand (const aarch64_operand *sel= f, case 299: case 300: case 301: + case 302: return aarch64_ext_simple_index (self, info, code, inst, errors); case 43: return aarch64_ext_reglist (self, info, code, inst, errors); @@ -34567,9 +34567,8 @@ aarch64_extract_operand (const aarch64_operand *sel= f, case 92: case 118: case 122: - case 180: - case 182: - case 203: + case 181: + case 183: case 204: case 205: case 206: @@ -34578,14 +34577,15 @@ aarch64_extract_operand (const aarch64_operand *s= elf, case 209: case 210: case 211: - case 271: - case 302: + case 212: + case 272: case 303: - case 305: + case 304: case 306: - case 308: - case 313: + case 307: + case 309: case 314: + case 315: return aarch64_ext_imm (self, info, code, inst, errors); case 52: case 53: @@ -34597,10 +34597,10 @@ aarch64_extract_operand (const aarch64_operand *s= elf, case 57: return aarch64_ext_shll_imm (self, info, code, inst, errors); case 60: - case 170: + case 171: return aarch64_ext_fpimm (self, info, code, inst, errors); case 78: - case 178: + case 179: return aarch64_ext_limm (self, info, code, inst, errors); case 79: return aarch64_ext_aimm (self, info, code, inst, errors); @@ -34610,11 +34610,11 @@ aarch64_extract_operand (const aarch64_operand *s= elf, return aarch64_ext_fbits (self, info, code, inst, errors); case 83: case 84: - case 175: + case 176: return aarch64_ext_imm_rotate2 (self, info, code, inst, errors); case 85: - case 174: - case 176: + case 175: + case 177: return aarch64_ext_imm_rotate1 (self, info, code, inst, errors); case 86: case 87: @@ -34691,8 +34691,8 @@ aarch64_extract_operand (const aarch64_operand *sel= f, case 150: case 151: case 152: - return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors); case 153: + return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors); case 154: case 155: case 156: @@ -34700,118 +34700,115 @@ aarch64_extract_operand (const aarch64_operand = *self, case 158: case 159: case 160: - return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors); case 161: + return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors); case 162: case 163: case 164: - return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors); case 165: - return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors); + return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors); case 166: - return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors); + return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors); case 167: - return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors); + return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors); case 168: - return aarch64_ext_sve_aimm (self, info, code, inst, errors); + return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors); case 169: + return aarch64_ext_sve_aimm (self, info, code, inst, errors); + case 170: return aarch64_ext_sve_asimm (self, info, code, inst, errors); - case 171: - return aarch64_ext_sve_float_half_one (self, info, code, inst, error= s); case 172: - return aarch64_ext_sve_float_half_two (self, info, code, inst, error= s); + return aarch64_ext_sve_float_half_one (self, info, code, inst, error= s); case 173: + return aarch64_ext_sve_float_half_two (self, info, code, inst, error= s); + case 174: return aarch64_ext_sve_float_zero_one (self, info, code, inst, error= s); - case 177: + case 178: return aarch64_ext_inv_limm (self, info, code, inst, errors); - case 179: + case 180: return aarch64_ext_sve_limm_mov (self, info, code, inst, errors); - case 181: + case 182: return aarch64_ext_sve_scale (self, info, code, inst, errors); - case 197: case 198: case 199: - return aarch64_ext_sve_shlimm (self, info, code, inst, errors); case 200: + return aarch64_ext_sve_shlimm (self, info, code, inst, errors); case 201: case 202: - case 284: + case 203: + case 285: return aarch64_ext_sve_shrimm (self, info, code, inst, errors); - case 216: case 217: case 218: case 219: - return aarch64_ext_sme_za_vrs1 (self, info, code, inst, errors); case 220: + return aarch64_ext_sme_za_vrs1 (self, info, code, inst, errors); case 221: case 222: case 223: + case 224: return aarch64_ext_sme_za_vrs2 (self, info, code, inst, errors); - case 231: case 232: - case 234: + case 233: case 235: case 236: case 237: case 238: + case 239: return aarch64_ext_sve_quad_index (self, info, code, inst, errors); - case 240: case 241: - return aarch64_ext_sve_index (self, info, code, inst, errors); case 242: - case 244: - case 264: - return aarch64_ext_sve_reglist (self, info, code, inst, errors); + return aarch64_ext_sve_index (self, info, code, inst, errors); + case 243: case 245: + case 265: + return aarch64_ext_sve_reglist (self, info, code, inst, errors); case 246: - case 249: + case 247: case 250: case 251: case 252: case 253: - case 263: - return aarch64_ext_sve_aligned_reglist (self, info, code, inst, erro= rs); - case 247: case 254: + case 264: + return aarch64_ext_sve_aligned_reglist (self, info, code, inst, erro= rs); + case 248: case 255: + case 256: return aarch64_ext_sve_strided_reglist (self, info, code, inst, erro= rs); - case 259: - case 261: - case 272: - return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors); case 260: case 262: - return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, er= rors); case 273: + return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors); + case 261: + case 263: + return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, er= rors); case 274: case 275: case 276: case 277: case 278: case 279: - return aarch64_ext_sme_za_array (self, info, code, inst, errors); case 280: - return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors= ); + return aarch64_ext_sme_za_array (self, info, code, inst, errors); case 281: - return aarch64_ext_sme_sm_za (self, info, code, inst, errors); + return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors= ); case 282: - return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, = errors); + return aarch64_ext_sme_sm_za (self, info, code, inst, errors); case 283: + return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, = errors); + case 284: return aarch64_ext_plain_shrimm (self, info, code, inst, errors); - case 310: case 311: case 312: + case 313: return aarch64_ext_x0_to_x30 (self, info, code, inst, errors); - case 315: case 316: case 317: - return aarch64_ext_sve_reglist_zt (self, info, code, inst, errors); case 318: case 319: - case 320: - case 321: return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, er= rors); - case 322: + case 320: return aarch64_ext_rcpc3_addr_offset (self, info, code, inst, errors= ); default: assert (0); abort (); } diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index 3d067d4ad94..d42fea40f60 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -172,6 +172,7 @@ const struct aarch64_operand aarch64_operands[] =3D {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL1", (1 << OPD_F_OD_LSB) | O= PD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an= address with a scalar register offset"}, {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL2", (2 << OPD_F_OD_LSB) | O= PD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an= address with a scalar register offset"}, {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL3", (3 << OPD_F_OD_LSB) | O= PD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an= address with a scalar register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL4", (4 << OPD_F_OD_LSB) | O= PD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an= address with a scalar register offset"}, {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZX", OPD_F_HAS_INSERTER | OPD_F_H= AS_EXTRACTOR, {FLD_SVE_Zn,FLD_Rm}, "vector of address with a scalar registe= r offset"}, {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ", OPD_F_HAS_INSERTER | OPD_F_H= AS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register of= fset"}, {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL1", 1 << OPD_F_OD_LSB | OPD= _F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address = with a vector register offset"}, @@ -339,9 +340,6 @@ const struct aarch64_operand aarch64_operands[] =3D {AARCH64_OPND_CLASS_INT_REG, "MOPS_WB_Rd", OPD_F_HAS_INSERTER | OPD_F_HA= S_EXTRACTOR, {FLD_Rn}, "an integer register with writeback"}, {AARCH64_OPND_CLASS_IMMEDIATE, "CSSC_SIMM8", OPD_F_SEXT | OPD_F_HAS_INSE= RTER | OPD_F_HAS_EXTRACTOR, {FLD_CSSC_imm8}, "an 8-bit signed immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "CSSC_UIMM8", OPD_F_HAS_INSERTER | OPD_F_= HAS_EXTRACTOR, {FLD_CSSC_imm8}, "an 8-bit unsigned immediate"}, - {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zt2", 2 << OPD_F_OD_LSB | OPD_F_HA= S_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of 2 SVE vector reg= isters"}, - {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zt3", 3 << OPD_F_OD_LSB | OPD_F_HA= S_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of 3 SVE vector reg= isters"}, - {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zt4", 4 << OPD_F_OD_LSB | OPD_F_HA= S_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of 4 SVE vector reg= isters"}, {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_OPT_POSTIND", OPD_F_HAS_INSERTE= R | OPD_F_HAS_EXTRACTOR, {FLD_opc2}, "an address with post-incrementing by = ammount of loaded bytes"}, {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_OPT_PREIND_WB", OPD_F_HAS_INSER= TER | OPD_F_HAS_EXTRACTOR, {FLD_opc2}, "an address with pre-incrementing wi= th write-back by ammount of stored bytes"}, {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_POSTIND", OPD_F_HAS_INSERTER | = OPD_F_HAS_EXTRACTOR, {}, "an address with post-incrementing by ammount of l= oaded bytes"}, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 639347412d8..72eea596cae 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -1929,9 +1929,6 @@ operand_general_constraint_met_p (const aarch64_opnd_= info *opnds, int idx, case AARCH64_OPND_SME_Znx2: case AARCH64_OPND_SME_Znx2_BIT_INDEX: case AARCH64_OPND_SME_Znx4: - case AARCH64_OPND_SME_Zt2: - case AARCH64_OPND_SME_Zt3: - case AARCH64_OPND_SME_Zt4: num =3D get_operand_specific_data (&aarch64_operands[type]); if (!check_reglist (opnd, mismatch_detail, idx, num, 1)) return 0; @@ -2475,6 +2472,7 @@ operand_general_constraint_met_p (const aarch64_opnd_= info *opnds, int idx, case AARCH64_OPND_SVE_ADDR_RX_LSL1: case AARCH64_OPND_SVE_ADDR_RX_LSL2: case AARCH64_OPND_SVE_ADDR_RX_LSL3: + case AARCH64_OPND_SVE_ADDR_RX_LSL4: case AARCH64_OPND_SVE_ADDR_RZ: case AARCH64_OPND_SVE_ADDR_RZ_LSL1: case AARCH64_OPND_SVE_ADDR_RZ_LSL2: @@ -3768,10 +3766,7 @@ print_register_list (char *buf, size_t size, const a= arch64_opnd_info *opnd, /* The hyphenated form is preferred for disassembly if there is more than one register in the list, and the register numbers are monotonically increasing in increments of one. */ - if (stride =3D=3D 1 && num_regs > 1 - && ((opnd->type !=3D AARCH64_OPND_SME_Zt2) - && (opnd->type !=3D AARCH64_OPND_SME_Zt3) - && (opnd->type !=3D AARCH64_OPND_SME_Zt4))) + if (stride =3D=3D 1 && num_regs > 1) if (opnd->qualifier =3D=3D AARCH64_OPND_QLF_NIL) snprintf (buf, size, "{%s-%s}%s", style_reg (styler, "%s%d", prefix, first_reg), @@ -3877,36 +3872,51 @@ print_register_offset_address (char *buf, size_t si= ze, bool print_amount_p =3D true; const char *shift_name =3D aarch64_operand_modifiers[opnd->shifter.kind]= .name; =20 - if (!opnd->shifter.amount && (opnd->qualifier !=3D AARCH64_OPND_QLF_S_B - || !opnd->shifter.amount_present)) + /* This is the case where offset is the optional argument and the option= al + argument is ignored in the disassembly. */ + if (opnd->type =3D=3D AARCH64_OPND_SVE_ADDR_ZX && offset !=3D NULL + && strcmp (offset,"xzr") =3D=3D 0) { - /* Not print the shift/extend amount when the amount is zero and - when it is not the special case of 8-bit load/store instruction. = */ - print_amount_p =3D false; - /* Likewise, no need to print the shift operator LSL in such a - situation. */ - if (opnd->shifter.kind =3D=3D AARCH64_MOD_LSL) - print_extend_p =3D false; + /* Example: [.S{, }]. + When the assembly is [Z0.S, XZR] or [Z0.S], Xm is XZR in both the cases + and the preferred disassembly is [Z0.S], ignoring the optional Xm. */ + snprintf (buf, size, "[%s]", style_reg (styler, base)); } - - /* Prepare for the extend/shift. */ - if (print_extend_p) + else { - if (print_amount_p) - snprintf (tb, sizeof (tb), ", %s %s", - style_sub_mnem (styler, shift_name), - style_imm (styler, "#%" PRIi64, - /* PR 21096: The %100 is to silence a warning about possible truncation.= */ - (opnd->shifter.amount % 100))); + if (!opnd->shifter.amount && (opnd->qualifier !=3D AARCH64_OPND_QLF_= S_B + || !opnd->shifter.amount_present)) + { + /* Not print the shift/extend amount when the amount is zero and + when it is not the special case of 8-bit load/store + instruction. */ + print_amount_p =3D false; + /* Likewise, no need to print the shift operator LSL in such a + situation. */ + if (opnd->shifter.kind =3D=3D AARCH64_MOD_LSL) + print_extend_p =3D false; + } + + /* Prepare for the extend/shift. */ + if (print_extend_p) + { + if (print_amount_p) + snprintf (tb, sizeof (tb), ", %s %s", + style_sub_mnem (styler, shift_name), + style_imm (styler, "#%" PRIi64, + /* PR 21096: The %100 is to silence a warning about possible + truncation. */ + (opnd->shifter.amount % 100))); + else + snprintf (tb, sizeof (tb), ", %s", + style_sub_mnem (styler, shift_name)); + } else - snprintf (tb, sizeof (tb), ", %s", - style_sub_mnem (styler, shift_name)); - } - else - tb[0] =3D '\0'; + tb[0] =3D '\0'; =20 - snprintf (buf, size, "[%s, %s%s]", style_reg (styler, base), - style_reg (styler, offset), tb); + snprintf (buf, size, "[%s, %s%s]", style_reg (styler, base), + style_reg (styler, offset), tb); + } } =20 /* Print ZA tiles from imm8 in ZERO instruction. @@ -4257,9 +4267,6 @@ aarch64_print_operand (char *buf, size_t size, bfd_vm= a pc, case AARCH64_OPND_SME_Znx4: case AARCH64_OPND_SME_Ztx2_STRIDED: case AARCH64_OPND_SME_Ztx4_STRIDED: - case AARCH64_OPND_SME_Zt2: - case AARCH64_OPND_SME_Zt3: - case AARCH64_OPND_SME_Zt4: print_register_list (buf, size, opnd, "z", styler); break; =20 @@ -4724,6 +4731,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vm= a pc, case AARCH64_OPND_SVE_ADDR_RX_LSL1: case AARCH64_OPND_SVE_ADDR_RX_LSL2: case AARCH64_OPND_SVE_ADDR_RX_LSL3: + case AARCH64_OPND_SVE_ADDR_RX_LSL4: print_register_offset_address (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1), get_offset_int_reg_name (opnd), styler); diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 88921662775..8246de59f2f 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -1841,11 +1841,11 @@ { \ QLF3(S_S,P_Z,S_S), \ } -#define OP_SVE_SZS_QD \ +#define OP_SVE_QZD \ { \ QLF3(S_Q,P_Z,S_D), \ } -#define OP_SVE_SUS_QD \ +#define OP_SVE_QUD \ { \ QLF3(S_Q,NIL,S_D), \ } @@ -6642,21 +6642,23 @@ const struct aarch64_opcode aarch64_opcode_table[] = =3D =20 SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index, 0, OP2 (SVE_Zd, SV= E_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0), SVE2p1_INSNC("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP4 (SVE_Zd, SV= E_Zd, SVE_Zm_5, SVE_UIMM4), OP_SVE_BBBU, 0, C_SCAN_MOVPRFX, 1), - SVE2p1_INSNC("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt, SV= E_Pg3, SVE_ADDR_ZX), OP_SVE_SZS_QD, 0, C_SCAN_MOVPRFX, 0), - SVE2p1_INSNC("ld2q",0xa490e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt2, S= VE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), - SVE2p1_INSNC("ld3q",0xa510e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt3, S= VE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), - SVE2p1_INSNC("ld4q",0xa590e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt4, S= VE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), - SVE2p1_INSNC("ld2q",0xa4a08000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt2, S= VE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), - SVE2p1_INSNC("ld3q",0xa5208000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt3, S= VE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), - SVE2p1_INSNC("ld4q",0xa5a08000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt4, S= VE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), - - SVE2p1_INSNC("st1q",0xe4202000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt, SV= E_Pg3, SVE_ADDR_ZX), OP_SVE_SUS_QD, 0, C_SCAN_MOVPRFX, 0), - SVE2p1_INSNC("st2q",0xe4400000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt2, S= VE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0), - SVE2p1_INSNC("st3q",0xe4800000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt3, S= VE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0), - SVE2p1_INSNC("st4q",0xe4c00000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt4, S= VE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0), - SVE2p1_INSNC("st2q",0xe4600000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt2, S= VE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0), - SVE2p1_INSNC("st3q",0xe4a00000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt3, S= VE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0), - SVE2p1_INSNC("st4q",0xe4e00000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt4, S= VE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0), + + SVE2p1_INSN("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, S= VE_Pg3, SVE_ADDR_ZX), OP_SVE_QZD, F_OD (1), 0), + SVE2p1_INSN("ld2q",0xa490e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, S= VE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, F_OD (2), 0), + SVE2p1_INSN("ld3q",0xa510e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, S= VE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_QZU, F_OD (3), 0), + SVE2p1_INSN("ld4q",0xa590e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, S= VE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_QZU, F_OD (4), 0), + SVE2p1_INSN("ld2q",0xa4a08000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, S= VE_Pg3, SVE_ADDR_RX_LSL4), OP_SVE_QZU, F_OD (2), 0), + SVE2p1_INSN("ld3q",0xa5208000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, S= VE_Pg3, SVE_ADDR_RX_LSL4), OP_SVE_QZU, F_OD (3), 0), + SVE2p1_INSN("ld4q",0xa5a08000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, S= VE_Pg3, SVE_ADDR_RX_LSL4), OP_SVE_QZU, F_OD (4), 0), + + SVE2p1_INSN("st1q",0xe4202000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, S= VE_Pg3, SVE_ADDR_ZX), OP_SVE_QUD, F_OD (1), 0), + SVE2p1_INSN("st2q",0xe4400000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, S= VE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QUU, F_OD (2), 0), + SVE2p1_INSN("st3q",0xe4800000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, S= VE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_QUU, F_OD (3), 0), + SVE2p1_INSN("st4q",0xe4c00000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, S= VE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_QUU, F_OD (4), 0), + SVE2p1_INSN("st2q",0xe4600000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, S= VE_Pg3, SVE_ADDR_RX_LSL4), OP_SVE_QUU, F_OD (2), 0), + SVE2p1_INSN("st3q",0xe4a00000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, S= VE_Pg3, SVE_ADDR_RX_LSL4), OP_SVE_QUU, F_OD (3), 0), + SVE2p1_INSN("st4q",0xe4e00000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, S= VE_Pg3, SVE_ADDR_RX_LSL4), OP_SVE_QUU, F_OD (4), 0), + FP8_INSN("bf1cvtl", 0x2ea17800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn), QL_= V2FP8B8H, 0), FP8_INSN("bf1cvtl2", 0x6ea17800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn), QL= _V28H16B, 0), FP8_INSN("bf2cvtl", 0x2ee17800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn), QL_= V2FP8B8H, 0), @@ -7106,6 +7108,9 @@ const struct aarch64_opcode aarch64_opcode_table[] =3D Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RX_LSL3", \ (3 << OPD_F_OD_LSB) | OPD_F_NO_ZR, F(FLD_Rn,FLD_Rm), \ "an address with a scalar register offset") \ + Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RX_LSL4", \ + (4 << OPD_F_OD_LSB) | OPD_F_NO_ZR, F(FLD_Rn,FLD_Rm), \ + "an address with a scalar register offset") \ Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_ZX", \ 0 << OPD_F_OD_LSB , F(FLD_SVE_Zn,FLD_Rm), \ "vector of address with a scalar register offset") \ @@ -7493,15 +7498,6 @@ const struct aarch64_opcode aarch64_opcode_table[] = =3D "an 8-bit signed immediate") \ Y(IMMEDIATE, imm, "CSSC_UIMM8", 0, F(FLD_CSSC_imm8), \ "an 8-bit unsigned immediate") \ - X(SVE_REGLIST, ins_sve_reglist, ext_sve_reglist_zt, "SME_Zt2", \ - 2 << OPD_F_OD_LSB, F(FLD_SVE_Zt), \ - "a list of 2 SVE vector registers") \ - X(SVE_REGLIST, ins_sve_reglist, ext_sve_reglist_zt, "SME_Zt3", \ - 3 << OPD_F_OD_LSB, F(FLD_SVE_Zt), \ - "a list of 3 SVE vector registers") \ - X(SVE_REGLIST, ins_sve_reglist, ext_sve_reglist_zt, "SME_Zt4", \ - 4 << OPD_F_OD_LSB, F(FLD_SVE_Zt), \ - "a list of 4 SVE vector registers") \ X(ADDRESS, ins_rcpc3_addr_opt_offset, ext_rcpc3_addr_opt_offset, \ "RCPC3_ADDR_OPT_POSTIND", 0, F(FLD_opc2), \ "an address with post-incrementing by ammount of loaded bytes") \