* [binutils-gdb] x86/APX: optimize {nf}-form rotate-by-width-less-1
@ 2024-06-28 6:20 Jan Beulich
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From: Jan Beulich @ 2024-06-28 6:20 UTC (permalink / raw)
To: binutils-cvs
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=c7eae03eab750f93b6460e883f25b71d46dd1c47
commit c7eae03eab750f93b6460e883f25b71d46dd1c47
Author: Jan Beulich <jbeulich@suse.com>
Date: Fri Jun 28 08:19:32 2024 +0200
x86/APX: optimize {nf}-form rotate-by-width-less-1
Unlike for the legacy forms, where there's a difference in the resulting
EFLAGS.CF, for the NF variants the immediate can be got rid of in that
case by switching to a 1-bit rotate in the opposite direction.
Diff:
---
gas/config/tc-i386.c | 22 ++++++++++++++++-
gas/testsuite/gas/i386/x86-64-apx-nf-optimize.d | 32 +++++++++++++++++++++++++
gas/testsuite/gas/i386/x86-64-apx-nf.s | 20 ++++++++++++++++
opcodes/i386-opc.tbl | 22 ++++++++---------
opcodes/i386-tbl.h | 8 +++----
5 files changed, 88 insertions(+), 16 deletions(-)
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index c51402a9ced..7ffacf7a769 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -4927,6 +4927,7 @@ optimize_encoding (void)
}
else if (!optimize_for_space
&& i.tm.base_opcode == 0xd0
+ && i.tm.extension_opcode == 4
&& (i.tm.opcode_space == SPACE_BASE
|| i.tm.opcode_space == SPACE_EVEXMAP4)
&& !i.mem_operands)
@@ -4942,7 +4943,6 @@ optimize_encoding (void)
shll $1, %rN, %rM -> addl %rN, %rN, %rM
shlq $1, %rN, %rM -> addq %rN, %rN, %rM
*/
- gas_assert (i.tm.extension_opcode == 4);
i.tm.base_opcode = 0x00;
i.tm.extension_opcode = None;
if (i.operands >= 2)
@@ -5403,6 +5403,26 @@ optimize_nf_encoding (void)
i.imm_operands = 0;
--i.operands;
}
+ else if (i.tm.base_opcode == 0xc0
+ && i.op[0].imms->X_op == O_constant
+ && i.op[0].imms->X_add_number
+ == (i.types[i.operands - 1].bitfield.byte
+ || i.suffix == BYTE_MNEM_SUFFIX
+ ? 7 : i.types[i.operands - 1].bitfield.word
+ || i.suffix == WORD_MNEM_SUFFIX
+ ? 15 : 63 >> (i.types[i.operands - 1].bitfield.dword
+ || i.suffix == LONG_MNEM_SUFFIX)))
+ {
+ /* Optimize: -O:
+ {nf} rol $osz-1, ... -> {nf} ror $1, ...
+ {nf} ror $osz-1, ... -> {nf} rol $1, ...
+ */
+ gas_assert (i.tm.extension_opcode <= 1);
+ i.tm.extension_opcode ^= 1;
+ i.tm.base_opcode = 0xd0;
+ i.tm.operand_types[0].bitfield.imm1 = 1;
+ i.imm_operands = 0;
+ }
}
static void
diff --git a/gas/testsuite/gas/i386/x86-64-apx-nf-optimize.d b/gas/testsuite/gas/i386/x86-64-apx-nf-optimize.d
index ac05943386f..10561692da3 100644
--- a/gas/testsuite/gas/i386/x86-64-apx-nf-optimize.d
+++ b/gas/testsuite/gas/i386/x86-64-apx-nf-optimize.d
@@ -1480,4 +1480,36 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f4 74 1c ff 00[ ]+\{nf\} inc \(%rax\),%ecx
[ ]*[a-f0-9]+:[ ]*62 f4 fc 0c ff 00[ ]+\{nf\} incq \(%rax\)
[ ]*[a-f0-9]+:[ ]*62 f4 b4 1c ff 00[ ]+\{nf\} inc \(%rax\),%r9
+[ ]*[a-f0-9]+:[ ]*62 f4 7c 0c d0 ca[ ]+\{nf\} ror \$1,%dl
+[ ]*[a-f0-9]+:[ ]*62 f4 7c 1c d0 ca[ ]+\{nf\} ror \$1,%dl,%al
+[ ]*[a-f0-9]+:[ ]*62 f4 7d 0c d1 ca[ ]+\{nf\} ror \$1,%dx
+[ ]*[a-f0-9]+:[ ]*62 f4 7d 1c d1 ca[ ]+\{nf\} ror \$1,%dx,%ax
+[ ]*[a-f0-9]+:[ ]*62 f4 7c 0c d1 ca[ ]+\{nf\} ror \$1,%edx
+[ ]*[a-f0-9]+:[ ]*62 f4 7c 1c d1 ca[ ]+\{nf\} ror \$1,%edx,%eax
+[ ]*[a-f0-9]+:[ ]*62 f4 fc 0c d1 ca[ ]+\{nf\} ror \$1,%rdx
+[ ]*[a-f0-9]+:[ ]*62 f4 fc 1c d1 ca[ ]+\{nf\} ror \$1,%rdx,%rax
+[ ]*[a-f0-9]+:[ ]*62 f4 7c 0c d0 0a[ ]+\{nf\} rorb \$1,\(%rdx\)
+[ ]*[a-f0-9]+:[ ]*62 f4 7c 1c d0 0a[ ]+\{nf\} ror \$1,\(%rdx\),%al
+[ ]*[a-f0-9]+:[ ]*62 f4 7d 0c d1 0a[ ]+\{nf\} rorw \$1,\(%rdx\)
+[ ]*[a-f0-9]+:[ ]*62 f4 7d 1c d1 0a[ ]+\{nf\} ror \$1,\(%rdx\),%ax
+[ ]*[a-f0-9]+:[ ]*62 f4 7c 0c d1 0a[ ]+\{nf\} rorl \$1,\(%rdx\)
+[ ]*[a-f0-9]+:[ ]*62 f4 7c 1c d1 0a[ ]+\{nf\} ror \$1,\(%rdx\),%eax
+[ ]*[a-f0-9]+:[ ]*62 f4 fc 0c d1 0a[ ]+\{nf\} rorq \$1,\(%rdx\)
+[ ]*[a-f0-9]+:[ ]*62 f4 fc 1c d1 0a[ ]+\{nf\} ror \$1,\(%rdx\),%rax
+[ ]*[a-f0-9]+:[ ]*62 f4 7c 0c d0 c2[ ]+\{nf\} rol \$1,%dl
+[ ]*[a-f0-9]+:[ ]*62 f4 7c 1c d0 c2[ ]+\{nf\} rol \$1,%dl,%al
+[ ]*[a-f0-9]+:[ ]*62 f4 7d 0c d1 c2[ ]+\{nf\} rol \$1,%dx
+[ ]*[a-f0-9]+:[ ]*62 f4 7d 1c d1 c2[ ]+\{nf\} rol \$1,%dx,%ax
+[ ]*[a-f0-9]+:[ ]*62 f4 7c 0c d1 c2[ ]+\{nf\} rol \$1,%edx
+[ ]*[a-f0-9]+:[ ]*62 f4 7c 1c d1 c2[ ]+\{nf\} rol \$1,%edx,%eax
+[ ]*[a-f0-9]+:[ ]*62 f4 fc 0c d1 c2[ ]+\{nf\} rol \$1,%rdx
+[ ]*[a-f0-9]+:[ ]*62 f4 fc 1c d1 c2[ ]+\{nf\} rol \$1,%rdx,%rax
+[ ]*[a-f0-9]+:[ ]*62 f4 7c 0c d0 02[ ]+\{nf\} rolb \$1,\(%rdx\)
+[ ]*[a-f0-9]+:[ ]*62 f4 7c 1c d0 02[ ]+\{nf\} rol \$1,\(%rdx\),%al
+[ ]*[a-f0-9]+:[ ]*62 f4 7d 0c d1 02[ ]+\{nf\} rolw \$1,\(%rdx\)
+[ ]*[a-f0-9]+:[ ]*62 f4 7d 1c d1 02[ ]+\{nf\} rol \$1,\(%rdx\),%ax
+[ ]*[a-f0-9]+:[ ]*62 f4 7c 0c d1 02[ ]+\{nf\} roll \$1,\(%rdx\)
+[ ]*[a-f0-9]+:[ ]*62 f4 7c 1c d1 02[ ]+\{nf\} rol \$1,\(%rdx\),%eax
+[ ]*[a-f0-9]+:[ ]*62 f4 fc 0c d1 02[ ]+\{nf\} rolq \$1,\(%rdx\)
+[ ]*[a-f0-9]+:[ ]*62 f4 fc 1c d1 02[ ]+\{nf\} rol \$1,\(%rdx\),%rax
#pass
diff --git a/gas/testsuite/gas/i386/x86-64-apx-nf.s b/gas/testsuite/gas/i386/x86-64-apx-nf.s
index acb4ba639a0..14f65267317 100644
--- a/gas/testsuite/gas/i386/x86-64-apx-nf.s
+++ b/gas/testsuite/gas/i386/x86-64-apx-nf.s
@@ -1433,3 +1433,23 @@ optimize:
{nf} \op\()q $-1, (%rax)
{nf} \op $-1, (%rax), %r9
.endr
+
+ .irp dir, l, r
+ {nf} ro\dir $7, %dl
+ {nf} ro\dir $7, %dl, %al
+ {nf} ro\dir $15, %dx
+ {nf} ro\dir $15, %dx, %ax
+ {nf} ro\dir $31, %edx
+ {nf} ro\dir $31, %edx, %eax
+ {nf} ro\dir $63, %rdx
+ {nf} ro\dir $63, %rdx, %rax
+
+ {nf} ro\dir\()b $7, (%rdx)
+ {nf} ro\dir $7, (%rdx), %al
+ {nf} ro\dir\()w $15, (%rdx)
+ {nf} ro\dir $15, (%rdx), %ax
+ {nf} ro\dir\()l $31, (%rdx)
+ {nf} ro\dir $31, (%rdx), %eax
+ {nf} ro\dir\()q $63, (%rdx)
+ {nf} ro\dir $63, (%rdx), %rax
+ .endr
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 2715c5eb29c..bf4ecdb5a4a 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -446,22 +446,22 @@ imulzu, 0x69, APX_F, Modrm|No_bSuf|No_sSuf|RegKludge|EVexMap4|NF/*|ZU*/, { Imm16
<div>
-<sr:opc:imm8:opt1:nf, +
- rol:0:Imm8|Imm8S::NF, +
- ror:1:Imm8|Imm8S::NF, +
- rcl:2:Imm8::, +
- rcr:3:Imm8::, +
- sal:4:Imm8:Optimize:NF, +
- shl:4:Imm8:Optimize:NF, +
- shr:5:Imm8::NF, +
- sar:7:Imm8::NF>
+<sr:opc:imm8:opt1:opti:nf, +
+ rol:0:Imm8|Imm8S::Optimize:NF, +
+ ror:1:Imm8|Imm8S::Optimize:NF, +
+ rcl:2:Imm8:::, +
+ rcr:3:Imm8:::, +
+ sal:4:Imm8:Optimize::NF, +
+ shl:4:Imm8:Optimize::NF, +
+ shr:5:Imm8:::NF, +
+ sar:7:Imm8:::NF>
<sr>, 0xd0/<sr:opc>, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|<sr:opt1>|<sr:nf>, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
<sr>, 0xd0/<sr:opc>, 0, W|Modrm|No_sSuf|<sr:opt1>, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
<sr>, 0xd0/<sr:opc>, APX_F, W|Modrm|No_sSuf|EVexMap4|<sr:opt1>|<sr:nf>, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
-<sr>, 0xc0/<sr:opc>, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|<sr:nf>, { <sr:imm8>, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+<sr>, 0xc0/<sr:opc>, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|<sr:opti>|<sr:nf>, { <sr:imm8>, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
<sr>, 0xc0/<sr:opc>, i186, W|Modrm|No_sSuf, { <sr:imm8>, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
-<sr>, 0xc0/<sr:opc>, APX_F, W|Modrm|No_sSuf|EVexMap4|<sr:nf>, { <sr:imm8>, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+<sr>, 0xc0/<sr:opc>, APX_F, W|Modrm|No_sSuf|EVexMap4|<sr:opti>|<sr:nf>, { <sr:imm8>, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
<sr>, 0xd2/<sr:opc>, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|<sr:nf>, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
<sr>, 0xd2/<sr:opc>, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
<sr>, 0xd2/<sr:opc>, APX_F, W|Modrm|No_sSuf|EVexMap4|<sr:nf>, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 17cf8dc4b4b..c69ecb1adf0 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -3652,7 +3652,7 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 1, 0 } } } },
{ MN_rol, 0xc0, 3, SPACE_EVEXMAP4, 0,
{ 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 3, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 3, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
1, 0 },
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
@@ -3674,7 +3674,7 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 1, 0 } } } },
{ MN_rol, 0xc0, 2, SPACE_EVEXMAP4, 0,
{ 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
1, 0 },
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
@@ -3756,7 +3756,7 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 1, 0 } } } },
{ MN_ror, 0xc0, 3, SPACE_EVEXMAP4, 1,
{ 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 3, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 3, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
1, 0 },
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
@@ -3778,7 +3778,7 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 1, 0 } } } },
{ MN_ror, 0xc0, 2, SPACE_EVEXMAP4, 1,
{ 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
1, 0 },
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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