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* [binutils-gdb] aarch64: relax gas testsuite whitespace expectations
@ 2024-08-09  9:52 Jan Beulich
  0 siblings, 0 replies; only message in thread
From: Jan Beulich @ 2024-08-09  9:52 UTC (permalink / raw)
  To: binutils-cvs

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=e052622907b6d5014b0385b30e4ab4a8ab516496

commit e052622907b6d5014b0385b30e4ab4a8ab516496
Author: Jan Beulich <jbeulich@suse.com>
Date:   Fri Aug 9 11:52:18 2024 +0200

    aarch64: relax gas testsuite whitespace expectations
    
    In a subsequent change the scrubber is going to be changed to retain
    further whitespace. Test case expectations generally would better not
    depend on the specific whitespace treatment by the scrubber, unless of
    course a test is specifically about it. Adjust relevant test cases to
    permit blanks where those will subsequently appear.

Diff:
---
 gas/testsuite/gas/aarch64/advsimd-lut-bad.l        |   48 +-
 gas/testsuite/gas/aarch64/advsimd-lut-illegal.l    |  220 ++--
 gas/testsuite/gas/aarch64/bfloat16-2-invalid.l     |   12 +-
 gas/testsuite/gas/aarch64/cpa-addsub-bad.l         |   16 +-
 gas/testsuite/gas/aarch64/cpa-addsub-neg.l         |   12 +-
 gas/testsuite/gas/aarch64/diagnostic.l             |   72 +-
 gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.l    |  136 +--
 gas/testsuite/gas/aarch64/fp8-sme-fmlal-illegal.l  |  108 +-
 gas/testsuite/gas/aarch64/fp8-sme-fmlall-illegal.l |  108 +-
 gas/testsuite/gas/aarch64/illegal-sve2-sve1ext.l   |  142 +--
 gas/testsuite/gas/aarch64/illegal-sve2.l           |  368 +++---
 gas/testsuite/gas/aarch64/illegal.l                |   52 +-
 gas/testsuite/gas/aarch64/rcpc3-fp-fail.l          |    8 +-
 gas/testsuite/gas/aarch64/reglist-2.l              |   14 +-
 gas/testsuite/gas/aarch64/sme-4-illegal.l          |   68 +-
 gas/testsuite/gas/aarch64/sme-5-illegal.l          |   52 +-
 gas/testsuite/gas/aarch64/sme-6-illegal.l          |   40 +-
 gas/testsuite/gas/aarch64/sme-7-illegal.l          |   16 +-
 gas/testsuite/gas/aarch64/sme2-1-invalid.l         |  600 ++++-----
 gas/testsuite/gas/aarch64/sme2-1-noarch.l          |  576 ++++-----
 gas/testsuite/gas/aarch64/sme2-10-invalid.l        |   92 +-
 gas/testsuite/gas/aarch64/sme2-10-noarch.l         | 1280 ++++++++++----------
 gas/testsuite/gas/aarch64/sme2-11-invalid.l        |  158 +--
 gas/testsuite/gas/aarch64/sme2-11-noarch.l         |  232 ++--
 gas/testsuite/gas/aarch64/sme2-12-invalid.l        |  194 +--
 gas/testsuite/gas/aarch64/sme2-12-noarch.l         |  900 +++++++-------
 gas/testsuite/gas/aarch64/sme2-13-invalid.l        |  102 +-
 gas/testsuite/gas/aarch64/sme2-13-noarch.l         |  400 +++---
 gas/testsuite/gas/aarch64/sme2-14-invalid.l        |    4 +-
 gas/testsuite/gas/aarch64/sme2-14-noarch.l         |  172 +--
 gas/testsuite/gas/aarch64/sme2-15-invalid.l        |  148 +--
 gas/testsuite/gas/aarch64/sme2-15-noarch.l         |  372 +++---
 gas/testsuite/gas/aarch64/sme2-16-invalid.l        |  148 +--
 gas/testsuite/gas/aarch64/sme2-16-noarch.l         |  496 ++++----
 gas/testsuite/gas/aarch64/sme2-17-invalid.l        |   20 +-
 gas/testsuite/gas/aarch64/sme2-17-noarch.l         |   88 +-
 gas/testsuite/gas/aarch64/sme2-18-invalid.l        |   32 +-
 gas/testsuite/gas/aarch64/sme2-18-noarch.l         |   40 +-
 gas/testsuite/gas/aarch64/sme2-19-invalid.l        |   58 +-
 gas/testsuite/gas/aarch64/sme2-19-noarch.l         |   80 +-
 gas/testsuite/gas/aarch64/sme2-2-invalid.l         |  390 +++---
 gas/testsuite/gas/aarch64/sme2-2-noarch.l          |  960 +++++++--------
 gas/testsuite/gas/aarch64/sme2-20-invalid.l        |   36 +-
 gas/testsuite/gas/aarch64/sme2-20-noarch.l         |   40 +-
 gas/testsuite/gas/aarch64/sme2-22-invalid.l        |   20 +-
 gas/testsuite/gas/aarch64/sme2-22-noarch.l         |  220 ++--
 gas/testsuite/gas/aarch64/sme2-23-invalid.l        |   14 +-
 gas/testsuite/gas/aarch64/sme2-23-noarch.l         |  128 +-
 gas/testsuite/gas/aarch64/sme2-24-invalid.l        |   20 +-
 gas/testsuite/gas/aarch64/sme2-24-noarch.l         |   32 +-
 gas/testsuite/gas/aarch64/sme2-25-invalid.l        |   44 +-
 gas/testsuite/gas/aarch64/sme2-25-noarch.l         |   72 +-
 gas/testsuite/gas/aarch64/sme2-26-invalid.l        |   22 +-
 gas/testsuite/gas/aarch64/sme2-26-noarch.l         |   48 +-
 gas/testsuite/gas/aarch64/sme2-27-invalid.l        |   34 +-
 gas/testsuite/gas/aarch64/sme2-27-noarch.l         |   98 +-
 gas/testsuite/gas/aarch64/sme2-28-invalid.l        |   18 +-
 gas/testsuite/gas/aarch64/sme2-28-noarch.l         |   50 +-
 gas/testsuite/gas/aarch64/sme2-29-invalid.l        |   22 +-
 gas/testsuite/gas/aarch64/sme2-29-noarch.l         |   72 +-
 gas/testsuite/gas/aarch64/sme2-3-invalid.l         |  114 +-
 gas/testsuite/gas/aarch64/sme2-3-noarch.l          |  960 +++++++--------
 gas/testsuite/gas/aarch64/sme2-30-invalid.l        |   30 +-
 gas/testsuite/gas/aarch64/sme2-30-noarch.l         |  180 +--
 gas/testsuite/gas/aarch64/sme2-4-invalid.l         |  114 +-
 gas/testsuite/gas/aarch64/sme2-4-noarch.l          |  960 +++++++--------
 gas/testsuite/gas/aarch64/sme2-5-invalid.l         |  114 +-
 gas/testsuite/gas/aarch64/sme2-5-noarch.l          |  960 +++++++--------
 gas/testsuite/gas/aarch64/sme2-6-invalid.l         |   84 +-
 gas/testsuite/gas/aarch64/sme2-6-noarch.l          |  160 +--
 gas/testsuite/gas/aarch64/sme2-8-invalid.l         |   88 +-
 gas/testsuite/gas/aarch64/sme2-8-noarch.l          |  102 +-
 gas/testsuite/gas/aarch64/sme2-9-invalid.l         |  216 ++--
 gas/testsuite/gas/aarch64/sme2-9-noarch.l          |  352 +++---
 gas/testsuite/gas/aarch64/sme2-f64f64-1-invalid.l  |   36 +-
 gas/testsuite/gas/aarch64/sme2-f64f64-1-noarch.l   |   64 +-
 gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.l  |  154 +--
 gas/testsuite/gas/aarch64/sme2-f64f64-2-noarch.l   |  232 ++--
 gas/testsuite/gas/aarch64/sme2-faminmax-bad.l      |   96 +-
 gas/testsuite/gas/aarch64/sme2-faminmax-illegal.l  |   92 +-
 gas/testsuite/gas/aarch64/sme2-fp8-fail.l          |   96 +-
 gas/testsuite/gas/aarch64/sme2-i16i64-1-invalid.l  |  148 +--
 gas/testsuite/gas/aarch64/sme2-i16i64-1-noarch.l   |  112 +-
 gas/testsuite/gas/aarch64/sme2-i16i64-2-invalid.l  |  114 +-
 gas/testsuite/gas/aarch64/sme2-i16i64-2-noarch.l   |  400 +++---
 gas/testsuite/gas/aarch64/sme2-i16i64-3-invalid.l  |   20 +-
 gas/testsuite/gas/aarch64/sme2-i16i64-3-noarch.l   |  248 ++--
 gas/testsuite/gas/aarch64/sme2-i16i64-4-invalid.l  |   20 +-
 gas/testsuite/gas/aarch64/sme2-i16i64-4-noarch.l   |   40 +-
 gas/testsuite/gas/aarch64/sme2-lutv2-bad.l         |   18 +-
 gas/testsuite/gas/aarch64/sme2-lutv2-illegal.l     |   90 +-
 gas/testsuite/gas/aarch64/sme2p1-2-bad.l           |   82 +-
 gas/testsuite/gas/aarch64/sme2p1-3-bad.l           |   30 +-
 gas/testsuite/gas/aarch64/sve-invalid.l            |  320 ++---
 gas/testsuite/gas/aarch64/sve-reg-diagnostic.l     |    2 +-
 gas/testsuite/gas/aarch64/sve2-fp8-fail.l          |   32 +-
 gas/testsuite/gas/aarch64/sve2-lut-bad.l           |   66 +-
 gas/testsuite/gas/aarch64/sve2-lut-illegal.l       |  226 ++--
 gas/testsuite/gas/aarch64/sve2-sme2-2-invalid.l    |   24 +-
 gas/testsuite/gas/aarch64/sve2-sme2-2-noarch.l     |  512 ++++----
 gas/testsuite/gas/aarch64/sve2-sme2-5-invalid.l    |   18 +-
 gas/testsuite/gas/aarch64/sve2-sme2-5-noarch.l     |   24 +-
 gas/testsuite/gas/aarch64/sve2-sme2-6-invalid.l    |   20 +-
 gas/testsuite/gas/aarch64/sve2-sme2-6-noarch.l     |   30 +-
 gas/testsuite/gas/aarch64/sve2-sme2-7-invalid.l    |    2 +-
 gas/testsuite/gas/aarch64/sve2p1-4-invalid.l       |  110 +-
 gas/testsuite/gas/aarch64/sve2p1-6-invalid.l       |   12 +-
 gas/testsuite/gas/aarch64/verbose-error.l          |    4 +-
 108 files changed, 8976 insertions(+), 8976 deletions(-)

diff --git a/gas/testsuite/gas/aarch64/advsimd-lut-bad.l b/gas/testsuite/gas/aarch64/advsimd-lut-bad.l
index 3afe4a39c54..800f44cce97 100644
--- a/gas/testsuite/gas/aarch64/advsimd-lut-bad.l
+++ b/gas/testsuite/gas/aarch64/advsimd-lut-bad.l
@@ -1,25 +1,25 @@
 [^ :]+: Assembler messages:
-.*: Error: selected processor does not support `luti2 v0.16b,{v0.16b},v0\[0\]'
-.*: Error: selected processor does not support `luti2 v31.16b,{v0.16b},v0\[0\]'
-.*: Error: selected processor does not support `luti2 v0.16b,{v31.16b},v0\[0\]'
-.*: Error: selected processor does not support `luti2 v0.16b,{v0.16b},v31\[0\]'
-.*: Error: selected processor does not support `luti2 v0.16b,{v0.16b},v31\[3\]'
-.*: Error: selected processor does not support `luti2 v17.16b,{v21.16b},v27\[2\]'
-.*: Error: selected processor does not support `luti2 v0.8h,{v0.8h},v0\[0\]'
-.*: Error: selected processor does not support `luti2 v31.8h,{v0.8h},v0\[0\]'
-.*: Error: selected processor does not support `luti2 v0.8h,{v31.8h},v0\[0\]'
-.*: Error: selected processor does not support `luti2 v0.8h,{v0.8h},v31\[0\]'
-.*: Error: selected processor does not support `luti2 v0.8h,{v0.8h},v0\[7\]'
-.*: Error: selected processor does not support `luti2 v17.8h,{v21.8h},v27\[4\]'
-.*: Error: selected processor does not support `luti4 v0.16b,{v0.16b},v0\[0\]'
-.*: Error: selected processor does not support `luti4 v31.16b,{v0.16b},v0\[0\]'
-.*: Error: selected processor does not support `luti4 v0.16b,{v31.16b},v0\[0\]'
-.*: Error: selected processor does not support `luti4 v0.16b,{v0.16b},v31\[0\]'
-.*: Error: selected processor does not support `luti4 v0.16b,{v0.16b},v0\[1\]'
-.*: Error: selected processor does not support `luti4 v17.16b,{v21.16b},v27\[1\]'
-.*: Error: selected processor does not support `luti4 v0.8h,{v0.8h,v1.8h},v0\[0\]'
-.*: Error: selected processor does not support `luti4 v31.8h,{v0.8h,v1.8h},v0\[0\]'
-.*: Error: selected processor does not support `luti4 v0.8h,{v31.8h,v0.8h},v0\[0\]'
-.*: Error: selected processor does not support `luti4 v0.8h,{v0.8h,v1.8h},v31\[0\]'
-.*: Error: selected processor does not support `luti4 v0.8h,{v0.8h,v1.8h},v0\[3\]'
-.*: Error: selected processor does not support `luti4 v17.8h,{v21.8h,v22.8h},v27\[2\]'
+.*: Error: selected processor does not support `luti2 v0.16b,{ ?v0.16b ?},v0\[0\]'
+.*: Error: selected processor does not support `luti2 v31.16b,{ ?v0.16b ?},v0\[0\]'
+.*: Error: selected processor does not support `luti2 v0.16b,{ ?v31.16b ?},v0\[0\]'
+.*: Error: selected processor does not support `luti2 v0.16b,{ ?v0.16b ?},v31\[0\]'
+.*: Error: selected processor does not support `luti2 v0.16b,{ ?v0.16b ?},v31\[3\]'
+.*: Error: selected processor does not support `luti2 v17.16b,{ ?v21.16b ?},v27\[2\]'
+.*: Error: selected processor does not support `luti2 v0.8h,{ ?v0.8h ?},v0\[0\]'
+.*: Error: selected processor does not support `luti2 v31.8h,{ ?v0.8h ?},v0\[0\]'
+.*: Error: selected processor does not support `luti2 v0.8h,{ ?v31.8h ?},v0\[0\]'
+.*: Error: selected processor does not support `luti2 v0.8h,{ ?v0.8h ?},v31\[0\]'
+.*: Error: selected processor does not support `luti2 v0.8h,{ ?v0.8h ?},v0\[7\]'
+.*: Error: selected processor does not support `luti2 v17.8h,{ ?v21.8h ?},v27\[4\]'
+.*: Error: selected processor does not support `luti4 v0.16b,{ ?v0.16b ?},v0\[0\]'
+.*: Error: selected processor does not support `luti4 v31.16b,{ ?v0.16b ?},v0\[0\]'
+.*: Error: selected processor does not support `luti4 v0.16b,{ ?v31.16b ?},v0\[0\]'
+.*: Error: selected processor does not support `luti4 v0.16b,{ ?v0.16b ?},v31\[0\]'
+.*: Error: selected processor does not support `luti4 v0.16b,{ ?v0.16b ?},v0\[1\]'
+.*: Error: selected processor does not support `luti4 v17.16b,{ ?v21.16b ?},v27\[1\]'
+.*: Error: selected processor does not support `luti4 v0.8h,{ ?v0.8h,v1.8h ?},v0\[0\]'
+.*: Error: selected processor does not support `luti4 v31.8h,{ ?v0.8h,v1.8h ?},v0\[0\]'
+.*: Error: selected processor does not support `luti4 v0.8h,{ ?v31.8h,v0.8h ?},v0\[0\]'
+.*: Error: selected processor does not support `luti4 v0.8h,{ ?v0.8h,v1.8h ?},v31\[0\]'
+.*: Error: selected processor does not support `luti4 v0.8h,{ ?v0.8h,v1.8h ?},v0\[3\]'
+.*: Error: selected processor does not support `luti4 v17.8h,{ ?v21.8h,v22.8h ?},v27\[2\]'
diff --git a/gas/testsuite/gas/aarch64/advsimd-lut-illegal.l b/gas/testsuite/gas/aarch64/advsimd-lut-illegal.l
index 86f6a7d2fdb..53a2915bfd5 100644
--- a/gas/testsuite/gas/aarch64/advsimd-lut-illegal.l
+++ b/gas/testsuite/gas/aarch64/advsimd-lut-illegal.l
@@ -1,208 +1,208 @@
 [^ :]+: Assembler messages:
-[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 v2.16b,\{v4.8h\},v8\[1\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 v2.16b,\{ ?v4.8h ?\},v8\[1\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	luti2 v2.16b, \{v4.16b\}, v8\[1\]
-[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 v2.8h,\{v4.16b\},v8\[1\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 v2.8h,\{ ?v4.16b ?\},v8\[1\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	luti2 v2.16b, \{v4.16b\}, v8\[1\]
-[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 v2.16b,\{v4.8h\},v8\[5\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 v2.16b,\{ ?v4.8h ?\},v8\[5\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	luti4 v2.16b, \{v4.16b\}, v8\[5\]
-[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 v2.8h,\{v4.16b\},v8\[5\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 v2.8h,\{ ?v4.16b ?\},v8\[5\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	luti4 v2.16b, \{v4.16b\}, v8\[5\]
 [^ :]+:[0-9]+: Error: missing braces at operand 2 -- `luti2 v2.16b,v4.16b,v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `luti2 x12,\{v4.16b\},v8\[1\]'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `luti2 x12,\{ ?v4.16b ?\},v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 2 -- `luti2 v2.16b,\{x12\},v8\[1\]'
+[^ :]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 2 -- `luti2 v2.16b,\{ ?x12 ?\},v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti2 v2.16b,\{v4.16b\},x12\[1\]'
+[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti2 v2.16b,\{ ?v4.16b ?\},x12\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
 [^ :]+:[0-9]+: Error: missing braces at operand 2 -- `luti2 v2.8h,v4.8h,v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `luti2 x12,\{v4.8h\},v8\[1\]'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `luti2 x12,\{ ?v4.8h ?\},v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 2 -- `luti2 v2.8h,\{x12\},v8\[1\]'
+[^ :]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 2 -- `luti2 v2.8h,\{ ?x12 ?\},v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti2 v2.8h,\{v4.8h\},x12\[1\]'
+[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti2 v2.8h,\{ ?v4.8h ?\},x12\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
 [^ :]+:[0-9]+: Error: missing braces at operand 2 -- `luti4 v2.16b,v4.16b,v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `luti4 x12,\{v4.16b\},v8\[1\]'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `luti4 x12,\{ ?v4.16b ?\},v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 2 -- `luti4 v2.16b,\{x12\},v8\[1\]'
+[^ :]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 2 -- `luti4 v2.16b,\{ ?x12 ?\},v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti4 v2.16b,\{v4.16b\},x12\[1\]'
+[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti4 v2.16b,\{ ?v4.16b ?\},x12\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
 [^ :]+:[0-9]+: Error: missing braces at operand 2 -- `luti4 v2.8h,v4.8h,v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `luti4 x12,\{v4.8h\},v8\[1\]'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `luti4 x12,\{ ?v4.8h ?\},v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 2 -- `luti4 v2.8h,\{x12\},v8\[1\]'
+[^ :]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 2 -- `luti4 v2.8h,\{ ?x12 ?\},v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti4 v2.8h,\{v4.8h\},x12\[1\]'
+[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti4 v2.8h,\{ ?v4.8h ?\},x12\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: operand 2 must be a SIMD vector register list -- `luti4 v2.8h,\{v4.8h,x12\},v8\[1\]'
-[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 v2.8b,\{v4.8b\},v8\[1\]'
+[^ :]+:[0-9]+: Error: operand 2 must be a SIMD vector register list -- `luti4 v2.8h,\{ ?v4.8h,x12 ?\},v8\[1\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 v2.8b,\{ ?v4.8b ?\},v8\[1\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	luti2 v2.16b, \{v4.16b\}, v8\[1\]
-[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 v2.4h,\{v4.4h\},v8\[1\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 v2.4h,\{ ?v4.4h ?\},v8\[1\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	luti2 v2.16b, \{v4.16b\}, v8\[1\]
-[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 v2.8b,\{v4.8b\},v8\[5\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 v2.8b,\{ ?v4.8b ?\},v8\[5\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	luti4 v2.16b, \{v4.16b\}, v8\[5\]
-[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 v2.4h,\{v4.4h,v5.4h\},v8\[5\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 v2.4h,\{ ?v4.4h,v5.4h ?\},v8\[5\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	luti4 v2.16b, \{v4.16b-v5.16b\}, v8\[5\]
 [^ :]+:[0-9]+: Error: comma expected between operands at operand 2 -- `luti2 v2.16b'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: expected element type rather than vector type at operand 2 -- `luti2 v2.16b,\{v4.16b\}'
+[^ :]+:[0-9]+: Error: expected element type rather than vector type at operand 2 -- `luti2 v2.16b,\{ ?v4.16b ?\}'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 3 -- `luti2 v2.16b,\{v4.16b\},v8\[1\],v16.16b'
+[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 3 -- `luti2 v2.16b,\{ ?v4.16b ?\},v8\[1\],v16.16b'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 3 -- `luti2 v2.16b,\{v4.16b\},v8\[1\],\{v16.16b\}'
+[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 3 -- `luti2 v2.16b,\{ ?v4.16b ?\},v8\[1\],\{ ?v16.16b ?\}'
 [^ :]+:[0-9]+:  Info: macro invoked from here
 [^ :]+:[0-9]+: Error: comma expected between operands at operand 2 -- `luti2 v2.8h'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: expected element type rather than vector type at operand 2 -- `luti2 v2.8h,\{v4.8h\}'
+[^ :]+:[0-9]+: Error: expected element type rather than vector type at operand 2 -- `luti2 v2.8h,\{ ?v4.8h ?\}'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 3 -- `luti2 v2.8h,\{v4.8h\},v8\[1\],v16.8h'
+[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 3 -- `luti2 v2.8h,\{ ?v4.8h ?\},v8\[1\],v16.8h'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 3 -- `luti2 v2.8h,\{v4.8h\},v8\[1\],\{v16.8h\}'
+[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 3 -- `luti2 v2.8h,\{ ?v4.8h ?\},v8\[1\],\{ ?v16.8h ?\}'
 [^ :]+:[0-9]+:  Info: macro invoked from here
 [^ :]+:[0-9]+: Error: comma expected between operands at operand 2 -- `luti4 v2.16b'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: expected element type rather than vector type at operand 2 -- `luti4 v2.16b,\{v4.16b\}'
+[^ :]+:[0-9]+: Error: expected element type rather than vector type at operand 2 -- `luti4 v2.16b,\{ ?v4.16b ?\}'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 3 -- `luti4 v2.16b,\{v4.16b\},v8\[1\],v16.16b'
+[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 3 -- `luti4 v2.16b,\{ ?v4.16b ?\},v8\[1\],v16.16b'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 3 -- `luti4 v2.16b,\{v4.16b\},v8\[1\],\{v16.16b\}'
+[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 3 -- `luti4 v2.16b,\{ ?v4.16b ?\},v8\[1\],\{ ?v16.16b ?\}'
 [^ :]+:[0-9]+:  Info: macro invoked from here
 [^ :]+:[0-9]+: Error: comma expected between operands at operand 2 -- `luti4 v2.8h'
-[^ :]+:[0-9]+: Error: expected element type rather than vector type at operand 2 -- `luti4 v2.8h,\{v4.8h,v5.8h\}'
-[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 3 -- `luti4 v2.8h,\{v4.8h,v5.8h\},v8\[1\],v16.8h'
-[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 3 -- `luti4 v2.8h,\{v4.8h,v5.8h\},v8\[1\],\{v16.8h\}'
-[^ :]+:[0-9]+: Error: unexpected character `t' in element size at operand 2 -- `luti2 v2.16b,\{v4.16t\},v8\[1\]'
+[^ :]+:[0-9]+: Error: expected element type rather than vector type at operand 2 -- `luti4 v2.8h,\{ ?v4.8h,v5.8h ?\}'
+[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 3 -- `luti4 v2.8h,\{ ?v4.8h,v5.8h ?\},v8\[1\],v16.8h'
+[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 3 -- `luti4 v2.8h,\{ ?v4.8h,v5.8h ?\},v8\[1\],\{ ?v16.8h ?\}'
+[^ :]+:[0-9]+: Error: unexpected character `t' in element size at operand 2 -- `luti2 v2.16b,\{ ?v4.16t ?\},v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: unexpected character `t' in element size at operand 1 -- `luti2 v2.16t,\{v4.16b\},v8\[1\]'
+[^ :]+:[0-9]+: Error: unexpected character `t' in element size at operand 1 -- `luti2 v2.16t,\{ ?v4.16b ?\},v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: unexpected character `m' in element size at operand 2 -- `luti2 v2.8h,\{v4.8m\},v8\[1\]'
+[^ :]+:[0-9]+: Error: unexpected character `m' in element size at operand 2 -- `luti2 v2.8h,\{ ?v4.8m ?\},v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: unexpected character `m' in element size at operand 1 -- `luti2 v2.8m,\{v4.8h\},v8\[1\]'
+[^ :]+:[0-9]+: Error: unexpected character `m' in element size at operand 1 -- `luti2 v2.8m,\{ ?v4.8h ?\},v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: unexpected character `t' in element size at operand 2 -- `luti4 v2.16b,\{v4.16t\},v8\[1\]'
+[^ :]+:[0-9]+: Error: unexpected character `t' in element size at operand 2 -- `luti4 v2.16b,\{ ?v4.16t ?\},v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: unexpected character `t' in element size at operand 1 -- `luti4 v2.16t,\{v4.16b\},v8\[1\]'
+[^ :]+:[0-9]+: Error: unexpected character `t' in element size at operand 1 -- `luti4 v2.16t,\{ ?v4.16b ?\},v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: unexpected character `t' in element size at operand 2 -- `luti4 v2.8h,\{v4.8h,v5.8t\},v8\[1\]'
-[^ :]+:[0-9]+: Error: unexpected character `t' in element size at operand 1 -- `luti4 v2.8t,\{v4.8h,v5.8h\},v8\[1\]'
-[^ :]+:[0-9]+: Error: invalid use of vector register at operand 2 -- `luti2 v2.16b,\{v4\},v8\[1\]'
+[^ :]+:[0-9]+: Error: unexpected character `t' in element size at operand 2 -- `luti4 v2.8h,\{ ?v4.8h,v5.8t ?\},v8\[1\]'
+[^ :]+:[0-9]+: Error: unexpected character `t' in element size at operand 1 -- `luti4 v2.8t,\{ ?v4.8h,v5.8h ?\},v8\[1\]'
+[^ :]+:[0-9]+: Error: invalid use of vector register at operand 2 -- `luti2 v2.16b,\{ ?v4 ?\},v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: invalid use of vector register at operand 1 -- `luti2 v2,\{v4.16b\},v8\[1\]'
+[^ :]+:[0-9]+: Error: invalid use of vector register at operand 1 -- `luti2 v2,\{ ?v4.16b ?\},v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti2 2.16b,\{v4.16b\},v8\[1\]'
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti2 2.16b,\{ ?v4.16b ?\},v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: syntax error in register list at operand 2 -- `luti2 v2.16b,\{4.16b\},v8\[1\]'
+[^ :]+:[0-9]+: Error: syntax error in register list at operand 2 -- `luti2 v2.16b,\{ ?4.16b ?\},v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: invalid use of vector register at operand 2 -- `luti2 v2.8h,\{v4\},v8\[1\]'
+[^ :]+:[0-9]+: Error: invalid use of vector register at operand 2 -- `luti2 v2.8h,\{ ?v4 ?\},v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: invalid use of vector register at operand 1 -- `luti2 v2,\{v4.8h\},v8\[1\]'
+[^ :]+:[0-9]+: Error: invalid use of vector register at operand 1 -- `luti2 v2,\{ ?v4.8h ?\},v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti2 2.8h,\{v4.8h\},v8\[1\]'
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti2 2.8h,\{ ?v4.8h ?\},v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: syntax error in register list at operand 2 -- `luti2 v2.8h,\{4.8h\},v8\[1\]'
+[^ :]+:[0-9]+: Error: syntax error in register list at operand 2 -- `luti2 v2.8h,\{ ?4.8h ?\},v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: invalid use of vector register at operand 2 -- `luti4 v2.16b,\{v4\},v8\[1\]'
+[^ :]+:[0-9]+: Error: invalid use of vector register at operand 2 -- `luti4 v2.16b,\{ ?v4 ?\},v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: invalid use of vector register at operand 1 -- `luti4 v2,\{v4.16b\},v8\[1\]'
+[^ :]+:[0-9]+: Error: invalid use of vector register at operand 1 -- `luti4 v2,\{ ?v4.16b ?\},v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti4 2.16b,\{v4.16b\},v8\[1\]'
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti4 2.16b,\{ ?v4.16b ?\},v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: syntax error in register list at operand 2 -- `luti4 v2.16b,\{4.16b\},v8\[1\]'
+[^ :]+:[0-9]+: Error: syntax error in register list at operand 2 -- `luti4 v2.16b,\{ ?4.16b ?\},v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: invalid use of vector register at operand 2 -- `luti4 v2.16b,\{v4,v5.16b\},v8\[1\]'
-[^ :]+:[0-9]+: Error: invalid use of vector register at operand 1 -- `luti4 v2,\{v4.16b,v5.16b\},v8\[1\]'
-[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti4 2.16b,\{v4.16b,v5.16b\},v8\[1\]'
-[^ :]+:[0-9]+: Error: syntax error in register list at operand 2 -- `luti4 v2.16b,\{v4.16b,5.16b\},v8\[1\]'
-[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti2 v17.16b,\{v21.16b\},v27.16b\[3\]'
-[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti2 v17.8h,\{v21.8h\},v27.8h\[4\]'
-[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti4 v17.16b,\{v21.16b\},v27.16b\[1\]'
-[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti4 v17.8h,\{v21.8h,v22.8h\},v27.8h\[2\]'
-[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `luti2 v17.16b\[1\],\{v0.16b\},v31.16b'
+[^ :]+:[0-9]+: Error: invalid use of vector register at operand 2 -- `luti4 v2.16b,\{ ?v4,v5.16b ?\},v8\[1\]'
+[^ :]+:[0-9]+: Error: invalid use of vector register at operand 1 -- `luti4 v2,\{ ?v4.16b,v5.16b ?\},v8\[1\]'
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti4 2.16b,\{ ?v4.16b,v5.16b ?\},v8\[1\]'
+[^ :]+:[0-9]+: Error: syntax error in register list at operand 2 -- `luti4 v2.16b,\{ ?v4.16b,5.16b ?\},v8\[1\]'
+[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti2 v17.16b,\{ ?v21.16b ?\},v27.16b\[3\]'
+[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti2 v17.8h,\{ ?v21.8h ?\},v27.8h\[4\]'
+[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti4 v17.16b,\{ ?v21.16b ?\},v27.16b\[1\]'
+[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti4 v17.8h,\{ ?v21.8h,v22.8h ?\},v27.8h\[2\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `luti2 v17.16b\[1\],\{ ?v0.16b ?\},v31.16b'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: this type of register can't be indexed at operand 1 -- `luti2 v17\[1\],\{v0.16b\},v31.16b'
+[^ :]+:[0-9]+: Error: this type of register can't be indexed at operand 1 -- `luti2 v17\[1\],\{ ?v0.16b ?\},v31.16b'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: index not allowed inside register list at operand 2 -- `luti2 v17.16b,\{v0.16b\[1\]\},v31.16b'
+[^ :]+:[0-9]+: Error: index not allowed inside register list at operand 2 -- `luti2 v17.16b,\{ ?v0.16b\[1\] ?\},v31.16b'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: this type of register can't be indexed at operand 2 -- `luti2 v17.16b,\{v0\[1\]\},v31.16b'
+[^ :]+:[0-9]+: Error: this type of register can't be indexed at operand 2 -- `luti2 v17.16b,\{ ?v0\[1\] ?\},v31.16b'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `luti2 v17.8h\[1\],\{v0.8h\},v31.8h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `luti2 v17.8h\[1\],\{ ?v0.8h ?\},v31.8h'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: this type of register can't be indexed at operand 1 -- `luti2 v17\[1\],\{v0.8h\},v31.8h'
+[^ :]+:[0-9]+: Error: this type of register can't be indexed at operand 1 -- `luti2 v17\[1\],\{ ?v0.8h ?\},v31.8h'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: index not allowed inside register list at operand 2 -- `luti2 v17.8h,\{v0.8h\[1\]\},v31.8h'
+[^ :]+:[0-9]+: Error: index not allowed inside register list at operand 2 -- `luti2 v17.8h,\{ ?v0.8h\[1\] ?\},v31.8h'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: this type of register can't be indexed at operand 2 -- `luti2 v17.8h,\{v0\[1\]\},v31.8h'
+[^ :]+:[0-9]+: Error: this type of register can't be indexed at operand 2 -- `luti2 v17.8h,\{ ?v0\[1\] ?\},v31.8h'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `luti4 v17.16b\[1\],\{v0.16b\},v31.16b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `luti4 v17.16b\[1\],\{ ?v0.16b ?\},v31.16b'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: this type of register can't be indexed at operand 1 -- `luti4 v17\[1\],\{v0.16b\},v31.16b'
+[^ :]+:[0-9]+: Error: this type of register can't be indexed at operand 1 -- `luti4 v17\[1\],\{ ?v0.16b ?\},v31.16b'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: index not allowed inside register list at operand 2 -- `luti4 v17.16b,\{v0.16b\[1\]\},v31.16b'
+[^ :]+:[0-9]+: Error: index not allowed inside register list at operand 2 -- `luti4 v17.16b,\{ ?v0.16b\[1\] ?\},v31.16b'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: this type of register can't be indexed at operand 2 -- `luti4 v17.16b,\{v0\[1\]\},v31.16b'
+[^ :]+:[0-9]+: Error: this type of register can't be indexed at operand 2 -- `luti4 v17.16b,\{ ?v0\[1\] ?\},v31.16b'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `luti4 v17.8h\[1\],\{v0.8h,v1.8h\},v31.8h'
-[^ :]+:[0-9]+: Error: this type of register can't be indexed at operand 1 -- `luti4 v17\[1\],\{v0.8h,v1.8h\},v31.8h'
-[^ :]+:[0-9]+: Error: index not allowed inside register list at operand 2 -- `luti4 v17.8h,\{v0.8h\[1\],v1.8h\},v31.8h'
-[^ :]+:[0-9]+: Error: this type of register can't be indexed at operand 2 -- `luti4 v17.8h,\{v0\[1\],v1.8h\},v31.8h'
-[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti2 v2.16b,\{v4.16b\},v8.16b'
-[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti2 v2.16b,\{v4.16b\},v8'
-[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti2 v2.8h,\{v4.8h\},v8.8h'
-[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti2 v2.8h,\{v4.8h\},v8'
-[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti4 v2.16b,\{v4.16b\},v8.16b'
-[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti4 v2.16b,\{v4.16b\},v8'
-[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti4 v2.8h,\{v4.8h,v5.8h\},v8.8h'
-[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti4 v2.8h,\{v4.8h,v5.8h\},v8'
-[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti2 v32.16b,\{v4.16b\},v8\[1\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `luti4 v17.8h\[1\],\{ ?v0.8h,v1.8h ?\},v31.8h'
+[^ :]+:[0-9]+: Error: this type of register can't be indexed at operand 1 -- `luti4 v17\[1\],\{ ?v0.8h,v1.8h ?\},v31.8h'
+[^ :]+:[0-9]+: Error: index not allowed inside register list at operand 2 -- `luti4 v17.8h,\{ ?v0.8h\[1\],v1.8h ?\},v31.8h'
+[^ :]+:[0-9]+: Error: this type of register can't be indexed at operand 2 -- `luti4 v17.8h,\{ ?v0\[1\],v1.8h ?\},v31.8h'
+[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti2 v2.16b,\{ ?v4.16b ?\},v8.16b'
+[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti2 v2.16b,\{ ?v4.16b ?\},v8'
+[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti2 v2.8h,\{ ?v4.8h ?\},v8.8h'
+[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti2 v2.8h,\{ ?v4.8h ?\},v8'
+[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti4 v2.16b,\{ ?v4.16b ?\},v8.16b'
+[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti4 v2.16b,\{ ?v4.16b ?\},v8'
+[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti4 v2.8h,\{ ?v4.8h,v5.8h ?\},v8.8h'
+[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti4 v2.8h,\{ ?v4.8h,v5.8h ?\},v8'
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti2 v32.16b,\{ ?v4.16b ?\},v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 2 -- `luti2 v2.16b,\{v32.16b\},v8\[1\]'
+[^ :]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 2 -- `luti2 v2.16b,\{ ?v32.16b ?\},v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti2 v2.16b,\{v4.16b\},v32\[1\]'
+[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti2 v2.16b,\{ ?v4.16b ?\},v32\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `luti2 v2.16b,\{v4.16b\},v8\[4\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `luti2 v2.16b,\{ ?v4.16b ?\},v8\[4\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `luti2 v2.16b,\{v4.16b\},v8\[-1\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `luti2 v2.16b,\{ ?v4.16b ?\},v8\[-1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti2 v32.8h,\{v4.8h\},v8\[1\]'
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti2 v32.8h,\{ ?v4.8h ?\},v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 2 -- `luti2 v2.8h,\{v32.8h\},v8\[1\]'
+[^ :]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 2 -- `luti2 v2.8h,\{ ?v32.8h ?\},v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti2 v2.8h,\{v4.8h\},v32\[1\]'
+[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti2 v2.8h,\{ ?v4.8h ?\},v32\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `luti2 v2.8h,\{v4.8h\},v8\[8\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `luti2 v2.8h,\{ ?v4.8h ?\},v8\[8\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `luti2 v2.8h,\{v4.8h\},v8\[-1\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `luti2 v2.8h,\{ ?v4.8h ?\},v8\[-1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti4 v32.16b,\{v4.16b\},v8\[1\]'
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti4 v32.16b,\{ ?v4.16b ?\},v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 2 -- `luti4 v2.16b,\{v32.16b\},v8\[1\]'
+[^ :]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 2 -- `luti4 v2.16b,\{ ?v32.16b ?\},v8\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti4 v2.16b,\{v4.16b\},v32\[1\]'
+[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti4 v2.16b,\{ ?v4.16b ?\},v32\[1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `luti4 v2.16b,\{v4.16b\},v8\[2\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `luti4 v2.16b,\{ ?v4.16b ?\},v8\[2\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `luti4 v2.16b,\{v4.16b\},v8\[-1\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `luti4 v2.16b,\{ ?v4.16b ?\},v8\[-1\]'
 [^ :]+:[0-9]+:  Info: macro invoked from here
-[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti4 v32.8h,\{v4.8h,v5.8h\},v8\[1\]'
-[^ :]+:[0-9]+: Error: operand 2 must be a SIMD vector register list -- `luti4 v2.8h,\{v31.8h,v32.8h\},v8\[1\]'
-[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti4 v2.8h,\{v4.8h,v5.8h\},v32\[1\]'
-[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `luti4 v2.8h,\{v4.8h,v5.8h\},v8\[4\]'
-[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `luti4 v2.8h,\{v4.8h,v5.8h\},v8\[-1\]'
-[^ :]+:[0-9]+: Error: the register list must have a stride of 1 at operand 2 -- `luti4 v2.8h,\{v4.8h,v6.8h\},v8\[2\]'
-[^ :]+:[0-9]+: Error: expected a single-register list at operand 2 -- `luti2 v17.16b,\{v21.16b,v22.16b\},v27\[2\]'
-[^ :]+:[0-9]+: Error: expected a single-register list at operand 2 -- `luti2 v17.8h,\{v21.8h,v22.8h\},v27\[4\]'
-[^ :]+:[0-9]+: Error: expected a single-register list at operand 2 -- `luti4 v17.16b,\{v21.16b,v22.16b\},v27\[1\]'
-[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `luti4 v17.8h,\{v21.8h\},v27\[2\]'
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti4 v32.8h,\{ ?v4.8h,v5.8h ?\},v8\[1\]'
+[^ :]+:[0-9]+: Error: operand 2 must be a SIMD vector register list -- `luti4 v2.8h,\{ ?v31.8h,v32.8h ?\},v8\[1\]'
+[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector without a type qualifier encoding a bit index -- `luti4 v2.8h,\{ ?v4.8h,v5.8h ?\},v32\[1\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `luti4 v2.8h,\{ ?v4.8h,v5.8h ?\},v8\[4\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `luti4 v2.8h,\{ ?v4.8h,v5.8h ?\},v8\[-1\]'
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 at operand 2 -- `luti4 v2.8h,\{ ?v4.8h,v6.8h ?\},v8\[2\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 2 -- `luti2 v17.16b,\{ ?v21.16b,v22.16b ?\},v27\[2\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 2 -- `luti2 v17.8h,\{ ?v21.8h,v22.8h ?\},v27\[4\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 2 -- `luti4 v17.16b,\{ ?v21.16b,v22.16b ?\},v27\[1\]'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `luti4 v17.8h,\{ ?v21.8h ?\},v27\[2\]'
diff --git a/gas/testsuite/gas/aarch64/bfloat16-2-invalid.l b/gas/testsuite/gas/aarch64/bfloat16-2-invalid.l
index 5da96c72ae5..ae949cf7f76 100644
--- a/gas/testsuite/gas/aarch64/bfloat16-2-invalid.l
+++ b/gas/testsuite/gas/aarch64/bfloat16-2-invalid.l
@@ -166,7 +166,7 @@
 .*: Info:    did you mean this\?
 .*: Info:    	bfadd z31.h, z31.h, z31.h
 .*: Error: expected an SVE vector register at operand 1 -- `bfadd {z0.h},z0.h,z0.h'
-.*: Error: expected an SVE vector register at operand 1 -- `bfadd {z0.h-z0.h},z0.h'
+.*: Error: expected an SVE vector register at operand 1 -- `bfadd {z0.h ?- ?z0.h},z0.h'
 .*: Error: comma expected between operands at operand 3 -- `bfadd z0.h,z0.h'
 .*: Error: operand mismatch -- `bfclamp z0.b,z0.h,z0.h'
 .*: Info:    did you mean this\?
@@ -184,7 +184,7 @@
 .*: Info:    did you mean this\?
 .*: Info:    	bfclamp z31.h, z31.h, z31.h
 .*: Error: expected an SVE vector register at operand 1 -- `bfclamp {z0.h},z0.h,z0.h'
-.*: Error: expected an SVE vector register at operand 1 -- `bfclamp {z0.h-z0.h},z0.h'
+.*: Error: expected an SVE vector register at operand 1 -- `bfclamp {z0.h ?- ?z0.h},z0.h'
 .*: Error: comma expected between operands at operand 3 -- `bfclamp z0.h,z0.h'
 .*: Error: operand mismatch -- `bfmla z0.b,z0.h,z0.h\[0\]'
 .*: Info:    did you mean this\?
@@ -202,7 +202,7 @@
 .*: Info:    did you mean this\?
 .*: Info:    	bfmla z31.h, z31.h, z31.h\[8\]
 .*: Error: expected an SVE vector register at operand 1 -- `bfmla {z0.h},z0.h,z0.h\[1\]'
-.*: Error: expected an SVE vector register at operand 1 -- `bfmla {z0.h-z0.h},z0.h\[2\]'
+.*: Error: expected an SVE vector register at operand 1 -- `bfmla {z0.h ?- ?z0.h},z0.h\[2\]'
 .*: Error: expected an SVE predicate register at operand 2 -- `bfmla z0.h,z0.h\[3\]'
 .*: Error: operand mismatch -- `bfmls z0.b,z0.h,z0.h\[0\]'
 .*: Info:    did you mean this\?
@@ -220,7 +220,7 @@
 .*: Info:    did you mean this\?
 .*: Info:    	bfmls z31.h, z31.h, z31.h\[8\]
 .*: Error: expected an SVE vector register at operand 1 -- `bfmls {z0.h},z0.h,z0.h\[1\]'
-.*: Error: expected an SVE vector register at operand 1 -- `bfmls {z0.h-z0.h},z0.h\[2\]'
+.*: Error: expected an SVE vector register at operand 1 -- `bfmls {z0.h ?- ?z0.h},z0.h\[2\]'
 .*: Error: expected an SVE predicate register at operand 2 -- `bfmls z0.h,z0.h\[3\]'
 .*: Error: operand mismatch -- `bfmul z0.b,z0.h,z0.h\[0\]'
 .*: Info:    did you mean this\?
@@ -238,7 +238,7 @@
 .*: Info:    did you mean this\?
 .*: Info:    	bfmul z31.h, z31.h, z31.h\[8\]
 .*: Error: expected an SVE vector register at operand 1 -- `bfmul {z0.h},z0.h,z0.h\[1\]'
-.*: Error: expected an SVE vector register at operand 1 -- `bfmul {z0.h-z0.h},z0.h\[2\]'
+.*: Error: expected an SVE vector register at operand 1 -- `bfmul {z0.h ?- ?z0.h},z0.h\[2\]'
 .*: Error: expected an SVE predicate register at operand 2 -- `bfmul z0.h,z0.h\[3\]'
 .*: Error: operand mismatch -- `bfsub z0.b,z0.h,z0.h'
 .*: Info:    did you mean this\?
@@ -256,7 +256,7 @@
 .*: Info:    did you mean this\?
 .*: Info:    	bfsub z31.h, z31.h, z31.h
 .*: Error: expected an SVE vector register at operand 1 -- `bfsub {z0.h},z0.h,z0.h'
-.*: Error: expected an SVE vector register at operand 1 -- `bfsub {z0.h-z0.h},z0.h'
+.*: Error: expected an SVE vector register at operand 1 -- `bfsub {z0.h ?- ?z0.h},z0.h'
 .*: Error: comma expected between operands at operand 3 -- `bfsub z0.h,z0.h'
 .*: Warning: output register of preceding `movprfx' expected as output at operand 1 -- `bfclamp z1.h,z3.h,z16.h'
 .*: Warning: output register of preceding `movprfx' not used in current instruction at operand 1 -- `bfmla z10.h,z16.h,z3.h\[7\]'
diff --git a/gas/testsuite/gas/aarch64/cpa-addsub-bad.l b/gas/testsuite/gas/aarch64/cpa-addsub-bad.l
index c0c671bbfdf..bbce0a7350e 100644
--- a/gas/testsuite/gas/aarch64/cpa-addsub-bad.l
+++ b/gas/testsuite/gas/aarch64/cpa-addsub-bad.l
@@ -2,18 +2,18 @@
 .*: Error: operand mismatch -- `addpt w5,w8,w0'
 .*: Info:\s+did you mean this\?
 .*: Info:\s+addpt x5, x8, x0
-.*: Error: only 'LSL' shift is permitted at operand 3 -- `addpt x5,x8,x0,asr#6'
-.*: Error: shift amount out of range 0 to 7 at operand 3 -- `addpt x5,x8,x0,lsl#9'
-.*: Error: expected an integer or zero register at operand 3 -- `addpt x5,x8,sp,lsl#5'
-.*: Error: unexpected register type at operand 1 -- `addpt xzr,x8,x0,lsl#3'
+.*: Error: only 'LSL' shift is permitted at operand 3 -- `addpt x5,x8,x0,asr ?#6'
+.*: Error: shift amount out of range 0 to 7 at operand 3 -- `addpt x5,x8,x0,lsl ?#9'
+.*: Error: expected an integer or zero register at operand 3 -- `addpt x5,x8,sp,lsl ?#5'
+.*: Error: unexpected register type at operand 1 -- `addpt xzr,x8,x0,lsl ?#3'
 
 .*: Error: operand mismatch -- `subpt w5,w8,w0'
 .*: Info:\s+did you mean this\?
 .*: Info:\s+subpt x5, x8, x0
-.*: Error: only 'LSL' shift is permitted at operand 3 -- `subpt x5,x8,x0,asr#6'
-.*: Error: shift amount out of range 0 to 7 at operand 3 -- `subpt x5,x8,x0,lsl#9'
-.*: Error: expected an integer or zero register at operand 3 -- `subpt x5,x8,sp,lsl#5'
-.*: Error: unexpected register type at operand 1 -- `subpt xzr,x8,x0,lsl#3'
+.*: Error: only 'LSL' shift is permitted at operand 3 -- `subpt x5,x8,x0,asr ?#6'
+.*: Error: shift amount out of range 0 to 7 at operand 3 -- `subpt x5,x8,x0,lsl ?#9'
+.*: Error: expected an integer or zero register at operand 3 -- `subpt x5,x8,sp,lsl ?#5'
+.*: Error: unexpected register type at operand 1 -- `subpt xzr,x8,x0,lsl ?#3'
 
 .*: Error: operand mismatch -- `maddpt w1,x2,x3,x4'
 .*: Info:\s+did you mean this\?
diff --git a/gas/testsuite/gas/aarch64/cpa-addsub-neg.l b/gas/testsuite/gas/aarch64/cpa-addsub-neg.l
index 44a7236f38f..79ce81dbc16 100644
--- a/gas/testsuite/gas/aarch64/cpa-addsub-neg.l
+++ b/gas/testsuite/gas/aarch64/cpa-addsub-neg.l
@@ -3,16 +3,16 @@
 .*: Error: selected processor does not support `addpt sp,x0,x0'
 .*: Error: selected processor does not support `addpt x0,sp,x0'
 .*: Error: selected processor does not support `addpt x0,x0,xzr'
-.*: Error: selected processor does not support `addpt x0,x0,x0,lsl#0'
-.*: Error: selected processor does not support `addpt x0,x0,x0,lsl#7'
-.*: Error: selected processor does not support `addpt x8,x13,x29,lsl#5'
+.*: Error: selected processor does not support `addpt x0,x0,x0,lsl ?#0'
+.*: Error: selected processor does not support `addpt x0,x0,x0,lsl ?#7'
+.*: Error: selected processor does not support `addpt x8,x13,x29,lsl ?#5'
 .*: Error: selected processor does not support `subpt x0,x0,x0'
 .*: Error: selected processor does not support `subpt sp,x0,x0'
 .*: Error: selected processor does not support `subpt x0,sp,x0'
 .*: Error: selected processor does not support `subpt x0,x0,xzr'
-.*: Error: selected processor does not support `subpt x0,x0,x0,lsl#0'
-.*: Error: selected processor does not support `subpt x0,x0,x0,lsl#7'
-.*: Error: selected processor does not support `subpt x1,x10,x22,lsl#2'
+.*: Error: selected processor does not support `subpt x0,x0,x0,lsl ?#0'
+.*: Error: selected processor does not support `subpt x0,x0,x0,lsl ?#7'
+.*: Error: selected processor does not support `subpt x1,x10,x22,lsl ?#2'
 .*: Error: selected processor does not support `maddpt x0,x0,x0,x0'
 .*: Error: selected processor does not support `maddpt xzr,x0,x0,x0'
 .*: Error: selected processor does not support `maddpt x0,xzr,x0,x0'
diff --git a/gas/testsuite/gas/aarch64/diagnostic.l b/gas/testsuite/gas/aarch64/diagnostic.l
index 85ec9fe6900..1c83662774e 100644
--- a/gas/testsuite/gas/aarch64/diagnostic.l
+++ b/gas/testsuite/gas/aarch64/diagnostic.l
@@ -21,17 +21,17 @@
 [^:]*:23: Error: immediate value out of range 1 to 32 at operand 3 -- `scvtf s0,w0,0'
 [^:]*:24: Error: register number out of range 0 to 15 at operand 3 -- `smlal v0.4s,v31.4h,v16.h\[1\]'
 [^:]*:25: Error: register element index out of range 0 to 7 at operand 3 -- `smlal v0.4s,v31.4h,v15.h\[8\]'
-[^:]*:26: Error: extend operator expected at operand 3 -- `add sp,x0,x7,lsr#2'
-[^:]*:27: Error: shift amount out of range 0 to 4 at operand 3 -- `add x0,x0,x7,uxtx#5'
-[^:]*:28: Error: 'ROR' operator not allowed at operand 3 -- `add x0,xzr,x7,ror#5'
-[^:]*:29: Error: shift amount out of range 0 to 31 at operand 3 -- `add w0,wzr,w7,asr#32'
+[^:]*:26: Error: extend operator expected at operand 3 -- `add sp,x0,x7,lsr ?#2'
+[^:]*:27: Error: shift amount out of range 0 to 4 at operand 3 -- `add x0,x0,x7,uxtx ?#5'
+[^:]*:28: Error: 'ROR' operator not allowed at operand 3 -- `add x0,xzr,x7,ror ?#5'
+[^:]*:29: Error: shift amount out of range 0 to 31 at operand 3 -- `add w0,wzr,w7,asr ?#32'
 [^:]*:30: Error: invalid post-increment amount at operand 2 -- `st2 \{v0.4s,v1.4s\},\[sp\],#24'
-[^:]*:31: Error: invalid shift amount at operand 2 -- `ldr q0,\[x0,w0,uxtw#5\]'
+[^:]*:31: Error: invalid shift amount at operand 2 -- `ldr q0,\[x0,w0,uxtw ?#5\]'
 [^:]*:32: Error: expected a list of 2 registers at operand 1 -- `st2 \{v0.4s,v1.4s,v2.4s,v3.4s\},\[sp\],#64'
-[^:]*:33: Error: shift amount must be 0 or 12 at operand 3 -- `adds x1,sp,2134,lsl#4'
-[^:]*:34: Error: shift amount must be a multiple of 16 at operand 2 -- `movz w0,2134,lsl#8'
-[^:]*:35: Error: shift amount out of range 0 to 16 at operand 2 -- `movz w0,2134,lsl#32'
-[^:]*:36: Error: shift amount must be a multiple of 16 at operand 2 -- `movz x0,2134,lsl#47'
+[^:]*:33: Error: shift amount must be 0 or 12 at operand 3 -- `adds x1,sp,2134,lsl ?#4'
+[^:]*:34: Error: shift amount must be a multiple of 16 at operand 2 -- `movz w0,2134,lsl ?#8'
+[^:]*:35: Error: shift amount out of range 0 to 16 at operand 2 -- `movz w0,2134,lsl ?#32'
+[^:]*:36: Error: shift amount must be a multiple of 16 at operand 2 -- `movz x0,2134,lsl ?#47'
 [^:]*:37: Error: immediate value out of range 1 to 17 at operand 4 -- `sbfiz w0,w7,15,18'
 [^:]*:38: Error: immediate value out of range 1 to 32 at operand 4 -- `sbfiz w0,w7,15,0'
 [^:]*:39: Error: invalid shift amount at operand 3 -- `shll v1.4s,v2.4h,#15'
@@ -40,12 +40,12 @@
 [^:]*:42: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrn2 v2.16b,v3.8h,#17'
 [^:]*:43: Error: immediate value out of range -128 to 255 at operand 2 -- `movi v1.4h,256'
 [^:]*:44: Error: immediate value out of range -128 to 255 at operand 2 -- `movi v1.4h,-129'
-[^:]*:45: Error: invalid shift operator at operand 2 -- `movi v1.4h,255,msl#8'
+[^:]*:45: Error: invalid shift operator at operand 2 -- `movi v1.4h,255,msl ?#8'
 [^:]*:46: Error: invalid value for immediate at operand 2 -- `movi d0,256'
-[^:]*:47: Error: immediate value must be a multiple of 8 at operand 2 -- `movi v1.4h,255,lsl#7'
-[^:]*:48: Error: shift amount out of range 0 to 8 at operand 2 -- `movi v1.4h,255,lsl#16'
-[^:]*:49: Error: shift amount must be 0 or 16 at operand 2 -- `movi v2.2s,255,msl#0'
-[^:]*:50: Error: shift amount must be 0 or 16 at operand 2 -- `movi v2.2s,255,msl#15'
+[^:]*:47: Error: immediate value must be a multiple of 8 at operand 2 -- `movi v1.4h,255,lsl ?#7'
+[^:]*:48: Error: shift amount out of range 0 to 8 at operand 2 -- `movi v1.4h,255,lsl ?#16'
+[^:]*:49: Error: shift amount must be 0 or 16 at operand 2 -- `movi v2.2s,255,msl ?#0'
+[^:]*:50: Error: shift amount must be 0 or 16 at operand 2 -- `movi v2.2s,255,msl ?#15'
 [^:]*:51: Error: invalid floating-point constant at operand 2 -- `fmov v1.2s,1.01'
 [^:]*:52: Error: invalid floating-point constant at operand 2 -- `fmov v1.2d,1.01'
 [^:]*:53: Error: invalid floating-point constant at operand 2 -- `fmov s3,1.01'
@@ -53,27 +53,27 @@
 [^:]*:55: Error: immediate zero expected at operand 2 -- `fcmp d0,#1.0'
 [^:]*:56: Error: expected a scalar SIMD or floating-point register at operand 2 -- `fcmp d0,x0'
 [^:]*:57: Error: immediate zero expected at operand 3 -- `cmgt v0.4s,v2.4s,#1'
-[^:]*:58: Error: unexpected characters following instruction at operand 2 -- `fmov d3,1.00,lsl#3'
+[^:]*:58: Error: unexpected characters following instruction at operand 2 -- `fmov d3,1.00,lsl ?#3'
 [^:]*:59: Error: invalid offset register at operand 2 -- `st2 {v0.4s,v1.4s},\[sp\],sp'
 [^:]*:60: Error: writeback value must be an immediate constant at operand 2 -- `st2 {v0.4s,v1.4s},\[sp\],zr'
-[^:]*:61: Error: invalid shift for the register offset addressing mode at operand 2 -- `ldr q0,\[x0,w0,lsr#4\]'
-[^:]*:62: Error: only 'LSL' shift is permitted at operand 3 -- `adds x1,sp,2134,uxtw#12'
-[^:]*:63: Error: shift amount out of range 0 to 63 at operand 2 -- `movz x0,2134,lsl#64'
-[^:]*:64: Error: expected an integer or zero register at operand 1 -- `adds sp,sp,2134,lsl#12'
+[^:]*:61: Error: invalid shift for the register offset addressing mode at operand 2 -- `ldr q0,\[x0,w0,lsr ?#4\]'
+[^:]*:62: Error: only 'LSL' shift is permitted at operand 3 -- `adds x1,sp,2134,uxtw ?#12'
+[^:]*:63: Error: shift amount out of range 0 to 63 at operand 2 -- `movz x0,2134,lsl ?#64'
+[^:]*:64: Error: expected an integer or zero register at operand 1 -- `adds sp,sp,2134,lsl ?#12'
 [^:]*:65: Error: the optional immediate offset can only be 0 at operand 2 -- `ldxrb w2,\[x0,#1\]'
 [^:]*:66: Error: invalid addressing mode at operand 2 -- `ldrb w0,x1,x2,sxtx'
-[^:]*:67: Error: invalid shift amount at operand 2 -- `prfm PLDL3KEEP,\[x9,x15,sxtx#2\]'
+[^:]*:67: Error: invalid shift amount at operand 2 -- `prfm PLDL3KEEP,\[x9,x15,sxtx ?#2\]'
 [^:]*:68: Error: C0 - C15 expected at operand 3 -- `sysl x7,#1,C16,C30,#1'
 [^:]*:69: Error: C0 - C15 expected at operand 4 -- `sysl x7,#1,C15,C77,#1'
 [^:]*:70: Error: operand 3 must be a 4-bit opcode field named for historical reasons C0 - C15 -- `sysl x7,#1,x15,C1,#1'
-[^:]*:71: Error: extending shift is not permitted at operand 3 -- `add x0,xzr,x7,uxtx#5'
+[^:]*:71: Error: extending shift is not permitted at operand 3 -- `add x0,xzr,x7,uxtx ?#5'
 [^:]*:72: Error: bad expression at operand 2 -- `mov x0,##5'
 [^:]*:73: Error: unknown mnemonic `bad' -- `bad expression'
 [^:]*:74: Error: unknown mnemonic `mockup' -- `mockup-op'
-[^:]*:75: Error: comma expected between operands at operand 2 -- `orr x0. x0,#0xff,lsl#1'
+[^:]*:75: Error: comma expected between operands at operand 2 -- `orr x0. x0,#0xff,lsl ?#1'
 [^:]*:76: Error: the specified relocation type is not allowed for MOVK at operand 2 -- `movk x1,#:abs_g1_s:s12'
-[^:]*:77: Error: can't mix relocation modifier with explicit shift at operand 2 -- `movz x1,#:abs_g1_s:s12,lsl#16'
-[^:]*:78: Error: register offset not allowed in pre-indexed addressing mode at operand 2 -- `prfm pldl3strm,\[sp,w0,sxtw#3\]!'
+[^:]*:77: Error: can't mix relocation modifier with explicit shift at operand 2 -- `movz x1,#:abs_g1_s:s12,lsl ?#16'
+[^:]*:78: Error: register offset not allowed in pre-indexed addressing mode at operand 2 -- `prfm pldl3strm,\[sp,w0,sxtw ?#3\]!'
 [^:]*:79: Error: immediate value out of range 0 to 31 at operand 1 -- `prfm 0x2f,LABEL1'
 [^:]*:80: Error: immediate value out of range 0 to 15 at operand 1 -- `dmb #16'
 [^:]*:81: Error: immediate value out of range 0 to 31 at operand 2 -- `tbz w0,#40,0x17c'
@@ -84,8 +84,8 @@
 [^:]*:86: Error: immediate value must be a multiple of 4 at operand 3 -- `ldnp w7,w15,\[x3,#3\]'
 [^:]*:87: Error: unexpected address writeback at operand 3 -- `stnp x7,x15,\[x3,#32\]!'
 [^:]*:88: Error: immediate offset out of range -256 to 252 at operand 3 -- `ldnp w7,w15,\[x3,#256\]'
-[^:]*:89: Error: shift is not permitted at operand 2 -- `movi v1.2d,4294967295,lsl#0'
-[^:]*:90: Error: shift amount must be 0 at operand 2 -- `movi v1.8b,97,lsl#8'
+[^:]*:89: Error: shift is not permitted at operand 2 -- `movi v1.2d,4294967295,lsl ?#0'
+[^:]*:90: Error: shift amount must be 0 at operand 2 -- `movi v1.8b,97,lsl ?#8'
 [^:]*:91: Error: unknown or missing system register name at operand 1 -- `msr dummy,x1'
 [^:]*:92: Error: invalid floating-point constant at operand 2 -- `fmov s0,0x42000000'
 [^:]*:93: Error: immediate value must be a multiple of 8 at operand 3 -- `ldp x0,x1,\[x2,#4\]'
@@ -156,18 +156,18 @@
 [^:]*:280: Error: invalid addressing mode at operand 2 -- `prfum pldl1keep,\[x3\],x4'
 [^:]*:282: Error: '\]' expected at operand 2 -- `ldr x0,\[x1,#1,mul vl\]'
 [^:]*:283: Error: invalid use of 'MUL' at operand 2 -- `ldr x0,\[x1,x2,mul vl\]'
-[^:]*:284: Error: invalid use of 'MUL' at operand 2 -- `ldr x0,\[x1,x2,mul#1\]'
-[^:]*:285: Error: invalid use of 'MUL' at operand 2 -- `ldr x0,\[x1,x2,mul#4\]'
+[^:]*:284: Error: invalid use of 'MUL' at operand 2 -- `ldr x0,\[x1,x2,mul ?#1\]'
+[^:]*:285: Error: invalid use of 'MUL' at operand 2 -- `ldr x0,\[x1,x2,mul ?#4\]'
 [^:]*:287: Error: invalid use of 'MUL' at operand 2 -- `strb w7,\[x30,x0,mul\]'
-[^:]*:288: Error: invalid use of 'MUL' at operand 2 -- `strb w7,\[x30,x0,mul#1\]'
+[^:]*:288: Error: invalid use of 'MUL' at operand 2 -- `strb w7,\[x30,x0,mul ?#1\]'
 [^:]*:289: Error: invalid use of 'MUL' at operand 2 -- `strb w7,\[x30,w0,mul\]'
-[^:]*:290: Error: invalid use of 'MUL' at operand 2 -- `strb w7,\[x30,w0,mul#2\]'
-[^:]*:292: Error: invalid use of 'MUL' at operand 3 -- `adds x1,sp,1,mul#1'
-[^:]*:293: Error: invalid use of 'MUL' at operand 3 -- `adds x1,sp,2,mul#255'
-[^:]*:294: Error: invalid use of 'MUL' at operand 3 -- `adds x1,sp,3,mul#256'
-[^:]*:295: Error: invalid use of 'MUL' at operand 4 -- `orr x0,x0,#0xff,mul#1'
-[^:]*:296: Error: invalid use of 'MUL' at operand 4 -- `orr x0,x0,#0xfe,mul#255'
-[^:]*:297: Error: invalid use of 'MUL' at operand 4 -- `orr x0,x0,#0xfc,mul#256'
+[^:]*:290: Error: invalid use of 'MUL' at operand 2 -- `strb w7,\[x30,w0,mul ?#2\]'
+[^:]*:292: Error: invalid use of 'MUL' at operand 3 -- `adds x1,sp,1,mul ?#1'
+[^:]*:293: Error: invalid use of 'MUL' at operand 3 -- `adds x1,sp,2,mul ?#255'
+[^:]*:294: Error: invalid use of 'MUL' at operand 3 -- `adds x1,sp,3,mul ?#256'
+[^:]*:295: Error: invalid use of 'MUL' at operand 4 -- `orr x0,x0,#0xff,mul ?#1'
+[^:]*:296: Error: invalid use of 'MUL' at operand 4 -- `orr x0,x0,#0xfe,mul ?#255'
+[^:]*:297: Error: invalid use of 'MUL' at operand 4 -- `orr x0,x0,#0xfc,mul ?#256'
 [^:]*:299: Warning: ignoring redefinition of register alias 'ip0'
 [^:]*:300: Warning: ignoring redefinition of register alias 'ip1'
 [^:]*:301: Warning: ignoring redefinition of register alias 'lr'
diff --git a/gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.l b/gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.l
index 3444d738cdc..bd25bb34b2f 100644
--- a/gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.l
+++ b/gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.l
@@ -1,72 +1,72 @@
 [^:]*: Assembler messages:
-[^:]*:1: Error: z0-z15 expected at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z1\.b},z16\.b\[0\]'
-[^:]*:2: Error: start register out of range at operand 2 -- `fdot za\.s\[w8,0\],{z1\.b-z2\.b},z0\.b\[0\]'
-[^:]*:3: Error: expected a list of 2 registers at operand 2 -- `fdot za\.s\[w8,0,VGx2\],{z0\.b-z3\.b},z0\.b\[0\]'
-[^:]*:4: Error: register element index out of range 0 to 3 at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b\[4\]'
-[^:]*:5: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.s\[w8,8\],{z0\.b-z1\.b},z0\.b\[0\]'
-[^:]*:6: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w7,0\],{z0\.b-z1\.b},z0\.b\[0\]'
-[^:]*:7: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w12,0\],{z0\.b-z1\.b},z0\.b\[0\]'
-[^:]*:9: Error: z0-z15 expected at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z3\.b},z16\.b\[0\]'
-[^:]*:10: Error: start register out of range at operand 2 -- `fdot za\.s\[w8,0\],{z2\.b-z5\.b},z0\.b\[0\]'
-[^:]*:11: Error: expected a list of 4 registers at operand 2 -- `fdot za\.s\[w8,0,VGx4\],{z0\.b-z1\.b},z0\.b\[0\]'
-[^:]*:12: Error: register element index out of range 0 to 3 at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b\[4\]'
-[^:]*:13: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.s\[w8,8\],{z0\.b-z3\.b},z0\.b\[0\]'
-[^:]*:14: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w7,0\],{z0\.b-z3\.b},z0\.b\[0\]'
-[^:]*:15: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w12,0\],{z0\.b-z3\.b},z0\.b\[0\]'
-[^:]*:17: Error: z0-z15 expected at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z1\.b},z16\.b'
-[^:]*:18: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.s\[w8,8\],{z0\.b-z1\.b},z0\.b'
-[^:]*:19: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w7,0\],{z0\.b-z1\.b},z0\.b'
-[^:]*:20: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w12,0\],{z0\.b-z1\.b},z0\.b'
-[^:]*:21: Error: expected a list of 4 registers at operand 2 -- `fdot za\.s\[w8,0,VGx4\],{z0\.b-z1\.b},z0\.b'
-[^:]*:23: Error: z0-z15 expected at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z3\.b},z16\.b'
-[^:]*:24: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.s\[w8,8\],{z0\.b-z3\.b},z0\.b'
-[^:]*:25: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w7,0\],{z0\.b-z3\.b},z0\.b'
-[^:]*:26: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w12,0\],{z0\.b-z3\.b},z0\.b'
-[^:]*:27: Error: expected a list of 2 registers at operand 2 -- `fdot za\.s\[w8,0,VGx2\],{z0\.b-z3\.b},z0\.b'
-[^:]*:29: Error: expected a list of 2 registers at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z1\.b},{z0\.b-z3\.b}'
-[^:]*:30: Error: start register out of range at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z1\.b},{z1\.b-z2\.b}'
-[^:]*:31: Error: start register out of range at operand 2 -- `fdot za\.s\[w8,0\],{z1\.b-z2\.b},{z0\.b-z1\.b}'
-[^:]*:32: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w7,0\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
-[^:]*:33: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.s\[w8,8\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
-[^:]*:35: Error: expected a list of 4 registers at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z3\.b},{z0\.b-z1\.b}'
-[^:]*:36: Error: start register out of range at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z3\.b},{z2\.b-z5\.b}'
-[^:]*:37: Error: start register out of range at operand 2 -- `fdot za\.s\[w8,0\],{z2\.b-z5\.b},{z0\.b-z3\.b}'
-[^:]*:38: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w7,0\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
-[^:]*:39: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.s\[w8,8\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
-[^:]*:41: Error: z0-z15 expected at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z1\.b},z16\.b\[0\]'
-[^:]*:42: Error: start register out of range at operand 2 -- `fdot za\.h\[w8,0\],{z1\.b-z2\.b},z0\.b\[0\]'
-[^:]*:43: Error: expected a list of 2 registers at operand 2 -- `fdot za\.h\[w8,0,VGx2\],{z0\.b-z3\.b},z0\.b\[0\]'
-[^:]*:44: Error: register element index out of range 0 to 7 at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z1\.b},z0\.b\[8\]'
-[^:]*:45: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.h\[w8,8\],{z0\.b-z1\.b},z0\.b\[0\]'
-[^:]*:46: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w7,0\],{z0\.b-z1\.b},z0\.b\[0\]'
-[^:]*:47: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w12,0\],{z0\.b-z1\.b},z0\.b\[0\]'
-[^:]*:49: Error: z0-z15 expected at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z3\.b},z16\.b\[0\]'
-[^:]*:50: Error: start register out of range at operand 2 -- `fdot za\.h\[w8,0\],{z2\.b-z5\.b},z0\.b\[0\]'
-[^:]*:51: Error: expected a list of 4 registers at operand 2 -- `fdot za\.h\[w8,0,VGx4\],{z0\.b-z1\.b},z0\.b\[0\]'
-[^:]*:52: Error: register element index out of range 0 to 7 at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z3\.b},z0\.b\[8\]'
-[^:]*:53: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.h\[w8,8\],{z0\.b-z3\.b},z0\.b\[0\]'
-[^:]*:54: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w7,0\],{z0\.b-z3\.b},z0\.b\[0\]'
-[^:]*:55: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w12,0\],{z0\.b-z3\.b},z0\.b\[0\]'
-[^:]*:57: Error: z0-z15 expected at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z1\.b},z16\.b'
-[^:]*:58: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.h\[w8,8\],{z0\.b-z1\.b},z0\.b'
-[^:]*:59: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w7,0\],{z0\.b-z1\.b},z0\.b'
-[^:]*:60: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w12,0\],{z0\.b-z1\.b},z0\.b'
-[^:]*:61: Error: expected a list of 4 registers at operand 2 -- `fdot za\.h\[w8,0,VGx4\],{z0\.b-z1\.b},z0\.b'
-[^:]*:63: Error: z0-z15 expected at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z3\.b},z16\.b'
-[^:]*:64: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.h\[w8,8\],{z0\.b-z3\.b},z0\.b'
-[^:]*:65: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w7,0\],{z0\.b-z3\.b},z0\.b'
-[^:]*:66: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w12,0\],{z0\.b-z3\.b},z0\.b'
-[^:]*:67: Error: expected a list of 2 registers at operand 2 -- `fdot za\.h\[w8,0,VGx2\],{z0\.b-z3\.b},z0\.b'
-[^:]*:69: Error: expected a list of 2 registers at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z1\.b},{z0\.b-z3\.b}'
-[^:]*:70: Error: start register out of range at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z1\.b},{z1\.b-z2\.b}'
-[^:]*:71: Error: start register out of range at operand 2 -- `fdot za\.h\[w8,0\],{z1\.b-z2\.b},{z0\.b-z1\.b}'
-[^:]*:72: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w7,0\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
-[^:]*:73: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.h\[w8,8\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
-[^:]*:75: Error: expected a list of 4 registers at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z3\.b},{z0\.b-z1\.b}'
-[^:]*:76: Error: start register out of range at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z3\.b},{z2\.b-z5\.b}'
-[^:]*:77: Error: start register out of range at operand 2 -- `fdot za\.h\[w8,0\],{z2\.b-z5\.b},{z0\.b-z3\.b}'
-[^:]*:78: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w7,0\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
-[^:]*:79: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.h\[w8,8\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^:]*:1: Error: z0-z15 expected at operand 3 -- `fdot za\.s\[w8,0\],{ ?z0\.b-z1\.b ?},z16\.b\[0\]'
+[^:]*:2: Error: start register out of range at operand 2 -- `fdot za\.s\[w8,0\],{ ?z1\.b-z2\.b ?},z0\.b\[0\]'
+[^:]*:3: Error: expected a list of 2 registers at operand 2 -- `fdot za\.s\[w8,0,VGx2\],{ ?z0\.b-z3\.b ?},z0\.b\[0\]'
+[^:]*:4: Error: register element index out of range 0 to 3 at operand 3 -- `fdot za\.s\[w8,0\],{ ?z0\.b-z1\.b ?},z0\.b\[4\]'
+[^:]*:5: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.s\[w8,8\],{ ?z0\.b-z1\.b ?},z0\.b\[0\]'
+[^:]*:6: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w7,0\],{ ?z0\.b-z1\.b ?},z0\.b\[0\]'
+[^:]*:7: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w12,0\],{ ?z0\.b-z1\.b ?},z0\.b\[0\]'
+[^:]*:9: Error: z0-z15 expected at operand 3 -- `fdot za\.s\[w8,0\],{ ?z0\.b-z3\.b ?},z16\.b\[0\]'
+[^:]*:10: Error: start register out of range at operand 2 -- `fdot za\.s\[w8,0\],{ ?z2\.b-z5\.b ?},z0\.b\[0\]'
+[^:]*:11: Error: expected a list of 4 registers at operand 2 -- `fdot za\.s\[w8,0,VGx4\],{ ?z0\.b-z1\.b ?},z0\.b\[0\]'
+[^:]*:12: Error: register element index out of range 0 to 3 at operand 3 -- `fdot za\.s\[w8,0\],{ ?z0\.b-z3\.b ?},z0\.b\[4\]'
+[^:]*:13: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.s\[w8,8\],{ ?z0\.b-z3\.b ?},z0\.b\[0\]'
+[^:]*:14: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w7,0\],{ ?z0\.b-z3\.b ?},z0\.b\[0\]'
+[^:]*:15: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w12,0\],{ ?z0\.b-z3\.b ?},z0\.b\[0\]'
+[^:]*:17: Error: z0-z15 expected at operand 3 -- `fdot za\.s\[w8,0\],{ ?z0\.b-z1\.b ?},z16\.b'
+[^:]*:18: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.s\[w8,8\],{ ?z0\.b-z1\.b ?},z0\.b'
+[^:]*:19: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w7,0\],{ ?z0\.b-z1\.b ?},z0\.b'
+[^:]*:20: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w12,0\],{ ?z0\.b-z1\.b ?},z0\.b'
+[^:]*:21: Error: expected a list of 4 registers at operand 2 -- `fdot za\.s\[w8,0,VGx4\],{ ?z0\.b-z1\.b ?},z0\.b'
+[^:]*:23: Error: z0-z15 expected at operand 3 -- `fdot za\.s\[w8,0\],{ ?z0\.b-z3\.b ?},z16\.b'
+[^:]*:24: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.s\[w8,8\],{ ?z0\.b-z3\.b ?},z0\.b'
+[^:]*:25: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w7,0\],{ ?z0\.b-z3\.b ?},z0\.b'
+[^:]*:26: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w12,0\],{ ?z0\.b-z3\.b ?},z0\.b'
+[^:]*:27: Error: expected a list of 2 registers at operand 2 -- `fdot za\.s\[w8,0,VGx2\],{ ?z0\.b-z3\.b ?},z0\.b'
+[^:]*:29: Error: expected a list of 2 registers at operand 3 -- `fdot za\.s\[w8,0\],{ ?z0\.b-z1\.b ?},{ ?z0\.b-z3\.b}'
+[^:]*:30: Error: start register out of range at operand 3 -- `fdot za\.s\[w8,0\],{ ?z0\.b-z1\.b ?},{ ?z1\.b-z2\.b}'
+[^:]*:31: Error: start register out of range at operand 2 -- `fdot za\.s\[w8,0\],{ ?z1\.b-z2\.b ?},{ ?z0\.b-z1\.b}'
+[^:]*:32: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w7,0\],{ ?z0\.b-z1\.b ?},{ ?z0\.b-z1\.b}'
+[^:]*:33: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.s\[w8,8\],{ ?z0\.b-z1\.b ?},{ ?z0\.b-z1\.b}'
+[^:]*:35: Error: expected a list of 4 registers at operand 3 -- `fdot za\.s\[w8,0\],{ ?z0\.b-z3\.b ?},{ ?z0\.b-z1\.b}'
+[^:]*:36: Error: start register out of range at operand 3 -- `fdot za\.s\[w8,0\],{ ?z0\.b-z3\.b ?},{ ?z2\.b-z5\.b}'
+[^:]*:37: Error: start register out of range at operand 2 -- `fdot za\.s\[w8,0\],{ ?z2\.b-z5\.b ?},{ ?z0\.b-z3\.b}'
+[^:]*:38: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w7,0\],{ ?z0\.b-z3\.b ?},{ ?z0\.b-z3\.b}'
+[^:]*:39: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.s\[w8,8\],{ ?z0\.b-z3\.b ?},{ ?z0\.b-z3\.b}'
+[^:]*:41: Error: z0-z15 expected at operand 3 -- `fdot za\.h\[w8,0\],{ ?z0\.b-z1\.b ?},z16\.b\[0\]'
+[^:]*:42: Error: start register out of range at operand 2 -- `fdot za\.h\[w8,0\],{ ?z1\.b-z2\.b ?},z0\.b\[0\]'
+[^:]*:43: Error: expected a list of 2 registers at operand 2 -- `fdot za\.h\[w8,0,VGx2\],{ ?z0\.b-z3\.b ?},z0\.b\[0\]'
+[^:]*:44: Error: register element index out of range 0 to 7 at operand 3 -- `fdot za\.h\[w8,0\],{ ?z0\.b-z1\.b ?},z0\.b\[8\]'
+[^:]*:45: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.h\[w8,8\],{ ?z0\.b-z1\.b ?},z0\.b\[0\]'
+[^:]*:46: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w7,0\],{ ?z0\.b-z1\.b ?},z0\.b\[0\]'
+[^:]*:47: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w12,0\],{ ?z0\.b-z1\.b ?},z0\.b\[0\]'
+[^:]*:49: Error: z0-z15 expected at operand 3 -- `fdot za\.h\[w8,0\],{ ?z0\.b-z3\.b ?},z16\.b\[0\]'
+[^:]*:50: Error: start register out of range at operand 2 -- `fdot za\.h\[w8,0\],{ ?z2\.b-z5\.b ?},z0\.b\[0\]'
+[^:]*:51: Error: expected a list of 4 registers at operand 2 -- `fdot za\.h\[w8,0,VGx4\],{ ?z0\.b-z1\.b ?},z0\.b\[0\]'
+[^:]*:52: Error: register element index out of range 0 to 7 at operand 3 -- `fdot za\.h\[w8,0\],{ ?z0\.b-z3\.b ?},z0\.b\[8\]'
+[^:]*:53: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.h\[w8,8\],{ ?z0\.b-z3\.b ?},z0\.b\[0\]'
+[^:]*:54: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w7,0\],{ ?z0\.b-z3\.b ?},z0\.b\[0\]'
+[^:]*:55: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w12,0\],{ ?z0\.b-z3\.b ?},z0\.b\[0\]'
+[^:]*:57: Error: z0-z15 expected at operand 3 -- `fdot za\.h\[w8,0\],{ ?z0\.b-z1\.b ?},z16\.b'
+[^:]*:58: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.h\[w8,8\],{ ?z0\.b-z1\.b ?},z0\.b'
+[^:]*:59: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w7,0\],{ ?z0\.b-z1\.b ?},z0\.b'
+[^:]*:60: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w12,0\],{ ?z0\.b-z1\.b ?},z0\.b'
+[^:]*:61: Error: expected a list of 4 registers at operand 2 -- `fdot za\.h\[w8,0,VGx4\],{ ?z0\.b-z1\.b ?},z0\.b'
+[^:]*:63: Error: z0-z15 expected at operand 3 -- `fdot za\.h\[w8,0\],{ ?z0\.b-z3\.b ?},z16\.b'
+[^:]*:64: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.h\[w8,8\],{ ?z0\.b-z3\.b ?},z0\.b'
+[^:]*:65: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w7,0\],{ ?z0\.b-z3\.b ?},z0\.b'
+[^:]*:66: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w12,0\],{ ?z0\.b-z3\.b ?},z0\.b'
+[^:]*:67: Error: expected a list of 2 registers at operand 2 -- `fdot za\.h\[w8,0,VGx2\],{ ?z0\.b-z3\.b ?},z0\.b'
+[^:]*:69: Error: expected a list of 2 registers at operand 3 -- `fdot za\.h\[w8,0\],{ ?z0\.b-z1\.b ?},{ ?z0\.b-z3\.b}'
+[^:]*:70: Error: start register out of range at operand 3 -- `fdot za\.h\[w8,0\],{ ?z0\.b-z1\.b ?},{ ?z1\.b-z2\.b}'
+[^:]*:71: Error: start register out of range at operand 2 -- `fdot za\.h\[w8,0\],{ ?z1\.b-z2\.b ?},{ ?z0\.b-z1\.b}'
+[^:]*:72: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w7,0\],{ ?z0\.b-z1\.b ?},{ ?z0\.b-z1\.b}'
+[^:]*:73: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.h\[w8,8\],{ ?z0\.b-z1\.b ?},{ ?z0\.b-z1\.b}'
+[^:]*:75: Error: expected a list of 4 registers at operand 3 -- `fdot za\.h\[w8,0\],{ ?z0\.b-z3\.b ?},{ ?z0\.b-z1\.b}'
+[^:]*:76: Error: start register out of range at operand 3 -- `fdot za\.h\[w8,0\],{ ?z0\.b-z3\.b ?},{ ?z2\.b-z5\.b}'
+[^:]*:77: Error: start register out of range at operand 2 -- `fdot za\.h\[w8,0\],{ ?z2\.b-z5\.b ?},{ ?z0\.b-z3\.b}'
+[^:]*:78: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w7,0\],{ ?z0\.b-z3\.b ?},{ ?z0\.b-z3\.b}'
+[^:]*:79: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.h\[w8,8\],{ ?z0\.b-z3\.b ?},{ ?z0\.b-z3\.b}'
 [^:]*:81: Error: expected a selection register in the range w8-w11 at operand 1 -- `fvdot za\.h\[w7,0\],{z0\.b-z1\.b},z0\.b\[0\]'
 [^:]*:82: Error: expected a selection register in the range w8-w11 at operand 1 -- `fvdot za\.h\[w12,0\],{z0\.b-z1\.b},z0\.b\[0\]'
 [^:]*:83: Error: immediate offset out of range 0 to 7 at operand 1 -- `fvdot za\.h\[w8,8\],{z0\.b-z1\.b},z0\.b\[0\]'
diff --git a/gas/testsuite/gas/aarch64/fp8-sme-fmlal-illegal.l b/gas/testsuite/gas/aarch64/fp8-sme-fmlal-illegal.l
index 31551f97ee6..6749b24340a 100644
--- a/gas/testsuite/gas/aarch64/fp8-sme-fmlal-illegal.l
+++ b/gas/testsuite/gas/aarch64/fp8-sme-fmlal-illegal.l
@@ -8,26 +8,26 @@
 [^:]*:7: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],z0\.b,z0\.b\[0\]'
 [^:]*:8: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0:1\],z0\.b,z0\.b\[0\]'
 [^:]*:9: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0:1\],z0\.b,z0\.b\[0\]'
-[^:]*:11: Error: z0-z15 expected at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z1\.b},z16\.b\[0\]'
-[^:]*:12: Error: start register out of range at operand 2 -- `fmlal za\.h\[w8,0:1\],{z1\.b-z2\.b},z0\.b\[0\]'
-[^:]*:13: Error: expected a list of 2 registers at operand 2 -- `fmlal za\.h\[w8,0:1,VGx2\],{z0\.b-z3\.b},z0\.b\[0\]'
-[^:]*:14: Error: register element index out of range 0 to 15 at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z1\.b},z0\.b\[16\]'
-[^:]*:15: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],{z0\.b-z1\.b},z0\.b\[0\]'
-[^:]*:16: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],{z0\.b-z1\.b},z0\.b\[0\]'
-[^:]*:17: Error: immediate offset out of range 0 to 6 at operand 1 -- `fmlal za\.h\[w8,8:9\],{z0\.b-z1\.b},z0\.b\[0\]'
-[^:]*:18: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],{z0\.b-z1\.b},z0\.b\[0\]'
-[^:]*:19: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0:1\],{z0\.b-z1\.b},z0\.b\[0\]'
-[^:]*:20: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0:1\],{z0\.b-z1\.b},z0\.b\[0\]'
-[^:]*:22: Error: z0-z15 expected at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z3\.b},z16\.b\[0\]'
-[^:]*:23: Error: start register out of range at operand 2 -- `fmlal za\.h\[w8,0:1\],{z2\.b-z5\.b},z0\.b\[0\]'
-[^:]*:24: Error: expected a list of 4 registers at operand 2 -- `fmlal za\.h\[w8,0:1,VGx4\],{z0\.b-z1\.b},z0\.b\[0\]'
-[^:]*:25: Error: register element index out of range 0 to 15 at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z3\.b},z0\.b\[16\]'
-[^:]*:26: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],{z0\.b-z3\.b},z0\.b\[0\]'
-[^:]*:27: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],{z0\.b-z3\.b},z0\.b\[0\]'
-[^:]*:28: Error: immediate offset out of range 0 to 6 at operand 1 -- `fmlal za\.h\[w8,8:9\],{z0\.b-z3\.b},z0\.b\[0\]'
-[^:]*:29: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],{z0\.b-z3\.b},z0\.b\[0\]'
-[^:]*:30: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0\],{z0\.b-z3\.b},z0\.b\[0\]'
-[^:]*:31: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:11: Error: z0-z15 expected at operand 3 -- `fmlal za\.h\[w8,0:1\],{ ?z0\.b-z1\.b ?},z16\.b\[0\]'
+[^:]*:12: Error: start register out of range at operand 2 -- `fmlal za\.h\[w8,0:1\],{ ?z1\.b-z2\.b ?},z0\.b\[0\]'
+[^:]*:13: Error: expected a list of 2 registers at operand 2 -- `fmlal za\.h\[w8,0:1,VGx2\],{ ?z0\.b-z3\.b ?},z0\.b\[0\]'
+[^:]*:14: Error: register element index out of range 0 to 15 at operand 3 -- `fmlal za\.h\[w8,0:1\],{ ?z0\.b-z1\.b ?},z0\.b\[16\]'
+[^:]*:15: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],{ ?z0\.b-z1\.b ?},z0\.b\[0\]'
+[^:]*:16: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],{ ?z0\.b-z1\.b ?},z0\.b\[0\]'
+[^:]*:17: Error: immediate offset out of range 0 to 6 at operand 1 -- `fmlal za\.h\[w8,8:9\],{ ?z0\.b-z1\.b ?},z0\.b\[0\]'
+[^:]*:18: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],{ ?z0\.b-z1\.b ?},z0\.b\[0\]'
+[^:]*:19: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0:1\],{ ?z0\.b-z1\.b ?},z0\.b\[0\]'
+[^:]*:20: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0:1\],{ ?z0\.b-z1\.b ?},z0\.b\[0\]'
+[^:]*:22: Error: z0-z15 expected at operand 3 -- `fmlal za\.h\[w8,0:1\],{ ?z0\.b-z3\.b ?},z16\.b\[0\]'
+[^:]*:23: Error: start register out of range at operand 2 -- `fmlal za\.h\[w8,0:1\],{ ?z2\.b-z5\.b ?},z0\.b\[0\]'
+[^:]*:24: Error: expected a list of 4 registers at operand 2 -- `fmlal za\.h\[w8,0:1,VGx4\],{ ?z0\.b-z1\.b ?},z0\.b\[0\]'
+[^:]*:25: Error: register element index out of range 0 to 15 at operand 3 -- `fmlal za\.h\[w8,0:1\],{ ?z0\.b-z3\.b ?},z0\.b\[16\]'
+[^:]*:26: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],{ ?z0\.b-z3\.b ?},z0\.b\[0\]'
+[^:]*:27: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],{ ?z0\.b-z3\.b ?},z0\.b\[0\]'
+[^:]*:28: Error: immediate offset out of range 0 to 6 at operand 1 -- `fmlal za\.h\[w8,8:9\],{ ?z0\.b-z3\.b ?},z0\.b\[0\]'
+[^:]*:29: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],{ ?z0\.b-z3\.b ?},z0\.b\[0\]'
+[^:]*:30: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0\],{ ?z0\.b-z3\.b ?},z0\.b\[0\]'
+[^:]*:31: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0\],{ ?z0\.b-z3\.b ?},z0\.b\[0\]'
 [^:]*:33: Error: z0-z15 expected at operand 3 -- `fmlal za\.h\[w8,0:1\],z0\.b,z16\.b'
 [^:]*:34: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],z0\.b,z0\.b'
 [^:]*:35: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],z0\.b,z0\.b'
@@ -36,37 +36,37 @@
 [^:]*:38: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0\],z0\.b,z0\.b'
 [^:]*:39: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0\],z0\.b,z0\.b'
 [^:]*:40: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0,VGx4\],z0\.b,z0\.b'
-[^:]*:42: Error: z0-z15 expected at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z1\.b},z16\.b'
-[^:]*:43: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],{z0\.b-z1\.b},z0\.b'
-[^:]*:44: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],{z0\.b-z1\.b},z0\.b'
-[^:]*:45: Error: immediate offset out of range 0 to 6 at operand 1 -- `fmlal za\.h\[w8,8:9\],{z0\.b-z1\.b},z0\.b'
-[^:]*:46: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],{z0\.b-z1\.b},z0\.b'
-[^:]*:47: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0:1\],{z0\.b-z1\.b},z0\.b'
-[^:]*:48: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0:1\],{z0\.b-z1\.b},z0\.b'
-[^:]*:49: Error: expected a list of 4 registers at operand 2 -- `fmlal za\.h\[w8,0:1,VGx4\],{z0\.b-z1\.b},z0\.b'
-[^:]*:51: Error: z0-z15 expected at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z3\.b},z16\.b'
-[^:]*:52: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],{z0\.b-z3\.b},z0\.b'
-[^:]*:53: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],{z0\.b-z3\.b},z0\.b'
-[^:]*:54: Error: immediate offset out of range 0 to 6 at operand 1 -- `fmlal za\.h\[w8,8:9\],{z0\.b-z3\.b},z0\.b'
-[^:]*:55: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],{z0\.b-z3\.b},z0\.b'
-[^:]*:56: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0:1\],{z0\.b-z3\.b},z0\.b'
-[^:]*:57: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0:1\],{z0\.b-z3\.b},z0\.b'
-[^:]*:58: Error: expected a list of 2 registers at operand 2 -- `fmlal za\.h\[w8,0:1,VGx2\],{z0\.b-z3\.b},z0\.b'
-[^:]*:60: Error: expected a list of 2 registers at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z1\.b},{z0\.b-z3\.b}'
-[^:]*:61: Error: start register out of range at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z1\.b},{z1\.b-z2\.b}'
-[^:]*:62: Error: start register out of range at operand 2 -- `fmlal za\.h\[w8,0:1\],{z1\.b-z2\.b},{z0\.b-z1\.b}'
-[^:]*:63: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0:1\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
-[^:]*:64: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0:1\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
-[^:]*:65: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
-[^:]*:66: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
-[^:]*:67: Error: immediate offset out of range 0 to 6 at operand 1 -- `fmlal za\.h\[w8,8:9\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
-[^:]*:68: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
-[^:]*:70: Error: expected a list of 4 registers at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z3\.b},{z0\.b-z1\.b}'
-[^:]*:71: Error: start register out of range at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z3\.b},{z2\.b-z5\.b}'
-[^:]*:72: Error: start register out of range at operand 2 -- `fmlal za\.h\[w8,0:1\],{z2\.b-z5\.b},{z0\.b-z3\.b}'
-[^:]*:73: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0:1\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
-[^:]*:74: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0:1\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
-[^:]*:75: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
-[^:]*:76: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
-[^:]*:77: Error: immediate offset out of range 0 to 6 at operand 1 -- `fmlal za\.h\[w8,8:9\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
-[^:]*:78: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^:]*:42: Error: z0-z15 expected at operand 3 -- `fmlal za\.h\[w8,0:1\],{ ?z0\.b-z1\.b ?},z16\.b'
+[^:]*:43: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],{ ?z0\.b-z1\.b ?},z0\.b'
+[^:]*:44: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],{ ?z0\.b-z1\.b ?},z0\.b'
+[^:]*:45: Error: immediate offset out of range 0 to 6 at operand 1 -- `fmlal za\.h\[w8,8:9\],{ ?z0\.b-z1\.b ?},z0\.b'
+[^:]*:46: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],{ ?z0\.b-z1\.b ?},z0\.b'
+[^:]*:47: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0:1\],{ ?z0\.b-z1\.b ?},z0\.b'
+[^:]*:48: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0:1\],{ ?z0\.b-z1\.b ?},z0\.b'
+[^:]*:49: Error: expected a list of 4 registers at operand 2 -- `fmlal za\.h\[w8,0:1,VGx4\],{ ?z0\.b-z1\.b ?},z0\.b'
+[^:]*:51: Error: z0-z15 expected at operand 3 -- `fmlal za\.h\[w8,0:1\],{ ?z0\.b-z3\.b ?},z16\.b'
+[^:]*:52: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],{ ?z0\.b-z3\.b ?},z0\.b'
+[^:]*:53: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],{ ?z0\.b-z3\.b ?},z0\.b'
+[^:]*:54: Error: immediate offset out of range 0 to 6 at operand 1 -- `fmlal za\.h\[w8,8:9\],{ ?z0\.b-z3\.b ?},z0\.b'
+[^:]*:55: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],{ ?z0\.b-z3\.b ?},z0\.b'
+[^:]*:56: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0:1\],{ ?z0\.b-z3\.b ?},z0\.b'
+[^:]*:57: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0:1\],{ ?z0\.b-z3\.b ?},z0\.b'
+[^:]*:58: Error: expected a list of 2 registers at operand 2 -- `fmlal za\.h\[w8,0:1,VGx2\],{ ?z0\.b-z3\.b ?},z0\.b'
+[^:]*:60: Error: expected a list of 2 registers at operand 3 -- `fmlal za\.h\[w8,0:1\],{ ?z0\.b-z1\.b ?},{ ?z0\.b-z3\.b ?}'
+[^:]*:61: Error: start register out of range at operand 3 -- `fmlal za\.h\[w8,0:1\],{ ?z0\.b-z1\.b ?},{ ?z1\.b-z2\.b ?}'
+[^:]*:62: Error: start register out of range at operand 2 -- `fmlal za\.h\[w8,0:1\],{ ?z1\.b-z2\.b ?},{ ?z0\.b-z1\.b ?}'
+[^:]*:63: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0:1\],{ ?z0\.b-z1\.b ?},{ ?z0\.b-z1\.b ?}'
+[^:]*:64: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0:1\],{ ?z0\.b-z1\.b ?},{ ?z0\.b-z1\.b ?}'
+[^:]*:65: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],{ ?z0\.b-z1\.b ?},{ ?z0\.b-z1\.b ?}'
+[^:]*:66: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],{ ?z0\.b-z1\.b ?},{ ?z0\.b-z1\.b ?}'
+[^:]*:67: Error: immediate offset out of range 0 to 6 at operand 1 -- `fmlal za\.h\[w8,8:9\],{ ?z0\.b-z1\.b ?},{ ?z0\.b-z1\.b ?}'
+[^:]*:68: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],{ ?z0\.b-z1\.b ?},{ ?z0\.b-z1\.b ?}'
+[^:]*:70: Error: expected a list of 4 registers at operand 3 -- `fmlal za\.h\[w8,0:1\],{ ?z0\.b-z3\.b ?},{ ?z0\.b-z1\.b ?}'
+[^:]*:71: Error: start register out of range at operand 3 -- `fmlal za\.h\[w8,0:1\],{ ?z0\.b-z3\.b ?},{ ?z2\.b-z5\.b ?}'
+[^:]*:72: Error: start register out of range at operand 2 -- `fmlal za\.h\[w8,0:1\],{ ?z2\.b-z5\.b ?},{ ?z0\.b-z3\.b ?}'
+[^:]*:73: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0:1\],{ ?z0\.b-z3\.b ?},{ ?z0\.b-z3\.b ?}'
+[^:]*:74: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0:1\],{ ?z0\.b-z3\.b ?},{ ?z0\.b-z3\.b ?}'
+[^:]*:75: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],{ ?z0\.b-z3\.b ?},{ ?z0\.b-z3\.b ?}'
+[^:]*:76: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],{ ?z0\.b-z3\.b ?},{ ?z0\.b-z3\.b ?}'
+[^:]*:77: Error: immediate offset out of range 0 to 6 at operand 1 -- `fmlal za\.h\[w8,8:9\],{ ?z0\.b-z3\.b ?},{ ?z0\.b-z3\.b ?}'
+[^:]*:78: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],{ ?z0\.b-z3\.b ?},{ ?z0\.b-z3\.b ?}'
diff --git a/gas/testsuite/gas/aarch64/fp8-sme-fmlall-illegal.l b/gas/testsuite/gas/aarch64/fp8-sme-fmlall-illegal.l
index 12ffda0ad2b..cb419b98a73 100644
--- a/gas/testsuite/gas/aarch64/fp8-sme-fmlall-illegal.l
+++ b/gas/testsuite/gas/aarch64/fp8-sme-fmlall-illegal.l
@@ -8,26 +8,26 @@
 [^:]*:7: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0:1\],z0\.b,z0\.b\[0\]'
 [^:]*:8: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w7,0:3\],z0\.b,z0\.b\[0\]'
 [^:]*:9: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w12,0:3\],z0\.b,z0\.b\[0\]'
-[^:]*:11: Error: z0-z15 expected at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z1\.b},z16\.b\[0\]'
-[^:]*:12: Error: start register out of range at operand 2 -- `fmlall za\.s\[w8,0:3\],{z1\.b-z2\.b},z0\.b\[0\]'
-[^:]*:13: Error: expected a list of 2 registers at operand 2 -- `fmlall za\.s\[w8,0:3,VGx2\],{z0\.b-z3\.b},z0\.b\[0\]'
-[^:]*:14: Error: register element index out of range 0 to 15 at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z1\.b},z0\.b\[16\]'
-[^:]*:15: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b\[0\]'
-[^:]*:16: Error: starting offset is not a multiple of 4 at operand 1 -- `fmlall za\.s\[w8,2:5\],{z0\.b-z1\.b},z0\.b\[0\]'
-[^:]*:17: Error: immediate offset out of range 0 to 4 at operand 1 -- `fmlall za\.s\[w8,8:11\],{z0\.b-z1\.b},z0\.b\[0\]'
-[^:]*:18: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0:1\],{z0\.b-z1\.b},z0\.b\[0\]'
-[^:]*:19: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w7,0:3\],{z0\.b-z1\.b},z0\.b\[0\]'
-[^:]*:20: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w12,0:3\],{z0\.b-z1\.b},z0\.b\[0\]'
-[^:]*:22: Error: z0-z15 expected at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z3\.b},z16\.b\[0\]'
-[^:]*:23: Error: start register out of range at operand 2 -- `fmlall za\.s\[w8,0:3\],{z2\.b-z5\.b},z0\.b\[0\]'
-[^:]*:24: Error: expected a list of 4 registers at operand 2 -- `fmlall za\.s\[w8,0:3,VGx4\],{z0\.b-z1\.b},z0\.b\[0\]'
-[^:]*:25: Error: register element index out of range 0 to 15 at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z3\.b},z0\.b\[16\]'
-[^:]*:26: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b\[0\]'
-[^:]*:27: Error: starting offset is not a multiple of 4 at operand 1 -- `fmlall za\.s\[w8,2:5\],{z0\.b-z3\.b},z0\.b\[0\]'
-[^:]*:28: Error: immediate offset out of range 0 to 4 at operand 1 -- `fmlall za\.s\[w8,8:11\],{z0\.b-z3\.b},z0\.b\[0\]'
-[^:]*:29: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0:1\],{z0\.b-z3\.b},z0\.b\[0\]'
-[^:]*:30: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w7,0\],{z0\.b-z3\.b},z0\.b\[0\]'
-[^:]*:31: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w12,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:11: Error: z0-z15 expected at operand 3 -- `fmlall za\.s\[w8,0:3\],{ ?z0\.b-z1\.b ?},z16\.b\[0\]'
+[^:]*:12: Error: start register out of range at operand 2 -- `fmlall za\.s\[w8,0:3\],{ ?z1\.b-z2\.b ?},z0\.b\[0\]'
+[^:]*:13: Error: expected a list of 2 registers at operand 2 -- `fmlall za\.s\[w8,0:3,VGx2\],{ ?z0\.b-z3\.b ?},z0\.b\[0\]'
+[^:]*:14: Error: register element index out of range 0 to 15 at operand 3 -- `fmlall za\.s\[w8,0:3\],{ ?z0\.b-z1\.b ?},z0\.b\[16\]'
+[^:]*:15: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0\],{ ?z0\.b-z1\.b ?},z0\.b\[0\]'
+[^:]*:16: Error: starting offset is not a multiple of 4 at operand 1 -- `fmlall za\.s\[w8,2:5\],{ ?z0\.b-z1\.b ?},z0\.b\[0\]'
+[^:]*:17: Error: immediate offset out of range 0 to 4 at operand 1 -- `fmlall za\.s\[w8,8:11\],{ ?z0\.b-z1\.b ?},z0\.b\[0\]'
+[^:]*:18: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0:1\],{ ?z0\.b-z1\.b ?},z0\.b\[0\]'
+[^:]*:19: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w7,0:3\],{ ?z0\.b-z1\.b ?},z0\.b\[0\]'
+[^:]*:20: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w12,0:3\],{ ?z0\.b-z1\.b ?},z0\.b\[0\]'
+[^:]*:22: Error: z0-z15 expected at operand 3 -- `fmlall za\.s\[w8,0:3\],{ ?z0\.b-z3\.b ?},z16\.b\[0\]'
+[^:]*:23: Error: start register out of range at operand 2 -- `fmlall za\.s\[w8,0:3\],{ ?z2\.b-z5\.b ?},z0\.b\[0\]'
+[^:]*:24: Error: expected a list of 4 registers at operand 2 -- `fmlall za\.s\[w8,0:3,VGx4\],{ ?z0\.b-z1\.b ?},z0\.b\[0\]'
+[^:]*:25: Error: register element index out of range 0 to 15 at operand 3 -- `fmlall za\.s\[w8,0:3\],{ ?z0\.b-z3\.b ?},z0\.b\[16\]'
+[^:]*:26: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0\],{ ?z0\.b-z3\.b ?},z0\.b\[0\]'
+[^:]*:27: Error: starting offset is not a multiple of 4 at operand 1 -- `fmlall za\.s\[w8,2:5\],{ ?z0\.b-z3\.b ?},z0\.b\[0\]'
+[^:]*:28: Error: immediate offset out of range 0 to 4 at operand 1 -- `fmlall za\.s\[w8,8:11\],{ ?z0\.b-z3\.b ?},z0\.b\[0\]'
+[^:]*:29: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0:1\],{ ?z0\.b-z3\.b ?},z0\.b\[0\]'
+[^:]*:30: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w7,0\],{ ?z0\.b-z3\.b ?},z0\.b\[0\]'
+[^:]*:31: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w12,0\],{ ?z0\.b-z3\.b ?},z0\.b\[0\]'
 [^:]*:33: Error: z0-z15 expected at operand 3 -- `fmlall za\.s\[w8,0:3\],z0\.b,z16\.b'
 [^:]*:34: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0\],z0\.b,z0\.b'
 [^:]*:35: Error: starting offset is not a multiple of 4 at operand 1 -- `fmlall za\.s\[w8,2:5\],z0\.b,z0\.b'
@@ -36,37 +36,37 @@
 [^:]*:38: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w7,0\],z0\.b,z0\.b'
 [^:]*:39: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w12,0\],z0\.b,z0\.b'
 [^:]*:40: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0,VGx4\],z0\.b,z0\.b'
-[^:]*:42: Error: z0-z15 expected at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z1\.b},z16\.b'
-[^:]*:43: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b'
-[^:]*:44: Error: starting offset is not a multiple of 4 at operand 1 -- `fmlall za\.s\[w8,2:5\],{z0\.b-z1\.b},z0\.b'
-[^:]*:45: Error: immediate offset out of range 0 to 4 at operand 1 -- `fmlall za\.s\[w8,8:11\],{z0\.b-z1\.b},z0\.b'
-[^:]*:46: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0:1\],{z0\.b-z1\.b},z0\.b'
-[^:]*:47: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w7,0:3\],{z0\.b-z1\.b},z0\.b'
-[^:]*:48: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w12,0:3\],{z0\.b-z1\.b},z0\.b'
-[^:]*:49: Error: expected a list of 4 registers at operand 2 -- `fmlall za\.s\[w8,0:3,VGx4\],{z0\.b-z1\.b},z0\.b'
-[^:]*:51: Error: z0-z15 expected at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z3\.b},z16\.b'
-[^:]*:52: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b'
-[^:]*:53: Error: starting offset is not a multiple of 4 at operand 1 -- `fmlall za\.s\[w8,2:5\],{z0\.b-z3\.b},z0\.b'
-[^:]*:54: Error: immediate offset out of range 0 to 4 at operand 1 -- `fmlall za\.s\[w8,8:11\],{z0\.b-z3\.b},z0\.b'
-[^:]*:55: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0:1\],{z0\.b-z3\.b},z0\.b'
-[^:]*:56: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w7,0:3\],{z0\.b-z3\.b},z0\.b'
-[^:]*:57: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w12,0:3\],{z0\.b-z3\.b},z0\.b'
-[^:]*:58: Error: expected a list of 2 registers at operand 2 -- `fmlall za\.s\[w8,0:3,VGx2\],{z0\.b-z3\.b},z0\.b'
-[^:]*:60: Error: expected a list of 2 registers at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z1\.b},{z0\.b-z3\.b}'
-[^:]*:61: Error: start register out of range at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z1\.b},{z1\.b-z2\.b}'
-[^:]*:62: Error: start register out of range at operand 2 -- `fmlall za\.s\[w8,0:3\],{z1\.b-z2\.b},{z0\.b-z1\.b}'
-[^:]*:63: Error: expected a selection register in the range w8-w11 at opera[...]

[diff truncated at 100000 bytes]

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2024-08-09  9:52 [binutils-gdb] aarch64: relax gas testsuite whitespace expectations Jan Beulich

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