From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 16687 invoked by alias); 17 May 2014 21:09:14 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 16677 invoked by uid 89); 17 May 2014 21:09:14 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.6 required=5.0 tests=AWL,BAYES_00,MSGID_MULTIPLE_AT,UPPERCASE_50_75 autolearn=no version=3.3.2 X-HELO: mailhost.u-strasbg.fr Received: from mailhost.u-strasbg.fr (HELO mailhost.u-strasbg.fr) (130.79.222.218) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 17 May 2014 21:09:12 +0000 Received: from mailhost.u-strasbg.fr (localhost [127.0.0.1]) by antispam (Postfix) with ESMTP id 20424220DF9 for ; Sat, 17 May 2014 23:09:09 +0200 (CEST) Received: from mailhost.u-strasbg.fr (localhost [127.0.0.1]) by antivirus (Postfix) with ESMTP id 10925220FA8 for ; Sat, 17 May 2014 23:09:09 +0200 (CEST) Received: from md14.u-strasbg.fr (md14.u-strasbg.fr [130.79.200.249]) by mr8.u-strasbg.fr (Postfix) with ESMTP id F3EEF220DF9 for ; Sat, 17 May 2014 23:09:07 +0200 (CEST) Received: from ms16.u-strasbg.fr (ms16.u-strasbg.fr [130.79.204.116]) by md14.u-strasbg.fr (8.14.3/jtpda-5.5pre1) with ESMTP id s4HL975v027432 for ; Sat, 17 May 2014 23:09:07 +0200 Received: from E6510Muller (lec67-4-82-230-53-140.fbx.proxad.net [82.230.53.140]) (Authenticated sender: mullerp) by ms16.u-strasbg.fr (Postfix) with ESMTPSA id 4AF6C1FD7C for ; Sat, 17 May 2014 23:09:07 +0200 (CEST) From: "Pierre Muller" To: Subject: [RFA] fix mingw32 --enable-targets=all --enable-64-bit-bfd failure in or1k-desc.h Date: Sat, 17 May 2014 21:09:00 -0000 Message-ID: <000601cf7214$3d18c6a0$b74a53e0$@muller@ics-cnrs.unistra.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-SW-Source: 2014-05/txt/msg00152.txt.bz2 Compilation fails for mingw32 host with the following error: make[3]: Entering directory `/home/Pierre/git/build/mult-mingw32/opcodes' /bin/sh ./libtool --tag=CC --mode=compile gcc -DHAVE_CONFIG_H -I. -I../../../b inutils-gdb/opcodes -I. -I../../../binutils-gdb/opcodes -I../bfd -I../../../bin utils-gdb/opcodes/../include -I../../../binutils-gdb/opcodes/../bfd -D__USE_MING W_FSEEK -W -Wall -Wstrict-prototypes -Wmissing-prototypes -Wshadow -Wno-format -Werror -gdwarf-4 -O0 -D__USE_MINGW_ACCESS -MT or1k-asm.lo -MD -MP -MF .deps/or 1k-asm.Tpo -c -o or1k-asm.lo ../../../binutils-gdb/opcodes/or1k-asm.c libtool: compile: gcc -DHAVE_CONFIG_H -I. -I../../../binutils-gdb/opcodes -I. - I../../../binutils-gdb/opcodes -I../bfd -I../../../binutils-gdb/opcodes/../inclu de -I../../../binutils-gdb/opcodes/../bfd -D__USE_MINGW_FSEEK -W -Wall -Wstrict- prototypes -Wmissing-prototypes -Wshadow -Wno-format -Werror -gdwarf-4 -O0 -D__U SE_MINGW_ACCESS -MT or1k-asm.lo -MD -MP -MF .deps/or1k-asm.Tpo -c ../../../binut ils-gdb/opcodes/or1k-asm.c -o or1k-asm.o In file included from ../../../binutils-gdb/opcodes/or1k-asm.c:34:0: ../../../binutils-gdb/opcodes/or1k-desc.h:260:73: error: this decimal constant i s unsigned only in ISO C90 [-Werror] SPR_FIELD_MASK_SYS_VR_REV = 63, SPR_FIELD_MASK_SYS_VR_CFG = 16711680, SPR_FIE LD_MASK_SYS_VR_VER = 4278190080, SPR_FIELD_MASK_SYS_UPR_UP = 1 ^ ../../../binutils-gdb/opcodes/or1k-desc.h:263:73: error: this decimal constant i s unsigned only in ISO C90 [-Werror] , SPR_FIELD_MASK_SYS_UPR_PMP = 512, SPR_FIELD_MASK_SYS_UPR_TTP = 1024, SPR_FIE LD_MASK_SYS_UPR_CUP = 4278190080, SPR_FIELD_MASK_SYS_CPUCFGR_NSGR = 15 ^ ../../../binutils-gdb/opcodes/or1k-desc.h:270:4: error: this decimal constant is unsigned only in ISO C90 [-Werror] , SPR_FIELD_MASK_SYS_SR_CID = 4026531840, SPR_FIELD_MASK_SYS_FPCSR_FPEE = 1, S PR_FIELD_MASK_SYS_FPCSR_RM = 6, SPR_FIELD_MASK_SYS_FPCSR_OVF = 8 ^ cc1.exe: all warnings being treated as errors The error can be fixed by adding UL suffix, I found that ULL suffix was used elsewhere, but it seems that UL is enough here. ChangeLog entry: 2014-05-17 Pierre Muller * or1k-desc.h (enum spr_field_masks): Remove compilation warning on 32-bit systems. diff --git a/opcodes/or1k-desc.h b/opcodes/or1k-desc.h old mode 100644 new mode 100755 index d27872f..748a963 --- a/opcodes/or1k-desc.h +++ b/opcodes/or1k-desc.h @@ -257,17 +257,17 @@ typedef enum spr_field_lsbs { /* Enum declaration for SPR field masks. */ typedef enum spr_field_masks { - SPR_FIELD_MASK_SYS_VR_REV = 63, SPR_FIELD_MASK_SYS_VR_CFG = 16711680, SPR_FIELD_MASK_SYS_VR_VER = 4278190080, SPR_FIELD_MASK_SYS_UPR_UP = 1 + SPR_FIELD_MASK_SYS_VR_REV = 63, SPR_FIELD_MASK_SYS_VR_CFG = 16711680, SPR_FIELD_MASK_SYS_VR_VER = 4278190080UL, SPR_FIELD_MASK_SYS_UPR_UP = 1 , SPR_FIELD_MASK_SYS_UPR_DCP = 2, SPR_FIELD_MASK_SYS_UPR_ICP = 4, SPR_FIELD_MASK_SYS_UPR_DMP = 8, SPR_FIELD_MASK_SYS_UPR_MP = 16 , SPR_FIELD_MASK_SYS_UPR_IMP = 32, SPR_FIELD_MASK_SYS_UPR_DUP = 64, SPR_FIELD_MASK_SYS_UPR_PCUP = 128, SPR_FIELD_MASK_SYS_UPR_PICP = 256 - , SPR_FIELD_MASK_SYS_UPR_PMP = 512, SPR_FIELD_MASK_SYS_UPR_TTP = 1024, SPR_FIELD_MASK_SYS_UPR_CUP = 4278190080, SPR_FIELD_MASK_SYS_CPUCFGR_NSGR = 15 + , SPR_FIELD_MASK_SYS_UPR_PMP = 512, SPR_FIELD_MASK_SYS_UPR_TTP = 1024, SPR_FIELD_MASK_SYS_UPR_CUP = 4278190080UL, SPR_FIELD_MASK_SYS_CPUCFGR_NSGR = 15 , SPR_FIELD_MASK_SYS_CPUCFGR_CGF = 16, SPR_FIELD_MASK_SYS_CPUCFGR_OB32S = 32, SPR_FIELD_MASK_SYS_CPUCFGR_OB64S = 64, SPR_FIELD_MASK_SYS_CPUCFGR_OF32S = 128 , SPR_FIELD_MASK_SYS_CPUCFGR_OF64S = 256, SPR_FIELD_MASK_SYS_CPUCFGR_OV64S = 512, SPR_FIELD_MASK_SYS_CPUCFGR_ND = 1024, SPR_FIELD_MASK_SYS_SR_SM = 1 , SPR_FIELD_MASK_SYS_SR_TEE = 2, SPR_FIELD_MASK_SYS_SR_IEE = 4, SPR_FIELD_MASK_SYS_SR_DCE = 8, SPR_FIELD_MASK_SYS_SR_ICE = 16 , SPR_FIELD_MASK_SYS_SR_DME = 32, SPR_FIELD_MASK_SYS_SR_IME = 64, SPR_FIELD_MASK_SYS_SR_LEE = 128, SPR_FIELD_MASK_SYS_SR_CE = 256 , SPR_FIELD_MASK_SYS_SR_F = 512, SPR_FIELD_MASK_SYS_SR_CY = 1024, SPR_FIELD_MASK_SYS_SR_OV = 2048, SPR_FIELD_MASK_SYS_SR_OVE = 4096 , SPR_FIELD_MASK_SYS_SR_DSX = 8192, SPR_FIELD_MASK_SYS_SR_EPH = 16384, SPR_FIELD_MASK_SYS_SR_FO = 32768, SPR_FIELD_MASK_SYS_SR_SUMRA = 65536 - , SPR_FIELD_MASK_SYS_SR_CID = 4026531840, SPR_FIELD_MASK_SYS_FPCSR_FPEE = 1, SPR_FIELD_MASK_SYS_FPCSR_RM = 6, SPR_FIELD_MASK_SYS_FPCSR_OVF = 8 + , SPR_FIELD_MASK_SYS_SR_CID = 4026531840UL, SPR_FIELD_MASK_SYS_FPCSR_FPEE = 1, SPR_FIELD_MASK_SYS_FPCSR_RM = 6, SPR_FIELD_MASK_SYS_FPCSR_OVF = 8 , SPR_FIELD_MASK_SYS_FPCSR_UNF = 16, SPR_FIELD_MASK_SYS_FPCSR_SNF = 32, SPR_FIELD_MASK_SYS_FPCSR_QNF = 64, SPR_FIELD_MASK_SYS_FPCSR_ZF = 128 , SPR_FIELD_MASK_SYS_FPCSR_IXF = 256, SPR_FIELD_MASK_SYS_FPCSR_IVF = 512, SPR_FIELD_MASK_SYS_FPCSR_INF = 1024, SPR_FIELD_MASK_SYS_FPCSR_DZF = 2048 } SPR_FIELD_MASKS;