* [patch] GAS supports for MIPS32 MT ASE
@ 2005-08-26 22:05 Chao-ying Fu
2005-08-29 9:55 ` Maciej W. Rozycki
0 siblings, 1 reply; 15+ messages in thread
From: Chao-ying Fu @ 2005-08-26 22:05 UTC (permalink / raw)
To: Eric Christopher; +Cc: Thekkath, Radhika, Thiemo Seufer, binutils
[-- Attachment #1: Type: text/plain, Size: 2899 bytes --]
Hello, All,
We want to contribute another GAS patch for MIPS32 MT ASE. (This MT patch
is similar to the previous DSP patch, in terms of the code structure.)
The MT ASE defines 8 new instructions for multithreading as follows.
1. DMT: Disable multi-threaded execution
2. EMT: Enable multi-threaded execution
3. DVPE: Disable virtual processor execution
4. EVPE: Enable virtual processor execution
5. FORK: Allocate and schedule a new thread.
6. YIELD: Conditionally deschedule or deallocate the current thread.
7. MFTR: Move from thread context.
(It has assembler idioms: MFTC0, MFTGPR, MFTLO, MFTHI, MFTACX,
MFTDSP, MFTC1, MFTHC1, CFTC1, MFTC2, MFTHC2, CFTC2.)
8. MTTR: Move to thread context.
(It has assembler idioms: MTTC0, MTTGPR, MTTLO, MTTHI, MTTACX,
MTTDSP, MTTC1, MTTHC1, CTTC1, MTTC2, MTTHC2, CTTC2.)
I built and tested with mipsisa64-elf and mipsisa32-elf. No new
regressions.
Could you review this patch? We will revise the patch, if there are issues.
Thanks a lot!
Regards,
Chao-ying
include/opcode/ChangeLog
2005-08-26 Chao-ying Fu <fu@mips.com>
* mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
define.
Document !, $, *, &, g, +t, +T operand formats for MT instructions.
(INSN_ASE_MASK): Update to include INSN_MT.
(INSN_MT): New define for MT ASE.
opcodes/ChangeLog
2005-08-26 Chao-ying Fu <fu@mips.com>
* mips-opc.c (MT32): New define.
(mips_builtin_opcodes): Add MT instructions.
Move "bc0f", "bc0fl", "bc0t", "bc0tl" to the end to avoid opcode
collision with "mftr" and "mttr".
* mips-dis.c (mips_arch_choices): Enable INSN_MT for mips32r2.
(print_insn_args): Add supports for +t, +T, !, $, *, &, g operand
formats.
gas/ChangeLog
2005-08-26 Chao-ying Fu <fu@mips.com>
* config/tc-mips.c (mips_set_options): Add ase_mt for MT instructions.
(mips_opts): Add -1 to initialize ase_mt.
(file_ase_mt): New variable for -mt.
(CPU_HAS_MT): New define.
(validate_mips_insn): Add supports for +t, +T, !, $, *, &, g operand
formats.
(mips_ip): Check ase_mt to enable MT instructions.
Handle !, $, *, &, +T, +t, g operand formats.
For "mftc1", "mfthc1", "cftc1", "mttc1", "mtthc1", "cttc1", we allow
odd float registers.
(OPTION_MT, OPTION_NO_MT): New define.
(OPTION_COMPAT_ARCH_BASE): Change because of inserting MT define.
(md_parse_option): Parse OPTION_MT and OPTION_NO_MT.
(mips_after_parse_args): Set ase_mt based on CPU.
(s_mipsset): Handle ".set mt" and ".set nomt".
(mips_elf_final_processing): Remind of adding new flag for MT ASE.
(md_show_usage): Show usage of -mt and -mno-mt.
gas/testsuite/ChangeLog
2005-08-26 Chao-ying Fu <fu@mips.com>
* gas/mips/mips.exp: Run MT test for mips32r2 only.
* gas/mips/mips32-mt.[sdl]: New test.
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Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.44
diff -c -3 -p -r1.44 mips.h
*** include/opcode/mips.h 25 Aug 2005 18:09:24 -0000 1.44
--- include/opcode/mips.h 26 Aug 2005 21:16:27 -0000
*************** Software Foundation, 51 Franklin Street
*** 170,175 ****
--- 170,185 ----
#define OP_SH_RDDSP 16
#define OP_MASK_RDDSP 0x3f
+ /* MIPS MT ASE */
+ #define OP_SH_MT_U 5
+ #define OP_MASK_MT_U 0x1
+ #define OP_SH_MT_H 4
+ #define OP_MASK_MT_H 0x1
+ #define OP_SH_MTACC_T 18
+ #define OP_MASK_MTACC_T 0x3
+ #define OP_SH_MTACC_D 13
+ #define OP_MASK_MTACC_D 0x3
+
#define OP_OP_COP0 0x10
#define OP_OP_COP1 0x11
#define OP_OP_COP2 0x12
*************** struct mips_opcode
*** 331,336 ****
--- 341,355 ----
"'" 6 bit unsigned immediate (OP_*_RDDSP)
"@" 10 bit signed immediate (OP_*_IMM10)
+ MT ASE usage:
+ "!" 1 bit immediate at bit 5
+ "$" 1 bit immediate at bit 4
+ "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
+ "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
+ "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
+ "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
+ "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
+
Other:
"()" parens surrounding optional value
"," separates operands
*************** struct mips_opcode
*** 339,351 ****
Characters used so far, for quick reference when adding more:
"34567890"
! "%[]<>(),+:'@"
"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
! "abcdefhijklopqrstuvwxz"
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
! "ABCDEFGHI"
*/
/* These are the bits which may be set in the pinfo field of an
--- 358,371 ----
Characters used so far, for quick reference when adding more:
"34567890"
! "%[]<>(),+:'@!$*&"
"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
! "abcdefghijklopqrstuvwxz"
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
! "ABCDEFGHIT"
! "t"
*/
/* These are the bits which may be set in the pinfo field of an
*************** struct mips_opcode
*** 447,453 ****
#define INSN_ISA64R2 0x00000100
/* Masks used for MIPS-defined ASEs. */
! #define INSN_ASE_MASK 0x0000f000
/* DSP ASE */
#define INSN_DSP 0x00001000
--- 467,473 ----
#define INSN_ISA64R2 0x00000100
/* Masks used for MIPS-defined ASEs. */
! #define INSN_ASE_MASK 0x0400f000
/* DSP ASE */
#define INSN_DSP 0x00001000
*************** struct mips_opcode
*** 480,485 ****
--- 500,507 ----
#define INSN_5400 0x01000000
/* NEC VR5500 instruction. */
#define INSN_5500 0x02000000
+ /* MT ASE */
+ #define INSN_MT 0x04000000
/* MIPS ISA defines, use instead of hardcoding ISA level. */
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.52
diff -c -3 -p -r1.52 mips-opc.c
*** opcodes/mips-opc.c 25 Aug 2005 18:12:43 -0000 1.52
--- opcodes/mips-opc.c 26 Aug 2005 21:16:28 -0000
*************** Software Foundation, 51 Franklin Street
*** 146,151 ****
--- 146,154 ----
#define DSP_VOLA INSN_TRAP
#define D32 (INSN_DSP)
+ /* MIPS MT ASE support. */
+ #define MT32 (INSN_MT)
+
/* The order of overloaded instructions matters. Label arguments and
register arguments look the same. Instructions that can have either
for arguments must apear in the correct order in this table for the
*************** const struct mips_opcode mips_builtin_op
*** 220,229 ****
{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 },
/* b is at the top of the table. */
/* bal is at the top of the table. */
- {"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1 },
- {"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
- {"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1 },
- {"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
{"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
{"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
{"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
--- 223,228 ----
*************** const struct mips_opcode mips_builtin_op
*** 1352,1357 ****
--- 1351,1415 ----
{"subu_s.qb", "d,s,t", 0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"wrdsp", "s", 0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA, 0, D32 },
{"wrdsp", "s,8", 0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA, 0, D32 },
+ /* MIPS MT ASE Instructions. */
+ {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, MT32 },
+ {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
+ {"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, MT32 },
+ {"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
+ {"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 },
+ {"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
+ {"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, MT32 },
+ {"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
+ {"fork", "d,s,t", 0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t, 0, MT32 },
+ {"yield", "s", 0x7c000009, 0xfc1fffff, TRAP|RD_s, 0, MT32 },
+ {"yield", "d,s", 0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s, 0, MT32 },
+ {"mftc0", "d,+t", 0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0, 0, MT32 },
+ {"mftc0", "d,+T", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 },
+ {"mftc0", "d,E,H", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 },
+ {"mftgpr", "d,t", 0x41000020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 },
+ {"mftlo", "d", 0x41000021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
+ {"mftlo", "d,*", 0x41000021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
+ {"mfthi", "d", 0x41010021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
+ {"mfthi", "d,*", 0x41010021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
+ {"mftacx", "d", 0x41020021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
+ {"mftacx", "d,*", 0x41020021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
+ {"mftdsp", "d", 0x41100021, 0xffff07ff, TRAP|WR_d, 0, MT32 },
+ {"mftc1", "d,T", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 },
+ {"mftc1", "d,E", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 },
+ {"mfthc1", "d,T", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 },
+ {"mfthc1", "d,E", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 },
+ {"cftc1", "d,E", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 },
+ {"cftc1", "d,T", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 },
+ {"mftc2", "d,E", 0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
+ {"mfthc2", "d,E", 0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
+ {"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
+ {"mttc0", "t,G", 0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
+ {"mttc0", "t,+D", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
+ {"mttc0", "t,G,H", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
+ {"mttgpr", "t,d", 0x41800020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 },
+ {"mttlo", "t", 0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
+ {"mttlo", "t,&", 0x41800021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },
+ {"mtthi", "t", 0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
+ {"mtthi", "t,&", 0x41800821, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },
+ {"mttacx", "t", 0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
+ {"mttacx", "t,&", 0x41801021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },
+ {"mttdsp", "t", 0x41808021, 0xffe0ffff, TRAP|RD_t, 0, MT32 },
+ {"mttc1", "t,S", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 },
+ {"mttc1", "t,G", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 },
+ {"mtthc1", "t,S", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 },
+ {"mtthc1", "t,G", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 },
+ {"cttc1", "t,g", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 },
+ {"cttc1", "t,S", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 },
+ {"mttc2", "t,g", 0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 },
+ {"mtthc2", "t,g", 0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 },
+ {"cttc2", "t,g", 0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC, 0, MT32 },
+ {"mftr", "t,d,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d, 0, MT32 },
+ {"mttr", "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t, 0, MT32 },
+ /* Move bc0* after mftr and mttr to avoid opcode collision. */
+ {"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1 },
+ {"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
+ {"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1 },
+ {"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
};
#define MIPS_NUM_OPCODES \
Index: opcodes/mips-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-dis.c,v
retrieving revision 1.53
diff -c -3 -p -r1.53 mips-dis.c
*** opcodes/mips-dis.c 25 Aug 2005 18:12:44 -0000 1.53
--- opcodes/mips-dis.c 26 Aug 2005 21:16:28 -0000
*************** const struct mips_arch_choice mips_arch_
*** 376,382 ****
mips_hwr_names_numeric },
{ "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
! ISA_MIPS32R2 | INSN_MIPS16 | INSN_DSP,
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_hwr_names_mips3264r2 },
--- 376,382 ----
mips_hwr_names_numeric },
{ "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
! ISA_MIPS32R2 | INSN_MIPS16 | INSN_DSP | INSN_MT,
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_hwr_names_mips3264r2 },
*************** print_insn_args (const char *d,
*** 771,776 ****
--- 771,804 ----
(*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
break;
+ case 't': /* Coprocessor 0 reg name */
+ (*info->fprintf_func) (info->stream, "%s",
+ mips_cp0_names[(l >> OP_SH_RT) &
+ OP_MASK_RT]);
+ break;
+
+ case 'T': /* Coprocessor 0 reg name */
+ {
+ const struct mips_cp0sel_name *n;
+ unsigned int cp0reg, sel;
+
+ cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
+ sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
+
+ /* CP0 register including 'sel' code for mftc0, to be
+ printed textually if known. If not known, print both
+ CP0 register name and sel numerically since CP0 register
+ with sel 0 may have a name unrelated to register being
+ printed. */
+ n = lookup_mips_cp0sel_name(mips_cp0sel_names,
+ mips_cp0sel_names_len, cp0reg, sel);
+ if (n != NULL)
+ (*info->fprintf_func) (info->stream, "%s", n->name);
+ else
+ (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
+ break;
+ }
+
default:
/* xgettext:c-format */
(*info->fprintf_func) (info->stream,
*************** print_insn_args (const char *d,
*** 841,846 ****
--- 869,900 ----
(*info->fprintf_func) (info->stream, "%d", delta);
break;
+ case '!':
+ (*info->fprintf_func) (info->stream, "%ld",
+ (l >> OP_SH_MT_U) & OP_MASK_MT_U);
+ break;
+
+ case '$':
+ (*info->fprintf_func) (info->stream, "%ld",
+ (l >> OP_SH_MT_H) & OP_MASK_MT_H);
+ break;
+
+ case '*':
+ (*info->fprintf_func) (info->stream, "$ac%ld",
+ (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
+ break;
+
+ case '&':
+ (*info->fprintf_func) (info->stream, "$ac%ld",
+ (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
+ break;
+
+ case 'g':
+ /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
+ (*info->fprintf_func) (info->stream, "$%ld",
+ (l >> OP_SH_RD) & OP_MASK_RD);
+ break;
+
case 's':
case 'b':
case 'r':
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.318
diff -c -3 -p -r1.318 tc-mips.c
*** gas/config/tc-mips.c 25 Aug 2005 18:17:36 -0000 1.318
--- gas/config/tc-mips.c 26 Aug 2005 21:16:29 -0000
*************** struct mips_set_options
*** 194,199 ****
--- 194,200 ----
int ase_mips3d;
int ase_mdmx;
int ase_dsp;
+ int ase_mt;
/* Whether we are assembling for the mips16 processor. 0 if we are
not, 1 if we are, and -1 if the value has not been initialized.
Changed by `.set mips16' and `.set nomips16', and the -mips16 and
*************** static int file_mips_fp32 = -1;
*** 244,250 ****
static struct mips_set_options mips_opts =
{
! ISA_UNKNOWN, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE
};
/* These variables are filled in with the masks of registers used.
--- 245,251 ----
static struct mips_set_options mips_opts =
{
! ISA_UNKNOWN, -1, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE
};
/* These variables are filled in with the masks of registers used.
*************** static int file_ase_mdmx;
*** 272,277 ****
--- 273,282 ----
command line (e.g., by -march). */
static int file_ase_dsp;
+ /* True if -mt was passed or implied by arguments passed on the
+ command line (e.g., by -march). */
+ static int file_ase_mt;
+
/* The argument of the -march= flag. The architecture we are assembling. */
static int file_mips_arch = CPU_UNKNOWN;
static const char *mips_arch_string;
*************** static int mips_32bitmode = 0;
*** 374,379 ****
--- 379,388 ----
#define CPU_HAS_DSP(cpu) (FALSE \
)
+ /* Return true if the given CPU supports the MT ASE. */
+ #define CPU_HAS_MT(cpu) (FALSE \
+ )
+
/* True if CPU has a dror instruction. */
#define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
*************** validate_mips_insn (const struct mips_op
*** 7765,7770 ****
--- 7774,7782 ----
case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
case 'I': break;
+ case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
+ case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
+ USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
default:
as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
c, opc->name, opc->args);
*************** validate_mips_insn (const struct mips_op
*** 7837,7842 ****
--- 7849,7859 ----
case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
+ case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
+ case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
+ case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
+ case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
+ case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
default:
as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
c, opc->name, opc->args);
*************** mips_ip (char *str, struct mips_cl_insn
*** 7935,7940 ****
--- 7952,7958 ----
| (file_ase_mips16 ? INSN_MIPS16 : 0)
| (mips_opts.ase_mdmx ? INSN_MDMX : 0)
| (mips_opts.ase_dsp ? INSN_DSP : 0)
+ | (mips_opts.ase_mt ? INSN_MT : 0)
| (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
mips_opts.arch))
ok = TRUE;
*************** mips_ip (char *str, struct mips_cl_insn
*** 8156,8161 ****
--- 8174,8233 ----
s = expr_end;
continue;
+ case '!': /* mt 1-bit unsigned immediate in bit 5 */
+ my_getExpression (&imm_expr, s);
+ check_absolute_expr (ip, &imm_expr);
+ if (imm_expr.X_add_number & ~OP_MASK_MT_U)
+ {
+ as_warn (_("MT immediate not in range 0..%d (%lu)"),
+ OP_MASK_MT_U, (unsigned long) imm_expr.X_add_number);
+ imm_expr.X_add_number &= OP_MASK_MT_U;
+ }
+ ip->insn_opcode |= imm_expr.X_add_number << OP_SH_MT_U;
+ imm_expr.X_op = O_absent;
+ s = expr_end;
+ continue;
+
+ case '$': /* mt 1-bit unsigned immediate in bit 4 */
+ my_getExpression (&imm_expr, s);
+ check_absolute_expr (ip, &imm_expr);
+ if (imm_expr.X_add_number & ~OP_MASK_MT_H)
+ {
+ as_warn (_("MT immediate not in range 0..%d (%lu)"),
+ OP_MASK_MT_H, (unsigned long) imm_expr.X_add_number);
+ imm_expr.X_add_number &= OP_MASK_MT_H;
+ }
+ ip->insn_opcode |= imm_expr.X_add_number << OP_SH_MT_H;
+ imm_expr.X_op = O_absent;
+ s = expr_end;
+ continue;
+
+ case '*': /* four dsp accumulators in bits 18,19 */
+ if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
+ s[3] >= '0' && s[3] <= '3')
+ {
+ regno = s[3] - '0';
+ s += 4;
+ ip->insn_opcode |= regno << OP_SH_MTACC_T;
+ continue;
+ }
+ else
+ as_bad (_("Invalid dsp/smartmips acc register"));
+ break;
+
+ case '&': /* four dsp accumulators in bits 13,14 */
+ if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
+ s[3] >= '0' && s[3] <= '3')
+ {
+ regno = s[3] - '0';
+ s += 4;
+ ip->insn_opcode |= regno << OP_SH_MTACC_D;
+ continue;
+ }
+ else
+ as_bad (_("Invalid dsp/smartmips acc register"));
+ break;
+
case ',':
if (*s++ == *args)
continue;
*************** do_msbd:
*** 8308,8313 ****
--- 8380,8413 ----
s = expr_end;
continue;
+ case 'T': /* Coprocessor register */
+ /* +T is for disassembly only; never match. */
+ break;
+
+ case 't': /* Coprocessor register number */
+ if (s[0] == '$' && ISDIGIT (s[1]))
+ {
+ ++s;
+ regno = 0;
+ do
+ {
+ regno *= 10;
+ regno += *s - '0';
+ ++s;
+ }
+ while (ISDIGIT (*s));
+ if (regno > 31)
+ as_bad (_("Invalid register number (%d)"), regno);
+ else
+ {
+ ip->insn_opcode |= regno << OP_SH_RT;
+ continue;
+ }
+ }
+ else
+ as_bad (_("Invalid coprocessor 0 register number"));
+ break;
+
default:
as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
*args, insn->name, insn->args);
*************** do_msbd:
*** 8442,8447 ****
--- 8542,8548 ----
case 'x': /* ignore register name */
case 'z': /* must be zero register */
case 'U': /* destination register (clo/clz). */
+ case 'g': /* coprocessor destination register */
s_reset = s;
if (s[0] == '$')
{
*************** do_msbd:
*** 8566,8571 ****
--- 8667,8673 ----
case 'd':
case 'G':
case 'K':
+ case 'g':
INSERT_OPERAND (RD, *ip, regno);
break;
case 'U':
*************** do_msbd:
*** 8681,8687 ****
|| strcmp (str, "lwc1") == 0
|| strcmp (str, "swc1") == 0
|| strcmp (str, "l.s") == 0
! || strcmp (str, "s.s") == 0))
as_warn (_("Float register should be even, was %d"),
regno);
--- 8783,8795 ----
|| strcmp (str, "lwc1") == 0
|| strcmp (str, "swc1") == 0
|| strcmp (str, "l.s") == 0
! || strcmp (str, "s.s") == 0
! || strcmp (str, "mftc1") == 0
! || strcmp (str, "mfthc1") == 0
! || strcmp (str, "cftc1") == 0
! || strcmp (str, "mttc1") == 0
! || strcmp (str, "mtthc1") == 0
! || strcmp (str, "cttc1") == 0))
as_warn (_("Float register should be even, was %d"),
regno);
*************** struct option md_longopts[] =
*** 10222,10230 ****
{"mdsp", no_argument, NULL, OPTION_DSP},
#define OPTION_NO_DSP (OPTION_ASE_BASE + 7)
{"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
/* Old-style architecture options. Don't add more of these. */
! #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 8)
#define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
{"m4650", no_argument, NULL, OPTION_M4650},
#define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
--- 10330,10342 ----
{"mdsp", no_argument, NULL, OPTION_DSP},
#define OPTION_NO_DSP (OPTION_ASE_BASE + 7)
{"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
+ #define OPTION_MT (OPTION_ASE_BASE + 8)
+ {"mt", no_argument, NULL, OPTION_MT},
+ #define OPTION_NO_MT (OPTION_ASE_BASE + 9)
+ {"mno-mt", no_argument, NULL, OPTION_NO_MT},
/* Old-style architecture options. Don't add more of these. */
! #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 10)
#define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
{"m4650", no_argument, NULL, OPTION_M4650},
#define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
*************** md_parse_option (int c, char *arg)
*** 10484,10489 ****
--- 10596,10609 ----
mips_opts.ase_dsp = 0;
break;
+ case OPTION_MT:
+ mips_opts.ase_mt = 1;
+ break;
+
+ case OPTION_NO_MT:
+ mips_opts.ase_mt = 0;
+ break;
+
case OPTION_MIPS16:
mips_opts.mips16 = 1;
mips_no_prev_insn ();
*************** mips_after_parse_args (void)
*** 10840,10851 ****
--- 10960,10974 ----
mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0;
if (mips_opts.ase_dsp == -1)
mips_opts.ase_dsp = (CPU_HAS_DSP (file_mips_arch)) ? 1 : 0;
+ if (mips_opts.ase_mt == -1)
+ mips_opts.ase_mt = (CPU_HAS_MT (file_mips_arch)) ? 1 : 0;
file_mips_isa = mips_opts.isa;
file_ase_mips16 = mips_opts.mips16;
file_ase_mips3d = mips_opts.ase_mips3d;
file_ase_mdmx = mips_opts.ase_mdmx;
file_ase_dsp = mips_opts.ase_dsp;
+ file_ase_mt = mips_opts.ase_mt;
mips_opts.gp32 = file_mips_gp32;
mips_opts.fp32 = file_mips_fp32;
*************** s_mipsset (int x ATTRIBUTE_UNUSED)
*** 11787,11792 ****
--- 11910,11919 ----
mips_opts.ase_dsp = 1;
else if (strcmp (name, "nodsp") == 0)
mips_opts.ase_dsp = 0;
+ else if (strcmp (name, "mt") == 0)
+ mips_opts.ase_mt = 1;
+ else if (strcmp (name, "nomt") == 0)
+ mips_opts.ase_mt = 0;
else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
{
int reset = 0;
*************** mips_elf_final_processing (void)
*** 13523,13528 ****
--- 13650,13657 ----
/* Set MIPS ELF flags for ASEs. */
/* We may need to define a new flag for DSP ASE, and set this flag when
file_ase_dsp is true. */
+ /* We may need to define a new flag for MT ASE, and set this flag when
+ file_ase_mt is true. */
if (file_ase_mips16)
elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
#if 0 /* XXX FIXME */
*************** MIPS options:\n\
*** 14230,14235 ****
--- 14359,14367 ----
-mdsp generate DSP instructions\n\
-mno-dsp do not generate DSP instructions\n"));
fprintf (stream, _("\
+ -mt generate MT instructions\n\
+ -mno-mt do not generate MT instructions\n"));
+ fprintf (stream, _("\
-mfix-vr4120 work around certain VR4120 errata\n\
-mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
-mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.108
diff -c -3 -p -r1.108 mips.exp
*** gas/testsuite/gas/mips/mips.exp 25 Aug 2005 18:21:47 -0000 1.108
--- gas/testsuite/gas/mips/mips.exp 26 Aug 2005 21:16:29 -0000
*************** if { [istarget mips*-*-*] } then {
*** 763,768 ****
--- 763,769 ----
run_list_test "noat-7" ""
run_dump_test_arches "mips32-dsp" [mips_arch_list_matching mips32 !sb1]
+ run_dump_test_arches "mips32-mt" [mips_arch_list_matching mips32r2 !gpr64]
if { $elf && !$no_mips16 } {
run_dump_test "mips16-dwarf2"
[-- Attachment #3: mips32-mt.s --]
[-- Type: application/octet-stream, Size: 15990 bytes --]
# source file to test assembly of MIPS MT ASE for MIPS32 instructions
.set noreorder
.set noat
.text
text_label:
dmt
dmt $0
dvpe
dvpe $1
emt
emt $2
evpe
evpe $3
fork $4,$5,$6
yield $5
yield $6,$7
mftc0 $7,$8
mftc0 $8,$0,0
mftc0 $8,$0,1
mftc0 $8,$0,2
mftc0 $8,$0,3
mftc0 $8,$0,4
mftc0 $8,$0,5
mftc0 $8,$0,6
mftc0 $8,$0,7
mftc0 $8,$1,0
mftc0 $8,$1,1
mftc0 $8,$1,2
mftc0 $8,$1,3
mftc0 $8,$1,4
mftc0 $8,$1,5
mftc0 $8,$1,6
mftc0 $8,$1,7
mftc0 $8,$2,0
mftc0 $8,$2,1
mftc0 $8,$2,2
mftc0 $8,$2,3
mftc0 $8,$2,4
mftc0 $8,$2,5
mftc0 $8,$2,6
mftc0 $8,$2,7
mftc0 $8,$3,0
mftc0 $8,$3,1
mftc0 $8,$3,2
mftc0 $8,$3,3
mftc0 $8,$3,4
mftc0 $8,$3,5
mftc0 $8,$3,6
mftc0 $8,$3,7
mftc0 $8,$4,0
mftc0 $8,$4,1
mftc0 $8,$4,2
mftc0 $8,$4,3
mftc0 $8,$4,4
mftc0 $8,$4,5
mftc0 $8,$4,6
mftc0 $8,$4,7
mftc0 $8,$5,0
mftc0 $8,$5,1
mftc0 $8,$5,2
mftc0 $8,$5,3
mftc0 $8,$5,4
mftc0 $8,$5,5
mftc0 $8,$5,6
mftc0 $8,$5,7
mftc0 $8,$6,0
mftc0 $8,$6,1
mftc0 $8,$6,2
mftc0 $8,$6,3
mftc0 $8,$6,4
mftc0 $8,$6,5
mftc0 $8,$6,6
mftc0 $8,$6,7
mftc0 $8,$7,0
mftc0 $8,$7,1
mftc0 $8,$7,2
mftc0 $8,$7,3
mftc0 $8,$7,4
mftc0 $8,$7,5
mftc0 $8,$7,6
mftc0 $8,$7,7
mftc0 $8,$8,0
mftc0 $8,$8,1
mftc0 $8,$8,2
mftc0 $8,$8,3
mftc0 $8,$8,4
mftc0 $8,$8,5
mftc0 $8,$8,6
mftc0 $8,$8,7
mftc0 $8,$9,0
mftc0 $8,$9,1
mftc0 $8,$9,2
mftc0 $8,$9,3
mftc0 $8,$9,4
mftc0 $8,$9,5
mftc0 $8,$9,6
mftc0 $8,$9,7
mftc0 $8,$10,0
mftc0 $8,$10,1
mftc0 $8,$10,2
mftc0 $8,$10,3
mftc0 $8,$10,4
mftc0 $8,$10,5
mftc0 $8,$10,6
mftc0 $8,$10,7
mftc0 $8,$11,0
mftc0 $8,$11,1
mftc0 $8,$11,2
mftc0 $8,$11,3
mftc0 $8,$11,4
mftc0 $8,$11,5
mftc0 $8,$11,6
mftc0 $8,$11,7
mftc0 $8,$12,0
mftc0 $8,$12,1
mftc0 $8,$12,2
mftc0 $8,$12,3
mftc0 $8,$12,4
mftc0 $8,$12,5
mftc0 $8,$12,6
mftc0 $8,$12,7
mftc0 $8,$13,0
mftc0 $8,$13,1
mftc0 $8,$13,2
mftc0 $8,$13,3
mftc0 $8,$13,4
mftc0 $8,$13,5
mftc0 $8,$13,6
mftc0 $8,$13,7
mftc0 $8,$14,0
mftc0 $8,$14,1
mftc0 $8,$14,2
mftc0 $8,$14,3
mftc0 $8,$14,4
mftc0 $8,$14,5
mftc0 $8,$14,6
mftc0 $8,$14,7
mftc0 $8,$15,0
mftc0 $8,$15,1
mftc0 $8,$15,2
mftc0 $8,$15,3
mftc0 $8,$15,4
mftc0 $8,$15,5
mftc0 $8,$15,6
mftc0 $8,$15,7
mftc0 $8,$16,0
mftc0 $8,$16,1
mftc0 $8,$16,2
mftc0 $8,$16,3
mftc0 $8,$16,4
mftc0 $8,$16,5
mftc0 $8,$16,6
mftc0 $8,$16,7
mftc0 $8,$17,0
mftc0 $8,$17,1
mftc0 $8,$17,2
mftc0 $8,$17,3
mftc0 $8,$17,4
mftc0 $8,$17,5
mftc0 $8,$17,6
mftc0 $8,$17,7
mftc0 $8,$18,0
mftc0 $8,$18,1
mftc0 $8,$18,2
mftc0 $8,$18,3
mftc0 $8,$18,4
mftc0 $8,$18,5
mftc0 $8,$18,6
mftc0 $8,$18,7
mftc0 $8,$19,0
mftc0 $8,$19,1
mftc0 $8,$19,2
mftc0 $8,$19,3
mftc0 $8,$19,4
mftc0 $8,$19,5
mftc0 $8,$19,6
mftc0 $8,$19,7
mftc0 $8,$20,0
mftc0 $8,$20,1
mftc0 $8,$20,2
mftc0 $8,$20,3
mftc0 $8,$20,4
mftc0 $8,$20,5
mftc0 $8,$20,6
mftc0 $8,$20,7
mftc0 $8,$21,0
mftc0 $8,$21,1
mftc0 $8,$21,2
mftc0 $8,$21,3
mftc0 $8,$21,4
mftc0 $8,$21,5
mftc0 $8,$21,6
mftc0 $8,$21,7
mftc0 $8,$22,0
mftc0 $8,$22,1
mftc0 $8,$22,2
mftc0 $8,$22,3
mftc0 $8,$22,4
mftc0 $8,$22,5
mftc0 $8,$22,6
mftc0 $8,$22,7
mftc0 $8,$23,0
mftc0 $8,$23,1
mftc0 $8,$23,2
mftc0 $8,$23,3
mftc0 $8,$23,4
mftc0 $8,$23,5
mftc0 $8,$23,6
mftc0 $8,$23,7
mftc0 $8,$24,0
mftc0 $8,$24,1
mftc0 $8,$24,2
mftc0 $8,$24,3
mftc0 $8,$24,4
mftc0 $8,$24,5
mftc0 $8,$24,6
mftc0 $8,$24,7
mftc0 $8,$25,0
mftc0 $8,$25,1
mftc0 $8,$25,2
mftc0 $8,$25,3
mftc0 $8,$25,4
mftc0 $8,$25,5
mftc0 $8,$25,6
mftc0 $8,$25,7
mftc0 $8,$26,0
mftc0 $8,$26,1
mftc0 $8,$26,2
mftc0 $8,$26,3
mftc0 $8,$26,4
mftc0 $8,$26,5
mftc0 $8,$26,6
mftc0 $8,$26,7
mftc0 $8,$27,0
mftc0 $8,$27,1
mftc0 $8,$27,2
mftc0 $8,$27,3
mftc0 $8,$27,4
mftc0 $8,$27,5
mftc0 $8,$27,6
mftc0 $8,$27,7
mftc0 $8,$28,0
mftc0 $8,$28,1
mftc0 $8,$28,2
mftc0 $8,$28,3
mftc0 $8,$28,4
mftc0 $8,$28,5
mftc0 $8,$28,6
mftc0 $8,$28,7
mftc0 $8,$29,0
mftc0 $8,$29,1
mftc0 $8,$29,2
mftc0 $8,$29,3
mftc0 $8,$29,4
mftc0 $8,$29,5
mftc0 $8,$29,6
mftc0 $8,$29,7
mftc0 $8,$30,0
mftc0 $8,$30,1
mftc0 $8,$30,2
mftc0 $8,$30,3
mftc0 $8,$30,4
mftc0 $8,$30,5
mftc0 $8,$30,6
mftc0 $8,$30,7
mftc0 $8,$31,0
mftc0 $8,$31,1
mftc0 $8,$31,2
mftc0 $8,$31,3
mftc0 $8,$31,4
mftc0 $8,$31,5
mftc0 $8,$31,6
mftc0 $8,$31,7
mftgpr $9,$10
mftlo $10
mftlo $11,$ac0
mfthi $12
mfthi $13,$ac1
mftacx $14
mftacx $15,$ac2
mftdsp $16
mftc1 $17,$f18
mftc1 $18,$19
mfthc1 $19,$f20
mfthc1 $20,$22
cftc1 $21,$22
cftc1 $22,$f23
mftc2 $23,$24
mfthc2 $24,$25
cftc2 $25,$26
mttc0 $26,$27
mttc0 $27,$0,0
mttc0 $27,$0,1
mttc0 $27,$0,2
mttc0 $27,$0,3
mttc0 $27,$0,4
mttc0 $27,$0,5
mttc0 $27,$0,6
mttc0 $27,$0,7
mttc0 $27,$1,0
mttc0 $27,$1,1
mttc0 $27,$1,2
mttc0 $27,$1,3
mttc0 $27,$1,4
mttc0 $27,$1,5
mttc0 $27,$1,6
mttc0 $27,$1,7
mttc0 $27,$2,0
mttc0 $27,$2,1
mttc0 $27,$2,2
mttc0 $27,$2,3
mttc0 $27,$2,4
mttc0 $27,$2,5
mttc0 $27,$2,6
mttc0 $27,$2,7
mttc0 $27,$3,0
mttc0 $27,$3,1
mttc0 $27,$3,2
mttc0 $27,$3,3
mttc0 $27,$3,4
mttc0 $27,$3,5
mttc0 $27,$3,6
mttc0 $27,$3,7
mttc0 $27,$4,0
mttc0 $27,$4,1
mttc0 $27,$4,2
mttc0 $27,$4,3
mttc0 $27,$4,4
mttc0 $27,$4,5
mttc0 $27,$4,6
mttc0 $27,$4,7
mttc0 $27,$5,0
mttc0 $27,$5,1
mttc0 $27,$5,2
mttc0 $27,$5,3
mttc0 $27,$5,4
mttc0 $27,$5,5
mttc0 $27,$5,6
mttc0 $27,$5,7
mttc0 $27,$6,0
mttc0 $27,$6,1
mttc0 $27,$6,2
mttc0 $27,$6,3
mttc0 $27,$6,4
mttc0 $27,$6,5
mttc0 $27,$6,6
mttc0 $27,$6,7
mttc0 $27,$7,0
mttc0 $27,$7,1
mttc0 $27,$7,2
mttc0 $27,$7,3
mttc0 $27,$7,4
mttc0 $27,$7,5
mttc0 $27,$7,6
mttc0 $27,$7,7
mttc0 $27,$8,0
mttc0 $27,$8,1
mttc0 $27,$8,2
mttc0 $27,$8,3
mttc0 $27,$8,4
mttc0 $27,$8,5
mttc0 $27,$8,6
mttc0 $27,$8,7
mttc0 $27,$9,0
mttc0 $27,$9,1
mttc0 $27,$9,2
mttc0 $27,$9,3
mttc0 $27,$9,4
mttc0 $27,$9,5
mttc0 $27,$9,6
mttc0 $27,$9,7
mttc0 $27,$10,0
mttc0 $27,$10,1
mttc0 $27,$10,2
mttc0 $27,$10,3
mttc0 $27,$10,4
mttc0 $27,$10,5
mttc0 $27,$10,6
mttc0 $27,$10,7
mttc0 $27,$11,0
mttc0 $27,$11,1
mttc0 $27,$11,2
mttc0 $27,$11,3
mttc0 $27,$11,4
mttc0 $27,$11,5
mttc0 $27,$11,6
mttc0 $27,$11,7
mttc0 $27,$12,0
mttc0 $27,$12,1
mttc0 $27,$12,2
mttc0 $27,$12,3
mttc0 $27,$12,4
mttc0 $27,$12,5
mttc0 $27,$12,6
mttc0 $27,$12,7
mttc0 $27,$13,0
mttc0 $27,$13,1
mttc0 $27,$13,2
mttc0 $27,$13,3
mttc0 $27,$13,4
mttc0 $27,$13,5
mttc0 $27,$13,6
mttc0 $27,$13,7
mttc0 $27,$14,0
mttc0 $27,$14,1
mttc0 $27,$14,2
mttc0 $27,$14,3
mttc0 $27,$14,4
mttc0 $27,$14,5
mttc0 $27,$14,6
mttc0 $27,$14,7
mttc0 $27,$15,0
mttc0 $27,$15,1
mttc0 $27,$15,2
mttc0 $27,$15,3
mttc0 $27,$15,4
mttc0 $27,$15,5
mttc0 $27,$15,6
mttc0 $27,$15,7
mttc0 $27,$16,0
mttc0 $27,$16,1
mttc0 $27,$16,2
mttc0 $27,$16,3
mttc0 $27,$16,4
mttc0 $27,$16,5
mttc0 $27,$16,6
mttc0 $27,$16,7
mttc0 $27,$17,0
mttc0 $27,$17,1
mttc0 $27,$17,2
mttc0 $27,$17,3
mttc0 $27,$17,4
mttc0 $27,$17,5
mttc0 $27,$17,6
mttc0 $27,$17,7
mttc0 $27,$18,0
mttc0 $27,$18,1
mttc0 $27,$18,2
mttc0 $27,$18,3
mttc0 $27,$18,4
mttc0 $27,$18,5
mttc0 $27,$18,6
mttc0 $27,$18,7
mttc0 $27,$19,0
mttc0 $27,$19,1
mttc0 $27,$19,2
mttc0 $27,$19,3
mttc0 $27,$19,4
mttc0 $27,$19,5
mttc0 $27,$19,6
mttc0 $27,$19,7
mttc0 $27,$20,0
mttc0 $27,$20,1
mttc0 $27,$20,2
mttc0 $27,$20,3
mttc0 $27,$20,4
mttc0 $27,$20,5
mttc0 $27,$20,6
mttc0 $27,$20,7
mttc0 $27,$21,0
mttc0 $27,$21,1
mttc0 $27,$21,2
mttc0 $27,$21,3
mttc0 $27,$21,4
mttc0 $27,$21,5
mttc0 $27,$21,6
mttc0 $27,$21,7
mttc0 $27,$22,0
mttc0 $27,$22,1
mttc0 $27,$22,2
mttc0 $27,$22,3
mttc0 $27,$22,4
mttc0 $27,$22,5
mttc0 $27,$22,6
mttc0 $27,$22,7
mttc0 $27,$23,0
mttc0 $27,$23,1
mttc0 $27,$23,2
mttc0 $27,$23,3
mttc0 $27,$23,4
mttc0 $27,$23,5
mttc0 $27,$23,6
mttc0 $27,$23,7
mttc0 $27,$24,0
mttc0 $27,$24,1
mttc0 $27,$24,2
mttc0 $27,$24,3
mttc0 $27,$24,4
mttc0 $27,$24,5
mttc0 $27,$24,6
mttc0 $27,$24,7
mttc0 $27,$25,0
mttc0 $27,$25,1
mttc0 $27,$25,2
mttc0 $27,$25,3
mttc0 $27,$25,4
mttc0 $27,$25,5
mttc0 $27,$25,6
mttc0 $27,$25,7
mttc0 $27,$26,0
mttc0 $27,$26,1
mttc0 $27,$26,2
mttc0 $27,$26,3
mttc0 $27,$26,4
mttc0 $27,$26,5
mttc0 $27,$26,6
mttc0 $27,$26,7
mttc0 $27,$27,0
mttc0 $27,$27,1
mttc0 $27,$27,2
mttc0 $27,$27,3
mttc0 $27,$27,4
mttc0 $27,$27,5
mttc0 $27,$27,6
mttc0 $27,$27,7
mttc0 $27,$28,0
mttc0 $27,$28,1
mttc0 $27,$28,2
mttc0 $27,$28,3
mttc0 $27,$28,4
mttc0 $27,$28,5
mttc0 $27,$28,6
mttc0 $27,$28,7
mttc0 $27,$29,0
mttc0 $27,$29,1
mttc0 $27,$29,2
mttc0 $27,$29,3
mttc0 $27,$29,4
mttc0 $27,$29,5
mttc0 $27,$29,6
mttc0 $27,$29,7
mttc0 $27,$30,0
mttc0 $27,$30,1
mttc0 $27,$30,2
mttc0 $27,$30,3
mttc0 $27,$30,4
mttc0 $27,$30,5
mttc0 $27,$30,6
mttc0 $27,$30,7
mttc0 $27,$31,0
mttc0 $27,$31,1
mttc0 $27,$31,2
mttc0 $27,$31,3
mttc0 $27,$31,4
mttc0 $27,$31,5
mttc0 $27,$31,6
mttc0 $27,$31,7
mttgpr $28,$29
mttlo $29
mttlo $30,$ac3
mtthi $31
mtthi $0,$ac0
mttacx $1
mttacx $2,$ac1
mttdsp $3
mttc1 $4,$f5
mttc1 $5,$6
mtthc1 $6,$f8
mtthc1 $7,$10
cttc1 $8,$9
cttc1 $9,$f10
mttc2 $10,$11
mtthc2 $11,$12
cttc2 $12,$13
mftr $13,$14,-1,0,-1
mftr $13,$14,-1,1,-1
mftr $13,$14,-1,2,-1
mftr $13,$14,-1,3,-1
mftr $13,$14,-1,4,-1
mftr $13,$14,-1,5,-1
mftr $13,$14,-1,6,-1
mftr $13,$14,-1,7,-1
mftr $13,$14,-1,0,0
mftr $13,$14,-1,1,0
mftr $13,$14,-1,2,0
mftr $13,$14,-1,3,0
mftr $13,$14,-1,4,0
mftr $13,$14,-1,5,0
mftr $13,$14,-1,6,0
mftr $13,$14,-1,7,0
mftr $13,$14,-1,0,1
mftr $13,$14,-1,1,1
mftr $13,$14,-1,2,1
mftr $13,$14,-1,3,1
mftr $13,$14,-1,4,1
mftr $13,$14,-1,5,1
mftr $13,$14,-1,6,1
mftr $13,$14,-1,7,1
mftr $13,$14,-1,0,2
mftr $13,$14,-1,1,2
mftr $13,$14,-1,2,2
mftr $13,$14,-1,3,2
mftr $13,$14,-1,4,2
mftr $13,$14,-1,5,2
mftr $13,$14,-1,6,2
mftr $13,$14,-1,7,2
mftr $13,$14,0,0,-1
mftr $13,$14,0,1,-1
mftr $13,$14,0,2,-1
mftr $13,$14,0,3,-1
mftr $13,$14,0,4,-1
mftr $13,$14,0,5,-1
mftr $13,$14,0,6,-1
mftr $13,$14,0,7,-1
mftr $13,$14,0,0,0
mftr $13,$14,0,1,0
mftr $13,$14,0,2,0
mftr $13,$14,0,3,0
mftr $13,$14,0,4,0
mftr $13,$14,0,5,0
mftr $13,$14,0,6,0
mftr $13,$14,0,7,0
mftr $13,$14,0,0,1
mftr $13,$14,0,1,1
mftr $13,$14,0,2,1
mftr $13,$14,0,3,1
mftr $13,$14,0,4,1
mftr $13,$14,0,5,1
mftr $13,$14,0,6,1
mftr $13,$14,0,7,1
mftr $13,$14,0,0,2
mftr $13,$14,0,1,2
mftr $13,$14,0,2,2
mftr $13,$14,0,3,2
mftr $13,$14,0,4,2
mftr $13,$14,0,5,2
mftr $13,$14,0,6,2
mftr $13,$14,0,7,2
mftr $13,$14,1,0,-1
mftr $13,$14,1,1,-1
mftr $13,$14,1,2,-1
mftr $13,$14,1,3,-1
mftr $13,$14,1,4,-1
mftr $13,$14,1,5,-1
mftr $13,$14,1,6,-1
mftr $13,$14,1,7,-1
mftr $13,$14,1,0,0
mftr $13,$14,1,1,0
mftr $13,$14,1,2,0
mftr $13,$14,1,3,0
mftr $13,$14,1,4,0
mftr $13,$14,1,5,0
mftr $13,$14,1,6,0
mftr $13,$14,1,7,0
mftr $13,$14,1,0,1
mftr $13,$14,1,1,1
mftr $13,$14,1,2,1
mftr $13,$14,1,3,1
mftr $13,$14,1,4,1
mftr $13,$14,1,5,1
mftr $13,$14,1,6,1
mftr $13,$14,1,7,1
mftr $13,$14,1,0,2
mftr $13,$14,1,1,2
mftr $13,$14,1,2,2
mftr $13,$14,1,3,2
mftr $13,$14,1,4,2
mftr $13,$14,1,5,2
mftr $13,$14,1,6,2
mftr $13,$14,1,7,2
mftr $13,$14,2,0,-1
mftr $13,$14,2,1,-1
mftr $13,$14,2,2,-1
mftr $13,$14,2,3,-1
mftr $13,$14,2,4,-1
mftr $13,$14,2,5,-1
mftr $13,$14,2,6,-1
mftr $13,$14,2,7,-1
mftr $13,$14,2,0,0
mftr $13,$14,2,1,0
mftr $13,$14,2,2,0
mftr $13,$14,2,3,0
mftr $13,$14,2,4,0
mftr $13,$14,2,5,0
mftr $13,$14,2,6,0
mftr $13,$14,2,7,0
mftr $13,$14,2,0,1
mftr $13,$14,2,1,1
mftr $13,$14,2,2,1
mftr $13,$14,2,3,1
mftr $13,$14,2,4,1
mftr $13,$14,2,5,1
mftr $13,$14,2,6,1
mftr $13,$14,2,7,1
mftr $13,$14,2,0,2
mftr $13,$14,2,1,2
mftr $13,$14,2,2,2
mftr $13,$14,2,3,2
mftr $13,$14,2,4,2
mftr $13,$14,2,5,2
mftr $13,$14,2,6,2
mftr $13,$14,2,7,2
mttr $13,$14,-1,0,-1
mttr $13,$14,-1,1,-1
mttr $13,$14,-1,2,-1
mttr $13,$14,-1,3,-1
mttr $13,$14,-1,4,-1
mttr $13,$14,-1,5,-1
mttr $13,$14,-1,6,-1
mttr $13,$14,-1,7,-1
mttr $13,$14,-1,0,0
mttr $13,$14,-1,1,0
mttr $13,$14,-1,2,0
mttr $13,$14,-1,3,0
mttr $13,$14,-1,4,0
mttr $13,$14,-1,5,0
mttr $13,$14,-1,6,0
mttr $13,$14,-1,7,0
mttr $13,$14,-1,0,1
mttr $13,$14,-1,1,1
mttr $13,$14,-1,2,1
mttr $13,$14,-1,3,1
mttr $13,$14,-1,4,1
mttr $13,$14,-1,5,1
mttr $13,$14,-1,6,1
mttr $13,$14,-1,7,1
mttr $13,$14,-1,0,2
mttr $13,$14,-1,1,2
mttr $13,$14,-1,2,2
mttr $13,$14,-1,3,2
mttr $13,$14,-1,4,2
mttr $13,$14,-1,5,2
mttr $13,$14,-1,6,2
mttr $13,$14,-1,7,2
mttr $13,$14,0,0,-1
mttr $13,$14,0,1,-1
mttr $13,$14,0,2,-1
mttr $13,$14,0,3,-1
mttr $13,$14,0,4,-1
mttr $13,$14,0,5,-1
mttr $13,$14,0,6,-1
mttr $13,$14,0,7,-1
mttr $13,$14,0,0,0
mttr $13,$14,0,1,0
mttr $13,$14,0,2,0
mttr $13,$14,0,3,0
mttr $13,$14,0,4,0
mttr $13,$14,0,5,0
mttr $13,$14,0,6,0
mttr $13,$14,0,7,0
mttr $13,$14,0,0,1
mttr $13,$14,0,1,1
mttr $13,$14,0,2,1
mttr $13,$14,0,3,1
mttr $13,$14,0,4,1
mttr $13,$14,0,5,1
mttr $13,$14,0,6,1
mttr $13,$14,0,7,1
mttr $13,$14,0,0,2
mttr $13,$14,0,1,2
mttr $13,$14,0,2,2
mttr $13,$14,0,3,2
mttr $13,$14,0,4,2
mttr $13,$14,0,5,2
mttr $13,$14,0,6,2
mttr $13,$14,0,7,2
mttr $13,$14,1,0,-1
mttr $13,$14,1,1,-1
mttr $13,$14,1,2,-1
mttr $13,$14,1,3,-1
mttr $13,$14,1,4,-1
mttr $13,$14,1,5,-1
mttr $13,$14,1,6,-1
mttr $13,$14,1,7,-1
mttr $13,$14,1,0,0
mttr $13,$14,1,1,0
mttr $13,$14,1,2,0
mttr $13,$14,1,3,0
mttr $13,$14,1,4,0
mttr $13,$14,1,5,0
mttr $13,$14,1,6,0
mttr $13,$14,1,7,0
mttr $13,$14,1,0,1
mttr $13,$14,1,1,1
mttr $13,$14,1,2,1
mttr $13,$14,1,3,1
mttr $13,$14,1,4,1
mttr $13,$14,1,5,1
mttr $13,$14,1,6,1
mttr $13,$14,1,7,1
mttr $13,$14,1,0,2
mttr $13,$14,1,1,2
mttr $13,$14,1,2,2
mttr $13,$14,1,3,2
mttr $13,$14,1,4,2
mttr $13,$14,1,5,2
mttr $13,$14,1,6,2
mttr $13,$14,1,7,2
mttr $13,$14,2,0,-1
mttr $13,$14,2,1,-1
mttr $13,$14,2,2,-1
mttr $13,$14,2,3,-1
mttr $13,$14,2,4,-1
mttr $13,$14,2,5,-1
mttr $13,$14,2,6,-1
mttr $13,$14,2,7,-1
mttr $13,$14,2,0,0
mttr $13,$14,2,1,0
mttr $13,$14,2,2,0
mttr $13,$14,2,3,0
mttr $13,$14,2,4,0
mttr $13,$14,2,5,0
mttr $13,$14,2,6,0
mttr $13,$14,2,7,0
mttr $13,$14,2,0,1
mttr $13,$14,2,1,1
mttr $13,$14,2,2,1
mttr $13,$14,2,3,1
mttr $13,$14,2,4,1
mttr $13,$14,2,5,1
mttr $13,$14,2,6,1
mttr $13,$14,2,7,1
mttr $13,$14,2,0,2
mttr $13,$14,2,1,2
mttr $13,$14,2,2,2
mttr $13,$14,2,3,2
mttr $13,$14,2,4,2
mttr $13,$14,2,5,2
mttr $13,$14,2,6,2
mttr $13,$14,2,7,2
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8
[-- Attachment #4: mips32-mt.l --]
[-- Type: application/octet-stream, Size: 15257 bytes --]
.*: Assembler messages:
.*:568: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:568: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:569: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:569: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:570: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:570: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:571: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:571: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:572: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:572: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:573: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:573: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:574: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:574: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:575: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:575: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:576: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:577: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:578: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:579: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:580: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:581: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:582: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:583: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:584: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:585: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:586: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:587: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:588: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:589: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:590: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:591: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:592: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:592: Warning: MT immediate not in range 0..1 \(2\)
.*:593: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:593: Warning: MT immediate not in range 0..1 \(2\)
.*:594: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:594: Warning: MT immediate not in range 0..1 \(2\)
.*:595: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:595: Warning: MT immediate not in range 0..1 \(2\)
.*:596: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:596: Warning: MT immediate not in range 0..1 \(2\)
.*:597: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:597: Warning: MT immediate not in range 0..1 \(2\)
.*:598: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:598: Warning: MT immediate not in range 0..1 \(2\)
.*:599: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:599: Warning: MT immediate not in range 0..1 \(2\)
.*:600: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:601: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:602: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:603: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:604: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:605: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:606: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:607: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:624: Warning: MT immediate not in range 0..1 \(2\)
.*:625: Warning: MT immediate not in range 0..1 \(2\)
.*:626: Warning: MT immediate not in range 0..1 \(2\)
.*:627: Warning: MT immediate not in range 0..1 \(2\)
.*:628: Warning: MT immediate not in range 0..1 \(2\)
.*:629: Warning: MT immediate not in range 0..1 \(2\)
.*:630: Warning: MT immediate not in range 0..1 \(2\)
.*:631: Warning: MT immediate not in range 0..1 \(2\)
.*:632: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:633: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:634: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:635: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:636: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:637: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:638: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:639: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:656: Warning: MT immediate not in range 0..1 \(2\)
.*:657: Warning: MT immediate not in range 0..1 \(2\)
.*:658: Warning: MT immediate not in range 0..1 \(2\)
.*:659: Warning: MT immediate not in range 0..1 \(2\)
.*:660: Warning: MT immediate not in range 0..1 \(2\)
.*:661: Warning: MT immediate not in range 0..1 \(2\)
.*:662: Warning: MT immediate not in range 0..1 \(2\)
.*:663: Warning: MT immediate not in range 0..1 \(2\)
.*:664: Warning: MT immediate not in range 0..1 \(2\)
.*:664: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:665: Warning: MT immediate not in range 0..1 \(2\)
.*:665: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:666: Warning: MT immediate not in range 0..1 \(2\)
.*:666: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:667: Warning: MT immediate not in range 0..1 \(2\)
.*:667: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:668: Warning: MT immediate not in range 0..1 \(2\)
.*:668: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:669: Warning: MT immediate not in range 0..1 \(2\)
.*:669: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:670: Warning: MT immediate not in range 0..1 \(2\)
.*:670: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:671: Warning: MT immediate not in range 0..1 \(2\)
.*:671: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:672: Warning: MT immediate not in range 0..1 \(2\)
.*:673: Warning: MT immediate not in range 0..1 \(2\)
.*:674: Warning: MT immediate not in range 0..1 \(2\)
.*:675: Warning: MT immediate not in range 0..1 \(2\)
.*:676: Warning: MT immediate not in range 0..1 \(2\)
.*:677: Warning: MT immediate not in range 0..1 \(2\)
.*:678: Warning: MT immediate not in range 0..1 \(2\)
.*:679: Warning: MT immediate not in range 0..1 \(2\)
.*:680: Warning: MT immediate not in range 0..1 \(2\)
.*:681: Warning: MT immediate not in range 0..1 \(2\)
.*:682: Warning: MT immediate not in range 0..1 \(2\)
.*:683: Warning: MT immediate not in range 0..1 \(2\)
.*:684: Warning: MT immediate not in range 0..1 \(2\)
.*:685: Warning: MT immediate not in range 0..1 \(2\)
.*:686: Warning: MT immediate not in range 0..1 \(2\)
.*:687: Warning: MT immediate not in range 0..1 \(2\)
.*:688: Warning: MT immediate not in range 0..1 \(2\)
.*:688: Warning: MT immediate not in range 0..1 \(2\)
.*:689: Warning: MT immediate not in range 0..1 \(2\)
.*:689: Warning: MT immediate not in range 0..1 \(2\)
.*:690: Warning: MT immediate not in range 0..1 \(2\)
.*:690: Warning: MT immediate not in range 0..1 \(2\)
.*:691: Warning: MT immediate not in range 0..1 \(2\)
.*:691: Warning: MT immediate not in range 0..1 \(2\)
.*:692: Warning: MT immediate not in range 0..1 \(2\)
.*:692: Warning: MT immediate not in range 0..1 \(2\)
.*:693: Warning: MT immediate not in range 0..1 \(2\)
.*:693: Warning: MT immediate not in range 0..1 \(2\)
.*:694: Warning: MT immediate not in range 0..1 \(2\)
.*:694: Warning: MT immediate not in range 0..1 \(2\)
.*:695: Warning: MT immediate not in range 0..1 \(2\)
.*:695: Warning: MT immediate not in range 0..1 \(2\)
.*:696: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:696: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:697: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:697: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:698: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:698: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:699: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:699: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:700: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:700: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:701: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:701: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:702: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:702: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:703: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:703: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:704: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:705: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:706: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:707: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:708: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:709: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:710: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:711: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:712: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:713: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:714: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:715: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:716: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:717: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:718: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:719: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:720: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:720: Warning: MT immediate not in range 0..1 \(2\)
.*:721: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:721: Warning: MT immediate not in range 0..1 \(2\)
.*:722: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:722: Warning: MT immediate not in range 0..1 \(2\)
.*:723: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:723: Warning: MT immediate not in range 0..1 \(2\)
.*:724: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:724: Warning: MT immediate not in range 0..1 \(2\)
.*:725: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:725: Warning: MT immediate not in range 0..1 \(2\)
.*:726: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:726: Warning: MT immediate not in range 0..1 \(2\)
.*:727: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:727: Warning: MT immediate not in range 0..1 \(2\)
.*:728: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:729: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:730: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:731: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:732: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:733: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:734: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:735: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:752: Warning: MT immediate not in range 0..1 \(2\)
.*:753: Warning: MT immediate not in range 0..1 \(2\)
.*:754: Warning: MT immediate not in range 0..1 \(2\)
.*:755: Warning: MT immediate not in range 0..1 \(2\)
.*:756: Warning: MT immediate not in range 0..1 \(2\)
.*:757: Warning: MT immediate not in range 0..1 \(2\)
.*:758: Warning: MT immediate not in range 0..1 \(2\)
.*:759: Warning: MT immediate not in range 0..1 \(2\)
.*:760: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:761: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:762: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:763: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:764: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:765: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:766: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:767: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:784: Warning: MT immediate not in range 0..1 \(2\)
.*:785: Warning: MT immediate not in range 0..1 \(2\)
.*:786: Warning: MT immediate not in range 0..1 \(2\)
.*:787: Warning: MT immediate not in range 0..1 \(2\)
.*:788: Warning: MT immediate not in range 0..1 \(2\)
.*:789: Warning: MT immediate not in range 0..1 \(2\)
.*:790: Warning: MT immediate not in range 0..1 \(2\)
.*:791: Warning: MT immediate not in range 0..1 \(2\)
.*:792: Warning: MT immediate not in range 0..1 \(2\)
.*:792: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:793: Warning: MT immediate not in range 0..1 \(2\)
.*:793: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:794: Warning: MT immediate not in range 0..1 \(2\)
.*:794: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:795: Warning: MT immediate not in range 0..1 \(2\)
.*:795: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:796: Warning: MT immediate not in range 0..1 \(2\)
.*:796: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:797: Warning: MT immediate not in range 0..1 \(2\)
.*:797: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:798: Warning: MT immediate not in range 0..1 \(2\)
.*:798: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:799: Warning: MT immediate not in range 0..1 \(2\)
.*:799: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:800: Warning: MT immediate not in range 0..1 \(2\)
.*:801: Warning: MT immediate not in range 0..1 \(2\)
.*:802: Warning: MT immediate not in range 0..1 \(2\)
.*:803: Warning: MT immediate not in range 0..1 \(2\)
.*:804: Warning: MT immediate not in range 0..1 \(2\)
.*:805: Warning: MT immediate not in range 0..1 \(2\)
.*:806: Warning: MT immediate not in range 0..1 \(2\)
.*:807: Warning: MT immediate not in range 0..1 \(2\)
.*:808: Warning: MT immediate not in range 0..1 \(2\)
.*:809: Warning: MT immediate not in range 0..1 \(2\)
.*:810: Warning: MT immediate not in range 0..1 \(2\)
.*:811: Warning: MT immediate not in range 0..1 \(2\)
.*:812: Warning: MT immediate not in range 0..1 \(2\)
.*:813: Warning: MT immediate not in range 0..1 \(2\)
.*:814: Warning: MT immediate not in range 0..1 \(2\)
.*:815: Warning: MT immediate not in range 0..1 \(2\)
.*:816: Warning: MT immediate not in range 0..1 \(2\)
.*:816: Warning: MT immediate not in range 0..1 \(2\)
.*:817: Warning: MT immediate not in range 0..1 \(2\)
.*:817: Warning: MT immediate not in range 0..1 \(2\)
.*:818: Warning: MT immediate not in range 0..1 \(2\)
.*:818: Warning: MT immediate not in range 0..1 \(2\)
.*:819: Warning: MT immediate not in range 0..1 \(2\)
.*:819: Warning: MT immediate not in range 0..1 \(2\)
.*:820: Warning: MT immediate not in range 0..1 \(2\)
.*:820: Warning: MT immediate not in range 0..1 \(2\)
.*:821: Warning: MT immediate not in range 0..1 \(2\)
.*:821: Warning: MT immediate not in range 0..1 \(2\)
.*:822: Warning: MT immediate not in range 0..1 \(2\)
.*:822: Warning: MT immediate not in range 0..1 \(2\)
.*:823: Warning: MT immediate not in range 0..1 \(2\)
.*:823: Warning: MT immediate not in range 0..1 \(2\)
[-- Attachment #5: mips32-mt.d --]
[-- Type: application/octet-stream, Size: 34708 bytes --]
#objdump: -dr --prefix-addresses --show-raw-insn -M cp0-names=mips32
#name: MIPS MT ASE for MIPS32
#as: -mt
#stderr: mips32-mt.l
# Check MIPS MT ASE for MIPS32 Instruction Assembly
.*: +file format .*mips.*
Disassembly of section .text:
0+0000 <[^>]*> 41600bc1 dmt
0+0004 <[^>]*> 41600bc1 dmt
0+0008 <[^>]*> 41600001 dvpe
0+000c <[^>]*> 41610001 dvpe at
0+0010 <[^>]*> 41600be1 emt
0+0014 <[^>]*> 41620be1 emt v0
0+0018 <[^>]*> 41600021 evpe
0+001c <[^>]*> 41630021 evpe v1
0+0020 <[^>]*> 7ca62008 fork a0,a1,a2
0+0024 <[^>]*> 7ca00009 yield a1
0+0028 <[^>]*> 7ce03009 yield a2,a3
0+002c <[^>]*> 41083800 mftc0 a3,c0_badvaddr
0+0030 <[^>]*> 41004000 mftc0 t0,c0_index
0+0034 <[^>]*> 41004001 mftc0 t0,\$0,1
0+0038 <[^>]*> 41004002 mftc0 t0,\$0,2
0+003c <[^>]*> 41004003 mftc0 t0,\$0,3
0+0040 <[^>]*> 41004004 mftc0 t0,\$0,4
0+0044 <[^>]*> 41004005 mftc0 t0,\$0,5
0+0048 <[^>]*> 41004006 mftc0 t0,\$0,6
0+004c <[^>]*> 41004007 mftc0 t0,\$0,7
0+0050 <[^>]*> 41014000 mftc0 t0,c0_random
0+0054 <[^>]*> 41014001 mftc0 t0,\$1,1
0+0058 <[^>]*> 41014002 mftc0 t0,\$1,2
0+005c <[^>]*> 41014003 mftc0 t0,\$1,3
0+0060 <[^>]*> 41014004 mftc0 t0,\$1,4
0+0064 <[^>]*> 41014005 mftc0 t0,\$1,5
0+0068 <[^>]*> 41014006 mftc0 t0,\$1,6
0+006c <[^>]*> 41014007 mftc0 t0,\$1,7
0+0070 <[^>]*> 41024000 mftc0 t0,c0_entrylo0
0+0074 <[^>]*> 41024001 mftc0 t0,\$2,1
0+0078 <[^>]*> 41024002 mftc0 t0,\$2,2
0+007c <[^>]*> 41024003 mftc0 t0,\$2,3
0+0080 <[^>]*> 41024004 mftc0 t0,\$2,4
0+0084 <[^>]*> 41024005 mftc0 t0,\$2,5
0+0088 <[^>]*> 41024006 mftc0 t0,\$2,6
0+008c <[^>]*> 41024007 mftc0 t0,\$2,7
0+0090 <[^>]*> 41034000 mftc0 t0,c0_entrylo1
0+0094 <[^>]*> 41034001 mftc0 t0,\$3,1
0+0098 <[^>]*> 41034002 mftc0 t0,\$3,2
0+009c <[^>]*> 41034003 mftc0 t0,\$3,3
0+00a0 <[^>]*> 41034004 mftc0 t0,\$3,4
0+00a4 <[^>]*> 41034005 mftc0 t0,\$3,5
0+00a8 <[^>]*> 41034006 mftc0 t0,\$3,6
0+00ac <[^>]*> 41034007 mftc0 t0,\$3,7
0+00b0 <[^>]*> 41044000 mftc0 t0,c0_context
0+00b4 <[^>]*> 41044001 mftc0 t0,\$4,1
0+00b8 <[^>]*> 41044002 mftc0 t0,\$4,2
0+00bc <[^>]*> 41044003 mftc0 t0,\$4,3
0+00c0 <[^>]*> 41044004 mftc0 t0,\$4,4
0+00c4 <[^>]*> 41044005 mftc0 t0,\$4,5
0+00c8 <[^>]*> 41044006 mftc0 t0,\$4,6
0+00cc <[^>]*> 41044007 mftc0 t0,\$4,7
0+00d0 <[^>]*> 41054000 mftc0 t0,c0_pagemask
0+00d4 <[^>]*> 41054001 mftc0 t0,\$5,1
0+00d8 <[^>]*> 41054002 mftc0 t0,\$5,2
0+00dc <[^>]*> 41054003 mftc0 t0,\$5,3
0+00e0 <[^>]*> 41054004 mftc0 t0,\$5,4
0+00e4 <[^>]*> 41054005 mftc0 t0,\$5,5
0+00e8 <[^>]*> 41054006 mftc0 t0,\$5,6
0+00ec <[^>]*> 41054007 mftc0 t0,\$5,7
0+00f0 <[^>]*> 41064000 mftc0 t0,c0_wired
0+00f4 <[^>]*> 41064001 mftc0 t0,\$6,1
0+00f8 <[^>]*> 41064002 mftc0 t0,\$6,2
0+00fc <[^>]*> 41064003 mftc0 t0,\$6,3
0+0100 <[^>]*> 41064004 mftc0 t0,\$6,4
0+0104 <[^>]*> 41064005 mftc0 t0,\$6,5
0+0108 <[^>]*> 41064006 mftc0 t0,\$6,6
0+010c <[^>]*> 41064007 mftc0 t0,\$6,7
0+0110 <[^>]*> 41074000 mftc0 t0,\$7
0+0114 <[^>]*> 41074001 mftc0 t0,\$7,1
0+0118 <[^>]*> 41074002 mftc0 t0,\$7,2
0+011c <[^>]*> 41074003 mftc0 t0,\$7,3
0+0120 <[^>]*> 41074004 mftc0 t0,\$7,4
0+0124 <[^>]*> 41074005 mftc0 t0,\$7,5
0+0128 <[^>]*> 41074006 mftc0 t0,\$7,6
0+012c <[^>]*> 41074007 mftc0 t0,\$7,7
0+0130 <[^>]*> 41084000 mftc0 t0,c0_badvaddr
0+0134 <[^>]*> 41084001 mftc0 t0,\$8,1
0+0138 <[^>]*> 41084002 mftc0 t0,\$8,2
0+013c <[^>]*> 41084003 mftc0 t0,\$8,3
0+0140 <[^>]*> 41084004 mftc0 t0,\$8,4
0+0144 <[^>]*> 41084005 mftc0 t0,\$8,5
0+0148 <[^>]*> 41084006 mftc0 t0,\$8,6
0+014c <[^>]*> 41084007 mftc0 t0,\$8,7
0+0150 <[^>]*> 41094000 mftc0 t0,c0_count
0+0154 <[^>]*> 41094001 mftc0 t0,\$9,1
0+0158 <[^>]*> 41094002 mftc0 t0,\$9,2
0+015c <[^>]*> 41094003 mftc0 t0,\$9,3
0+0160 <[^>]*> 41094004 mftc0 t0,\$9,4
0+0164 <[^>]*> 41094005 mftc0 t0,\$9,5
0+0168 <[^>]*> 41094006 mftc0 t0,\$9,6
0+016c <[^>]*> 41094007 mftc0 t0,\$9,7
0+0170 <[^>]*> 410a4000 mftc0 t0,c0_entryhi
0+0174 <[^>]*> 410a4001 mftc0 t0,\$10,1
0+0178 <[^>]*> 410a4002 mftc0 t0,\$10,2
0+017c <[^>]*> 410a4003 mftc0 t0,\$10,3
0+0180 <[^>]*> 410a4004 mftc0 t0,\$10,4
0+0184 <[^>]*> 410a4005 mftc0 t0,\$10,5
0+0188 <[^>]*> 410a4006 mftc0 t0,\$10,6
0+018c <[^>]*> 410a4007 mftc0 t0,\$10,7
0+0190 <[^>]*> 410b4000 mftc0 t0,c0_compare
0+0194 <[^>]*> 410b4001 mftc0 t0,\$11,1
0+0198 <[^>]*> 410b4002 mftc0 t0,\$11,2
0+019c <[^>]*> 410b4003 mftc0 t0,\$11,3
0+01a0 <[^>]*> 410b4004 mftc0 t0,\$11,4
0+01a4 <[^>]*> 410b4005 mftc0 t0,\$11,5
0+01a8 <[^>]*> 410b4006 mftc0 t0,\$11,6
0+01ac <[^>]*> 410b4007 mftc0 t0,\$11,7
0+01b0 <[^>]*> 410c4000 mftc0 t0,c0_status
0+01b4 <[^>]*> 410c4001 mftc0 t0,\$12,1
0+01b8 <[^>]*> 410c4002 mftc0 t0,\$12,2
0+01bc <[^>]*> 410c4003 mftc0 t0,\$12,3
0+01c0 <[^>]*> 410c4004 mftc0 t0,\$12,4
0+01c4 <[^>]*> 410c4005 mftc0 t0,\$12,5
0+01c8 <[^>]*> 410c4006 mftc0 t0,\$12,6
0+01cc <[^>]*> 410c4007 mftc0 t0,\$12,7
0+01d0 <[^>]*> 410d4000 mftc0 t0,c0_cause
0+01d4 <[^>]*> 410d4001 mftc0 t0,\$13,1
0+01d8 <[^>]*> 410d4002 mftc0 t0,\$13,2
0+01dc <[^>]*> 410d4003 mftc0 t0,\$13,3
0+01e0 <[^>]*> 410d4004 mftc0 t0,\$13,4
0+01e4 <[^>]*> 410d4005 mftc0 t0,\$13,5
0+01e8 <[^>]*> 410d4006 mftc0 t0,\$13,6
0+01ec <[^>]*> 410d4007 mftc0 t0,\$13,7
0+01f0 <[^>]*> 410e4000 mftc0 t0,c0_epc
0+01f4 <[^>]*> 410e4001 mftc0 t0,\$14,1
0+01f8 <[^>]*> 410e4002 mftc0 t0,\$14,2
0+01fc <[^>]*> 410e4003 mftc0 t0,\$14,3
0+0200 <[^>]*> 410e4004 mftc0 t0,\$14,4
0+0204 <[^>]*> 410e4005 mftc0 t0,\$14,5
0+0208 <[^>]*> 410e4006 mftc0 t0,\$14,6
0+020c <[^>]*> 410e4007 mftc0 t0,\$14,7
0+0210 <[^>]*> 410f4000 mftc0 t0,c0_prid
0+0214 <[^>]*> 410f4001 mftc0 t0,\$15,1
0+0218 <[^>]*> 410f4002 mftc0 t0,\$15,2
0+021c <[^>]*> 410f4003 mftc0 t0,\$15,3
0+0220 <[^>]*> 410f4004 mftc0 t0,\$15,4
0+0224 <[^>]*> 410f4005 mftc0 t0,\$15,5
0+0228 <[^>]*> 410f4006 mftc0 t0,\$15,6
0+022c <[^>]*> 410f4007 mftc0 t0,\$15,7
0+0230 <[^>]*> 41104000 mftc0 t0,c0_config
0+0234 <[^>]*> 41104001 mftc0 t0,c0_config1
0+0238 <[^>]*> 41104002 mftc0 t0,c0_config2
0+023c <[^>]*> 41104003 mftc0 t0,c0_config3
0+0240 <[^>]*> 41104004 mftc0 t0,\$16,4
0+0244 <[^>]*> 41104005 mftc0 t0,\$16,5
0+0248 <[^>]*> 41104006 mftc0 t0,\$16,6
0+024c <[^>]*> 41104007 mftc0 t0,\$16,7
0+0250 <[^>]*> 41114000 mftc0 t0,c0_lladdr
0+0254 <[^>]*> 41114001 mftc0 t0,\$17,1
0+0258 <[^>]*> 41114002 mftc0 t0,\$17,2
0+025c <[^>]*> 41114003 mftc0 t0,\$17,3
0+0260 <[^>]*> 41114004 mftc0 t0,\$17,4
0+0264 <[^>]*> 41114005 mftc0 t0,\$17,5
0+0268 <[^>]*> 41114006 mftc0 t0,\$17,6
0+026c <[^>]*> 41114007 mftc0 t0,\$17,7
0+0270 <[^>]*> 41124000 mftc0 t0,c0_watchlo
0+0274 <[^>]*> 41124001 mftc0 t0,c0_watchlo,1
0+0278 <[^>]*> 41124002 mftc0 t0,c0_watchlo,2
0+027c <[^>]*> 41124003 mftc0 t0,c0_watchlo,3
0+0280 <[^>]*> 41124004 mftc0 t0,c0_watchlo,4
0+0284 <[^>]*> 41124005 mftc0 t0,c0_watchlo,5
0+0288 <[^>]*> 41124006 mftc0 t0,c0_watchlo,6
0+028c <[^>]*> 41124007 mftc0 t0,c0_watchlo,7
0+0290 <[^>]*> 41134000 mftc0 t0,c0_watchhi
0+0294 <[^>]*> 41134001 mftc0 t0,c0_watchhi,1
0+0298 <[^>]*> 41134002 mftc0 t0,c0_watchhi,2
0+029c <[^>]*> 41134003 mftc0 t0,c0_watchhi,3
0+02a0 <[^>]*> 41134004 mftc0 t0,c0_watchhi,4
0+02a4 <[^>]*> 41134005 mftc0 t0,c0_watchhi,5
0+02a8 <[^>]*> 41134006 mftc0 t0,c0_watchhi,6
0+02ac <[^>]*> 41134007 mftc0 t0,c0_watchhi,7
0+02b0 <[^>]*> 41144000 mftc0 t0,c0_xcontext
0+02b4 <[^>]*> 41144001 mftc0 t0,\$20,1
0+02b8 <[^>]*> 41144002 mftc0 t0,\$20,2
0+02bc <[^>]*> 41144003 mftc0 t0,\$20,3
0+02c0 <[^>]*> 41144004 mftc0 t0,\$20,4
0+02c4 <[^>]*> 41144005 mftc0 t0,\$20,5
0+02c8 <[^>]*> 41144006 mftc0 t0,\$20,6
0+02cc <[^>]*> 41144007 mftc0 t0,\$20,7
0+02d0 <[^>]*> 41154000 mftc0 t0,\$21
0+02d4 <[^>]*> 41154001 mftc0 t0,\$21,1
0+02d8 <[^>]*> 41154002 mftc0 t0,\$21,2
0+02dc <[^>]*> 41154003 mftc0 t0,\$21,3
0+02e0 <[^>]*> 41154004 mftc0 t0,\$21,4
0+02e4 <[^>]*> 41154005 mftc0 t0,\$21,5
0+02e8 <[^>]*> 41154006 mftc0 t0,\$21,6
0+02ec <[^>]*> 41154007 mftc0 t0,\$21,7
0+02f0 <[^>]*> 41164000 mftc0 t0,\$22
0+02f4 <[^>]*> 41164001 mftc0 t0,\$22,1
0+02f8 <[^>]*> 41164002 mftc0 t0,\$22,2
0+02fc <[^>]*> 41164003 mftc0 t0,\$22,3
0+0300 <[^>]*> 41164004 mftc0 t0,\$22,4
0+0304 <[^>]*> 41164005 mftc0 t0,\$22,5
0+0308 <[^>]*> 41164006 mftc0 t0,\$22,6
0+030c <[^>]*> 41164007 mftc0 t0,\$22,7
0+0310 <[^>]*> 41174000 mftc0 t0,c0_debug
0+0314 <[^>]*> 41174001 mftc0 t0,\$23,1
0+0318 <[^>]*> 41174002 mftc0 t0,\$23,2
0+031c <[^>]*> 41174003 mftc0 t0,\$23,3
0+0320 <[^>]*> 41174004 mftc0 t0,\$23,4
0+0324 <[^>]*> 41174005 mftc0 t0,\$23,5
0+0328 <[^>]*> 41174006 mftc0 t0,\$23,6
0+032c <[^>]*> 41174007 mftc0 t0,\$23,7
0+0330 <[^>]*> 41184000 mftc0 t0,c0_depc
0+0334 <[^>]*> 41184001 mftc0 t0,\$24,1
0+0338 <[^>]*> 41184002 mftc0 t0,\$24,2
0+033c <[^>]*> 41184003 mftc0 t0,\$24,3
0+0340 <[^>]*> 41184004 mftc0 t0,\$24,4
0+0344 <[^>]*> 41184005 mftc0 t0,\$24,5
0+0348 <[^>]*> 41184006 mftc0 t0,\$24,6
0+034c <[^>]*> 41184007 mftc0 t0,\$24,7
0+0350 <[^>]*> 41194000 mftc0 t0,c0_perfcnt
0+0354 <[^>]*> 41194001 mftc0 t0,c0_perfcnt,1
0+0358 <[^>]*> 41194002 mftc0 t0,c0_perfcnt,2
0+035c <[^>]*> 41194003 mftc0 t0,c0_perfcnt,3
0+0360 <[^>]*> 41194004 mftc0 t0,c0_perfcnt,4
0+0364 <[^>]*> 41194005 mftc0 t0,c0_perfcnt,5
0+0368 <[^>]*> 41194006 mftc0 t0,c0_perfcnt,6
0+036c <[^>]*> 41194007 mftc0 t0,c0_perfcnt,7
0+0370 <[^>]*> 411a4000 mftc0 t0,c0_errctl
0+0374 <[^>]*> 411a4001 mftc0 t0,\$26,1
0+0378 <[^>]*> 411a4002 mftc0 t0,\$26,2
0+037c <[^>]*> 411a4003 mftc0 t0,\$26,3
0+0380 <[^>]*> 411a4004 mftc0 t0,\$26,4
0+0384 <[^>]*> 411a4005 mftc0 t0,\$26,5
0+0388 <[^>]*> 411a4006 mftc0 t0,\$26,6
0+038c <[^>]*> 411a4007 mftc0 t0,\$26,7
0+0390 <[^>]*> 411b4000 mftc0 t0,c0_cacheerr
0+0394 <[^>]*> 411b4001 mftc0 t0,c0_cacheerr,1
0+0398 <[^>]*> 411b4002 mftc0 t0,c0_cacheerr,2
0+039c <[^>]*> 411b4003 mftc0 t0,c0_cacheerr,3
0+03a0 <[^>]*> 411b4004 mftc0 t0,\$27,4
0+03a4 <[^>]*> 411b4005 mftc0 t0,\$27,5
0+03a8 <[^>]*> 411b4006 mftc0 t0,\$27,6
0+03ac <[^>]*> 411b4007 mftc0 t0,\$27,7
0+03b0 <[^>]*> 411c4000 mftc0 t0,c0_taglo
0+03b4 <[^>]*> 411c4001 mftc0 t0,c0_datalo
0+03b8 <[^>]*> 411c4002 mftc0 t0,\$28,2
0+03bc <[^>]*> 411c4003 mftc0 t0,\$28,3
0+03c0 <[^>]*> 411c4004 mftc0 t0,\$28,4
0+03c4 <[^>]*> 411c4005 mftc0 t0,\$28,5
0+03c8 <[^>]*> 411c4006 mftc0 t0,\$28,6
0+03cc <[^>]*> 411c4007 mftc0 t0,\$28,7
0+03d0 <[^>]*> 411d4000 mftc0 t0,c0_taghi
0+03d4 <[^>]*> 411d4001 mftc0 t0,c0_datahi
0+03d8 <[^>]*> 411d4002 mftc0 t0,\$29,2
0+03dc <[^>]*> 411d4003 mftc0 t0,\$29,3
0+03e0 <[^>]*> 411d4004 mftc0 t0,\$29,4
0+03e4 <[^>]*> 411d4005 mftc0 t0,\$29,5
0+03e8 <[^>]*> 411d4006 mftc0 t0,\$29,6
0+03ec <[^>]*> 411d4007 mftc0 t0,\$29,7
0+03f0 <[^>]*> 411e4000 mftc0 t0,c0_errorepc
0+03f4 <[^>]*> 411e4001 mftc0 t0,\$30,1
0+03f8 <[^>]*> 411e4002 mftc0 t0,\$30,2
0+03fc <[^>]*> 411e4003 mftc0 t0,\$30,3
0+0400 <[^>]*> 411e4004 mftc0 t0,\$30,4
0+0404 <[^>]*> 411e4005 mftc0 t0,\$30,5
0+0408 <[^>]*> 411e4006 mftc0 t0,\$30,6
0+040c <[^>]*> 411e4007 mftc0 t0,\$30,7
0+0410 <[^>]*> 411f4000 mftc0 t0,c0_desave
0+0414 <[^>]*> 411f4001 mftc0 t0,\$31,1
0+0418 <[^>]*> 411f4002 mftc0 t0,\$31,2
0+041c <[^>]*> 411f4003 mftc0 t0,\$31,3
0+0420 <[^>]*> 411f4004 mftc0 t0,\$31,4
0+0424 <[^>]*> 411f4005 mftc0 t0,\$31,5
0+0428 <[^>]*> 411f4006 mftc0 t0,\$31,6
0+042c <[^>]*> 411f4007 mftc0 t0,\$31,7
0+0430 <[^>]*> 410a4820 mftgpr t1,t2
0+0434 <[^>]*> 41005021 mftlo t2
0+0438 <[^>]*> 41005821 mftlo t3
0+043c <[^>]*> 41016021 mfthi t4
0+0440 <[^>]*> 41056821 mfthi t5,\$ac1
0+0444 <[^>]*> 41027021 mftacx t6
0+0448 <[^>]*> 410a7821 mftacx t7,\$ac2
0+044c <[^>]*> 41108021 mftdsp s0
0+0450 <[^>]*> 41128822 mftc1 s1,\$f18
0+0454 <[^>]*> 41139022 mftc1 s2,\$f19
0+0458 <[^>]*> 41149832 mfthc1 s3,\$f20
0+045c <[^>]*> 4116a032 mfthc1 s4,\$f22
0+0460 <[^>]*> 4116a823 cftc1 s5,\$22
0+0464 <[^>]*> 4117b023 cftc1 s6,\$23
0+0468 <[^>]*> 4118b824 mftc2 s7,\$24
0+046c <[^>]*> 4119c034 mfthc2 t8,\$25
0+0470 <[^>]*> 411ac825 cftc2 t9,\$26
0+0474 <[^>]*> 419ad800 mttc0 k0,c0_cacheerr
0+0478 <[^>]*> 419b0000 mttc0 k1,c0_index
0+047c <[^>]*> 419b0001 mttc0 k1,\$0,1
0+0480 <[^>]*> 419b0002 mttc0 k1,\$0,2
0+0484 <[^>]*> 419b0003 mttc0 k1,\$0,3
0+0488 <[^>]*> 419b0004 mttc0 k1,\$0,4
0+048c <[^>]*> 419b0005 mttc0 k1,\$0,5
0+0490 <[^>]*> 419b0006 mttc0 k1,\$0,6
0+0494 <[^>]*> 419b0007 mttc0 k1,\$0,7
0+0498 <[^>]*> 419b0800 mttc0 k1,c0_random
0+049c <[^>]*> 419b0801 mttc0 k1,\$1,1
0+04a0 <[^>]*> 419b0802 mttc0 k1,\$1,2
0+04a4 <[^>]*> 419b0803 mttc0 k1,\$1,3
0+04a8 <[^>]*> 419b0804 mttc0 k1,\$1,4
0+04ac <[^>]*> 419b0805 mttc0 k1,\$1,5
0+04b0 <[^>]*> 419b0806 mttc0 k1,\$1,6
0+04b4 <[^>]*> 419b0807 mttc0 k1,\$1,7
0+04b8 <[^>]*> 419b1000 mttc0 k1,c0_entrylo0
0+04bc <[^>]*> 419b1001 mttc0 k1,\$2,1
0+04c0 <[^>]*> 419b1002 mttc0 k1,\$2,2
0+04c4 <[^>]*> 419b1003 mttc0 k1,\$2,3
0+04c8 <[^>]*> 419b1004 mttc0 k1,\$2,4
0+04cc <[^>]*> 419b1005 mttc0 k1,\$2,5
0+04d0 <[^>]*> 419b1006 mttc0 k1,\$2,6
0+04d4 <[^>]*> 419b1007 mttc0 k1,\$2,7
0+04d8 <[^>]*> 419b1800 mttc0 k1,c0_entrylo1
0+04dc <[^>]*> 419b1801 mttc0 k1,\$3,1
0+04e0 <[^>]*> 419b1802 mttc0 k1,\$3,2
0+04e4 <[^>]*> 419b1803 mttc0 k1,\$3,3
0+04e8 <[^>]*> 419b1804 mttc0 k1,\$3,4
0+04ec <[^>]*> 419b1805 mttc0 k1,\$3,5
0+04f0 <[^>]*> 419b1806 mttc0 k1,\$3,6
0+04f4 <[^>]*> 419b1807 mttc0 k1,\$3,7
0+04f8 <[^>]*> 419b2000 mttc0 k1,c0_context
0+04fc <[^>]*> 419b2001 mttc0 k1,\$4,1
0+0500 <[^>]*> 419b2002 mttc0 k1,\$4,2
0+0504 <[^>]*> 419b2003 mttc0 k1,\$4,3
0+0508 <[^>]*> 419b2004 mttc0 k1,\$4,4
0+050c <[^>]*> 419b2005 mttc0 k1,\$4,5
0+0510 <[^>]*> 419b2006 mttc0 k1,\$4,6
0+0514 <[^>]*> 419b2007 mttc0 k1,\$4,7
0+0518 <[^>]*> 419b2800 mttc0 k1,c0_pagemask
0+051c <[^>]*> 419b2801 mttc0 k1,\$5,1
0+0520 <[^>]*> 419b2802 mttc0 k1,\$5,2
0+0524 <[^>]*> 419b2803 mttc0 k1,\$5,3
0+0528 <[^>]*> 419b2804 mttc0 k1,\$5,4
0+052c <[^>]*> 419b2805 mttc0 k1,\$5,5
0+0530 <[^>]*> 419b2806 mttc0 k1,\$5,6
0+0534 <[^>]*> 419b2807 mttc0 k1,\$5,7
0+0538 <[^>]*> 419b3000 mttc0 k1,c0_wired
0+053c <[^>]*> 419b3001 mttc0 k1,\$6,1
0+0540 <[^>]*> 419b3002 mttc0 k1,\$6,2
0+0544 <[^>]*> 419b3003 mttc0 k1,\$6,3
0+0548 <[^>]*> 419b3004 mttc0 k1,\$6,4
0+054c <[^>]*> 419b3005 mttc0 k1,\$6,5
0+0550 <[^>]*> 419b3006 mttc0 k1,\$6,6
0+0554 <[^>]*> 419b3007 mttc0 k1,\$6,7
0+0558 <[^>]*> 419b3800 mttc0 k1,\$7
0+055c <[^>]*> 419b3801 mttc0 k1,\$7,1
0+0560 <[^>]*> 419b3802 mttc0 k1,\$7,2
0+0564 <[^>]*> 419b3803 mttc0 k1,\$7,3
0+0568 <[^>]*> 419b3804 mttc0 k1,\$7,4
0+056c <[^>]*> 419b3805 mttc0 k1,\$7,5
0+0570 <[^>]*> 419b3806 mttc0 k1,\$7,6
0+0574 <[^>]*> 419b3807 mttc0 k1,\$7,7
0+0578 <[^>]*> 419b4000 mttc0 k1,c0_badvaddr
0+057c <[^>]*> 419b4001 mttc0 k1,\$8,1
0+0580 <[^>]*> 419b4002 mttc0 k1,\$8,2
0+0584 <[^>]*> 419b4003 mttc0 k1,\$8,3
0+0588 <[^>]*> 419b4004 mttc0 k1,\$8,4
0+058c <[^>]*> 419b4005 mttc0 k1,\$8,5
0+0590 <[^>]*> 419b4006 mttc0 k1,\$8,6
0+0594 <[^>]*> 419b4007 mttc0 k1,\$8,7
0+0598 <[^>]*> 419b4800 mttc0 k1,c0_count
0+059c <[^>]*> 419b4801 mttc0 k1,\$9,1
0+05a0 <[^>]*> 419b4802 mttc0 k1,\$9,2
0+05a4 <[^>]*> 419b4803 mttc0 k1,\$9,3
0+05a8 <[^>]*> 419b4804 mttc0 k1,\$9,4
0+05ac <[^>]*> 419b4805 mttc0 k1,\$9,5
0+05b0 <[^>]*> 419b4806 mttc0 k1,\$9,6
0+05b4 <[^>]*> 419b4807 mttc0 k1,\$9,7
0+05b8 <[^>]*> 419b5000 mttc0 k1,c0_entryhi
0+05bc <[^>]*> 419b5001 mttc0 k1,\$10,1
0+05c0 <[^>]*> 419b5002 mttc0 k1,\$10,2
0+05c4 <[^>]*> 419b5003 mttc0 k1,\$10,3
0+05c8 <[^>]*> 419b5004 mttc0 k1,\$10,4
0+05cc <[^>]*> 419b5005 mttc0 k1,\$10,5
0+05d0 <[^>]*> 419b5006 mttc0 k1,\$10,6
0+05d4 <[^>]*> 419b5007 mttc0 k1,\$10,7
0+05d8 <[^>]*> 419b5800 mttc0 k1,c0_compare
0+05dc <[^>]*> 419b5801 mttc0 k1,\$11,1
0+05e0 <[^>]*> 419b5802 mttc0 k1,\$11,2
0+05e4 <[^>]*> 419b5803 mttc0 k1,\$11,3
0+05e8 <[^>]*> 419b5804 mttc0 k1,\$11,4
0+05ec <[^>]*> 419b5805 mttc0 k1,\$11,5
0+05f0 <[^>]*> 419b5806 mttc0 k1,\$11,6
0+05f4 <[^>]*> 419b5807 mttc0 k1,\$11,7
0+05f8 <[^>]*> 419b6000 mttc0 k1,c0_status
0+05fc <[^>]*> 419b6001 mttc0 k1,\$12,1
0+0600 <[^>]*> 419b6002 mttc0 k1,\$12,2
0+0604 <[^>]*> 419b6003 mttc0 k1,\$12,3
0+0608 <[^>]*> 419b6004 mttc0 k1,\$12,4
0+060c <[^>]*> 419b6005 mttc0 k1,\$12,5
0+0610 <[^>]*> 419b6006 mttc0 k1,\$12,6
0+0614 <[^>]*> 419b6007 mttc0 k1,\$12,7
0+0618 <[^>]*> 419b6800 mttc0 k1,c0_cause
0+061c <[^>]*> 419b6801 mttc0 k1,\$13,1
0+0620 <[^>]*> 419b6802 mttc0 k1,\$13,2
0+0624 <[^>]*> 419b6803 mttc0 k1,\$13,3
0+0628 <[^>]*> 419b6804 mttc0 k1,\$13,4
0+062c <[^>]*> 419b6805 mttc0 k1,\$13,5
0+0630 <[^>]*> 419b6806 mttc0 k1,\$13,6
0+0634 <[^>]*> 419b6807 mttc0 k1,\$13,7
0+0638 <[^>]*> 419b7000 mttc0 k1,c0_epc
0+063c <[^>]*> 419b7001 mttc0 k1,\$14,1
0+0640 <[^>]*> 419b7002 mttc0 k1,\$14,2
0+0644 <[^>]*> 419b7003 mttc0 k1,\$14,3
0+0648 <[^>]*> 419b7004 mttc0 k1,\$14,4
0+064c <[^>]*> 419b7005 mttc0 k1,\$14,5
0+0650 <[^>]*> 419b7006 mttc0 k1,\$14,6
0+0654 <[^>]*> 419b7007 mttc0 k1,\$14,7
0+0658 <[^>]*> 419b7800 mttc0 k1,c0_prid
0+065c <[^>]*> 419b7801 mttc0 k1,\$15,1
0+0660 <[^>]*> 419b7802 mttc0 k1,\$15,2
0+0664 <[^>]*> 419b7803 mttc0 k1,\$15,3
0+0668 <[^>]*> 419b7804 mttc0 k1,\$15,4
0+066c <[^>]*> 419b7805 mttc0 k1,\$15,5
0+0670 <[^>]*> 419b7806 mttc0 k1,\$15,6
0+0674 <[^>]*> 419b7807 mttc0 k1,\$15,7
0+0678 <[^>]*> 419b8000 mttc0 k1,c0_config
0+067c <[^>]*> 419b8001 mttc0 k1,c0_config1
0+0680 <[^>]*> 419b8002 mttc0 k1,c0_config2
0+0684 <[^>]*> 419b8003 mttc0 k1,c0_config3
0+0688 <[^>]*> 419b8004 mttc0 k1,\$16,4
0+068c <[^>]*> 419b8005 mttc0 k1,\$16,5
0+0690 <[^>]*> 419b8006 mttc0 k1,\$16,6
0+0694 <[^>]*> 419b8007 mttc0 k1,\$16,7
0+0698 <[^>]*> 419b8800 mttc0 k1,c0_lladdr
0+069c <[^>]*> 419b8801 mttc0 k1,\$17,1
0+06a0 <[^>]*> 419b8802 mttc0 k1,\$17,2
0+06a4 <[^>]*> 419b8803 mttc0 k1,\$17,3
0+06a8 <[^>]*> 419b8804 mttc0 k1,\$17,4
0+06ac <[^>]*> 419b8805 mttc0 k1,\$17,5
0+06b0 <[^>]*> 419b8806 mttc0 k1,\$17,6
0+06b4 <[^>]*> 419b8807 mttc0 k1,\$17,7
0+06b8 <[^>]*> 419b9000 mttc0 k1,c0_watchlo
0+06bc <[^>]*> 419b9001 mttc0 k1,c0_watchlo,1
0+06c0 <[^>]*> 419b9002 mttc0 k1,c0_watchlo,2
0+06c4 <[^>]*> 419b9003 mttc0 k1,c0_watchlo,3
0+06c8 <[^>]*> 419b9004 mttc0 k1,c0_watchlo,4
0+06cc <[^>]*> 419b9005 mttc0 k1,c0_watchlo,5
0+06d0 <[^>]*> 419b9006 mttc0 k1,c0_watchlo,6
0+06d4 <[^>]*> 419b9007 mttc0 k1,c0_watchlo,7
0+06d8 <[^>]*> 419b9800 mttc0 k1,c0_watchhi
0+06dc <[^>]*> 419b9801 mttc0 k1,c0_watchhi,1
0+06e0 <[^>]*> 419b9802 mttc0 k1,c0_watchhi,2
0+06e4 <[^>]*> 419b9803 mttc0 k1,c0_watchhi,3
0+06e8 <[^>]*> 419b9804 mttc0 k1,c0_watchhi,4
0+06ec <[^>]*> 419b9805 mttc0 k1,c0_watchhi,5
0+06f0 <[^>]*> 419b9806 mttc0 k1,c0_watchhi,6
0+06f4 <[^>]*> 419b9807 mttc0 k1,c0_watchhi,7
0+06f8 <[^>]*> 419ba000 mttc0 k1,c0_xcontext
0+06fc <[^>]*> 419ba001 mttc0 k1,\$20,1
0+0700 <[^>]*> 419ba002 mttc0 k1,\$20,2
0+0704 <[^>]*> 419ba003 mttc0 k1,\$20,3
0+0708 <[^>]*> 419ba004 mttc0 k1,\$20,4
0+070c <[^>]*> 419ba005 mttc0 k1,\$20,5
0+0710 <[^>]*> 419ba006 mttc0 k1,\$20,6
0+0714 <[^>]*> 419ba007 mttc0 k1,\$20,7
0+0718 <[^>]*> 419ba800 mttc0 k1,\$21
0+071c <[^>]*> 419ba801 mttc0 k1,\$21,1
0+0720 <[^>]*> 419ba802 mttc0 k1,\$21,2
0+0724 <[^>]*> 419ba803 mttc0 k1,\$21,3
0+0728 <[^>]*> 419ba804 mttc0 k1,\$21,4
0+072c <[^>]*> 419ba805 mttc0 k1,\$21,5
0+0730 <[^>]*> 419ba806 mttc0 k1,\$21,6
0+0734 <[^>]*> 419ba807 mttc0 k1,\$21,7
0+0738 <[^>]*> 419bb000 mttc0 k1,\$22
0+073c <[^>]*> 419bb001 mttc0 k1,\$22,1
0+0740 <[^>]*> 419bb002 mttc0 k1,\$22,2
0+0744 <[^>]*> 419bb003 mttc0 k1,\$22,3
0+0748 <[^>]*> 419bb004 mttc0 k1,\$22,4
0+074c <[^>]*> 419bb005 mttc0 k1,\$22,5
0+0750 <[^>]*> 419bb006 mttc0 k1,\$22,6
0+0754 <[^>]*> 419bb007 mttc0 k1,\$22,7
0+0758 <[^>]*> 419bb800 mttc0 k1,c0_debug
0+075c <[^>]*> 419bb801 mttc0 k1,\$23,1
0+0760 <[^>]*> 419bb802 mttc0 k1,\$23,2
0+0764 <[^>]*> 419bb803 mttc0 k1,\$23,3
0+0768 <[^>]*> 419bb804 mttc0 k1,\$23,4
0+076c <[^>]*> 419bb805 mttc0 k1,\$23,5
0+0770 <[^>]*> 419bb806 mttc0 k1,\$23,6
0+0774 <[^>]*> 419bb807 mttc0 k1,\$23,7
0+0778 <[^>]*> 419bc000 mttc0 k1,c0_depc
0+077c <[^>]*> 419bc001 mttc0 k1,\$24,1
0+0780 <[^>]*> 419bc002 mttc0 k1,\$24,2
0+0784 <[^>]*> 419bc003 mttc0 k1,\$24,3
0+0788 <[^>]*> 419bc004 mttc0 k1,\$24,4
0+078c <[^>]*> 419bc005 mttc0 k1,\$24,5
0+0790 <[^>]*> 419bc006 mttc0 k1,\$24,6
0+0794 <[^>]*> 419bc007 mttc0 k1,\$24,7
0+0798 <[^>]*> 419bc800 mttc0 k1,c0_perfcnt
0+079c <[^>]*> 419bc801 mttc0 k1,c0_perfcnt,1
0+07a0 <[^>]*> 419bc802 mttc0 k1,c0_perfcnt,2
0+07a4 <[^>]*> 419bc803 mttc0 k1,c0_perfcnt,3
0+07a8 <[^>]*> 419bc804 mttc0 k1,c0_perfcnt,4
0+07ac <[^>]*> 419bc805 mttc0 k1,c0_perfcnt,5
0+07b0 <[^>]*> 419bc806 mttc0 k1,c0_perfcnt,6
0+07b4 <[^>]*> 419bc807 mttc0 k1,c0_perfcnt,7
0+07b8 <[^>]*> 419bd000 mttc0 k1,c0_errctl
0+07bc <[^>]*> 419bd001 mttc0 k1,\$26,1
0+07c0 <[^>]*> 419bd002 mttc0 k1,\$26,2
0+07c4 <[^>]*> 419bd003 mttc0 k1,\$26,3
0+07c8 <[^>]*> 419bd004 mttc0 k1,\$26,4
0+07cc <[^>]*> 419bd005 mttc0 k1,\$26,5
0+07d0 <[^>]*> 419bd006 mttc0 k1,\$26,6
0+07d4 <[^>]*> 419bd007 mttc0 k1,\$26,7
0+07d8 <[^>]*> 419bd800 mttc0 k1,c0_cacheerr
0+07dc <[^>]*> 419bd801 mttc0 k1,c0_cacheerr,1
0+07e0 <[^>]*> 419bd802 mttc0 k1,c0_cacheerr,2
0+07e4 <[^>]*> 419bd803 mttc0 k1,c0_cacheerr,3
0+07e8 <[^>]*> 419bd804 mttc0 k1,\$27,4
0+07ec <[^>]*> 419bd805 mttc0 k1,\$27,5
0+07f0 <[^>]*> 419bd806 mttc0 k1,\$27,6
0+07f4 <[^>]*> 419bd807 mttc0 k1,\$27,7
0+07f8 <[^>]*> 419be000 mttc0 k1,c0_taglo
0+07fc <[^>]*> 419be001 mttc0 k1,c0_datalo
0+0800 <[^>]*> 419be002 mttc0 k1,\$28,2
0+0804 <[^>]*> 419be003 mttc0 k1,\$28,3
0+0808 <[^>]*> 419be004 mttc0 k1,\$28,4
0+080c <[^>]*> 419be005 mttc0 k1,\$28,5
0+0810 <[^>]*> 419be006 mttc0 k1,\$28,6
0+0814 <[^>]*> 419be007 mttc0 k1,\$28,7
0+0818 <[^>]*> 419be800 mttc0 k1,c0_taghi
0+081c <[^>]*> 419be801 mttc0 k1,c0_datahi
0+0820 <[^>]*> 419be802 mttc0 k1,\$29,2
0+0824 <[^>]*> 419be803 mttc0 k1,\$29,3
0+0828 <[^>]*> 419be804 mttc0 k1,\$29,4
0+082c <[^>]*> 419be805 mttc0 k1,\$29,5
0+0830 <[^>]*> 419be806 mttc0 k1,\$29,6
0+0834 <[^>]*> 419be807 mttc0 k1,\$29,7
0+0838 <[^>]*> 419bf000 mttc0 k1,c0_errorepc
0+083c <[^>]*> 419bf001 mttc0 k1,\$30,1
0+0840 <[^>]*> 419bf002 mttc0 k1,\$30,2
0+0844 <[^>]*> 419bf003 mttc0 k1,\$30,3
0+0848 <[^>]*> 419bf004 mttc0 k1,\$30,4
0+084c <[^>]*> 419bf005 mttc0 k1,\$30,5
0+0850 <[^>]*> 419bf006 mttc0 k1,\$30,6
0+0854 <[^>]*> 419bf007 mttc0 k1,\$30,7
0+0858 <[^>]*> 419bf800 mttc0 k1,c0_desave
0+085c <[^>]*> 419bf801 mttc0 k1,\$31,1
0+0860 <[^>]*> 419bf802 mttc0 k1,\$31,2
0+0864 <[^>]*> 419bf803 mttc0 k1,\$31,3
0+0868 <[^>]*> 419bf804 mttc0 k1,\$31,4
0+086c <[^>]*> 419bf805 mttc0 k1,\$31,5
0+0870 <[^>]*> 419bf806 mttc0 k1,\$31,6
0+0874 <[^>]*> 419bf807 mttc0 k1,\$31,7
0+0878 <[^>]*> 419ce820 mttgpr gp,sp
0+087c <[^>]*> 419d0021 mttlo sp
0+0880 <[^>]*> 419e6021 mttlo s8,\$ac3
0+0884 <[^>]*> 419f0821 mtthi ra
0+0888 <[^>]*> 41800821 mtthi zero
0+088c <[^>]*> 41811021 mttacx at
0+0890 <[^>]*> 41823021 mttacx v0,\$ac1
0+0894 <[^>]*> 41838021 mttdsp v1
0+0898 <[^>]*> 41842822 mttc1 a0,\$f5
0+089c <[^>]*> 41853022 mttc1 a1,\$f6
0+08a0 <[^>]*> 41864032 mtthc1 a2,\$f8
0+08a4 <[^>]*> 41875032 mtthc1 a3,\$f10
0+08a8 <[^>]*> 41884823 cttc1 t0,\$9
0+08ac <[^>]*> 41895023 cttc1 t1,\$10
0+08b0 <[^>]*> 418a5824 mttc2 t2,\$11
0+08b4 <[^>]*> 418b6034 mtthc2 t3,\$12
0+08b8 <[^>]*> 418c6825 cttc2 t4,\$13
0+08bc <[^>]*> 410d7030 mftr t5,t6,1,0,1
0+08c0 <[^>]*> 410d7031 mftr t5,t6,1,1,1
0+08c4 <[^>]*> 410d7032 mfthc1 t6,\$f13
0+08c8 <[^>]*> 410d7033 mftr t5,t6,1,3,1
0+08cc <[^>]*> 410d7034 mfthc2 t6,\$13
0+08d0 <[^>]*> 410d7035 mftr t5,t6,1,5,1
0+08d4 <[^>]*> 410d7036 mftr t5,t6,1,6,1
0+08d8 <[^>]*> 410d7037 mftr t5,t6,1,7,1
0+08dc <[^>]*> 410d7020 mftgpr t6,t5
0+08e0 <[^>]*> 410d7021 mfthi t6,\$ac3
0+08e4 <[^>]*> 410d7022 mftc1 t6,\$f13
0+08e8 <[^>]*> 410d7023 cftc1 t6,\$13
0+08ec <[^>]*> 410d7024 mftc2 t6,\$13
0+08f0 <[^>]*> 410d7025 cftc2 t6,\$13
0+08f4 <[^>]*> 410d7026 mftr t5,t6,1,6,0
0+08f8 <[^>]*> 410d7027 mftr t5,t6,1,7,0
0+08fc <[^>]*> 410d7030 mftr t5,t6,1,0,1
0+0900 <[^>]*> 410d7031 mftr t5,t6,1,1,1
0+0904 <[^>]*> 410d7032 mfthc1 t6,\$f13
0+0908 <[^>]*> 410d7033 mftr t5,t6,1,3,1
0+090c <[^>]*> 410d7034 mfthc2 t6,\$13
0+0910 <[^>]*> 410d7035 mftr t5,t6,1,5,1
0+0914 <[^>]*> 410d7036 mftr t5,t6,1,6,1
0+0918 <[^>]*> 410d7037 mftr t5,t6,1,7,1
0+091c <[^>]*> 410d7020 mftgpr t6,t5
0+0920 <[^>]*> 410d7021 mfthi t6,\$ac3
0+0924 <[^>]*> 410d7022 mftc1 t6,\$f13
0+0928 <[^>]*> 410d7023 cftc1 t6,\$13
0+092c <[^>]*> 410d7024 mftc2 t6,\$13
0+0930 <[^>]*> 410d7025 cftc2 t6,\$13
0+0934 <[^>]*> 410d7026 mftr t5,t6,1,6,0
0+0938 <[^>]*> 410d7027 mftr t5,t6,1,7,0
0+093c <[^>]*> 410d7010 mftr t5,t6,0,0,1
0+0940 <[^>]*> 410d7011 mftr t5,t6,0,1,1
0+0944 <[^>]*> 410d7012 mftr t5,t6,0,2,1
0+0948 <[^>]*> 410d7013 mftr t5,t6,0,3,1
0+094c <[^>]*> 410d7014 mftr t5,t6,0,4,1
0+0950 <[^>]*> 410d7015 mftr t5,t6,0,5,1
0+0954 <[^>]*> 410d7016 mftr t5,t6,0,6,1
0+0958 <[^>]*> 410d7017 mftr t5,t6,0,7,1
0+095c <[^>]*> 410d7000 mftc0 t6,c0_cause
0+0960 <[^>]*> 410d7001 mftc0 t6,\$13,1
0+0964 <[^>]*> 410d7002 mftc0 t6,\$13,2
0+0968 <[^>]*> 410d7003 mftc0 t6,\$13,3
0+096c <[^>]*> 410d7004 mftc0 t6,\$13,4
0+0970 <[^>]*> 410d7005 mftc0 t6,\$13,5
0+0974 <[^>]*> 410d7006 mftc0 t6,\$13,6
0+0978 <[^>]*> 410d7007 mftc0 t6,\$13,7
0+097c <[^>]*> 410d7010 mftr t5,t6,0,0,1
0+0980 <[^>]*> 410d7011 mftr t5,t6,0,1,1
0+0984 <[^>]*> 410d7012 mftr t5,t6,0,2,1
0+0988 <[^>]*> 410d7013 mftr t5,t6,0,3,1
0+098c <[^>]*> 410d7014 mftr t5,t6,0,4,1
0+0990 <[^>]*> 410d7015 mftr t5,t6,0,5,1
0+0994 <[^>]*> 410d7016 mftr t5,t6,0,6,1
0+0998 <[^>]*> 410d7017 mftr t5,t6,0,7,1
0+099c <[^>]*> 410d7000 mftc0 t6,c0_cause
0+09a0 <[^>]*> 410d7001 mftc0 t6,\$13,1
0+09a4 <[^>]*> 410d7002 mftc0 t6,\$13,2
0+09a8 <[^>]*> 410d7003 mftc0 t6,\$13,3
0+09ac <[^>]*> 410d7004 mftc0 t6,\$13,4
0+09b0 <[^>]*> 410d7005 mftc0 t6,\$13,5
0+09b4 <[^>]*> 410d7006 mftc0 t6,\$13,6
0+09b8 <[^>]*> 410d7007 mftc0 t6,\$13,7
0+09bc <[^>]*> 410d7030 mftr t5,t6,1,0,1
0+09c0 <[^>]*> 410d7031 mftr t5,t6,1,1,1
0+09c4 <[^>]*> 410d7032 mfthc1 t6,\$f13
0+09c8 <[^>]*> 410d7033 mftr t5,t6,1,3,1
0+09cc <[^>]*> 410d7034 mfthc2 t6,\$13
0+09d0 <[^>]*> 410d7035 mftr t5,t6,1,5,1
0+09d4 <[^>]*> 410d7036 mftr t5,t6,1,6,1
0+09d8 <[^>]*> 410d7037 mftr t5,t6,1,7,1
0+09dc <[^>]*> 410d7020 mftgpr t6,t5
0+09e0 <[^>]*> 410d7021 mfthi t6,\$ac3
0+09e4 <[^>]*> 410d7022 mftc1 t6,\$f13
0+09e8 <[^>]*> 410d7023 cftc1 t6,\$13
0+09ec <[^>]*> 410d7024 mftc2 t6,\$13
0+09f0 <[^>]*> 410d7025 cftc2 t6,\$13
0+09f4 <[^>]*> 410d7026 mftr t5,t6,1,6,0
0+09f8 <[^>]*> 410d7027 mftr t5,t6,1,7,0
0+09fc <[^>]*> 410d7030 mftr t5,t6,1,0,1
0+0a00 <[^>]*> 410d7031 mftr t5,t6,1,1,1
0+0a04 <[^>]*> 410d7032 mfthc1 t6,\$f13
0+0a08 <[^>]*> 410d7033 mftr t5,t6,1,3,1
0+0a0c <[^>]*> 410d7034 mfthc2 t6,\$13
0+0a10 <[^>]*> 410d7035 mftr t5,t6,1,5,1
0+0a14 <[^>]*> 410d7036 mftr t5,t6,1,6,1
0+0a18 <[^>]*> 410d7037 mftr t5,t6,1,7,1
0+0a1c <[^>]*> 410d7020 mftgpr t6,t5
0+0a20 <[^>]*> 410d7021 mfthi t6,\$ac3
0+0a24 <[^>]*> 410d7022 mftc1 t6,\$f13
0+0a28 <[^>]*> 410d7023 cftc1 t6,\$13
0+0a2c <[^>]*> 410d7024 mftc2 t6,\$13
0+0a30 <[^>]*> 410d7025 cftc2 t6,\$13
0+0a34 <[^>]*> 410d7026 mftr t5,t6,1,6,0
0+0a38 <[^>]*> 410d7027 mftr t5,t6,1,7,0
0+0a3c <[^>]*> 410d7010 mftr t5,t6,0,0,1
0+0a40 <[^>]*> 410d7011 mftr t5,t6,0,1,1
0+0a44 <[^>]*> 410d7012 mftr t5,t6,0,2,1
0+0a48 <[^>]*> 410d7013 mftr t5,t6,0,3,1
0+0a4c <[^>]*> 410d7014 mftr t5,t6,0,4,1
0+0a50 <[^>]*> 410d7015 mftr t5,t6,0,5,1
0+0a54 <[^>]*> 410d7016 mftr t5,t6,0,6,1
0+0a58 <[^>]*> 410d7017 mftr t5,t6,0,7,1
0+0a5c <[^>]*> 410d7000 mftc0 t6,c0_cause
0+0a60 <[^>]*> 410d7001 mftc0 t6,\$13,1
0+0a64 <[^>]*> 410d7002 mftc0 t6,\$13,2
0+0a68 <[^>]*> 410d7003 mftc0 t6,\$13,3
0+0a6c <[^>]*> 410d7004 mftc0 t6,\$13,4
0+0a70 <[^>]*> 410d7005 mftc0 t6,\$13,5
0+0a74 <[^>]*> 410d7006 mftc0 t6,\$13,6
0+0a78 <[^>]*> 410d7007 mftc0 t6,\$13,7
0+0a7c <[^>]*> 410d7010 mftr t5,t6,0,0,1
0+0a80 <[^>]*> 410d7011 mftr t5,t6,0,1,1
0+0a84 <[^>]*> 410d7012 mftr t5,t6,0,2,1
0+0a88 <[^>]*> 410d7013 mftr t5,t6,0,3,1
0+0a8c <[^>]*> 410d7014 mftr t5,t6,0,4,1
0+0a90 <[^>]*> 410d7015 mftr t5,t6,0,5,1
0+0a94 <[^>]*> 410d7016 mftr t5,t6,0,6,1
0+0a98 <[^>]*> 410d7017 mftr t5,t6,0,7,1
0+0a9c <[^>]*> 410d7000 mftc0 t6,c0_cause
0+0aa0 <[^>]*> 410d7001 mftc0 t6,\$13,1
0+0aa4 <[^>]*> 410d7002 mftc0 t6,\$13,2
0+0aa8 <[^>]*> 410d7003 mftc0 t6,\$13,3
0+0aac <[^>]*> 410d7004 mftc0 t6,\$13,4
0+0ab0 <[^>]*> 410d7005 mftc0 t6,\$13,5
0+0ab4 <[^>]*> 410d7006 mftc0 t6,\$13,6
0+0ab8 <[^>]*> 410d7007 mftc0 t6,\$13,7
0+0abc <[^>]*> 418d7030 mttr t5,t6,1,0,1
0+0ac0 <[^>]*> 418d7031 mttr t5,t6,1,1,1
0+0ac4 <[^>]*> 418d7032 mtthc1 t5,\$f14
0+0ac8 <[^>]*> 418d7033 mttr t5,t6,1,3,1
0+0acc <[^>]*> 418d7034 mtthc2 t5,\$14
0+0ad0 <[^>]*> 418d7035 mttr t5,t6,1,5,1
0+0ad4 <[^>]*> 418d7036 mttr t5,t6,1,6,1
0+0ad8 <[^>]*> 418d7037 mttr t5,t6,1,7,1
0+0adc <[^>]*> 418d7020 mttgpr t5,t6
0+0ae0 <[^>]*> 418d7021 mttacx t5,\$ac3
0+0ae4 <[^>]*> 418d7022 mttc1 t5,\$f14
0+0ae8 <[^>]*> 418d7023 cttc1 t5,\$14
0+0aec <[^>]*> 418d7024 mttc2 t5,\$14
0+0af0 <[^>]*> 418d7025 cttc2 t5,\$14
0+0af4 <[^>]*> 418d7026 mttr t5,t6,1,6,0
0+0af8 <[^>]*> 418d7027 mttr t5,t6,1,7,0
0+0afc <[^>]*> 418d7030 mttr t5,t6,1,0,1
0+0b00 <[^>]*> 418d7031 mttr t5,t6,1,1,1
0+0b04 <[^>]*> 418d7032 mtthc1 t5,\$f14
0+0b08 <[^>]*> 418d7033 mttr t5,t6,1,3,1
0+0b0c <[^>]*> 418d7034 mtthc2 t5,\$14
0+0b10 <[^>]*> 418d7035 mttr t5,t6,1,5,1
0+0b14 <[^>]*> 418d7036 mttr t5,t6,1,6,1
0+0b18 <[^>]*> 418d7037 mttr t5,t6,1,7,1
0+0b1c <[^>]*> 418d7020 mttgpr t5,t6
0+0b20 <[^>]*> 418d7021 mttacx t5,\$ac3
0+0b24 <[^>]*> 418d7022 mttc1 t5,\$f14
0+0b28 <[^>]*> 418d7023 cttc1 t5,\$14
0+0b2c <[^>]*> 418d7024 mttc2 t5,\$14
0+0b30 <[^>]*> 418d7025 cttc2 t5,\$14
0+0b34 <[^>]*> 418d7026 mttr t5,t6,1,6,0
0+0b38 <[^>]*> 418d7027 mttr t5,t6,1,7,0
0+0b3c <[^>]*> 418d7010 mttr t5,t6,0,0,1
0+0b40 <[^>]*> 418d7011 mttr t5,t6,0,1,1
0+0b44 <[^>]*> 418d7012 mttr t5,t6,0,2,1
0+0b48 <[^>]*> 418d7013 mttr t5,t6,0,3,1
0+0b4c <[^>]*> 418d7014 mttr t5,t6,0,4,1
0+0b50 <[^>]*> 418d7015 mttr t5,t6,0,5,1
0+0b54 <[^>]*> 418d7016 mttr t5,t6,0,6,1
0+0b58 <[^>]*> 418d7017 mttr t5,t6,0,7,1
0+0b5c <[^>]*> 418d7000 mttc0 t5,c0_epc
0+0b60 <[^>]*> 418d7001 mttc0 t5,\$14,1
0+0b64 <[^>]*> 418d7002 mttc0 t5,\$14,2
0+0b68 <[^>]*> 418d7003 mttc0 t5,\$14,3
0+0b6c <[^>]*> 418d7004 mttc0 t5,\$14,4
0+0b70 <[^>]*> 418d7005 mttc0 t5,\$14,5
0+0b74 <[^>]*> 418d7006 mttc0 t5,\$14,6
0+0b78 <[^>]*> 418d7007 mttc0 t5,\$14,7
0+0b7c <[^>]*> 418d7010 mttr t5,t6,0,0,1
0+0b80 <[^>]*> 418d7011 mttr t5,t6,0,1,1
0+0b84 <[^>]*> 418d7012 mttr t5,t6,0,2,1
0+0b88 <[^>]*> 418d7013 mttr t5,t6,0,3,1
0+0b8c <[^>]*> 418d7014 mttr t5,t6,0,4,1
0+0b90 <[^>]*> 418d7015 mttr t5,t6,0,5,1
0+0b94 <[^>]*> 418d7016 mttr t5,t6,0,6,1
0+0b98 <[^>]*> 418d7017 mttr t5,t6,0,7,1
0+0b9c <[^>]*> 418d7000 mttc0 t5,c0_epc
0+0ba0 <[^>]*> 418d7001 mttc0 t5,\$14,1
0+0ba4 <[^>]*> 418d7002 mttc0 t5,\$14,2
0+0ba8 <[^>]*> 418d7003 mttc0 t5,\$14,3
0+0bac <[^>]*> 418d7004 mttc0 t5,\$14,4
0+0bb0 <[^>]*> 418d7005 mttc0 t5,\$14,5
0+0bb4 <[^>]*> 418d7006 mttc0 t5,\$14,6
0+0bb8 <[^>]*> 418d7007 mttc0 t5,\$14,7
0+0bbc <[^>]*> 418d7030 mttr t5,t6,1,0,1
0+0bc0 <[^>]*> 418d7031 mttr t5,t6,1,1,1
0+0bc4 <[^>]*> 418d7032 mtthc1 t5,\$f14
0+0bc8 <[^>]*> 418d7033 mttr t5,t6,1,3,1
0+0bcc <[^>]*> 418d7034 mtthc2 t5,\$14
0+0bd0 <[^>]*> 418d7035 mttr t5,t6,1,5,1
0+0bd4 <[^>]*> 418d7036 mttr t5,t6,1,6,1
0+0bd8 <[^>]*> 418d7037 mttr t5,t6,1,7,1
0+0bdc <[^>]*> 418d7020 mttgpr t5,t6
0+0be0 <[^>]*> 418d7021 mttacx t5,\$ac3
0+0be4 <[^>]*> 418d7022 mttc1 t5,\$f14
0+0be8 <[^>]*> 418d7023 cttc1 t5,\$14
0+0bec <[^>]*> 418d7024 mttc2 t5,\$14
0+0bf0 <[^>]*> 418d7025 cttc2 t5,\$14
0+0bf4 <[^>]*> 418d7026 mttr t5,t6,1,6,0
0+0bf8 <[^>]*> 418d7027 mttr t5,t6,1,7,0
0+0bfc <[^>]*> 418d7030 mttr t5,t6,1,0,1
0+0c00 <[^>]*> 418d7031 mttr t5,t6,1,1,1
0+0c04 <[^>]*> 418d7032 mtthc1 t5,\$f14
0+0c08 <[^>]*> 418d7033 mttr t5,t6,1,3,1
0+0c0c <[^>]*> 418d7034 mtthc2 t5,\$14
0+0c10 <[^>]*> 418d7035 mttr t5,t6,1,5,1
0+0c14 <[^>]*> 418d7036 mttr t5,t6,1,6,1
0+0c18 <[^>]*> 418d7037 mttr t5,t6,1,7,1
0+0c1c <[^>]*> 418d7020 mttgpr t5,t6
0+0c20 <[^>]*> 418d7021 mttacx t5,\$ac3
0+0c24 <[^>]*> 418d7022 mttc1 t5,\$f14
0+0c28 <[^>]*> 418d7023 cttc1 t5,\$14
0+0c2c <[^>]*> 418d7024 mttc2 t5,\$14
0+0c30 <[^>]*> 418d7025 cttc2 t5,\$14
0+0c34 <[^>]*> 418d7026 mttr t5,t6,1,6,0
0+0c38 <[^>]*> 418d7027 mttr t5,t6,1,7,0
0+0c3c <[^>]*> 418d7010 mttr t5,t6,0,0,1
0+0c40 <[^>]*> 418d7011 mttr t5,t6,0,1,1
0+0c44 <[^>]*> 418d7012 mttr t5,t6,0,2,1
0+0c48 <[^>]*> 418d7013 mttr t5,t6,0,3,1
0+0c4c <[^>]*> 418d7014 mttr t5,t6,0,4,1
0+0c50 <[^>]*> 418d7015 mttr t5,t6,0,5,1
0+0c54 <[^>]*> 418d7016 mttr t5,t6,0,6,1
0+0c58 <[^>]*> 418d7017 mttr t5,t6,0,7,1
0+0c5c <[^>]*> 418d7000 mttc0 t5,c0_epc
0+0c60 <[^>]*> 418d7001 mttc0 t5,\$14,1
0+0c64 <[^>]*> 418d7002 mttc0 t5,\$14,2
0+0c68 <[^>]*> 418d7003 mttc0 t5,\$14,3
0+0c6c <[^>]*> 418d7004 mttc0 t5,\$14,4
0+0c70 <[^>]*> 418d7005 mttc0 t5,\$14,5
0+0c74 <[^>]*> 418d7006 mttc0 t5,\$14,6
0+0c78 <[^>]*> 418d7007 mttc0 t5,\$14,7
0+0c7c <[^>]*> 418d7010 mttr t5,t6,0,0,1
0+0c80 <[^>]*> 418d7011 mttr t5,t6,0,1,1
0+0c84 <[^>]*> 418d7012 mttr t5,t6,0,2,1
0+0c88 <[^>]*> 418d7013 mttr t5,t6,0,3,1
0+0c8c <[^>]*> 418d7014 mttr t5,t6,0,4,1
0+0c90 <[^>]*> 418d7015 mttr t5,t6,0,5,1
0+0c94 <[^>]*> 418d7016 mttr t5,t6,0,6,1
0+0c98 <[^>]*> 418d7017 mttr t5,t6,0,7,1
0+0c9c <[^>]*> 418d7000 mttc0 t5,c0_epc
0+0ca0 <[^>]*> 418d7001 mttc0 t5,\$14,1
0+0ca4 <[^>]*> 418d7002 mttc0 t5,\$14,2
0+0ca8 <[^>]*> 418d7003 mttc0 t5,\$14,3
0+0cac <[^>]*> 418d7004 mttc0 t5,\$14,4
0+0cb0 <[^>]*> 418d7005 mttc0 t5,\$14,5
0+0cb4 <[^>]*> 418d7006 mttc0 t5,\$14,6
0+0cb8 <[^>]*> 418d7007 mttc0 t5,\$14,7
...
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [patch] GAS supports for MIPS32 MT ASE
2005-08-26 22:05 [patch] GAS supports for MIPS32 MT ASE Chao-ying Fu
@ 2005-08-29 9:55 ` Maciej W. Rozycki
2005-08-29 23:23 ` Chao-ying Fu
0 siblings, 1 reply; 15+ messages in thread
From: Maciej W. Rozycki @ 2005-08-29 9:55 UTC (permalink / raw)
To: Chao-ying Fu; +Cc: Eric Christopher, Thekkath, Radhika, Thiemo Seufer, binutils
On Fri, 26 Aug 2005, Chao-ying Fu wrote:
> Could you review this patch? We will revise the patch, if there are issues.
Posting patches inline helps commenting significantly... Cutting &
pasting for now.
*** 220,229 ****
{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0,
/* b is at the top of the table. */
/* bal is at the top of the table. */
- {"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0,
- {"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0,
- {"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0,
- {"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0,
{"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD|RD_CC|FP_S, 0,
{"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, 0,
{"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD|RD_CC|FP_S, 0,
--- 223,228 ----
A comment is missing about the instructions having been relocated (like
one for "b" and "bal" seen immediately above!).
--- 1351,1415 ----
{"subu_s.qb", "d,s,t", 0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t,
{"wrdsp", "s", 0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA, 0,
{"wrdsp", "s,8", 0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA, 0,
+ /* MIPS MT ASE Instructions. */
+ {"dmt", "", 0x41600bc1, 0xffffffff, TRAP,
+ {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0,
+ {"dvpe", "", 0x41600001, 0xffffffff, TRAP,
Note that the table is meant to be sorted alphabetically (except from
when conflicts arise)...
--- 14359,14367 ----
-mdsp generate DSP instructions\n\
-mno-dsp do not generate DSP instructions\n"));
fprintf (stream, _("\
+ -mt generate MT instructions\n\
+ -mno-mt do not generate MT instructions\n"));
+ fprintf (stream, _("\
-mfix-vr4120 work around certain VR4120 errata\n\
-mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
-mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
Hmm, there is an inconsistency here -- I think "-mmt/-mno-mt" sounds
better than "-mt/-mno-t".
dmt
dmt $0
dvpe
dvpe $1
Testing "dmt" with a non-$0 argument might be a bit more useful to
assure `objdump' gets the disassembly right for the single-operand
variation.
I'll leave the rest to the maintainers...
Maciej
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [patch] GAS supports for MIPS32 MT ASE
2005-08-29 9:55 ` Maciej W. Rozycki
@ 2005-08-29 23:23 ` Chao-ying Fu
2005-08-29 23:41 ` Thiemo Seufer
0 siblings, 1 reply; 15+ messages in thread
From: Chao-ying Fu @ 2005-08-29 23:23 UTC (permalink / raw)
To: Maciej W. Rozycki
Cc: Eric Christopher, Thekkath, Radhika, Thiemo Seufer, binutils
[-- Attachment #1: Type: text/plain, Size: 5093 bytes --]
Ok. I fixed all the issues except the option name
-mt/-mno-mt, because it seems redundant to have two "m"s (-mmt).
Any suggestion?
(I still attach the diff file to avoid the line-wrap problem from my email
program.)
Regards,
Chao-ying
include/opcode/ChangeLog
2005-08-29 Chao-ying Fu <fu@mips.com>
* mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
define.
Document !, $, *, &, g, +t, +T operand formats for MT instructions.
(INSN_ASE_MASK): Update to include INSN_MT.
(INSN_MT): New define for MT ASE.
opcodes/ChangeLog
2005-08-29 Chao-ying Fu <fu@mips.com>
* mips-opc.c (MT32): New define.
(mips_builtin_opcodes): Add MT instructions.
Move "bc0f", "bc0fl", "bc0t", "bc0tl" to the end to avoid opcode
collision with "mftr" and "mttr".
* mips-dis.c (mips_arch_choices): Enable INSN_MT for mips32r2.
(print_insn_args): Add supports for +t, +T, !, $, *, &, g operand
formats.
gas/ChangeLog
2005-08-29 Chao-ying Fu <fu@mips.com>
* config/tc-mips.c (mips_set_options): Add ase_mt for MT instructions.
(mips_opts): Add -1 to initialize ase_mt.
(file_ase_mt): New variable for -mt.
(CPU_HAS_MT): New define.
(validate_mips_insn): Add supports for +t, +T, !, $, *, &, g operand
formats.
(mips_ip): Check ase_mt to enable MT instructions.
Handle !, $, *, &, +T, +t, g operand formats.
For "mftc1", "mfthc1", "cftc1", "mttc1", "mtthc1", "cttc1", we allow
odd float registers.
(OPTION_MT, OPTION_NO_MT): New define.
(OPTION_COMPAT_ARCH_BASE): Change because of inserting MT define.
(md_parse_option): Parse OPTION_MT and OPTION_NO_MT.
(mips_after_parse_args): Set ase_mt based on CPU.
(s_mipsset): Handle ".set mt" and ".set nomt".
(mips_elf_final_processing): Remind of adding new flag for MT ASE.
(md_show_usage): Show usage of -mt and -mno-mt.
gas/testsuite/ChangeLog
2005-08-29 Chao-ying Fu <fu@mips.com>
* gas/mips/mips.exp: Run MT test for mips32r2 only.
* gas/mips/mips32-mt.[sdl]: New test.
----- Original Message -----
From: "Maciej W. Rozycki" <macro@linux-mips.org>
To: "Chao-ying Fu" <fu@mips.com>
Cc: "Eric Christopher" <echristo@apple.com>; "Thekkath, Radhika"
<radhika@mips.com>; "Thiemo Seufer" <ths@networkno.de>;
<binutils@sourceware.org>
Sent: Monday, August 29, 2005 2:55 AM
Subject: Re: [patch] GAS supports for MIPS32 MT ASE
> On Fri, 26 Aug 2005, Chao-ying Fu wrote:
>
> > Could you review this patch? We will revise the patch, if there are
issues.
>
> Posting patches inline helps commenting significantly... Cutting &
> pasting for now.
>
> *** 220,229 ****
> {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0,
> /* b is at the top of the table. */
> /* bal is at the top of the table. */
> - {"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0,
> - {"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0,
> - {"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0,
> - {"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0,
> {"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD|RD_CC|FP_S, 0,
> {"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, 0,
> {"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD|RD_CC|FP_S, 0,
> --- 223,228 ----
>
> A comment is missing about the instructions having been relocated (like
> one for "b" and "bal" seen immediately above!).
>
> --- 1351,1415 ----
> {"subu_s.qb", "d,s,t", 0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t,
> {"wrdsp", "s", 0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA, 0,
> {"wrdsp", "s,8", 0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA, 0,
> + /* MIPS MT ASE Instructions. */
> + {"dmt", "", 0x41600bc1, 0xffffffff, TRAP,
> + {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0,
> + {"dvpe", "", 0x41600001, 0xffffffff, TRAP,
>
> Note that the table is meant to be sorted alphabetically (except from
> when conflicts arise)...
>
> --- 14359,14367 ----
> -mdsp generate DSP instructions\n\
> -mno-dsp do not generate DSP instructions\n"));
> fprintf (stream, _("\
> + -mt generate MT instructions\n\
> + -mno-mt do not generate MT instructions\n"));
> + fprintf (stream, _("\
> -mfix-vr4120 work around certain VR4120 errata\n\
> -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
> -mgp32 use 32-bit GPRs, regardless of the chosen
ISA\n\
>
> Hmm, there is an inconsistency here -- I think "-mmt/-mno-mt" sounds
> better than "-mt/-mno-t".
>
> dmt
> dmt $0
> dvpe
> dvpe $1
>
> Testing "dmt" with a non-$0 argument might be a bit more useful to
> assure `objdump' gets the disassembly right for the single-operand
> variation.
>
> I'll leave the rest to the maintainers...
>
> Maciej
>
[-- Attachment #2: src.diff --]
[-- Type: application/octet-stream, Size: 29953 bytes --]
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.44
diff -c -3 -p -r1.44 mips.h
*** include/opcode/mips.h 25 Aug 2005 18:09:24 -0000 1.44
--- include/opcode/mips.h 29 Aug 2005 23:00:09 -0000
*************** Software Foundation, 51 Franklin Street
*** 170,175 ****
--- 170,185 ----
#define OP_SH_RDDSP 16
#define OP_MASK_RDDSP 0x3f
+ /* MIPS MT ASE */
+ #define OP_SH_MT_U 5
+ #define OP_MASK_MT_U 0x1
+ #define OP_SH_MT_H 4
+ #define OP_MASK_MT_H 0x1
+ #define OP_SH_MTACC_T 18
+ #define OP_MASK_MTACC_T 0x3
+ #define OP_SH_MTACC_D 13
+ #define OP_MASK_MTACC_D 0x3
+
#define OP_OP_COP0 0x10
#define OP_OP_COP1 0x11
#define OP_OP_COP2 0x12
*************** struct mips_opcode
*** 331,336 ****
--- 341,355 ----
"'" 6 bit unsigned immediate (OP_*_RDDSP)
"@" 10 bit signed immediate (OP_*_IMM10)
+ MT ASE usage:
+ "!" 1 bit immediate at bit 5
+ "$" 1 bit immediate at bit 4
+ "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
+ "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
+ "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
+ "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
+ "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
+
Other:
"()" parens surrounding optional value
"," separates operands
*************** struct mips_opcode
*** 339,351 ****
Characters used so far, for quick reference when adding more:
"34567890"
! "%[]<>(),+:'@"
"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
! "abcdefhijklopqrstuvwxz"
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
! "ABCDEFGHI"
*/
/* These are the bits which may be set in the pinfo field of an
--- 358,371 ----
Characters used so far, for quick reference when adding more:
"34567890"
! "%[]<>(),+:'@!$*&"
"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
! "abcdefghijklopqrstuvwxz"
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
! "ABCDEFGHIT"
! "t"
*/
/* These are the bits which may be set in the pinfo field of an
*************** struct mips_opcode
*** 447,453 ****
#define INSN_ISA64R2 0x00000100
/* Masks used for MIPS-defined ASEs. */
! #define INSN_ASE_MASK 0x0000f000
/* DSP ASE */
#define INSN_DSP 0x00001000
--- 467,473 ----
#define INSN_ISA64R2 0x00000100
/* Masks used for MIPS-defined ASEs. */
! #define INSN_ASE_MASK 0x0400f000
/* DSP ASE */
#define INSN_DSP 0x00001000
*************** struct mips_opcode
*** 480,485 ****
--- 500,507 ----
#define INSN_5400 0x01000000
/* NEC VR5500 instruction. */
#define INSN_5500 0x02000000
+ /* MT ASE */
+ #define INSN_MT 0x04000000
/* MIPS ISA defines, use instead of hardcoding ISA level. */
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.52
diff -c -3 -p -r1.52 mips-opc.c
*** opcodes/mips-opc.c 25 Aug 2005 18:12:43 -0000 1.52
--- opcodes/mips-opc.c 29 Aug 2005 23:00:10 -0000
*************** Software Foundation, 51 Franklin Street
*** 146,151 ****
--- 146,154 ----
#define DSP_VOLA INSN_TRAP
#define D32 (INSN_DSP)
+ /* MIPS MT ASE support. */
+ #define MT32 (INSN_MT)
+
/* The order of overloaded instructions matters. Label arguments and
register arguments look the same. Instructions that can have either
for arguments must apear in the correct order in this table for the
*************** const struct mips_opcode mips_builtin_op
*** 220,229 ****
{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 },
/* b is at the top of the table. */
/* bal is at the top of the table. */
! {"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1 },
! {"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
! {"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1 },
! {"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
{"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
{"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
{"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
--- 223,229 ----
{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 },
/* b is at the top of the table. */
/* bal is at the top of the table. */
! /* bc0[tf]l? are at the bottom of the table. */
{"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
{"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
{"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
*************** const struct mips_opcode mips_builtin_op
*** 469,474 ****
--- 469,477 ----
{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 },
/* cfc2 is at the bottom of the table. */
{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 },
+ {"cftc1", "d,E", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 },
+ {"cftc1", "d,T", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 },
+ {"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
*************** const struct mips_opcode mips_builtin_op
*** 476,481 ****
--- 479,487 ----
{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 },
/* ctc2 is at the bottom of the table. */
{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
+ {"cttc1", "t,g", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 },
+ {"cttc1", "t,S", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 },
+ {"cttc2", "t,g", 0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC, 0, MT32 },
{"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, 0, I3 },
{"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_D|FP_S, 0, I1 },
{"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 },
*************** const struct mips_opcode mips_builtin_op
*** 556,561 ****
--- 562,569 ----
{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3 },
{"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 },
{"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 },
+ {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, MT32 },
+ {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3 },
{"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 },
{"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 },
*************** const struct mips_opcode mips_builtin_op
*** 620,628 ****
--- 628,642 ----
{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3 },
{"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3 },
+ {"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, MT32 },
+ {"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
{"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 },
{"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 },
+ {"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 },
+ {"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
{"eret", "", 0x42000018, 0xffffffff, 0, 0, I3|I32 },
+ {"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, MT32 },
+ {"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33 },
{"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, 0, I3 },
{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S, 0, I3 },
*************** const struct mips_opcode mips_builtin_op
*** 719,724 ****
--- 733,739 ----
{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 },
{"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */
{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I2 }, /* as lwr */
+ {"fork", "d,s,t", 0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t, 0, MT32 },
{"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 },
{"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3 },
{"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, 0, I4 },
*************** const struct mips_opcode mips_builtin_op
*** 755,760 ****
--- 770,793 ----
{"max.qh", "X,Y,Q", 0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
{"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 },
{"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 },
+ {"mftacx", "d", 0x41020021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
+ {"mftacx", "d,*", 0x41020021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
+ {"mftc0", "d,+t", 0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0, 0, MT32 },
+ {"mftc0", "d,+T", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 },
+ {"mftc0", "d,E,H", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 },
+ {"mftc1", "d,T", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 },
+ {"mftc1", "d,E", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 },
+ {"mftc2", "d,E", 0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
+ {"mftdsp", "d", 0x41100021, 0xffff07ff, TRAP|WR_d, 0, MT32 },
+ {"mftgpr", "d,t", 0x41000020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 },
+ {"mfthc1", "d,T", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 },
+ {"mfthc1", "d,E", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 },
+ {"mfthc2", "d,E", 0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
+ {"mfthi", "d", 0x41010021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
+ {"mfthi", "d,*", 0x41010021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
+ {"mftlo", "d", 0x41000021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
+ {"mftlo", "d,*", 0x41000021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
+ {"mftr", "t,d,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d, 0, MT32 },
{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 },
{"mfc0", "t,+D", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 },
{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 },
*************** const struct mips_opcode mips_builtin_op
*** 836,841 ****
--- 869,892 ----
{"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_s|WR_HI, 0, D32 },
{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 },
{"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_s|WR_LO, 0, D32 },
+ {"mttc0", "t,G", 0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
+ {"mttc0", "t,+D", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
+ {"mttc0", "t,G,H", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
+ {"mttc1", "t,S", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 },
+ {"mttc1", "t,G", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 },
+ {"mttc2", "t,g", 0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 },
+ {"mttacx", "t", 0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
+ {"mttacx", "t,&", 0x41801021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },
+ {"mttdsp", "t", 0x41808021, 0xffe0ffff, TRAP|RD_t, 0, MT32 },
+ {"mttgpr", "t,d", 0x41800020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 },
+ {"mtthc1", "t,S", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 },
+ {"mtthc1", "t,G", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 },
+ {"mtthc2", "t,g", 0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 },
+ {"mtthi", "t", 0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
+ {"mtthi", "t,&", 0x41800821, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },
+ {"mttlo", "t", 0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
+ {"mttlo", "t,&", 0x41800021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },
+ {"mttr", "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t, 0, MT32 },
{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 },
{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
{"mul.ob", "X,Y,Q", 0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
*************** const struct mips_opcode mips_builtin_op
*** 1209,1214 ****
--- 1260,1267 ----
{"xor.ob", "D,S,k", 0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
{"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, 0, I1 },
+ {"yield", "s", 0x7c000009, 0xfc1fffff, TRAP|RD_s, 0, MT32 },
+ {"yield", "d,s", 0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s, 0, MT32 },
/* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
instructions so they are here for the latters to take precedence. */
*************** const struct mips_opcode mips_builtin_op
*** 1352,1357 ****
--- 1405,1415 ----
{"subu_s.qb", "d,s,t", 0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"wrdsp", "s", 0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA, 0, D32 },
{"wrdsp", "s,8", 0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA, 0, D32 },
+ /* Move bc0* after mftr and mttr to avoid opcode collision. */
+ {"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1 },
+ {"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
+ {"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1 },
+ {"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
};
#define MIPS_NUM_OPCODES \
Index: opcodes/mips-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-dis.c,v
retrieving revision 1.53
diff -c -3 -p -r1.53 mips-dis.c
*** opcodes/mips-dis.c 25 Aug 2005 18:12:44 -0000 1.53
--- opcodes/mips-dis.c 29 Aug 2005 23:00:10 -0000
*************** const struct mips_arch_choice mips_arch_
*** 376,382 ****
mips_hwr_names_numeric },
{ "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
! ISA_MIPS32R2 | INSN_MIPS16 | INSN_DSP,
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_hwr_names_mips3264r2 },
--- 376,382 ----
mips_hwr_names_numeric },
{ "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
! ISA_MIPS32R2 | INSN_MIPS16 | INSN_DSP | INSN_MT,
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_hwr_names_mips3264r2 },
*************** print_insn_args (const char *d,
*** 771,776 ****
--- 771,804 ----
(*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
break;
+ case 't': /* Coprocessor 0 reg name */
+ (*info->fprintf_func) (info->stream, "%s",
+ mips_cp0_names[(l >> OP_SH_RT) &
+ OP_MASK_RT]);
+ break;
+
+ case 'T': /* Coprocessor 0 reg name */
+ {
+ const struct mips_cp0sel_name *n;
+ unsigned int cp0reg, sel;
+
+ cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
+ sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
+
+ /* CP0 register including 'sel' code for mftc0, to be
+ printed textually if known. If not known, print both
+ CP0 register name and sel numerically since CP0 register
+ with sel 0 may have a name unrelated to register being
+ printed. */
+ n = lookup_mips_cp0sel_name(mips_cp0sel_names,
+ mips_cp0sel_names_len, cp0reg, sel);
+ if (n != NULL)
+ (*info->fprintf_func) (info->stream, "%s", n->name);
+ else
+ (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
+ break;
+ }
+
default:
/* xgettext:c-format */
(*info->fprintf_func) (info->stream,
*************** print_insn_args (const char *d,
*** 841,846 ****
--- 869,900 ----
(*info->fprintf_func) (info->stream, "%d", delta);
break;
+ case '!':
+ (*info->fprintf_func) (info->stream, "%ld",
+ (l >> OP_SH_MT_U) & OP_MASK_MT_U);
+ break;
+
+ case '$':
+ (*info->fprintf_func) (info->stream, "%ld",
+ (l >> OP_SH_MT_H) & OP_MASK_MT_H);
+ break;
+
+ case '*':
+ (*info->fprintf_func) (info->stream, "$ac%ld",
+ (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
+ break;
+
+ case '&':
+ (*info->fprintf_func) (info->stream, "$ac%ld",
+ (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
+ break;
+
+ case 'g':
+ /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
+ (*info->fprintf_func) (info->stream, "$%ld",
+ (l >> OP_SH_RD) & OP_MASK_RD);
+ break;
+
case 's':
case 'b':
case 'r':
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.318
diff -c -3 -p -r1.318 tc-mips.c
*** gas/config/tc-mips.c 25 Aug 2005 18:17:36 -0000 1.318
--- gas/config/tc-mips.c 29 Aug 2005 23:00:12 -0000
*************** struct mips_set_options
*** 194,199 ****
--- 194,200 ----
int ase_mips3d;
int ase_mdmx;
int ase_dsp;
+ int ase_mt;
/* Whether we are assembling for the mips16 processor. 0 if we are
not, 1 if we are, and -1 if the value has not been initialized.
Changed by `.set mips16' and `.set nomips16', and the -mips16 and
*************** static int file_mips_fp32 = -1;
*** 244,250 ****
static struct mips_set_options mips_opts =
{
! ISA_UNKNOWN, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE
};
/* These variables are filled in with the masks of registers used.
--- 245,251 ----
static struct mips_set_options mips_opts =
{
! ISA_UNKNOWN, -1, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE
};
/* These variables are filled in with the masks of registers used.
*************** static int file_ase_mdmx;
*** 272,277 ****
--- 273,282 ----
command line (e.g., by -march). */
static int file_ase_dsp;
+ /* True if -mt was passed or implied by arguments passed on the
+ command line (e.g., by -march). */
+ static int file_ase_mt;
+
/* The argument of the -march= flag. The architecture we are assembling. */
static int file_mips_arch = CPU_UNKNOWN;
static const char *mips_arch_string;
*************** static int mips_32bitmode = 0;
*** 374,379 ****
--- 379,388 ----
#define CPU_HAS_DSP(cpu) (FALSE \
)
+ /* Return true if the given CPU supports the MT ASE. */
+ #define CPU_HAS_MT(cpu) (FALSE \
+ )
+
/* True if CPU has a dror instruction. */
#define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
*************** validate_mips_insn (const struct mips_op
*** 7765,7770 ****
--- 7774,7782 ----
case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
case 'I': break;
+ case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
+ case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
+ USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
default:
as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
c, opc->name, opc->args);
*************** validate_mips_insn (const struct mips_op
*** 7837,7842 ****
--- 7849,7859 ----
case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
+ case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
+ case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
+ case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
+ case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
+ case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
default:
as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
c, opc->name, opc->args);
*************** mips_ip (char *str, struct mips_cl_insn
*** 7935,7940 ****
--- 7952,7958 ----
| (file_ase_mips16 ? INSN_MIPS16 : 0)
| (mips_opts.ase_mdmx ? INSN_MDMX : 0)
| (mips_opts.ase_dsp ? INSN_DSP : 0)
+ | (mips_opts.ase_mt ? INSN_MT : 0)
| (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
mips_opts.arch))
ok = TRUE;
*************** mips_ip (char *str, struct mips_cl_insn
*** 8156,8161 ****
--- 8174,8233 ----
s = expr_end;
continue;
+ case '!': /* mt 1-bit unsigned immediate in bit 5 */
+ my_getExpression (&imm_expr, s);
+ check_absolute_expr (ip, &imm_expr);
+ if (imm_expr.X_add_number & ~OP_MASK_MT_U)
+ {
+ as_warn (_("MT immediate not in range 0..%d (%lu)"),
+ OP_MASK_MT_U, (unsigned long) imm_expr.X_add_number);
+ imm_expr.X_add_number &= OP_MASK_MT_U;
+ }
+ ip->insn_opcode |= imm_expr.X_add_number << OP_SH_MT_U;
+ imm_expr.X_op = O_absent;
+ s = expr_end;
+ continue;
+
+ case '$': /* mt 1-bit unsigned immediate in bit 4 */
+ my_getExpression (&imm_expr, s);
+ check_absolute_expr (ip, &imm_expr);
+ if (imm_expr.X_add_number & ~OP_MASK_MT_H)
+ {
+ as_warn (_("MT immediate not in range 0..%d (%lu)"),
+ OP_MASK_MT_H, (unsigned long) imm_expr.X_add_number);
+ imm_expr.X_add_number &= OP_MASK_MT_H;
+ }
+ ip->insn_opcode |= imm_expr.X_add_number << OP_SH_MT_H;
+ imm_expr.X_op = O_absent;
+ s = expr_end;
+ continue;
+
+ case '*': /* four dsp accumulators in bits 18,19 */
+ if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
+ s[3] >= '0' && s[3] <= '3')
+ {
+ regno = s[3] - '0';
+ s += 4;
+ ip->insn_opcode |= regno << OP_SH_MTACC_T;
+ continue;
+ }
+ else
+ as_bad (_("Invalid dsp/smartmips acc register"));
+ break;
+
+ case '&': /* four dsp accumulators in bits 13,14 */
+ if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
+ s[3] >= '0' && s[3] <= '3')
+ {
+ regno = s[3] - '0';
+ s += 4;
+ ip->insn_opcode |= regno << OP_SH_MTACC_D;
+ continue;
+ }
+ else
+ as_bad (_("Invalid dsp/smartmips acc register"));
+ break;
+
case ',':
if (*s++ == *args)
continue;
*************** do_msbd:
*** 8308,8313 ****
--- 8380,8413 ----
s = expr_end;
continue;
+ case 'T': /* Coprocessor register */
+ /* +T is for disassembly only; never match. */
+ break;
+
+ case 't': /* Coprocessor register number */
+ if (s[0] == '$' && ISDIGIT (s[1]))
+ {
+ ++s;
+ regno = 0;
+ do
+ {
+ regno *= 10;
+ regno += *s - '0';
+ ++s;
+ }
+ while (ISDIGIT (*s));
+ if (regno > 31)
+ as_bad (_("Invalid register number (%d)"), regno);
+ else
+ {
+ ip->insn_opcode |= regno << OP_SH_RT;
+ continue;
+ }
+ }
+ else
+ as_bad (_("Invalid coprocessor 0 register number"));
+ break;
+
default:
as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
*args, insn->name, insn->args);
*************** do_msbd:
*** 8442,8447 ****
--- 8542,8548 ----
case 'x': /* ignore register name */
case 'z': /* must be zero register */
case 'U': /* destination register (clo/clz). */
+ case 'g': /* coprocessor destination register */
s_reset = s;
if (s[0] == '$')
{
*************** do_msbd:
*** 8566,8571 ****
--- 8667,8673 ----
case 'd':
case 'G':
case 'K':
+ case 'g':
INSERT_OPERAND (RD, *ip, regno);
break;
case 'U':
*************** do_msbd:
*** 8681,8687 ****
|| strcmp (str, "lwc1") == 0
|| strcmp (str, "swc1") == 0
|| strcmp (str, "l.s") == 0
! || strcmp (str, "s.s") == 0))
as_warn (_("Float register should be even, was %d"),
regno);
--- 8783,8795 ----
|| strcmp (str, "lwc1") == 0
|| strcmp (str, "swc1") == 0
|| strcmp (str, "l.s") == 0
! || strcmp (str, "s.s") == 0
! || strcmp (str, "mftc1") == 0
! || strcmp (str, "mfthc1") == 0
! || strcmp (str, "cftc1") == 0
! || strcmp (str, "mttc1") == 0
! || strcmp (str, "mtthc1") == 0
! || strcmp (str, "cttc1") == 0))
as_warn (_("Float register should be even, was %d"),
regno);
*************** struct option md_longopts[] =
*** 10222,10230 ****
{"mdsp", no_argument, NULL, OPTION_DSP},
#define OPTION_NO_DSP (OPTION_ASE_BASE + 7)
{"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
/* Old-style architecture options. Don't add more of these. */
! #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 8)
#define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
{"m4650", no_argument, NULL, OPTION_M4650},
#define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
--- 10330,10342 ----
{"mdsp", no_argument, NULL, OPTION_DSP},
#define OPTION_NO_DSP (OPTION_ASE_BASE + 7)
{"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
+ #define OPTION_MT (OPTION_ASE_BASE + 8)
+ {"mt", no_argument, NULL, OPTION_MT},
+ #define OPTION_NO_MT (OPTION_ASE_BASE + 9)
+ {"mno-mt", no_argument, NULL, OPTION_NO_MT},
/* Old-style architecture options. Don't add more of these. */
! #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 10)
#define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
{"m4650", no_argument, NULL, OPTION_M4650},
#define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
*************** md_parse_option (int c, char *arg)
*** 10484,10489 ****
--- 10596,10609 ----
mips_opts.ase_dsp = 0;
break;
+ case OPTION_MT:
+ mips_opts.ase_mt = 1;
+ break;
+
+ case OPTION_NO_MT:
+ mips_opts.ase_mt = 0;
+ break;
+
case OPTION_MIPS16:
mips_opts.mips16 = 1;
mips_no_prev_insn ();
*************** mips_after_parse_args (void)
*** 10840,10851 ****
--- 10960,10974 ----
mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0;
if (mips_opts.ase_dsp == -1)
mips_opts.ase_dsp = (CPU_HAS_DSP (file_mips_arch)) ? 1 : 0;
+ if (mips_opts.ase_mt == -1)
+ mips_opts.ase_mt = (CPU_HAS_MT (file_mips_arch)) ? 1 : 0;
file_mips_isa = mips_opts.isa;
file_ase_mips16 = mips_opts.mips16;
file_ase_mips3d = mips_opts.ase_mips3d;
file_ase_mdmx = mips_opts.ase_mdmx;
file_ase_dsp = mips_opts.ase_dsp;
+ file_ase_mt = mips_opts.ase_mt;
mips_opts.gp32 = file_mips_gp32;
mips_opts.fp32 = file_mips_fp32;
*************** s_mipsset (int x ATTRIBUTE_UNUSED)
*** 11787,11792 ****
--- 11910,11919 ----
mips_opts.ase_dsp = 1;
else if (strcmp (name, "nodsp") == 0)
mips_opts.ase_dsp = 0;
+ else if (strcmp (name, "mt") == 0)
+ mips_opts.ase_mt = 1;
+ else if (strcmp (name, "nomt") == 0)
+ mips_opts.ase_mt = 0;
else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
{
int reset = 0;
*************** mips_elf_final_processing (void)
*** 13523,13528 ****
--- 13650,13657 ----
/* Set MIPS ELF flags for ASEs. */
/* We may need to define a new flag for DSP ASE, and set this flag when
file_ase_dsp is true. */
+ /* We may need to define a new flag for MT ASE, and set this flag when
+ file_ase_mt is true. */
if (file_ase_mips16)
elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
#if 0 /* XXX FIXME */
*************** MIPS options:\n\
*** 14230,14235 ****
--- 14359,14367 ----
-mdsp generate DSP instructions\n\
-mno-dsp do not generate DSP instructions\n"));
fprintf (stream, _("\
+ -mt generate MT instructions\n\
+ -mno-mt do not generate MT instructions\n"));
+ fprintf (stream, _("\
-mfix-vr4120 work around certain VR4120 errata\n\
-mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
-mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.108
diff -c -3 -p -r1.108 mips.exp
*** gas/testsuite/gas/mips/mips.exp 25 Aug 2005 18:21:47 -0000 1.108
--- gas/testsuite/gas/mips/mips.exp 29 Aug 2005 23:00:12 -0000
*************** if { [istarget mips*-*-*] } then {
*** 763,768 ****
--- 763,769 ----
run_list_test "noat-7" ""
run_dump_test_arches "mips32-dsp" [mips_arch_list_matching mips32 !sb1]
+ run_dump_test_arches "mips32-mt" [mips_arch_list_matching mips32r2 !gpr64]
if { $elf && !$no_mips16 } {
run_dump_test "mips16-dwarf2"
[-- Attachment #3: mips32-mt.s --]
[-- Type: application/octet-stream, Size: 15991 bytes --]
# source file to test assembly of MIPS MT ASE for MIPS32 instructions
.set noreorder
.set noat
.text
text_label:
dmt
dmt $31
dvpe
dvpe $1
emt
emt $2
evpe
evpe $3
fork $4,$5,$6
yield $5
yield $6,$7
mftc0 $7,$8
mftc0 $8,$0,0
mftc0 $8,$0,1
mftc0 $8,$0,2
mftc0 $8,$0,3
mftc0 $8,$0,4
mftc0 $8,$0,5
mftc0 $8,$0,6
mftc0 $8,$0,7
mftc0 $8,$1,0
mftc0 $8,$1,1
mftc0 $8,$1,2
mftc0 $8,$1,3
mftc0 $8,$1,4
mftc0 $8,$1,5
mftc0 $8,$1,6
mftc0 $8,$1,7
mftc0 $8,$2,0
mftc0 $8,$2,1
mftc0 $8,$2,2
mftc0 $8,$2,3
mftc0 $8,$2,4
mftc0 $8,$2,5
mftc0 $8,$2,6
mftc0 $8,$2,7
mftc0 $8,$3,0
mftc0 $8,$3,1
mftc0 $8,$3,2
mftc0 $8,$3,3
mftc0 $8,$3,4
mftc0 $8,$3,5
mftc0 $8,$3,6
mftc0 $8,$3,7
mftc0 $8,$4,0
mftc0 $8,$4,1
mftc0 $8,$4,2
mftc0 $8,$4,3
mftc0 $8,$4,4
mftc0 $8,$4,5
mftc0 $8,$4,6
mftc0 $8,$4,7
mftc0 $8,$5,0
mftc0 $8,$5,1
mftc0 $8,$5,2
mftc0 $8,$5,3
mftc0 $8,$5,4
mftc0 $8,$5,5
mftc0 $8,$5,6
mftc0 $8,$5,7
mftc0 $8,$6,0
mftc0 $8,$6,1
mftc0 $8,$6,2
mftc0 $8,$6,3
mftc0 $8,$6,4
mftc0 $8,$6,5
mftc0 $8,$6,6
mftc0 $8,$6,7
mftc0 $8,$7,0
mftc0 $8,$7,1
mftc0 $8,$7,2
mftc0 $8,$7,3
mftc0 $8,$7,4
mftc0 $8,$7,5
mftc0 $8,$7,6
mftc0 $8,$7,7
mftc0 $8,$8,0
mftc0 $8,$8,1
mftc0 $8,$8,2
mftc0 $8,$8,3
mftc0 $8,$8,4
mftc0 $8,$8,5
mftc0 $8,$8,6
mftc0 $8,$8,7
mftc0 $8,$9,0
mftc0 $8,$9,1
mftc0 $8,$9,2
mftc0 $8,$9,3
mftc0 $8,$9,4
mftc0 $8,$9,5
mftc0 $8,$9,6
mftc0 $8,$9,7
mftc0 $8,$10,0
mftc0 $8,$10,1
mftc0 $8,$10,2
mftc0 $8,$10,3
mftc0 $8,$10,4
mftc0 $8,$10,5
mftc0 $8,$10,6
mftc0 $8,$10,7
mftc0 $8,$11,0
mftc0 $8,$11,1
mftc0 $8,$11,2
mftc0 $8,$11,3
mftc0 $8,$11,4
mftc0 $8,$11,5
mftc0 $8,$11,6
mftc0 $8,$11,7
mftc0 $8,$12,0
mftc0 $8,$12,1
mftc0 $8,$12,2
mftc0 $8,$12,3
mftc0 $8,$12,4
mftc0 $8,$12,5
mftc0 $8,$12,6
mftc0 $8,$12,7
mftc0 $8,$13,0
mftc0 $8,$13,1
mftc0 $8,$13,2
mftc0 $8,$13,3
mftc0 $8,$13,4
mftc0 $8,$13,5
mftc0 $8,$13,6
mftc0 $8,$13,7
mftc0 $8,$14,0
mftc0 $8,$14,1
mftc0 $8,$14,2
mftc0 $8,$14,3
mftc0 $8,$14,4
mftc0 $8,$14,5
mftc0 $8,$14,6
mftc0 $8,$14,7
mftc0 $8,$15,0
mftc0 $8,$15,1
mftc0 $8,$15,2
mftc0 $8,$15,3
mftc0 $8,$15,4
mftc0 $8,$15,5
mftc0 $8,$15,6
mftc0 $8,$15,7
mftc0 $8,$16,0
mftc0 $8,$16,1
mftc0 $8,$16,2
mftc0 $8,$16,3
mftc0 $8,$16,4
mftc0 $8,$16,5
mftc0 $8,$16,6
mftc0 $8,$16,7
mftc0 $8,$17,0
mftc0 $8,$17,1
mftc0 $8,$17,2
mftc0 $8,$17,3
mftc0 $8,$17,4
mftc0 $8,$17,5
mftc0 $8,$17,6
mftc0 $8,$17,7
mftc0 $8,$18,0
mftc0 $8,$18,1
mftc0 $8,$18,2
mftc0 $8,$18,3
mftc0 $8,$18,4
mftc0 $8,$18,5
mftc0 $8,$18,6
mftc0 $8,$18,7
mftc0 $8,$19,0
mftc0 $8,$19,1
mftc0 $8,$19,2
mftc0 $8,$19,3
mftc0 $8,$19,4
mftc0 $8,$19,5
mftc0 $8,$19,6
mftc0 $8,$19,7
mftc0 $8,$20,0
mftc0 $8,$20,1
mftc0 $8,$20,2
mftc0 $8,$20,3
mftc0 $8,$20,4
mftc0 $8,$20,5
mftc0 $8,$20,6
mftc0 $8,$20,7
mftc0 $8,$21,0
mftc0 $8,$21,1
mftc0 $8,$21,2
mftc0 $8,$21,3
mftc0 $8,$21,4
mftc0 $8,$21,5
mftc0 $8,$21,6
mftc0 $8,$21,7
mftc0 $8,$22,0
mftc0 $8,$22,1
mftc0 $8,$22,2
mftc0 $8,$22,3
mftc0 $8,$22,4
mftc0 $8,$22,5
mftc0 $8,$22,6
mftc0 $8,$22,7
mftc0 $8,$23,0
mftc0 $8,$23,1
mftc0 $8,$23,2
mftc0 $8,$23,3
mftc0 $8,$23,4
mftc0 $8,$23,5
mftc0 $8,$23,6
mftc0 $8,$23,7
mftc0 $8,$24,0
mftc0 $8,$24,1
mftc0 $8,$24,2
mftc0 $8,$24,3
mftc0 $8,$24,4
mftc0 $8,$24,5
mftc0 $8,$24,6
mftc0 $8,$24,7
mftc0 $8,$25,0
mftc0 $8,$25,1
mftc0 $8,$25,2
mftc0 $8,$25,3
mftc0 $8,$25,4
mftc0 $8,$25,5
mftc0 $8,$25,6
mftc0 $8,$25,7
mftc0 $8,$26,0
mftc0 $8,$26,1
mftc0 $8,$26,2
mftc0 $8,$26,3
mftc0 $8,$26,4
mftc0 $8,$26,5
mftc0 $8,$26,6
mftc0 $8,$26,7
mftc0 $8,$27,0
mftc0 $8,$27,1
mftc0 $8,$27,2
mftc0 $8,$27,3
mftc0 $8,$27,4
mftc0 $8,$27,5
mftc0 $8,$27,6
mftc0 $8,$27,7
mftc0 $8,$28,0
mftc0 $8,$28,1
mftc0 $8,$28,2
mftc0 $8,$28,3
mftc0 $8,$28,4
mftc0 $8,$28,5
mftc0 $8,$28,6
mftc0 $8,$28,7
mftc0 $8,$29,0
mftc0 $8,$29,1
mftc0 $8,$29,2
mftc0 $8,$29,3
mftc0 $8,$29,4
mftc0 $8,$29,5
mftc0 $8,$29,6
mftc0 $8,$29,7
mftc0 $8,$30,0
mftc0 $8,$30,1
mftc0 $8,$30,2
mftc0 $8,$30,3
mftc0 $8,$30,4
mftc0 $8,$30,5
mftc0 $8,$30,6
mftc0 $8,$30,7
mftc0 $8,$31,0
mftc0 $8,$31,1
mftc0 $8,$31,2
mftc0 $8,$31,3
mftc0 $8,$31,4
mftc0 $8,$31,5
mftc0 $8,$31,6
mftc0 $8,$31,7
mftgpr $9,$10
mftlo $10
mftlo $11,$ac0
mfthi $12
mfthi $13,$ac1
mftacx $14
mftacx $15,$ac2
mftdsp $16
mftc1 $17,$f18
mftc1 $18,$19
mfthc1 $19,$f20
mfthc1 $20,$22
cftc1 $21,$22
cftc1 $22,$f23
mftc2 $23,$24
mfthc2 $24,$25
cftc2 $25,$26
mttc0 $26,$27
mttc0 $27,$0,0
mttc0 $27,$0,1
mttc0 $27,$0,2
mttc0 $27,$0,3
mttc0 $27,$0,4
mttc0 $27,$0,5
mttc0 $27,$0,6
mttc0 $27,$0,7
mttc0 $27,$1,0
mttc0 $27,$1,1
mttc0 $27,$1,2
mttc0 $27,$1,3
mttc0 $27,$1,4
mttc0 $27,$1,5
mttc0 $27,$1,6
mttc0 $27,$1,7
mttc0 $27,$2,0
mttc0 $27,$2,1
mttc0 $27,$2,2
mttc0 $27,$2,3
mttc0 $27,$2,4
mttc0 $27,$2,5
mttc0 $27,$2,6
mttc0 $27,$2,7
mttc0 $27,$3,0
mttc0 $27,$3,1
mttc0 $27,$3,2
mttc0 $27,$3,3
mttc0 $27,$3,4
mttc0 $27,$3,5
mttc0 $27,$3,6
mttc0 $27,$3,7
mttc0 $27,$4,0
mttc0 $27,$4,1
mttc0 $27,$4,2
mttc0 $27,$4,3
mttc0 $27,$4,4
mttc0 $27,$4,5
mttc0 $27,$4,6
mttc0 $27,$4,7
mttc0 $27,$5,0
mttc0 $27,$5,1
mttc0 $27,$5,2
mttc0 $27,$5,3
mttc0 $27,$5,4
mttc0 $27,$5,5
mttc0 $27,$5,6
mttc0 $27,$5,7
mttc0 $27,$6,0
mttc0 $27,$6,1
mttc0 $27,$6,2
mttc0 $27,$6,3
mttc0 $27,$6,4
mttc0 $27,$6,5
mttc0 $27,$6,6
mttc0 $27,$6,7
mttc0 $27,$7,0
mttc0 $27,$7,1
mttc0 $27,$7,2
mttc0 $27,$7,3
mttc0 $27,$7,4
mttc0 $27,$7,5
mttc0 $27,$7,6
mttc0 $27,$7,7
mttc0 $27,$8,0
mttc0 $27,$8,1
mttc0 $27,$8,2
mttc0 $27,$8,3
mttc0 $27,$8,4
mttc0 $27,$8,5
mttc0 $27,$8,6
mttc0 $27,$8,7
mttc0 $27,$9,0
mttc0 $27,$9,1
mttc0 $27,$9,2
mttc0 $27,$9,3
mttc0 $27,$9,4
mttc0 $27,$9,5
mttc0 $27,$9,6
mttc0 $27,$9,7
mttc0 $27,$10,0
mttc0 $27,$10,1
mttc0 $27,$10,2
mttc0 $27,$10,3
mttc0 $27,$10,4
mttc0 $27,$10,5
mttc0 $27,$10,6
mttc0 $27,$10,7
mttc0 $27,$11,0
mttc0 $27,$11,1
mttc0 $27,$11,2
mttc0 $27,$11,3
mttc0 $27,$11,4
mttc0 $27,$11,5
mttc0 $27,$11,6
mttc0 $27,$11,7
mttc0 $27,$12,0
mttc0 $27,$12,1
mttc0 $27,$12,2
mttc0 $27,$12,3
mttc0 $27,$12,4
mttc0 $27,$12,5
mttc0 $27,$12,6
mttc0 $27,$12,7
mttc0 $27,$13,0
mttc0 $27,$13,1
mttc0 $27,$13,2
mttc0 $27,$13,3
mttc0 $27,$13,4
mttc0 $27,$13,5
mttc0 $27,$13,6
mttc0 $27,$13,7
mttc0 $27,$14,0
mttc0 $27,$14,1
mttc0 $27,$14,2
mttc0 $27,$14,3
mttc0 $27,$14,4
mttc0 $27,$14,5
mttc0 $27,$14,6
mttc0 $27,$14,7
mttc0 $27,$15,0
mttc0 $27,$15,1
mttc0 $27,$15,2
mttc0 $27,$15,3
mttc0 $27,$15,4
mttc0 $27,$15,5
mttc0 $27,$15,6
mttc0 $27,$15,7
mttc0 $27,$16,0
mttc0 $27,$16,1
mttc0 $27,$16,2
mttc0 $27,$16,3
mttc0 $27,$16,4
mttc0 $27,$16,5
mttc0 $27,$16,6
mttc0 $27,$16,7
mttc0 $27,$17,0
mttc0 $27,$17,1
mttc0 $27,$17,2
mttc0 $27,$17,3
mttc0 $27,$17,4
mttc0 $27,$17,5
mttc0 $27,$17,6
mttc0 $27,$17,7
mttc0 $27,$18,0
mttc0 $27,$18,1
mttc0 $27,$18,2
mttc0 $27,$18,3
mttc0 $27,$18,4
mttc0 $27,$18,5
mttc0 $27,$18,6
mttc0 $27,$18,7
mttc0 $27,$19,0
mttc0 $27,$19,1
mttc0 $27,$19,2
mttc0 $27,$19,3
mttc0 $27,$19,4
mttc0 $27,$19,5
mttc0 $27,$19,6
mttc0 $27,$19,7
mttc0 $27,$20,0
mttc0 $27,$20,1
mttc0 $27,$20,2
mttc0 $27,$20,3
mttc0 $27,$20,4
mttc0 $27,$20,5
mttc0 $27,$20,6
mttc0 $27,$20,7
mttc0 $27,$21,0
mttc0 $27,$21,1
mttc0 $27,$21,2
mttc0 $27,$21,3
mttc0 $27,$21,4
mttc0 $27,$21,5
mttc0 $27,$21,6
mttc0 $27,$21,7
mttc0 $27,$22,0
mttc0 $27,$22,1
mttc0 $27,$22,2
mttc0 $27,$22,3
mttc0 $27,$22,4
mttc0 $27,$22,5
mttc0 $27,$22,6
mttc0 $27,$22,7
mttc0 $27,$23,0
mttc0 $27,$23,1
mttc0 $27,$23,2
mttc0 $27,$23,3
mttc0 $27,$23,4
mttc0 $27,$23,5
mttc0 $27,$23,6
mttc0 $27,$23,7
mttc0 $27,$24,0
mttc0 $27,$24,1
mttc0 $27,$24,2
mttc0 $27,$24,3
mttc0 $27,$24,4
mttc0 $27,$24,5
mttc0 $27,$24,6
mttc0 $27,$24,7
mttc0 $27,$25,0
mttc0 $27,$25,1
mttc0 $27,$25,2
mttc0 $27,$25,3
mttc0 $27,$25,4
mttc0 $27,$25,5
mttc0 $27,$25,6
mttc0 $27,$25,7
mttc0 $27,$26,0
mttc0 $27,$26,1
mttc0 $27,$26,2
mttc0 $27,$26,3
mttc0 $27,$26,4
mttc0 $27,$26,5
mttc0 $27,$26,6
mttc0 $27,$26,7
mttc0 $27,$27,0
mttc0 $27,$27,1
mttc0 $27,$27,2
mttc0 $27,$27,3
mttc0 $27,$27,4
mttc0 $27,$27,5
mttc0 $27,$27,6
mttc0 $27,$27,7
mttc0 $27,$28,0
mttc0 $27,$28,1
mttc0 $27,$28,2
mttc0 $27,$28,3
mttc0 $27,$28,4
mttc0 $27,$28,5
mttc0 $27,$28,6
mttc0 $27,$28,7
mttc0 $27,$29,0
mttc0 $27,$29,1
mttc0 $27,$29,2
mttc0 $27,$29,3
mttc0 $27,$29,4
mttc0 $27,$29,5
mttc0 $27,$29,6
mttc0 $27,$29,7
mttc0 $27,$30,0
mttc0 $27,$30,1
mttc0 $27,$30,2
mttc0 $27,$30,3
mttc0 $27,$30,4
mttc0 $27,$30,5
mttc0 $27,$30,6
mttc0 $27,$30,7
mttc0 $27,$31,0
mttc0 $27,$31,1
mttc0 $27,$31,2
mttc0 $27,$31,3
mttc0 $27,$31,4
mttc0 $27,$31,5
mttc0 $27,$31,6
mttc0 $27,$31,7
mttgpr $28,$29
mttlo $29
mttlo $30,$ac3
mtthi $31
mtthi $0,$ac0
mttacx $1
mttacx $2,$ac1
mttdsp $3
mttc1 $4,$f5
mttc1 $5,$6
mtthc1 $6,$f8
mtthc1 $7,$10
cttc1 $8,$9
cttc1 $9,$f10
mttc2 $10,$11
mtthc2 $11,$12
cttc2 $12,$13
mftr $13,$14,-1,0,-1
mftr $13,$14,-1,1,-1
mftr $13,$14,-1,2,-1
mftr $13,$14,-1,3,-1
mftr $13,$14,-1,4,-1
mftr $13,$14,-1,5,-1
mftr $13,$14,-1,6,-1
mftr $13,$14,-1,7,-1
mftr $13,$14,-1,0,0
mftr $13,$14,-1,1,0
mftr $13,$14,-1,2,0
mftr $13,$14,-1,3,0
mftr $13,$14,-1,4,0
mftr $13,$14,-1,5,0
mftr $13,$14,-1,6,0
mftr $13,$14,-1,7,0
mftr $13,$14,-1,0,1
mftr $13,$14,-1,1,1
mftr $13,$14,-1,2,1
mftr $13,$14,-1,3,1
mftr $13,$14,-1,4,1
mftr $13,$14,-1,5,1
mftr $13,$14,-1,6,1
mftr $13,$14,-1,7,1
mftr $13,$14,-1,0,2
mftr $13,$14,-1,1,2
mftr $13,$14,-1,2,2
mftr $13,$14,-1,3,2
mftr $13,$14,-1,4,2
mftr $13,$14,-1,5,2
mftr $13,$14,-1,6,2
mftr $13,$14,-1,7,2
mftr $13,$14,0,0,-1
mftr $13,$14,0,1,-1
mftr $13,$14,0,2,-1
mftr $13,$14,0,3,-1
mftr $13,$14,0,4,-1
mftr $13,$14,0,5,-1
mftr $13,$14,0,6,-1
mftr $13,$14,0,7,-1
mftr $13,$14,0,0,0
mftr $13,$14,0,1,0
mftr $13,$14,0,2,0
mftr $13,$14,0,3,0
mftr $13,$14,0,4,0
mftr $13,$14,0,5,0
mftr $13,$14,0,6,0
mftr $13,$14,0,7,0
mftr $13,$14,0,0,1
mftr $13,$14,0,1,1
mftr $13,$14,0,2,1
mftr $13,$14,0,3,1
mftr $13,$14,0,4,1
mftr $13,$14,0,5,1
mftr $13,$14,0,6,1
mftr $13,$14,0,7,1
mftr $13,$14,0,0,2
mftr $13,$14,0,1,2
mftr $13,$14,0,2,2
mftr $13,$14,0,3,2
mftr $13,$14,0,4,2
mftr $13,$14,0,5,2
mftr $13,$14,0,6,2
mftr $13,$14,0,7,2
mftr $13,$14,1,0,-1
mftr $13,$14,1,1,-1
mftr $13,$14,1,2,-1
mftr $13,$14,1,3,-1
mftr $13,$14,1,4,-1
mftr $13,$14,1,5,-1
mftr $13,$14,1,6,-1
mftr $13,$14,1,7,-1
mftr $13,$14,1,0,0
mftr $13,$14,1,1,0
mftr $13,$14,1,2,0
mftr $13,$14,1,3,0
mftr $13,$14,1,4,0
mftr $13,$14,1,5,0
mftr $13,$14,1,6,0
mftr $13,$14,1,7,0
mftr $13,$14,1,0,1
mftr $13,$14,1,1,1
mftr $13,$14,1,2,1
mftr $13,$14,1,3,1
mftr $13,$14,1,4,1
mftr $13,$14,1,5,1
mftr $13,$14,1,6,1
mftr $13,$14,1,7,1
mftr $13,$14,1,0,2
mftr $13,$14,1,1,2
mftr $13,$14,1,2,2
mftr $13,$14,1,3,2
mftr $13,$14,1,4,2
mftr $13,$14,1,5,2
mftr $13,$14,1,6,2
mftr $13,$14,1,7,2
mftr $13,$14,2,0,-1
mftr $13,$14,2,1,-1
mftr $13,$14,2,2,-1
mftr $13,$14,2,3,-1
mftr $13,$14,2,4,-1
mftr $13,$14,2,5,-1
mftr $13,$14,2,6,-1
mftr $13,$14,2,7,-1
mftr $13,$14,2,0,0
mftr $13,$14,2,1,0
mftr $13,$14,2,2,0
mftr $13,$14,2,3,0
mftr $13,$14,2,4,0
mftr $13,$14,2,5,0
mftr $13,$14,2,6,0
mftr $13,$14,2,7,0
mftr $13,$14,2,0,1
mftr $13,$14,2,1,1
mftr $13,$14,2,2,1
mftr $13,$14,2,3,1
mftr $13,$14,2,4,1
mftr $13,$14,2,5,1
mftr $13,$14,2,6,1
mftr $13,$14,2,7,1
mftr $13,$14,2,0,2
mftr $13,$14,2,1,2
mftr $13,$14,2,2,2
mftr $13,$14,2,3,2
mftr $13,$14,2,4,2
mftr $13,$14,2,5,2
mftr $13,$14,2,6,2
mftr $13,$14,2,7,2
mttr $13,$14,-1,0,-1
mttr $13,$14,-1,1,-1
mttr $13,$14,-1,2,-1
mttr $13,$14,-1,3,-1
mttr $13,$14,-1,4,-1
mttr $13,$14,-1,5,-1
mttr $13,$14,-1,6,-1
mttr $13,$14,-1,7,-1
mttr $13,$14,-1,0,0
mttr $13,$14,-1,1,0
mttr $13,$14,-1,2,0
mttr $13,$14,-1,3,0
mttr $13,$14,-1,4,0
mttr $13,$14,-1,5,0
mttr $13,$14,-1,6,0
mttr $13,$14,-1,7,0
mttr $13,$14,-1,0,1
mttr $13,$14,-1,1,1
mttr $13,$14,-1,2,1
mttr $13,$14,-1,3,1
mttr $13,$14,-1,4,1
mttr $13,$14,-1,5,1
mttr $13,$14,-1,6,1
mttr $13,$14,-1,7,1
mttr $13,$14,-1,0,2
mttr $13,$14,-1,1,2
mttr $13,$14,-1,2,2
mttr $13,$14,-1,3,2
mttr $13,$14,-1,4,2
mttr $13,$14,-1,5,2
mttr $13,$14,-1,6,2
mttr $13,$14,-1,7,2
mttr $13,$14,0,0,-1
mttr $13,$14,0,1,-1
mttr $13,$14,0,2,-1
mttr $13,$14,0,3,-1
mttr $13,$14,0,4,-1
mttr $13,$14,0,5,-1
mttr $13,$14,0,6,-1
mttr $13,$14,0,7,-1
mttr $13,$14,0,0,0
mttr $13,$14,0,1,0
mttr $13,$14,0,2,0
mttr $13,$14,0,3,0
mttr $13,$14,0,4,0
mttr $13,$14,0,5,0
mttr $13,$14,0,6,0
mttr $13,$14,0,7,0
mttr $13,$14,0,0,1
mttr $13,$14,0,1,1
mttr $13,$14,0,2,1
mttr $13,$14,0,3,1
mttr $13,$14,0,4,1
mttr $13,$14,0,5,1
mttr $13,$14,0,6,1
mttr $13,$14,0,7,1
mttr $13,$14,0,0,2
mttr $13,$14,0,1,2
mttr $13,$14,0,2,2
mttr $13,$14,0,3,2
mttr $13,$14,0,4,2
mttr $13,$14,0,5,2
mttr $13,$14,0,6,2
mttr $13,$14,0,7,2
mttr $13,$14,1,0,-1
mttr $13,$14,1,1,-1
mttr $13,$14,1,2,-1
mttr $13,$14,1,3,-1
mttr $13,$14,1,4,-1
mttr $13,$14,1,5,-1
mttr $13,$14,1,6,-1
mttr $13,$14,1,7,-1
mttr $13,$14,1,0,0
mttr $13,$14,1,1,0
mttr $13,$14,1,2,0
mttr $13,$14,1,3,0
mttr $13,$14,1,4,0
mttr $13,$14,1,5,0
mttr $13,$14,1,6,0
mttr $13,$14,1,7,0
mttr $13,$14,1,0,1
mttr $13,$14,1,1,1
mttr $13,$14,1,2,1
mttr $13,$14,1,3,1
mttr $13,$14,1,4,1
mttr $13,$14,1,5,1
mttr $13,$14,1,6,1
mttr $13,$14,1,7,1
mttr $13,$14,1,0,2
mttr $13,$14,1,1,2
mttr $13,$14,1,2,2
mttr $13,$14,1,3,2
mttr $13,$14,1,4,2
mttr $13,$14,1,5,2
mttr $13,$14,1,6,2
mttr $13,$14,1,7,2
mttr $13,$14,2,0,-1
mttr $13,$14,2,1,-1
mttr $13,$14,2,2,-1
mttr $13,$14,2,3,-1
mttr $13,$14,2,4,-1
mttr $13,$14,2,5,-1
mttr $13,$14,2,6,-1
mttr $13,$14,2,7,-1
mttr $13,$14,2,0,0
mttr $13,$14,2,1,0
mttr $13,$14,2,2,0
mttr $13,$14,2,3,0
mttr $13,$14,2,4,0
mttr $13,$14,2,5,0
mttr $13,$14,2,6,0
mttr $13,$14,2,7,0
mttr $13,$14,2,0,1
mttr $13,$14,2,1,1
mttr $13,$14,2,2,1
mttr $13,$14,2,3,1
mttr $13,$14,2,4,1
mttr $13,$14,2,5,1
mttr $13,$14,2,6,1
mttr $13,$14,2,7,1
mttr $13,$14,2,0,2
mttr $13,$14,2,1,2
mttr $13,$14,2,2,2
mttr $13,$14,2,3,2
mttr $13,$14,2,4,2
mttr $13,$14,2,5,2
mttr $13,$14,2,6,2
mttr $13,$14,2,7,2
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8
[-- Attachment #4: mips32-mt.l --]
[-- Type: application/octet-stream, Size: 15257 bytes --]
.*: Assembler messages:
.*:568: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:568: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:569: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:569: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:570: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:570: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:571: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:571: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:572: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:572: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:573: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:573: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:574: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:574: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:575: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:575: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:576: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:577: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:578: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:579: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:580: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:581: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:582: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:583: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:584: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:585: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:586: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:587: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:588: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:589: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:590: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:591: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:592: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:592: Warning: MT immediate not in range 0..1 \(2\)
.*:593: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:593: Warning: MT immediate not in range 0..1 \(2\)
.*:594: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:594: Warning: MT immediate not in range 0..1 \(2\)
.*:595: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:595: Warning: MT immediate not in range 0..1 \(2\)
.*:596: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:596: Warning: MT immediate not in range 0..1 \(2\)
.*:597: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:597: Warning: MT immediate not in range 0..1 \(2\)
.*:598: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:598: Warning: MT immediate not in range 0..1 \(2\)
.*:599: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:599: Warning: MT immediate not in range 0..1 \(2\)
.*:600: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:601: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:602: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:603: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:604: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:605: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:606: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:607: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:624: Warning: MT immediate not in range 0..1 \(2\)
.*:625: Warning: MT immediate not in range 0..1 \(2\)
.*:626: Warning: MT immediate not in range 0..1 \(2\)
.*:627: Warning: MT immediate not in range 0..1 \(2\)
.*:628: Warning: MT immediate not in range 0..1 \(2\)
.*:629: Warning: MT immediate not in range 0..1 \(2\)
.*:630: Warning: MT immediate not in range 0..1 \(2\)
.*:631: Warning: MT immediate not in range 0..1 \(2\)
.*:632: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:633: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:634: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:635: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:636: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:637: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:638: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:639: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:656: Warning: MT immediate not in range 0..1 \(2\)
.*:657: Warning: MT immediate not in range 0..1 \(2\)
.*:658: Warning: MT immediate not in range 0..1 \(2\)
.*:659: Warning: MT immediate not in range 0..1 \(2\)
.*:660: Warning: MT immediate not in range 0..1 \(2\)
.*:661: Warning: MT immediate not in range 0..1 \(2\)
.*:662: Warning: MT immediate not in range 0..1 \(2\)
.*:663: Warning: MT immediate not in range 0..1 \(2\)
.*:664: Warning: MT immediate not in range 0..1 \(2\)
.*:664: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:665: Warning: MT immediate not in range 0..1 \(2\)
.*:665: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:666: Warning: MT immediate not in range 0..1 \(2\)
.*:666: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:667: Warning: MT immediate not in range 0..1 \(2\)
.*:667: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:668: Warning: MT immediate not in range 0..1 \(2\)
.*:668: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:669: Warning: MT immediate not in range 0..1 \(2\)
.*:669: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:670: Warning: MT immediate not in range 0..1 \(2\)
.*:670: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:671: Warning: MT immediate not in range 0..1 \(2\)
.*:671: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:672: Warning: MT immediate not in range 0..1 \(2\)
.*:673: Warning: MT immediate not in range 0..1 \(2\)
.*:674: Warning: MT immediate not in range 0..1 \(2\)
.*:675: Warning: MT immediate not in range 0..1 \(2\)
.*:676: Warning: MT immediate not in range 0..1 \(2\)
.*:677: Warning: MT immediate not in range 0..1 \(2\)
.*:678: Warning: MT immediate not in range 0..1 \(2\)
.*:679: Warning: MT immediate not in range 0..1 \(2\)
.*:680: Warning: MT immediate not in range 0..1 \(2\)
.*:681: Warning: MT immediate not in range 0..1 \(2\)
.*:682: Warning: MT immediate not in range 0..1 \(2\)
.*:683: Warning: MT immediate not in range 0..1 \(2\)
.*:684: Warning: MT immediate not in range 0..1 \(2\)
.*:685: Warning: MT immediate not in range 0..1 \(2\)
.*:686: Warning: MT immediate not in range 0..1 \(2\)
.*:687: Warning: MT immediate not in range 0..1 \(2\)
.*:688: Warning: MT immediate not in range 0..1 \(2\)
.*:688: Warning: MT immediate not in range 0..1 \(2\)
.*:689: Warning: MT immediate not in range 0..1 \(2\)
.*:689: Warning: MT immediate not in range 0..1 \(2\)
.*:690: Warning: MT immediate not in range 0..1 \(2\)
.*:690: Warning: MT immediate not in range 0..1 \(2\)
.*:691: Warning: MT immediate not in range 0..1 \(2\)
.*:691: Warning: MT immediate not in range 0..1 \(2\)
.*:692: Warning: MT immediate not in range 0..1 \(2\)
.*:692: Warning: MT immediate not in range 0..1 \(2\)
.*:693: Warning: MT immediate not in range 0..1 \(2\)
.*:693: Warning: MT immediate not in range 0..1 \(2\)
.*:694: Warning: MT immediate not in range 0..1 \(2\)
.*:694: Warning: MT immediate not in range 0..1 \(2\)
.*:695: Warning: MT immediate not in range 0..1 \(2\)
.*:695: Warning: MT immediate not in range 0..1 \(2\)
.*:696: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:696: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:697: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:697: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:698: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:698: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:699: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:699: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:700: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:700: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:701: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:701: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:702: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:702: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:703: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:703: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:704: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:705: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:706: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:707: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:708: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:709: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:710: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:711: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:712: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:713: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:714: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:715: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:716: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:717: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:718: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:719: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:720: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:720: Warning: MT immediate not in range 0..1 \(2\)
.*:721: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:721: Warning: MT immediate not in range 0..1 \(2\)
.*:722: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:722: Warning: MT immediate not in range 0..1 \(2\)
.*:723: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:723: Warning: MT immediate not in range 0..1 \(2\)
.*:724: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:724: Warning: MT immediate not in range 0..1 \(2\)
.*:725: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:725: Warning: MT immediate not in range 0..1 \(2\)
.*:726: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:726: Warning: MT immediate not in range 0..1 \(2\)
.*:727: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:727: Warning: MT immediate not in range 0..1 \(2\)
.*:728: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:729: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:730: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:731: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:732: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:733: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:734: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:735: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:752: Warning: MT immediate not in range 0..1 \(2\)
.*:753: Warning: MT immediate not in range 0..1 \(2\)
.*:754: Warning: MT immediate not in range 0..1 \(2\)
.*:755: Warning: MT immediate not in range 0..1 \(2\)
.*:756: Warning: MT immediate not in range 0..1 \(2\)
.*:757: Warning: MT immediate not in range 0..1 \(2\)
.*:758: Warning: MT immediate not in range 0..1 \(2\)
.*:759: Warning: MT immediate not in range 0..1 \(2\)
.*:760: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:761: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:762: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:763: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:764: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:765: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:766: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:767: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:784: Warning: MT immediate not in range 0..1 \(2\)
.*:785: Warning: MT immediate not in range 0..1 \(2\)
.*:786: Warning: MT immediate not in range 0..1 \(2\)
.*:787: Warning: MT immediate not in range 0..1 \(2\)
.*:788: Warning: MT immediate not in range 0..1 \(2\)
.*:789: Warning: MT immediate not in range 0..1 \(2\)
.*:790: Warning: MT immediate not in range 0..1 \(2\)
.*:791: Warning: MT immediate not in range 0..1 \(2\)
.*:792: Warning: MT immediate not in range 0..1 \(2\)
.*:792: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:793: Warning: MT immediate not in range 0..1 \(2\)
.*:793: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:794: Warning: MT immediate not in range 0..1 \(2\)
.*:794: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:795: Warning: MT immediate not in range 0..1 \(2\)
.*:795: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:796: Warning: MT immediate not in range 0..1 \(2\)
.*:796: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:797: Warning: MT immediate not in range 0..1 \(2\)
.*:797: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:798: Warning: MT immediate not in range 0..1 \(2\)
.*:798: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:799: Warning: MT immediate not in range 0..1 \(2\)
.*:799: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:800: Warning: MT immediate not in range 0..1 \(2\)
.*:801: Warning: MT immediate not in range 0..1 \(2\)
.*:802: Warning: MT immediate not in range 0..1 \(2\)
.*:803: Warning: MT immediate not in range 0..1 \(2\)
.*:804: Warning: MT immediate not in range 0..1 \(2\)
.*:805: Warning: MT immediate not in range 0..1 \(2\)
.*:806: Warning: MT immediate not in range 0..1 \(2\)
.*:807: Warning: MT immediate not in range 0..1 \(2\)
.*:808: Warning: MT immediate not in range 0..1 \(2\)
.*:809: Warning: MT immediate not in range 0..1 \(2\)
.*:810: Warning: MT immediate not in range 0..1 \(2\)
.*:811: Warning: MT immediate not in range 0..1 \(2\)
.*:812: Warning: MT immediate not in range 0..1 \(2\)
.*:813: Warning: MT immediate not in range 0..1 \(2\)
.*:814: Warning: MT immediate not in range 0..1 \(2\)
.*:815: Warning: MT immediate not in range 0..1 \(2\)
.*:816: Warning: MT immediate not in range 0..1 \(2\)
.*:816: Warning: MT immediate not in range 0..1 \(2\)
.*:817: Warning: MT immediate not in range 0..1 \(2\)
.*:817: Warning: MT immediate not in range 0..1 \(2\)
.*:818: Warning: MT immediate not in range 0..1 \(2\)
.*:818: Warning: MT immediate not in range 0..1 \(2\)
.*:819: Warning: MT immediate not in range 0..1 \(2\)
.*:819: Warning: MT immediate not in range 0..1 \(2\)
.*:820: Warning: MT immediate not in range 0..1 \(2\)
.*:820: Warning: MT immediate not in range 0..1 \(2\)
.*:821: Warning: MT immediate not in range 0..1 \(2\)
.*:821: Warning: MT immediate not in range 0..1 \(2\)
.*:822: Warning: MT immediate not in range 0..1 \(2\)
.*:822: Warning: MT immediate not in range 0..1 \(2\)
.*:823: Warning: MT immediate not in range 0..1 \(2\)
.*:823: Warning: MT immediate not in range 0..1 \(2\)
[-- Attachment #5: mips32-mt.d --]
[-- Type: application/octet-stream, Size: 34711 bytes --]
#objdump: -dr --prefix-addresses --show-raw-insn -M cp0-names=mips32
#name: MIPS MT ASE for MIPS32
#as: -mt
#stderr: mips32-mt.l
# Check MIPS MT ASE for MIPS32 Instruction Assembly
.*: +file format .*mips.*
Disassembly of section .text:
0+0000 <[^>]*> 41600bc1 dmt
0+0004 <[^>]*> 417f0bc1 dmt ra
0+0008 <[^>]*> 41600001 dvpe
0+000c <[^>]*> 41610001 dvpe at
0+0010 <[^>]*> 41600be1 emt
0+0014 <[^>]*> 41620be1 emt v0
0+0018 <[^>]*> 41600021 evpe
0+001c <[^>]*> 41630021 evpe v1
0+0020 <[^>]*> 7ca62008 fork a0,a1,a2
0+0024 <[^>]*> 7ca00009 yield a1
0+0028 <[^>]*> 7ce03009 yield a2,a3
0+002c <[^>]*> 41083800 mftc0 a3,c0_badvaddr
0+0030 <[^>]*> 41004000 mftc0 t0,c0_index
0+0034 <[^>]*> 41004001 mftc0 t0,\$0,1
0+0038 <[^>]*> 41004002 mftc0 t0,\$0,2
0+003c <[^>]*> 41004003 mftc0 t0,\$0,3
0+0040 <[^>]*> 41004004 mftc0 t0,\$0,4
0+0044 <[^>]*> 41004005 mftc0 t0,\$0,5
0+0048 <[^>]*> 41004006 mftc0 t0,\$0,6
0+004c <[^>]*> 41004007 mftc0 t0,\$0,7
0+0050 <[^>]*> 41014000 mftc0 t0,c0_random
0+0054 <[^>]*> 41014001 mftc0 t0,\$1,1
0+0058 <[^>]*> 41014002 mftc0 t0,\$1,2
0+005c <[^>]*> 41014003 mftc0 t0,\$1,3
0+0060 <[^>]*> 41014004 mftc0 t0,\$1,4
0+0064 <[^>]*> 41014005 mftc0 t0,\$1,5
0+0068 <[^>]*> 41014006 mftc0 t0,\$1,6
0+006c <[^>]*> 41014007 mftc0 t0,\$1,7
0+0070 <[^>]*> 41024000 mftc0 t0,c0_entrylo0
0+0074 <[^>]*> 41024001 mftc0 t0,\$2,1
0+0078 <[^>]*> 41024002 mftc0 t0,\$2,2
0+007c <[^>]*> 41024003 mftc0 t0,\$2,3
0+0080 <[^>]*> 41024004 mftc0 t0,\$2,4
0+0084 <[^>]*> 41024005 mftc0 t0,\$2,5
0+0088 <[^>]*> 41024006 mftc0 t0,\$2,6
0+008c <[^>]*> 41024007 mftc0 t0,\$2,7
0+0090 <[^>]*> 41034000 mftc0 t0,c0_entrylo1
0+0094 <[^>]*> 41034001 mftc0 t0,\$3,1
0+0098 <[^>]*> 41034002 mftc0 t0,\$3,2
0+009c <[^>]*> 41034003 mftc0 t0,\$3,3
0+00a0 <[^>]*> 41034004 mftc0 t0,\$3,4
0+00a4 <[^>]*> 41034005 mftc0 t0,\$3,5
0+00a8 <[^>]*> 41034006 mftc0 t0,\$3,6
0+00ac <[^>]*> 41034007 mftc0 t0,\$3,7
0+00b0 <[^>]*> 41044000 mftc0 t0,c0_context
0+00b4 <[^>]*> 41044001 mftc0 t0,\$4,1
0+00b8 <[^>]*> 41044002 mftc0 t0,\$4,2
0+00bc <[^>]*> 41044003 mftc0 t0,\$4,3
0+00c0 <[^>]*> 41044004 mftc0 t0,\$4,4
0+00c4 <[^>]*> 41044005 mftc0 t0,\$4,5
0+00c8 <[^>]*> 41044006 mftc0 t0,\$4,6
0+00cc <[^>]*> 41044007 mftc0 t0,\$4,7
0+00d0 <[^>]*> 41054000 mftc0 t0,c0_pagemask
0+00d4 <[^>]*> 41054001 mftc0 t0,\$5,1
0+00d8 <[^>]*> 41054002 mftc0 t0,\$5,2
0+00dc <[^>]*> 41054003 mftc0 t0,\$5,3
0+00e0 <[^>]*> 41054004 mftc0 t0,\$5,4
0+00e4 <[^>]*> 41054005 mftc0 t0,\$5,5
0+00e8 <[^>]*> 41054006 mftc0 t0,\$5,6
0+00ec <[^>]*> 41054007 mftc0 t0,\$5,7
0+00f0 <[^>]*> 41064000 mftc0 t0,c0_wired
0+00f4 <[^>]*> 41064001 mftc0 t0,\$6,1
0+00f8 <[^>]*> 41064002 mftc0 t0,\$6,2
0+00fc <[^>]*> 41064003 mftc0 t0,\$6,3
0+0100 <[^>]*> 41064004 mftc0 t0,\$6,4
0+0104 <[^>]*> 41064005 mftc0 t0,\$6,5
0+0108 <[^>]*> 41064006 mftc0 t0,\$6,6
0+010c <[^>]*> 41064007 mftc0 t0,\$6,7
0+0110 <[^>]*> 41074000 mftc0 t0,\$7
0+0114 <[^>]*> 41074001 mftc0 t0,\$7,1
0+0118 <[^>]*> 41074002 mftc0 t0,\$7,2
0+011c <[^>]*> 41074003 mftc0 t0,\$7,3
0+0120 <[^>]*> 41074004 mftc0 t0,\$7,4
0+0124 <[^>]*> 41074005 mftc0 t0,\$7,5
0+0128 <[^>]*> 41074006 mftc0 t0,\$7,6
0+012c <[^>]*> 41074007 mftc0 t0,\$7,7
0+0130 <[^>]*> 41084000 mftc0 t0,c0_badvaddr
0+0134 <[^>]*> 41084001 mftc0 t0,\$8,1
0+0138 <[^>]*> 41084002 mftc0 t0,\$8,2
0+013c <[^>]*> 41084003 mftc0 t0,\$8,3
0+0140 <[^>]*> 41084004 mftc0 t0,\$8,4
0+0144 <[^>]*> 41084005 mftc0 t0,\$8,5
0+0148 <[^>]*> 41084006 mftc0 t0,\$8,6
0+014c <[^>]*> 41084007 mftc0 t0,\$8,7
0+0150 <[^>]*> 41094000 mftc0 t0,c0_count
0+0154 <[^>]*> 41094001 mftc0 t0,\$9,1
0+0158 <[^>]*> 41094002 mftc0 t0,\$9,2
0+015c <[^>]*> 41094003 mftc0 t0,\$9,3
0+0160 <[^>]*> 41094004 mftc0 t0,\$9,4
0+0164 <[^>]*> 41094005 mftc0 t0,\$9,5
0+0168 <[^>]*> 41094006 mftc0 t0,\$9,6
0+016c <[^>]*> 41094007 mftc0 t0,\$9,7
0+0170 <[^>]*> 410a4000 mftc0 t0,c0_entryhi
0+0174 <[^>]*> 410a4001 mftc0 t0,\$10,1
0+0178 <[^>]*> 410a4002 mftc0 t0,\$10,2
0+017c <[^>]*> 410a4003 mftc0 t0,\$10,3
0+0180 <[^>]*> 410a4004 mftc0 t0,\$10,4
0+0184 <[^>]*> 410a4005 mftc0 t0,\$10,5
0+0188 <[^>]*> 410a4006 mftc0 t0,\$10,6
0+018c <[^>]*> 410a4007 mftc0 t0,\$10,7
0+0190 <[^>]*> 410b4000 mftc0 t0,c0_compare
0+0194 <[^>]*> 410b4001 mftc0 t0,\$11,1
0+0198 <[^>]*> 410b4002 mftc0 t0,\$11,2
0+019c <[^>]*> 410b4003 mftc0 t0,\$11,3
0+01a0 <[^>]*> 410b4004 mftc0 t0,\$11,4
0+01a4 <[^>]*> 410b4005 mftc0 t0,\$11,5
0+01a8 <[^>]*> 410b4006 mftc0 t0,\$11,6
0+01ac <[^>]*> 410b4007 mftc0 t0,\$11,7
0+01b0 <[^>]*> 410c4000 mftc0 t0,c0_status
0+01b4 <[^>]*> 410c4001 mftc0 t0,\$12,1
0+01b8 <[^>]*> 410c4002 mftc0 t0,\$12,2
0+01bc <[^>]*> 410c4003 mftc0 t0,\$12,3
0+01c0 <[^>]*> 410c4004 mftc0 t0,\$12,4
0+01c4 <[^>]*> 410c4005 mftc0 t0,\$12,5
0+01c8 <[^>]*> 410c4006 mftc0 t0,\$12,6
0+01cc <[^>]*> 410c4007 mftc0 t0,\$12,7
0+01d0 <[^>]*> 410d4000 mftc0 t0,c0_cause
0+01d4 <[^>]*> 410d4001 mftc0 t0,\$13,1
0+01d8 <[^>]*> 410d4002 mftc0 t0,\$13,2
0+01dc <[^>]*> 410d4003 mftc0 t0,\$13,3
0+01e0 <[^>]*> 410d4004 mftc0 t0,\$13,4
0+01e4 <[^>]*> 410d4005 mftc0 t0,\$13,5
0+01e8 <[^>]*> 410d4006 mftc0 t0,\$13,6
0+01ec <[^>]*> 410d4007 mftc0 t0,\$13,7
0+01f0 <[^>]*> 410e4000 mftc0 t0,c0_epc
0+01f4 <[^>]*> 410e4001 mftc0 t0,\$14,1
0+01f8 <[^>]*> 410e4002 mftc0 t0,\$14,2
0+01fc <[^>]*> 410e4003 mftc0 t0,\$14,3
0+0200 <[^>]*> 410e4004 mftc0 t0,\$14,4
0+0204 <[^>]*> 410e4005 mftc0 t0,\$14,5
0+0208 <[^>]*> 410e4006 mftc0 t0,\$14,6
0+020c <[^>]*> 410e4007 mftc0 t0,\$14,7
0+0210 <[^>]*> 410f4000 mftc0 t0,c0_prid
0+0214 <[^>]*> 410f4001 mftc0 t0,\$15,1
0+0218 <[^>]*> 410f4002 mftc0 t0,\$15,2
0+021c <[^>]*> 410f4003 mftc0 t0,\$15,3
0+0220 <[^>]*> 410f4004 mftc0 t0,\$15,4
0+0224 <[^>]*> 410f4005 mftc0 t0,\$15,5
0+0228 <[^>]*> 410f4006 mftc0 t0,\$15,6
0+022c <[^>]*> 410f4007 mftc0 t0,\$15,7
0+0230 <[^>]*> 41104000 mftc0 t0,c0_config
0+0234 <[^>]*> 41104001 mftc0 t0,c0_config1
0+0238 <[^>]*> 41104002 mftc0 t0,c0_config2
0+023c <[^>]*> 41104003 mftc0 t0,c0_config3
0+0240 <[^>]*> 41104004 mftc0 t0,\$16,4
0+0244 <[^>]*> 41104005 mftc0 t0,\$16,5
0+0248 <[^>]*> 41104006 mftc0 t0,\$16,6
0+024c <[^>]*> 41104007 mftc0 t0,\$16,7
0+0250 <[^>]*> 41114000 mftc0 t0,c0_lladdr
0+0254 <[^>]*> 41114001 mftc0 t0,\$17,1
0+0258 <[^>]*> 41114002 mftc0 t0,\$17,2
0+025c <[^>]*> 41114003 mftc0 t0,\$17,3
0+0260 <[^>]*> 41114004 mftc0 t0,\$17,4
0+0264 <[^>]*> 41114005 mftc0 t0,\$17,5
0+0268 <[^>]*> 41114006 mftc0 t0,\$17,6
0+026c <[^>]*> 41114007 mftc0 t0,\$17,7
0+0270 <[^>]*> 41124000 mftc0 t0,c0_watchlo
0+0274 <[^>]*> 41124001 mftc0 t0,c0_watchlo,1
0+0278 <[^>]*> 41124002 mftc0 t0,c0_watchlo,2
0+027c <[^>]*> 41124003 mftc0 t0,c0_watchlo,3
0+0280 <[^>]*> 41124004 mftc0 t0,c0_watchlo,4
0+0284 <[^>]*> 41124005 mftc0 t0,c0_watchlo,5
0+0288 <[^>]*> 41124006 mftc0 t0,c0_watchlo,6
0+028c <[^>]*> 41124007 mftc0 t0,c0_watchlo,7
0+0290 <[^>]*> 41134000 mftc0 t0,c0_watchhi
0+0294 <[^>]*> 41134001 mftc0 t0,c0_watchhi,1
0+0298 <[^>]*> 41134002 mftc0 t0,c0_watchhi,2
0+029c <[^>]*> 41134003 mftc0 t0,c0_watchhi,3
0+02a0 <[^>]*> 41134004 mftc0 t0,c0_watchhi,4
0+02a4 <[^>]*> 41134005 mftc0 t0,c0_watchhi,5
0+02a8 <[^>]*> 41134006 mftc0 t0,c0_watchhi,6
0+02ac <[^>]*> 41134007 mftc0 t0,c0_watchhi,7
0+02b0 <[^>]*> 41144000 mftc0 t0,c0_xcontext
0+02b4 <[^>]*> 41144001 mftc0 t0,\$20,1
0+02b8 <[^>]*> 41144002 mftc0 t0,\$20,2
0+02bc <[^>]*> 41144003 mftc0 t0,\$20,3
0+02c0 <[^>]*> 41144004 mftc0 t0,\$20,4
0+02c4 <[^>]*> 41144005 mftc0 t0,\$20,5
0+02c8 <[^>]*> 41144006 mftc0 t0,\$20,6
0+02cc <[^>]*> 41144007 mftc0 t0,\$20,7
0+02d0 <[^>]*> 41154000 mftc0 t0,\$21
0+02d4 <[^>]*> 41154001 mftc0 t0,\$21,1
0+02d8 <[^>]*> 41154002 mftc0 t0,\$21,2
0+02dc <[^>]*> 41154003 mftc0 t0,\$21,3
0+02e0 <[^>]*> 41154004 mftc0 t0,\$21,4
0+02e4 <[^>]*> 41154005 mftc0 t0,\$21,5
0+02e8 <[^>]*> 41154006 mftc0 t0,\$21,6
0+02ec <[^>]*> 41154007 mftc0 t0,\$21,7
0+02f0 <[^>]*> 41164000 mftc0 t0,\$22
0+02f4 <[^>]*> 41164001 mftc0 t0,\$22,1
0+02f8 <[^>]*> 41164002 mftc0 t0,\$22,2
0+02fc <[^>]*> 41164003 mftc0 t0,\$22,3
0+0300 <[^>]*> 41164004 mftc0 t0,\$22,4
0+0304 <[^>]*> 41164005 mftc0 t0,\$22,5
0+0308 <[^>]*> 41164006 mftc0 t0,\$22,6
0+030c <[^>]*> 41164007 mftc0 t0,\$22,7
0+0310 <[^>]*> 41174000 mftc0 t0,c0_debug
0+0314 <[^>]*> 41174001 mftc0 t0,\$23,1
0+0318 <[^>]*> 41174002 mftc0 t0,\$23,2
0+031c <[^>]*> 41174003 mftc0 t0,\$23,3
0+0320 <[^>]*> 41174004 mftc0 t0,\$23,4
0+0324 <[^>]*> 41174005 mftc0 t0,\$23,5
0+0328 <[^>]*> 41174006 mftc0 t0,\$23,6
0+032c <[^>]*> 41174007 mftc0 t0,\$23,7
0+0330 <[^>]*> 41184000 mftc0 t0,c0_depc
0+0334 <[^>]*> 41184001 mftc0 t0,\$24,1
0+0338 <[^>]*> 41184002 mftc0 t0,\$24,2
0+033c <[^>]*> 41184003 mftc0 t0,\$24,3
0+0340 <[^>]*> 41184004 mftc0 t0,\$24,4
0+0344 <[^>]*> 41184005 mftc0 t0,\$24,5
0+0348 <[^>]*> 41184006 mftc0 t0,\$24,6
0+034c <[^>]*> 41184007 mftc0 t0,\$24,7
0+0350 <[^>]*> 41194000 mftc0 t0,c0_perfcnt
0+0354 <[^>]*> 41194001 mftc0 t0,c0_perfcnt,1
0+0358 <[^>]*> 41194002 mftc0 t0,c0_perfcnt,2
0+035c <[^>]*> 41194003 mftc0 t0,c0_perfcnt,3
0+0360 <[^>]*> 41194004 mftc0 t0,c0_perfcnt,4
0+0364 <[^>]*> 41194005 mftc0 t0,c0_perfcnt,5
0+0368 <[^>]*> 41194006 mftc0 t0,c0_perfcnt,6
0+036c <[^>]*> 41194007 mftc0 t0,c0_perfcnt,7
0+0370 <[^>]*> 411a4000 mftc0 t0,c0_errctl
0+0374 <[^>]*> 411a4001 mftc0 t0,\$26,1
0+0378 <[^>]*> 411a4002 mftc0 t0,\$26,2
0+037c <[^>]*> 411a4003 mftc0 t0,\$26,3
0+0380 <[^>]*> 411a4004 mftc0 t0,\$26,4
0+0384 <[^>]*> 411a4005 mftc0 t0,\$26,5
0+0388 <[^>]*> 411a4006 mftc0 t0,\$26,6
0+038c <[^>]*> 411a4007 mftc0 t0,\$26,7
0+0390 <[^>]*> 411b4000 mftc0 t0,c0_cacheerr
0+0394 <[^>]*> 411b4001 mftc0 t0,c0_cacheerr,1
0+0398 <[^>]*> 411b4002 mftc0 t0,c0_cacheerr,2
0+039c <[^>]*> 411b4003 mftc0 t0,c0_cacheerr,3
0+03a0 <[^>]*> 411b4004 mftc0 t0,\$27,4
0+03a4 <[^>]*> 411b4005 mftc0 t0,\$27,5
0+03a8 <[^>]*> 411b4006 mftc0 t0,\$27,6
0+03ac <[^>]*> 411b4007 mftc0 t0,\$27,7
0+03b0 <[^>]*> 411c4000 mftc0 t0,c0_taglo
0+03b4 <[^>]*> 411c4001 mftc0 t0,c0_datalo
0+03b8 <[^>]*> 411c4002 mftc0 t0,\$28,2
0+03bc <[^>]*> 411c4003 mftc0 t0,\$28,3
0+03c0 <[^>]*> 411c4004 mftc0 t0,\$28,4
0+03c4 <[^>]*> 411c4005 mftc0 t0,\$28,5
0+03c8 <[^>]*> 411c4006 mftc0 t0,\$28,6
0+03cc <[^>]*> 411c4007 mftc0 t0,\$28,7
0+03d0 <[^>]*> 411d4000 mftc0 t0,c0_taghi
0+03d4 <[^>]*> 411d4001 mftc0 t0,c0_datahi
0+03d8 <[^>]*> 411d4002 mftc0 t0,\$29,2
0+03dc <[^>]*> 411d4003 mftc0 t0,\$29,3
0+03e0 <[^>]*> 411d4004 mftc0 t0,\$29,4
0+03e4 <[^>]*> 411d4005 mftc0 t0,\$29,5
0+03e8 <[^>]*> 411d4006 mftc0 t0,\$29,6
0+03ec <[^>]*> 411d4007 mftc0 t0,\$29,7
0+03f0 <[^>]*> 411e4000 mftc0 t0,c0_errorepc
0+03f4 <[^>]*> 411e4001 mftc0 t0,\$30,1
0+03f8 <[^>]*> 411e4002 mftc0 t0,\$30,2
0+03fc <[^>]*> 411e4003 mftc0 t0,\$30,3
0+0400 <[^>]*> 411e4004 mftc0 t0,\$30,4
0+0404 <[^>]*> 411e4005 mftc0 t0,\$30,5
0+0408 <[^>]*> 411e4006 mftc0 t0,\$30,6
0+040c <[^>]*> 411e4007 mftc0 t0,\$30,7
0+0410 <[^>]*> 411f4000 mftc0 t0,c0_desave
0+0414 <[^>]*> 411f4001 mftc0 t0,\$31,1
0+0418 <[^>]*> 411f4002 mftc0 t0,\$31,2
0+041c <[^>]*> 411f4003 mftc0 t0,\$31,3
0+0420 <[^>]*> 411f4004 mftc0 t0,\$31,4
0+0424 <[^>]*> 411f4005 mftc0 t0,\$31,5
0+0428 <[^>]*> 411f4006 mftc0 t0,\$31,6
0+042c <[^>]*> 411f4007 mftc0 t0,\$31,7
0+0430 <[^>]*> 410a4820 mftgpr t1,t2
0+0434 <[^>]*> 41005021 mftlo t2
0+0438 <[^>]*> 41005821 mftlo t3
0+043c <[^>]*> 41016021 mfthi t4
0+0440 <[^>]*> 41056821 mfthi t5,\$ac1
0+0444 <[^>]*> 41027021 mftacx t6
0+0448 <[^>]*> 410a7821 mftacx t7,\$ac2
0+044c <[^>]*> 41108021 mftdsp s0
0+0450 <[^>]*> 41128822 mftc1 s1,\$f18
0+0454 <[^>]*> 41139022 mftc1 s2,\$f19
0+0458 <[^>]*> 41149832 mfthc1 s3,\$f20
0+045c <[^>]*> 4116a032 mfthc1 s4,\$f22
0+0460 <[^>]*> 4116a823 cftc1 s5,\$22
0+0464 <[^>]*> 4117b023 cftc1 s6,\$23
0+0468 <[^>]*> 4118b824 mftc2 s7,\$24
0+046c <[^>]*> 4119c034 mfthc2 t8,\$25
0+0470 <[^>]*> 411ac825 cftc2 t9,\$26
0+0474 <[^>]*> 419ad800 mttc0 k0,c0_cacheerr
0+0478 <[^>]*> 419b0000 mttc0 k1,c0_index
0+047c <[^>]*> 419b0001 mttc0 k1,\$0,1
0+0480 <[^>]*> 419b0002 mttc0 k1,\$0,2
0+0484 <[^>]*> 419b0003 mttc0 k1,\$0,3
0+0488 <[^>]*> 419b0004 mttc0 k1,\$0,4
0+048c <[^>]*> 419b0005 mttc0 k1,\$0,5
0+0490 <[^>]*> 419b0006 mttc0 k1,\$0,6
0+0494 <[^>]*> 419b0007 mttc0 k1,\$0,7
0+0498 <[^>]*> 419b0800 mttc0 k1,c0_random
0+049c <[^>]*> 419b0801 mttc0 k1,\$1,1
0+04a0 <[^>]*> 419b0802 mttc0 k1,\$1,2
0+04a4 <[^>]*> 419b0803 mttc0 k1,\$1,3
0+04a8 <[^>]*> 419b0804 mttc0 k1,\$1,4
0+04ac <[^>]*> 419b0805 mttc0 k1,\$1,5
0+04b0 <[^>]*> 419b0806 mttc0 k1,\$1,6
0+04b4 <[^>]*> 419b0807 mttc0 k1,\$1,7
0+04b8 <[^>]*> 419b1000 mttc0 k1,c0_entrylo0
0+04bc <[^>]*> 419b1001 mttc0 k1,\$2,1
0+04c0 <[^>]*> 419b1002 mttc0 k1,\$2,2
0+04c4 <[^>]*> 419b1003 mttc0 k1,\$2,3
0+04c8 <[^>]*> 419b1004 mttc0 k1,\$2,4
0+04cc <[^>]*> 419b1005 mttc0 k1,\$2,5
0+04d0 <[^>]*> 419b1006 mttc0 k1,\$2,6
0+04d4 <[^>]*> 419b1007 mttc0 k1,\$2,7
0+04d8 <[^>]*> 419b1800 mttc0 k1,c0_entrylo1
0+04dc <[^>]*> 419b1801 mttc0 k1,\$3,1
0+04e0 <[^>]*> 419b1802 mttc0 k1,\$3,2
0+04e4 <[^>]*> 419b1803 mttc0 k1,\$3,3
0+04e8 <[^>]*> 419b1804 mttc0 k1,\$3,4
0+04ec <[^>]*> 419b1805 mttc0 k1,\$3,5
0+04f0 <[^>]*> 419b1806 mttc0 k1,\$3,6
0+04f4 <[^>]*> 419b1807 mttc0 k1,\$3,7
0+04f8 <[^>]*> 419b2000 mttc0 k1,c0_context
0+04fc <[^>]*> 419b2001 mttc0 k1,\$4,1
0+0500 <[^>]*> 419b2002 mttc0 k1,\$4,2
0+0504 <[^>]*> 419b2003 mttc0 k1,\$4,3
0+0508 <[^>]*> 419b2004 mttc0 k1,\$4,4
0+050c <[^>]*> 419b2005 mttc0 k1,\$4,5
0+0510 <[^>]*> 419b2006 mttc0 k1,\$4,6
0+0514 <[^>]*> 419b2007 mttc0 k1,\$4,7
0+0518 <[^>]*> 419b2800 mttc0 k1,c0_pagemask
0+051c <[^>]*> 419b2801 mttc0 k1,\$5,1
0+0520 <[^>]*> 419b2802 mttc0 k1,\$5,2
0+0524 <[^>]*> 419b2803 mttc0 k1,\$5,3
0+0528 <[^>]*> 419b2804 mttc0 k1,\$5,4
0+052c <[^>]*> 419b2805 mttc0 k1,\$5,5
0+0530 <[^>]*> 419b2806 mttc0 k1,\$5,6
0+0534 <[^>]*> 419b2807 mttc0 k1,\$5,7
0+0538 <[^>]*> 419b3000 mttc0 k1,c0_wired
0+053c <[^>]*> 419b3001 mttc0 k1,\$6,1
0+0540 <[^>]*> 419b3002 mttc0 k1,\$6,2
0+0544 <[^>]*> 419b3003 mttc0 k1,\$6,3
0+0548 <[^>]*> 419b3004 mttc0 k1,\$6,4
0+054c <[^>]*> 419b3005 mttc0 k1,\$6,5
0+0550 <[^>]*> 419b3006 mttc0 k1,\$6,6
0+0554 <[^>]*> 419b3007 mttc0 k1,\$6,7
0+0558 <[^>]*> 419b3800 mttc0 k1,\$7
0+055c <[^>]*> 419b3801 mttc0 k1,\$7,1
0+0560 <[^>]*> 419b3802 mttc0 k1,\$7,2
0+0564 <[^>]*> 419b3803 mttc0 k1,\$7,3
0+0568 <[^>]*> 419b3804 mttc0 k1,\$7,4
0+056c <[^>]*> 419b3805 mttc0 k1,\$7,5
0+0570 <[^>]*> 419b3806 mttc0 k1,\$7,6
0+0574 <[^>]*> 419b3807 mttc0 k1,\$7,7
0+0578 <[^>]*> 419b4000 mttc0 k1,c0_badvaddr
0+057c <[^>]*> 419b4001 mttc0 k1,\$8,1
0+0580 <[^>]*> 419b4002 mttc0 k1,\$8,2
0+0584 <[^>]*> 419b4003 mttc0 k1,\$8,3
0+0588 <[^>]*> 419b4004 mttc0 k1,\$8,4
0+058c <[^>]*> 419b4005 mttc0 k1,\$8,5
0+0590 <[^>]*> 419b4006 mttc0 k1,\$8,6
0+0594 <[^>]*> 419b4007 mttc0 k1,\$8,7
0+0598 <[^>]*> 419b4800 mttc0 k1,c0_count
0+059c <[^>]*> 419b4801 mttc0 k1,\$9,1
0+05a0 <[^>]*> 419b4802 mttc0 k1,\$9,2
0+05a4 <[^>]*> 419b4803 mttc0 k1,\$9,3
0+05a8 <[^>]*> 419b4804 mttc0 k1,\$9,4
0+05ac <[^>]*> 419b4805 mttc0 k1,\$9,5
0+05b0 <[^>]*> 419b4806 mttc0 k1,\$9,6
0+05b4 <[^>]*> 419b4807 mttc0 k1,\$9,7
0+05b8 <[^>]*> 419b5000 mttc0 k1,c0_entryhi
0+05bc <[^>]*> 419b5001 mttc0 k1,\$10,1
0+05c0 <[^>]*> 419b5002 mttc0 k1,\$10,2
0+05c4 <[^>]*> 419b5003 mttc0 k1,\$10,3
0+05c8 <[^>]*> 419b5004 mttc0 k1,\$10,4
0+05cc <[^>]*> 419b5005 mttc0 k1,\$10,5
0+05d0 <[^>]*> 419b5006 mttc0 k1,\$10,6
0+05d4 <[^>]*> 419b5007 mttc0 k1,\$10,7
0+05d8 <[^>]*> 419b5800 mttc0 k1,c0_compare
0+05dc <[^>]*> 419b5801 mttc0 k1,\$11,1
0+05e0 <[^>]*> 419b5802 mttc0 k1,\$11,2
0+05e4 <[^>]*> 419b5803 mttc0 k1,\$11,3
0+05e8 <[^>]*> 419b5804 mttc0 k1,\$11,4
0+05ec <[^>]*> 419b5805 mttc0 k1,\$11,5
0+05f0 <[^>]*> 419b5806 mttc0 k1,\$11,6
0+05f4 <[^>]*> 419b5807 mttc0 k1,\$11,7
0+05f8 <[^>]*> 419b6000 mttc0 k1,c0_status
0+05fc <[^>]*> 419b6001 mttc0 k1,\$12,1
0+0600 <[^>]*> 419b6002 mttc0 k1,\$12,2
0+0604 <[^>]*> 419b6003 mttc0 k1,\$12,3
0+0608 <[^>]*> 419b6004 mttc0 k1,\$12,4
0+060c <[^>]*> 419b6005 mttc0 k1,\$12,5
0+0610 <[^>]*> 419b6006 mttc0 k1,\$12,6
0+0614 <[^>]*> 419b6007 mttc0 k1,\$12,7
0+0618 <[^>]*> 419b6800 mttc0 k1,c0_cause
0+061c <[^>]*> 419b6801 mttc0 k1,\$13,1
0+0620 <[^>]*> 419b6802 mttc0 k1,\$13,2
0+0624 <[^>]*> 419b6803 mttc0 k1,\$13,3
0+0628 <[^>]*> 419b6804 mttc0 k1,\$13,4
0+062c <[^>]*> 419b6805 mttc0 k1,\$13,5
0+0630 <[^>]*> 419b6806 mttc0 k1,\$13,6
0+0634 <[^>]*> 419b6807 mttc0 k1,\$13,7
0+0638 <[^>]*> 419b7000 mttc0 k1,c0_epc
0+063c <[^>]*> 419b7001 mttc0 k1,\$14,1
0+0640 <[^>]*> 419b7002 mttc0 k1,\$14,2
0+0644 <[^>]*> 419b7003 mttc0 k1,\$14,3
0+0648 <[^>]*> 419b7004 mttc0 k1,\$14,4
0+064c <[^>]*> 419b7005 mttc0 k1,\$14,5
0+0650 <[^>]*> 419b7006 mttc0 k1,\$14,6
0+0654 <[^>]*> 419b7007 mttc0 k1,\$14,7
0+0658 <[^>]*> 419b7800 mttc0 k1,c0_prid
0+065c <[^>]*> 419b7801 mttc0 k1,\$15,1
0+0660 <[^>]*> 419b7802 mttc0 k1,\$15,2
0+0664 <[^>]*> 419b7803 mttc0 k1,\$15,3
0+0668 <[^>]*> 419b7804 mttc0 k1,\$15,4
0+066c <[^>]*> 419b7805 mttc0 k1,\$15,5
0+0670 <[^>]*> 419b7806 mttc0 k1,\$15,6
0+0674 <[^>]*> 419b7807 mttc0 k1,\$15,7
0+0678 <[^>]*> 419b8000 mttc0 k1,c0_config
0+067c <[^>]*> 419b8001 mttc0 k1,c0_config1
0+0680 <[^>]*> 419b8002 mttc0 k1,c0_config2
0+0684 <[^>]*> 419b8003 mttc0 k1,c0_config3
0+0688 <[^>]*> 419b8004 mttc0 k1,\$16,4
0+068c <[^>]*> 419b8005 mttc0 k1,\$16,5
0+0690 <[^>]*> 419b8006 mttc0 k1,\$16,6
0+0694 <[^>]*> 419b8007 mttc0 k1,\$16,7
0+0698 <[^>]*> 419b8800 mttc0 k1,c0_lladdr
0+069c <[^>]*> 419b8801 mttc0 k1,\$17,1
0+06a0 <[^>]*> 419b8802 mttc0 k1,\$17,2
0+06a4 <[^>]*> 419b8803 mttc0 k1,\$17,3
0+06a8 <[^>]*> 419b8804 mttc0 k1,\$17,4
0+06ac <[^>]*> 419b8805 mttc0 k1,\$17,5
0+06b0 <[^>]*> 419b8806 mttc0 k1,\$17,6
0+06b4 <[^>]*> 419b8807 mttc0 k1,\$17,7
0+06b8 <[^>]*> 419b9000 mttc0 k1,c0_watchlo
0+06bc <[^>]*> 419b9001 mttc0 k1,c0_watchlo,1
0+06c0 <[^>]*> 419b9002 mttc0 k1,c0_watchlo,2
0+06c4 <[^>]*> 419b9003 mttc0 k1,c0_watchlo,3
0+06c8 <[^>]*> 419b9004 mttc0 k1,c0_watchlo,4
0+06cc <[^>]*> 419b9005 mttc0 k1,c0_watchlo,5
0+06d0 <[^>]*> 419b9006 mttc0 k1,c0_watchlo,6
0+06d4 <[^>]*> 419b9007 mttc0 k1,c0_watchlo,7
0+06d8 <[^>]*> 419b9800 mttc0 k1,c0_watchhi
0+06dc <[^>]*> 419b9801 mttc0 k1,c0_watchhi,1
0+06e0 <[^>]*> 419b9802 mttc0 k1,c0_watchhi,2
0+06e4 <[^>]*> 419b9803 mttc0 k1,c0_watchhi,3
0+06e8 <[^>]*> 419b9804 mttc0 k1,c0_watchhi,4
0+06ec <[^>]*> 419b9805 mttc0 k1,c0_watchhi,5
0+06f0 <[^>]*> 419b9806 mttc0 k1,c0_watchhi,6
0+06f4 <[^>]*> 419b9807 mttc0 k1,c0_watchhi,7
0+06f8 <[^>]*> 419ba000 mttc0 k1,c0_xcontext
0+06fc <[^>]*> 419ba001 mttc0 k1,\$20,1
0+0700 <[^>]*> 419ba002 mttc0 k1,\$20,2
0+0704 <[^>]*> 419ba003 mttc0 k1,\$20,3
0+0708 <[^>]*> 419ba004 mttc0 k1,\$20,4
0+070c <[^>]*> 419ba005 mttc0 k1,\$20,5
0+0710 <[^>]*> 419ba006 mttc0 k1,\$20,6
0+0714 <[^>]*> 419ba007 mttc0 k1,\$20,7
0+0718 <[^>]*> 419ba800 mttc0 k1,\$21
0+071c <[^>]*> 419ba801 mttc0 k1,\$21,1
0+0720 <[^>]*> 419ba802 mttc0 k1,\$21,2
0+0724 <[^>]*> 419ba803 mttc0 k1,\$21,3
0+0728 <[^>]*> 419ba804 mttc0 k1,\$21,4
0+072c <[^>]*> 419ba805 mttc0 k1,\$21,5
0+0730 <[^>]*> 419ba806 mttc0 k1,\$21,6
0+0734 <[^>]*> 419ba807 mttc0 k1,\$21,7
0+0738 <[^>]*> 419bb000 mttc0 k1,\$22
0+073c <[^>]*> 419bb001 mttc0 k1,\$22,1
0+0740 <[^>]*> 419bb002 mttc0 k1,\$22,2
0+0744 <[^>]*> 419bb003 mttc0 k1,\$22,3
0+0748 <[^>]*> 419bb004 mttc0 k1,\$22,4
0+074c <[^>]*> 419bb005 mttc0 k1,\$22,5
0+0750 <[^>]*> 419bb006 mttc0 k1,\$22,6
0+0754 <[^>]*> 419bb007 mttc0 k1,\$22,7
0+0758 <[^>]*> 419bb800 mttc0 k1,c0_debug
0+075c <[^>]*> 419bb801 mttc0 k1,\$23,1
0+0760 <[^>]*> 419bb802 mttc0 k1,\$23,2
0+0764 <[^>]*> 419bb803 mttc0 k1,\$23,3
0+0768 <[^>]*> 419bb804 mttc0 k1,\$23,4
0+076c <[^>]*> 419bb805 mttc0 k1,\$23,5
0+0770 <[^>]*> 419bb806 mttc0 k1,\$23,6
0+0774 <[^>]*> 419bb807 mttc0 k1,\$23,7
0+0778 <[^>]*> 419bc000 mttc0 k1,c0_depc
0+077c <[^>]*> 419bc001 mttc0 k1,\$24,1
0+0780 <[^>]*> 419bc002 mttc0 k1,\$24,2
0+0784 <[^>]*> 419bc003 mttc0 k1,\$24,3
0+0788 <[^>]*> 419bc004 mttc0 k1,\$24,4
0+078c <[^>]*> 419bc005 mttc0 k1,\$24,5
0+0790 <[^>]*> 419bc006 mttc0 k1,\$24,6
0+0794 <[^>]*> 419bc007 mttc0 k1,\$24,7
0+0798 <[^>]*> 419bc800 mttc0 k1,c0_perfcnt
0+079c <[^>]*> 419bc801 mttc0 k1,c0_perfcnt,1
0+07a0 <[^>]*> 419bc802 mttc0 k1,c0_perfcnt,2
0+07a4 <[^>]*> 419bc803 mttc0 k1,c0_perfcnt,3
0+07a8 <[^>]*> 419bc804 mttc0 k1,c0_perfcnt,4
0+07ac <[^>]*> 419bc805 mttc0 k1,c0_perfcnt,5
0+07b0 <[^>]*> 419bc806 mttc0 k1,c0_perfcnt,6
0+07b4 <[^>]*> 419bc807 mttc0 k1,c0_perfcnt,7
0+07b8 <[^>]*> 419bd000 mttc0 k1,c0_errctl
0+07bc <[^>]*> 419bd001 mttc0 k1,\$26,1
0+07c0 <[^>]*> 419bd002 mttc0 k1,\$26,2
0+07c4 <[^>]*> 419bd003 mttc0 k1,\$26,3
0+07c8 <[^>]*> 419bd004 mttc0 k1,\$26,4
0+07cc <[^>]*> 419bd005 mttc0 k1,\$26,5
0+07d0 <[^>]*> 419bd006 mttc0 k1,\$26,6
0+07d4 <[^>]*> 419bd007 mttc0 k1,\$26,7
0+07d8 <[^>]*> 419bd800 mttc0 k1,c0_cacheerr
0+07dc <[^>]*> 419bd801 mttc0 k1,c0_cacheerr,1
0+07e0 <[^>]*> 419bd802 mttc0 k1,c0_cacheerr,2
0+07e4 <[^>]*> 419bd803 mttc0 k1,c0_cacheerr,3
0+07e8 <[^>]*> 419bd804 mttc0 k1,\$27,4
0+07ec <[^>]*> 419bd805 mttc0 k1,\$27,5
0+07f0 <[^>]*> 419bd806 mttc0 k1,\$27,6
0+07f4 <[^>]*> 419bd807 mttc0 k1,\$27,7
0+07f8 <[^>]*> 419be000 mttc0 k1,c0_taglo
0+07fc <[^>]*> 419be001 mttc0 k1,c0_datalo
0+0800 <[^>]*> 419be002 mttc0 k1,\$28,2
0+0804 <[^>]*> 419be003 mttc0 k1,\$28,3
0+0808 <[^>]*> 419be004 mttc0 k1,\$28,4
0+080c <[^>]*> 419be005 mttc0 k1,\$28,5
0+0810 <[^>]*> 419be006 mttc0 k1,\$28,6
0+0814 <[^>]*> 419be007 mttc0 k1,\$28,7
0+0818 <[^>]*> 419be800 mttc0 k1,c0_taghi
0+081c <[^>]*> 419be801 mttc0 k1,c0_datahi
0+0820 <[^>]*> 419be802 mttc0 k1,\$29,2
0+0824 <[^>]*> 419be803 mttc0 k1,\$29,3
0+0828 <[^>]*> 419be804 mttc0 k1,\$29,4
0+082c <[^>]*> 419be805 mttc0 k1,\$29,5
0+0830 <[^>]*> 419be806 mttc0 k1,\$29,6
0+0834 <[^>]*> 419be807 mttc0 k1,\$29,7
0+0838 <[^>]*> 419bf000 mttc0 k1,c0_errorepc
0+083c <[^>]*> 419bf001 mttc0 k1,\$30,1
0+0840 <[^>]*> 419bf002 mttc0 k1,\$30,2
0+0844 <[^>]*> 419bf003 mttc0 k1,\$30,3
0+0848 <[^>]*> 419bf004 mttc0 k1,\$30,4
0+084c <[^>]*> 419bf005 mttc0 k1,\$30,5
0+0850 <[^>]*> 419bf006 mttc0 k1,\$30,6
0+0854 <[^>]*> 419bf007 mttc0 k1,\$30,7
0+0858 <[^>]*> 419bf800 mttc0 k1,c0_desave
0+085c <[^>]*> 419bf801 mttc0 k1,\$31,1
0+0860 <[^>]*> 419bf802 mttc0 k1,\$31,2
0+0864 <[^>]*> 419bf803 mttc0 k1,\$31,3
0+0868 <[^>]*> 419bf804 mttc0 k1,\$31,4
0+086c <[^>]*> 419bf805 mttc0 k1,\$31,5
0+0870 <[^>]*> 419bf806 mttc0 k1,\$31,6
0+0874 <[^>]*> 419bf807 mttc0 k1,\$31,7
0+0878 <[^>]*> 419ce820 mttgpr gp,sp
0+087c <[^>]*> 419d0021 mttlo sp
0+0880 <[^>]*> 419e6021 mttlo s8,\$ac3
0+0884 <[^>]*> 419f0821 mtthi ra
0+0888 <[^>]*> 41800821 mtthi zero
0+088c <[^>]*> 41811021 mttacx at
0+0890 <[^>]*> 41823021 mttacx v0,\$ac1
0+0894 <[^>]*> 41838021 mttdsp v1
0+0898 <[^>]*> 41842822 mttc1 a0,\$f5
0+089c <[^>]*> 41853022 mttc1 a1,\$f6
0+08a0 <[^>]*> 41864032 mtthc1 a2,\$f8
0+08a4 <[^>]*> 41875032 mtthc1 a3,\$f10
0+08a8 <[^>]*> 41884823 cttc1 t0,\$9
0+08ac <[^>]*> 41895023 cttc1 t1,\$10
0+08b0 <[^>]*> 418a5824 mttc2 t2,\$11
0+08b4 <[^>]*> 418b6034 mtthc2 t3,\$12
0+08b8 <[^>]*> 418c6825 cttc2 t4,\$13
0+08bc <[^>]*> 410d7030 mftr t5,t6,1,0,1
0+08c0 <[^>]*> 410d7031 mftr t5,t6,1,1,1
0+08c4 <[^>]*> 410d7032 mfthc1 t6,\$f13
0+08c8 <[^>]*> 410d7033 mftr t5,t6,1,3,1
0+08cc <[^>]*> 410d7034 mfthc2 t6,\$13
0+08d0 <[^>]*> 410d7035 mftr t5,t6,1,5,1
0+08d4 <[^>]*> 410d7036 mftr t5,t6,1,6,1
0+08d8 <[^>]*> 410d7037 mftr t5,t6,1,7,1
0+08dc <[^>]*> 410d7020 mftgpr t6,t5
0+08e0 <[^>]*> 410d7021 mfthi t6,\$ac3
0+08e4 <[^>]*> 410d7022 mftc1 t6,\$f13
0+08e8 <[^>]*> 410d7023 cftc1 t6,\$13
0+08ec <[^>]*> 410d7024 mftc2 t6,\$13
0+08f0 <[^>]*> 410d7025 cftc2 t6,\$13
0+08f4 <[^>]*> 410d7026 mftr t5,t6,1,6,0
0+08f8 <[^>]*> 410d7027 mftr t5,t6,1,7,0
0+08fc <[^>]*> 410d7030 mftr t5,t6,1,0,1
0+0900 <[^>]*> 410d7031 mftr t5,t6,1,1,1
0+0904 <[^>]*> 410d7032 mfthc1 t6,\$f13
0+0908 <[^>]*> 410d7033 mftr t5,t6,1,3,1
0+090c <[^>]*> 410d7034 mfthc2 t6,\$13
0+0910 <[^>]*> 410d7035 mftr t5,t6,1,5,1
0+0914 <[^>]*> 410d7036 mftr t5,t6,1,6,1
0+0918 <[^>]*> 410d7037 mftr t5,t6,1,7,1
0+091c <[^>]*> 410d7020 mftgpr t6,t5
0+0920 <[^>]*> 410d7021 mfthi t6,\$ac3
0+0924 <[^>]*> 410d7022 mftc1 t6,\$f13
0+0928 <[^>]*> 410d7023 cftc1 t6,\$13
0+092c <[^>]*> 410d7024 mftc2 t6,\$13
0+0930 <[^>]*> 410d7025 cftc2 t6,\$13
0+0934 <[^>]*> 410d7026 mftr t5,t6,1,6,0
0+0938 <[^>]*> 410d7027 mftr t5,t6,1,7,0
0+093c <[^>]*> 410d7010 mftr t5,t6,0,0,1
0+0940 <[^>]*> 410d7011 mftr t5,t6,0,1,1
0+0944 <[^>]*> 410d7012 mftr t5,t6,0,2,1
0+0948 <[^>]*> 410d7013 mftr t5,t6,0,3,1
0+094c <[^>]*> 410d7014 mftr t5,t6,0,4,1
0+0950 <[^>]*> 410d7015 mftr t5,t6,0,5,1
0+0954 <[^>]*> 410d7016 mftr t5,t6,0,6,1
0+0958 <[^>]*> 410d7017 mftr t5,t6,0,7,1
0+095c <[^>]*> 410d7000 mftc0 t6,c0_cause
0+0960 <[^>]*> 410d7001 mftc0 t6,\$13,1
0+0964 <[^>]*> 410d7002 mftc0 t6,\$13,2
0+0968 <[^>]*> 410d7003 mftc0 t6,\$13,3
0+096c <[^>]*> 410d7004 mftc0 t6,\$13,4
0+0970 <[^>]*> 410d7005 mftc0 t6,\$13,5
0+0974 <[^>]*> 410d7006 mftc0 t6,\$13,6
0+0978 <[^>]*> 410d7007 mftc0 t6,\$13,7
0+097c <[^>]*> 410d7010 mftr t5,t6,0,0,1
0+0980 <[^>]*> 410d7011 mftr t5,t6,0,1,1
0+0984 <[^>]*> 410d7012 mftr t5,t6,0,2,1
0+0988 <[^>]*> 410d7013 mftr t5,t6,0,3,1
0+098c <[^>]*> 410d7014 mftr t5,t6,0,4,1
0+0990 <[^>]*> 410d7015 mftr t5,t6,0,5,1
0+0994 <[^>]*> 410d7016 mftr t5,t6,0,6,1
0+0998 <[^>]*> 410d7017 mftr t5,t6,0,7,1
0+099c <[^>]*> 410d7000 mftc0 t6,c0_cause
0+09a0 <[^>]*> 410d7001 mftc0 t6,\$13,1
0+09a4 <[^>]*> 410d7002 mftc0 t6,\$13,2
0+09a8 <[^>]*> 410d7003 mftc0 t6,\$13,3
0+09ac <[^>]*> 410d7004 mftc0 t6,\$13,4
0+09b0 <[^>]*> 410d7005 mftc0 t6,\$13,5
0+09b4 <[^>]*> 410d7006 mftc0 t6,\$13,6
0+09b8 <[^>]*> 410d7007 mftc0 t6,\$13,7
0+09bc <[^>]*> 410d7030 mftr t5,t6,1,0,1
0+09c0 <[^>]*> 410d7031 mftr t5,t6,1,1,1
0+09c4 <[^>]*> 410d7032 mfthc1 t6,\$f13
0+09c8 <[^>]*> 410d7033 mftr t5,t6,1,3,1
0+09cc <[^>]*> 410d7034 mfthc2 t6,\$13
0+09d0 <[^>]*> 410d7035 mftr t5,t6,1,5,1
0+09d4 <[^>]*> 410d7036 mftr t5,t6,1,6,1
0+09d8 <[^>]*> 410d7037 mftr t5,t6,1,7,1
0+09dc <[^>]*> 410d7020 mftgpr t6,t5
0+09e0 <[^>]*> 410d7021 mfthi t6,\$ac3
0+09e4 <[^>]*> 410d7022 mftc1 t6,\$f13
0+09e8 <[^>]*> 410d7023 cftc1 t6,\$13
0+09ec <[^>]*> 410d7024 mftc2 t6,\$13
0+09f0 <[^>]*> 410d7025 cftc2 t6,\$13
0+09f4 <[^>]*> 410d7026 mftr t5,t6,1,6,0
0+09f8 <[^>]*> 410d7027 mftr t5,t6,1,7,0
0+09fc <[^>]*> 410d7030 mftr t5,t6,1,0,1
0+0a00 <[^>]*> 410d7031 mftr t5,t6,1,1,1
0+0a04 <[^>]*> 410d7032 mfthc1 t6,\$f13
0+0a08 <[^>]*> 410d7033 mftr t5,t6,1,3,1
0+0a0c <[^>]*> 410d7034 mfthc2 t6,\$13
0+0a10 <[^>]*> 410d7035 mftr t5,t6,1,5,1
0+0a14 <[^>]*> 410d7036 mftr t5,t6,1,6,1
0+0a18 <[^>]*> 410d7037 mftr t5,t6,1,7,1
0+0a1c <[^>]*> 410d7020 mftgpr t6,t5
0+0a20 <[^>]*> 410d7021 mfthi t6,\$ac3
0+0a24 <[^>]*> 410d7022 mftc1 t6,\$f13
0+0a28 <[^>]*> 410d7023 cftc1 t6,\$13
0+0a2c <[^>]*> 410d7024 mftc2 t6,\$13
0+0a30 <[^>]*> 410d7025 cftc2 t6,\$13
0+0a34 <[^>]*> 410d7026 mftr t5,t6,1,6,0
0+0a38 <[^>]*> 410d7027 mftr t5,t6,1,7,0
0+0a3c <[^>]*> 410d7010 mftr t5,t6,0,0,1
0+0a40 <[^>]*> 410d7011 mftr t5,t6,0,1,1
0+0a44 <[^>]*> 410d7012 mftr t5,t6,0,2,1
0+0a48 <[^>]*> 410d7013 mftr t5,t6,0,3,1
0+0a4c <[^>]*> 410d7014 mftr t5,t6,0,4,1
0+0a50 <[^>]*> 410d7015 mftr t5,t6,0,5,1
0+0a54 <[^>]*> 410d7016 mftr t5,t6,0,6,1
0+0a58 <[^>]*> 410d7017 mftr t5,t6,0,7,1
0+0a5c <[^>]*> 410d7000 mftc0 t6,c0_cause
0+0a60 <[^>]*> 410d7001 mftc0 t6,\$13,1
0+0a64 <[^>]*> 410d7002 mftc0 t6,\$13,2
0+0a68 <[^>]*> 410d7003 mftc0 t6,\$13,3
0+0a6c <[^>]*> 410d7004 mftc0 t6,\$13,4
0+0a70 <[^>]*> 410d7005 mftc0 t6,\$13,5
0+0a74 <[^>]*> 410d7006 mftc0 t6,\$13,6
0+0a78 <[^>]*> 410d7007 mftc0 t6,\$13,7
0+0a7c <[^>]*> 410d7010 mftr t5,t6,0,0,1
0+0a80 <[^>]*> 410d7011 mftr t5,t6,0,1,1
0+0a84 <[^>]*> 410d7012 mftr t5,t6,0,2,1
0+0a88 <[^>]*> 410d7013 mftr t5,t6,0,3,1
0+0a8c <[^>]*> 410d7014 mftr t5,t6,0,4,1
0+0a90 <[^>]*> 410d7015 mftr t5,t6,0,5,1
0+0a94 <[^>]*> 410d7016 mftr t5,t6,0,6,1
0+0a98 <[^>]*> 410d7017 mftr t5,t6,0,7,1
0+0a9c <[^>]*> 410d7000 mftc0 t6,c0_cause
0+0aa0 <[^>]*> 410d7001 mftc0 t6,\$13,1
0+0aa4 <[^>]*> 410d7002 mftc0 t6,\$13,2
0+0aa8 <[^>]*> 410d7003 mftc0 t6,\$13,3
0+0aac <[^>]*> 410d7004 mftc0 t6,\$13,4
0+0ab0 <[^>]*> 410d7005 mftc0 t6,\$13,5
0+0ab4 <[^>]*> 410d7006 mftc0 t6,\$13,6
0+0ab8 <[^>]*> 410d7007 mftc0 t6,\$13,7
0+0abc <[^>]*> 418d7030 mttr t5,t6,1,0,1
0+0ac0 <[^>]*> 418d7031 mttr t5,t6,1,1,1
0+0ac4 <[^>]*> 418d7032 mtthc1 t5,\$f14
0+0ac8 <[^>]*> 418d7033 mttr t5,t6,1,3,1
0+0acc <[^>]*> 418d7034 mtthc2 t5,\$14
0+0ad0 <[^>]*> 418d7035 mttr t5,t6,1,5,1
0+0ad4 <[^>]*> 418d7036 mttr t5,t6,1,6,1
0+0ad8 <[^>]*> 418d7037 mttr t5,t6,1,7,1
0+0adc <[^>]*> 418d7020 mttgpr t5,t6
0+0ae0 <[^>]*> 418d7021 mttacx t5,\$ac3
0+0ae4 <[^>]*> 418d7022 mttc1 t5,\$f14
0+0ae8 <[^>]*> 418d7023 cttc1 t5,\$14
0+0aec <[^>]*> 418d7024 mttc2 t5,\$14
0+0af0 <[^>]*> 418d7025 cttc2 t5,\$14
0+0af4 <[^>]*> 418d7026 mttr t5,t6,1,6,0
0+0af8 <[^>]*> 418d7027 mttr t5,t6,1,7,0
0+0afc <[^>]*> 418d7030 mttr t5,t6,1,0,1
0+0b00 <[^>]*> 418d7031 mttr t5,t6,1,1,1
0+0b04 <[^>]*> 418d7032 mtthc1 t5,\$f14
0+0b08 <[^>]*> 418d7033 mttr t5,t6,1,3,1
0+0b0c <[^>]*> 418d7034 mtthc2 t5,\$14
0+0b10 <[^>]*> 418d7035 mttr t5,t6,1,5,1
0+0b14 <[^>]*> 418d7036 mttr t5,t6,1,6,1
0+0b18 <[^>]*> 418d7037 mttr t5,t6,1,7,1
0+0b1c <[^>]*> 418d7020 mttgpr t5,t6
0+0b20 <[^>]*> 418d7021 mttacx t5,\$ac3
0+0b24 <[^>]*> 418d7022 mttc1 t5,\$f14
0+0b28 <[^>]*> 418d7023 cttc1 t5,\$14
0+0b2c <[^>]*> 418d7024 mttc2 t5,\$14
0+0b30 <[^>]*> 418d7025 cttc2 t5,\$14
0+0b34 <[^>]*> 418d7026 mttr t5,t6,1,6,0
0+0b38 <[^>]*> 418d7027 mttr t5,t6,1,7,0
0+0b3c <[^>]*> 418d7010 mttr t5,t6,0,0,1
0+0b40 <[^>]*> 418d7011 mttr t5,t6,0,1,1
0+0b44 <[^>]*> 418d7012 mttr t5,t6,0,2,1
0+0b48 <[^>]*> 418d7013 mttr t5,t6,0,3,1
0+0b4c <[^>]*> 418d7014 mttr t5,t6,0,4,1
0+0b50 <[^>]*> 418d7015 mttr t5,t6,0,5,1
0+0b54 <[^>]*> 418d7016 mttr t5,t6,0,6,1
0+0b58 <[^>]*> 418d7017 mttr t5,t6,0,7,1
0+0b5c <[^>]*> 418d7000 mttc0 t5,c0_epc
0+0b60 <[^>]*> 418d7001 mttc0 t5,\$14,1
0+0b64 <[^>]*> 418d7002 mttc0 t5,\$14,2
0+0b68 <[^>]*> 418d7003 mttc0 t5,\$14,3
0+0b6c <[^>]*> 418d7004 mttc0 t5,\$14,4
0+0b70 <[^>]*> 418d7005 mttc0 t5,\$14,5
0+0b74 <[^>]*> 418d7006 mttc0 t5,\$14,6
0+0b78 <[^>]*> 418d7007 mttc0 t5,\$14,7
0+0b7c <[^>]*> 418d7010 mttr t5,t6,0,0,1
0+0b80 <[^>]*> 418d7011 mttr t5,t6,0,1,1
0+0b84 <[^>]*> 418d7012 mttr t5,t6,0,2,1
0+0b88 <[^>]*> 418d7013 mttr t5,t6,0,3,1
0+0b8c <[^>]*> 418d7014 mttr t5,t6,0,4,1
0+0b90 <[^>]*> 418d7015 mttr t5,t6,0,5,1
0+0b94 <[^>]*> 418d7016 mttr t5,t6,0,6,1
0+0b98 <[^>]*> 418d7017 mttr t5,t6,0,7,1
0+0b9c <[^>]*> 418d7000 mttc0 t5,c0_epc
0+0ba0 <[^>]*> 418d7001 mttc0 t5,\$14,1
0+0ba4 <[^>]*> 418d7002 mttc0 t5,\$14,2
0+0ba8 <[^>]*> 418d7003 mttc0 t5,\$14,3
0+0bac <[^>]*> 418d7004 mttc0 t5,\$14,4
0+0bb0 <[^>]*> 418d7005 mttc0 t5,\$14,5
0+0bb4 <[^>]*> 418d7006 mttc0 t5,\$14,6
0+0bb8 <[^>]*> 418d7007 mttc0 t5,\$14,7
0+0bbc <[^>]*> 418d7030 mttr t5,t6,1,0,1
0+0bc0 <[^>]*> 418d7031 mttr t5,t6,1,1,1
0+0bc4 <[^>]*> 418d7032 mtthc1 t5,\$f14
0+0bc8 <[^>]*> 418d7033 mttr t5,t6,1,3,1
0+0bcc <[^>]*> 418d7034 mtthc2 t5,\$14
0+0bd0 <[^>]*> 418d7035 mttr t5,t6,1,5,1
0+0bd4 <[^>]*> 418d7036 mttr t5,t6,1,6,1
0+0bd8 <[^>]*> 418d7037 mttr t5,t6,1,7,1
0+0bdc <[^>]*> 418d7020 mttgpr t5,t6
0+0be0 <[^>]*> 418d7021 mttacx t5,\$ac3
0+0be4 <[^>]*> 418d7022 mttc1 t5,\$f14
0+0be8 <[^>]*> 418d7023 cttc1 t5,\$14
0+0bec <[^>]*> 418d7024 mttc2 t5,\$14
0+0bf0 <[^>]*> 418d7025 cttc2 t5,\$14
0+0bf4 <[^>]*> 418d7026 mttr t5,t6,1,6,0
0+0bf8 <[^>]*> 418d7027 mttr t5,t6,1,7,0
0+0bfc <[^>]*> 418d7030 mttr t5,t6,1,0,1
0+0c00 <[^>]*> 418d7031 mttr t5,t6,1,1,1
0+0c04 <[^>]*> 418d7032 mtthc1 t5,\$f14
0+0c08 <[^>]*> 418d7033 mttr t5,t6,1,3,1
0+0c0c <[^>]*> 418d7034 mtthc2 t5,\$14
0+0c10 <[^>]*> 418d7035 mttr t5,t6,1,5,1
0+0c14 <[^>]*> 418d7036 mttr t5,t6,1,6,1
0+0c18 <[^>]*> 418d7037 mttr t5,t6,1,7,1
0+0c1c <[^>]*> 418d7020 mttgpr t5,t6
0+0c20 <[^>]*> 418d7021 mttacx t5,\$ac3
0+0c24 <[^>]*> 418d7022 mttc1 t5,\$f14
0+0c28 <[^>]*> 418d7023 cttc1 t5,\$14
0+0c2c <[^>]*> 418d7024 mttc2 t5,\$14
0+0c30 <[^>]*> 418d7025 cttc2 t5,\$14
0+0c34 <[^>]*> 418d7026 mttr t5,t6,1,6,0
0+0c38 <[^>]*> 418d7027 mttr t5,t6,1,7,0
0+0c3c <[^>]*> 418d7010 mttr t5,t6,0,0,1
0+0c40 <[^>]*> 418d7011 mttr t5,t6,0,1,1
0+0c44 <[^>]*> 418d7012 mttr t5,t6,0,2,1
0+0c48 <[^>]*> 418d7013 mttr t5,t6,0,3,1
0+0c4c <[^>]*> 418d7014 mttr t5,t6,0,4,1
0+0c50 <[^>]*> 418d7015 mttr t5,t6,0,5,1
0+0c54 <[^>]*> 418d7016 mttr t5,t6,0,6,1
0+0c58 <[^>]*> 418d7017 mttr t5,t6,0,7,1
0+0c5c <[^>]*> 418d7000 mttc0 t5,c0_epc
0+0c60 <[^>]*> 418d7001 mttc0 t5,\$14,1
0+0c64 <[^>]*> 418d7002 mttc0 t5,\$14,2
0+0c68 <[^>]*> 418d7003 mttc0 t5,\$14,3
0+0c6c <[^>]*> 418d7004 mttc0 t5,\$14,4
0+0c70 <[^>]*> 418d7005 mttc0 t5,\$14,5
0+0c74 <[^>]*> 418d7006 mttc0 t5,\$14,6
0+0c78 <[^>]*> 418d7007 mttc0 t5,\$14,7
0+0c7c <[^>]*> 418d7010 mttr t5,t6,0,0,1
0+0c80 <[^>]*> 418d7011 mttr t5,t6,0,1,1
0+0c84 <[^>]*> 418d7012 mttr t5,t6,0,2,1
0+0c88 <[^>]*> 418d7013 mttr t5,t6,0,3,1
0+0c8c <[^>]*> 418d7014 mttr t5,t6,0,4,1
0+0c90 <[^>]*> 418d7015 mttr t5,t6,0,5,1
0+0c94 <[^>]*> 418d7016 mttr t5,t6,0,6,1
0+0c98 <[^>]*> 418d7017 mttr t5,t6,0,7,1
0+0c9c <[^>]*> 418d7000 mttc0 t5,c0_epc
0+0ca0 <[^>]*> 418d7001 mttc0 t5,\$14,1
0+0ca4 <[^>]*> 418d7002 mttc0 t5,\$14,2
0+0ca8 <[^>]*> 418d7003 mttc0 t5,\$14,3
0+0cac <[^>]*> 418d7004 mttc0 t5,\$14,4
0+0cb0 <[^>]*> 418d7005 mttc0 t5,\$14,5
0+0cb4 <[^>]*> 418d7006 mttc0 t5,\$14,6
0+0cb8 <[^>]*> 418d7007 mttc0 t5,\$14,7
...
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [patch] GAS supports for MIPS32 MT ASE
2005-08-29 23:23 ` Chao-ying Fu
@ 2005-08-29 23:41 ` Thiemo Seufer
2005-08-30 22:54 ` Chao-ying Fu
0 siblings, 1 reply; 15+ messages in thread
From: Thiemo Seufer @ 2005-08-29 23:41 UTC (permalink / raw)
To: Chao-ying Fu
Cc: Maciej W. Rozycki, Eric Christopher, Thekkath, Radhika, binutils
Chao-ying Fu wrote:
> Ok. I fixed all the issues except the option name
> -mt/-mno-mt, because it seems redundant to have two "m"s (-mmt).
> Any suggestion?
It really should be -mmt/-mno-mt in order to be compatible to the gcc
conventions. This avoids hackery in the gcc driver like it was needed
to distinguish -mipsN from -m<linker-emulation>, especially in the
light of future generic options which may start with -m.
Thiemo
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [patch] GAS supports for MIPS32 MT ASE
2005-08-29 23:41 ` Thiemo Seufer
@ 2005-08-30 22:54 ` Chao-ying Fu
2005-08-30 22:57 ` Eric Christopher
0 siblings, 1 reply; 15+ messages in thread
From: Chao-ying Fu @ 2005-08-30 22:54 UTC (permalink / raw)
To: Thiemo Seufer
Cc: Maciej W. Rozycki, Eric Christopher, Thekkath, Radhika, binutils
Ok. I will use -mmt/-mno-mt.
But, not all GAS options have the same style.
Ex, -mips16/-no-mips16, -mips3d/-no-mips3d
Should the options be -mmips16/-mno-mips16 and
-mmips3d/-mno-mips3d?
Regards,
Chao-ying
----- Original Message -----
From: "Thiemo Seufer" <ths@networkno.de>
To: "Chao-ying Fu" <fu@mips.com>
Cc: "Maciej W. Rozycki" <macro@linux-mips.org>; "Eric Christopher"
<echristo@apple.com>; "Thekkath, Radhika" <radhika@mips.com>;
<binutils@sourceware.org>
Sent: Monday, August 29, 2005 4:41 PM
Subject: Re: [patch] GAS supports for MIPS32 MT ASE
> Chao-ying Fu wrote:
> > Ok. I fixed all the issues except the option name
> > -mt/-mno-mt, because it seems redundant to have two "m"s (-mmt).
> > Any suggestion?
>
> It really should be -mmt/-mno-mt in order to be compatible to the gcc
> conventions. This avoids hackery in the gcc driver like it was needed
> to distinguish -mipsN from -m<linker-emulation>, especially in the
> light of future generic options which may start with -m.
>
>
> Thiemo
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [patch] GAS supports for MIPS32 MT ASE
2005-08-30 22:54 ` Chao-ying Fu
@ 2005-08-30 22:57 ` Eric Christopher
2005-08-30 23:01 ` Daniel Jacobowitz
0 siblings, 1 reply; 15+ messages in thread
From: Eric Christopher @ 2005-08-30 22:57 UTC (permalink / raw)
To: Chao-ying Fu
Cc: Thiemo Seufer, Maciej W. Rozycki, Thekkath, Radhika, binutils
On Aug 30, 2005, at 3:53 PM, Chao-ying Fu wrote:
> Ok. I will use -mmt/-mno-mt.
> But, not all GAS options have the same style.
> Ex, -mips16/-no-mips16, -mips3d/-no-mips3d
> Should the options be -mmips16/-mno-mips16 and
> -mmips3d/-mno-mips3d?
Those are historical (with the exception of the mips3d stuff), and in
general we should use -m<option>.
I don't think this justifies being a special case, unless you wanted
to name it -mips-mt.
-eric
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [patch] GAS supports for MIPS32 MT ASE
2005-08-30 22:57 ` Eric Christopher
@ 2005-08-30 23:01 ` Daniel Jacobowitz
2005-08-31 0:25 ` Eric Christopher
0 siblings, 1 reply; 15+ messages in thread
From: Daniel Jacobowitz @ 2005-08-30 23:01 UTC (permalink / raw)
To: Eric Christopher
Cc: Chao-ying Fu, Thiemo Seufer, Maciej W. Rozycki, Thekkath,
Radhika, binutils
On Tue, Aug 30, 2005 at 03:56:50PM -0700, Eric Christopher wrote:
>
> On Aug 30, 2005, at 3:53 PM, Chao-ying Fu wrote:
>
> > Ok. I will use -mmt/-mno-mt.
> >But, not all GAS options have the same style.
> >Ex, -mips16/-no-mips16, -mips3d/-no-mips3d
> >Should the options be -mmips16/-mno-mips16 and
> >-mmips3d/-mno-mips3d?
>
> Those are historical (with the exception of the mips3d stuff), and in
> general we should use -m<option>.
>
> I don't think this justifies being a special case, unless you wanted
> to name it -mips-mt.
... please don't. The other options should be fixed and only
compatibility aliases kept, IMO.
--
Daniel Jacobowitz
CodeSourcery, LLC
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [patch] GAS supports for MIPS32 MT ASE
2005-08-30 23:01 ` Daniel Jacobowitz
@ 2005-08-31 0:25 ` Eric Christopher
2005-08-31 0:49 ` Chao-ying Fu
0 siblings, 1 reply; 15+ messages in thread
From: Eric Christopher @ 2005-08-31 0:25 UTC (permalink / raw)
To: Daniel Jacobowitz
Cc: Chao-ying Fu, Thiemo Seufer, Maciej W. Rozycki, Thekkath,
Radhika, binutils
>
> ... please don't. The other options should be fixed and only
> compatibility aliases kept, IMO.
OK. :)
I didn't have a strong opinion either way.
-eric
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [patch] GAS supports for MIPS32 MT ASE
2005-08-31 0:25 ` Eric Christopher
@ 2005-08-31 0:49 ` Chao-ying Fu
2005-09-02 12:15 ` Thiemo Seufer
0 siblings, 1 reply; 15+ messages in thread
From: Chao-ying Fu @ 2005-08-31 0:49 UTC (permalink / raw)
To: Eric Christopher
Cc: Daniel Jacobowitz, Thiemo Seufer, Maciej W. Rozycki, Thekkath,
Radhika, binutils
[-- Attachment #1: Type: text/plain, Size: 2683 bytes --]
Hello,
Here is the latest patch with the change: -mmt/-mno-mt.
Also, "mips32-mt.d" is changed to use "-mmt".
I built and tested for mipsisa32-elf and mipsisa64-elf. No
new regression. Any comments? Thanks!
Regards,
Chao-ying
include/opcode/ChangeLog
2005-08-30 Chao-ying Fu <fu@mips.com>
* mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
define.
Document !, $, *, &, g, +t, +T operand formats for MT instructions.
(INSN_ASE_MASK): Update to include INSN_MT.
(INSN_MT): New define for MT ASE.
opcodes/ChangeLog
2005-08-30 Chao-ying Fu <fu@mips.com>
* mips-opc.c (MT32): New define.
(mips_builtin_opcodes): Move "bc0f", "bc0fl", "bc0t", "bc0tl" to the
bottom to avoid opcode collision with "mftr" and "mttr".
Add MT instructions.
* mips-dis.c (mips_arch_choices): Enable INSN_MT for mips32r2.
(print_insn_args): Add supports for +t, +T, !, $, *, &, g operand
formats.
gas/ChangeLog
2005-08-30 Chao-ying Fu <fu@mips.com>
* config/tc-mips.c (mips_set_options): Add ase_mt for MT instructions.
(mips_opts): Add -1 to initialize ase_mt.
(file_ase_mt): New variable for -mmt.
(CPU_HAS_MT): New define.
(validate_mips_insn): Add supports for +t, +T, !, $, *, &, g operand
formats.
(mips_ip): Check ase_mt to enable MT instructions.
Handle !, $, *, &, +T, +t, g operand formats.
For "mftc1", "mfthc1", "cftc1", "mttc1", "mtthc1", "cttc1", we allow
odd float registers.
(OPTION_MT, OPTION_NO_MT): New define.
(OPTION_COMPAT_ARCH_BASE): Change because of inserting MT define.
(md_parse_option): Parse OPTION_MT and OPTION_NO_MT.
(mips_after_parse_args): Set ase_mt based on CPU.
(s_mipsset): Handle ".set mt" and ".set nomt".
(mips_elf_final_processing): Remind of adding new flag for MT ASE.
(md_show_usage): Show usage of -mmt and -mno-mt.
gas/testsuite/ChangeLog
2005-08-30 Chao-ying Fu <fu@mips.com>
* gas/mips/mips.exp: Run MT test for mips32r2 only.
* gas/mips/mips32-mt.[sdl]: New test.
----- Original Message -----
From: "Eric Christopher" <echristo@apple.com>
To: "Daniel Jacobowitz" <drow@false.org>
Cc: "Chao-ying Fu" <fu@mips.com>; "Thiemo Seufer" <ths@networkno.de>;
"Maciej W. Rozycki" <macro@linux-mips.org>; "Thekkath, Radhika"
<radhika@mips.com>; <binutils@sourceware.org>
Sent: Tuesday, August 30, 2005 5:25 PM
Subject: Re: [patch] GAS supports for MIPS32 MT ASE
> >
> > ... please don't. The other options should be fixed and only
> > compatibility aliases kept, IMO.
>
> OK. :)
>
> I didn't have a strong opinion either way.
>
> -eric
>
[-- Attachment #2: src.diff --]
[-- Type: application/octet-stream, Size: 29956 bytes --]
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.44
diff -c -3 -p -r1.44 mips.h
*** include/opcode/mips.h 25 Aug 2005 18:09:24 -0000 1.44
--- include/opcode/mips.h 31 Aug 2005 00:10:28 -0000
*************** Software Foundation, 51 Franklin Street
*** 170,175 ****
--- 170,185 ----
#define OP_SH_RDDSP 16
#define OP_MASK_RDDSP 0x3f
+ /* MIPS MT ASE */
+ #define OP_SH_MT_U 5
+ #define OP_MASK_MT_U 0x1
+ #define OP_SH_MT_H 4
+ #define OP_MASK_MT_H 0x1
+ #define OP_SH_MTACC_T 18
+ #define OP_MASK_MTACC_T 0x3
+ #define OP_SH_MTACC_D 13
+ #define OP_MASK_MTACC_D 0x3
+
#define OP_OP_COP0 0x10
#define OP_OP_COP1 0x11
#define OP_OP_COP2 0x12
*************** struct mips_opcode
*** 331,336 ****
--- 341,355 ----
"'" 6 bit unsigned immediate (OP_*_RDDSP)
"@" 10 bit signed immediate (OP_*_IMM10)
+ MT ASE usage:
+ "!" 1 bit immediate at bit 5
+ "$" 1 bit immediate at bit 4
+ "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
+ "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
+ "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
+ "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
+ "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
+
Other:
"()" parens surrounding optional value
"," separates operands
*************** struct mips_opcode
*** 339,351 ****
Characters used so far, for quick reference when adding more:
"34567890"
! "%[]<>(),+:'@"
"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
! "abcdefhijklopqrstuvwxz"
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
! "ABCDEFGHI"
*/
/* These are the bits which may be set in the pinfo field of an
--- 358,371 ----
Characters used so far, for quick reference when adding more:
"34567890"
! "%[]<>(),+:'@!$*&"
"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
! "abcdefghijklopqrstuvwxz"
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
! "ABCDEFGHIT"
! "t"
*/
/* These are the bits which may be set in the pinfo field of an
*************** struct mips_opcode
*** 447,453 ****
#define INSN_ISA64R2 0x00000100
/* Masks used for MIPS-defined ASEs. */
! #define INSN_ASE_MASK 0x0000f000
/* DSP ASE */
#define INSN_DSP 0x00001000
--- 467,473 ----
#define INSN_ISA64R2 0x00000100
/* Masks used for MIPS-defined ASEs. */
! #define INSN_ASE_MASK 0x0400f000
/* DSP ASE */
#define INSN_DSP 0x00001000
*************** struct mips_opcode
*** 480,485 ****
--- 500,507 ----
#define INSN_5400 0x01000000
/* NEC VR5500 instruction. */
#define INSN_5500 0x02000000
+ /* MT ASE */
+ #define INSN_MT 0x04000000
/* MIPS ISA defines, use instead of hardcoding ISA level. */
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.52
diff -c -3 -p -r1.52 mips-opc.c
*** opcodes/mips-opc.c 25 Aug 2005 18:12:43 -0000 1.52
--- opcodes/mips-opc.c 31 Aug 2005 00:10:29 -0000
*************** Software Foundation, 51 Franklin Street
*** 146,151 ****
--- 146,154 ----
#define DSP_VOLA INSN_TRAP
#define D32 (INSN_DSP)
+ /* MIPS MT ASE support. */
+ #define MT32 (INSN_MT)
+
/* The order of overloaded instructions matters. Label arguments and
register arguments look the same. Instructions that can have either
for arguments must apear in the correct order in this table for the
*************** const struct mips_opcode mips_builtin_op
*** 220,229 ****
{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 },
/* b is at the top of the table. */
/* bal is at the top of the table. */
! {"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1 },
! {"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
! {"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1 },
! {"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
{"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
{"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
{"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
--- 223,229 ----
{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 },
/* b is at the top of the table. */
/* bal is at the top of the table. */
! /* bc0[tf]l? are at the bottom of the table. */
{"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
{"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
{"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
*************** const struct mips_opcode mips_builtin_op
*** 469,474 ****
--- 469,477 ----
{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 },
/* cfc2 is at the bottom of the table. */
{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 },
+ {"cftc1", "d,E", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 },
+ {"cftc1", "d,T", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 },
+ {"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
*************** const struct mips_opcode mips_builtin_op
*** 476,481 ****
--- 479,487 ----
{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 },
/* ctc2 is at the bottom of the table. */
{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
+ {"cttc1", "t,g", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 },
+ {"cttc1", "t,S", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 },
+ {"cttc2", "t,g", 0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC, 0, MT32 },
{"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, 0, I3 },
{"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_D|FP_S, 0, I1 },
{"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 },
*************** const struct mips_opcode mips_builtin_op
*** 556,561 ****
--- 562,569 ----
{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3 },
{"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 },
{"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 },
+ {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, MT32 },
+ {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3 },
{"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 },
{"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 },
*************** const struct mips_opcode mips_builtin_op
*** 620,628 ****
--- 628,642 ----
{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3 },
{"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3 },
+ {"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, MT32 },
+ {"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
{"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 },
{"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 },
+ {"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 },
+ {"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
{"eret", "", 0x42000018, 0xffffffff, 0, 0, I3|I32 },
+ {"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, MT32 },
+ {"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33 },
{"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, 0, I3 },
{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S, 0, I3 },
*************** const struct mips_opcode mips_builtin_op
*** 719,724 ****
--- 733,739 ----
{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 },
{"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */
{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I2 }, /* as lwr */
+ {"fork", "d,s,t", 0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t, 0, MT32 },
{"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 },
{"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3 },
{"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, 0, I4 },
*************** const struct mips_opcode mips_builtin_op
*** 755,760 ****
--- 770,793 ----
{"max.qh", "X,Y,Q", 0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
{"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 },
{"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 },
+ {"mftacx", "d", 0x41020021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
+ {"mftacx", "d,*", 0x41020021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
+ {"mftc0", "d,+t", 0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0, 0, MT32 },
+ {"mftc0", "d,+T", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 },
+ {"mftc0", "d,E,H", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 },
+ {"mftc1", "d,T", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 },
+ {"mftc1", "d,E", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 },
+ {"mftc2", "d,E", 0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
+ {"mftdsp", "d", 0x41100021, 0xffff07ff, TRAP|WR_d, 0, MT32 },
+ {"mftgpr", "d,t", 0x41000020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 },
+ {"mfthc1", "d,T", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 },
+ {"mfthc1", "d,E", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 },
+ {"mfthc2", "d,E", 0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
+ {"mfthi", "d", 0x41010021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
+ {"mfthi", "d,*", 0x41010021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
+ {"mftlo", "d", 0x41000021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
+ {"mftlo", "d,*", 0x41000021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
+ {"mftr", "t,d,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d, 0, MT32 },
{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 },
{"mfc0", "t,+D", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 },
{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 },
*************** const struct mips_opcode mips_builtin_op
*** 836,841 ****
--- 869,892 ----
{"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_s|WR_HI, 0, D32 },
{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 },
{"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_s|WR_LO, 0, D32 },
+ {"mttc0", "t,G", 0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
+ {"mttc0", "t,+D", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
+ {"mttc0", "t,G,H", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
+ {"mttc1", "t,S", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 },
+ {"mttc1", "t,G", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 },
+ {"mttc2", "t,g", 0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 },
+ {"mttacx", "t", 0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
+ {"mttacx", "t,&", 0x41801021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },
+ {"mttdsp", "t", 0x41808021, 0xffe0ffff, TRAP|RD_t, 0, MT32 },
+ {"mttgpr", "t,d", 0x41800020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 },
+ {"mtthc1", "t,S", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 },
+ {"mtthc1", "t,G", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 },
+ {"mtthc2", "t,g", 0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 },
+ {"mtthi", "t", 0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
+ {"mtthi", "t,&", 0x41800821, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },
+ {"mttlo", "t", 0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
+ {"mttlo", "t,&", 0x41800021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },
+ {"mttr", "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t, 0, MT32 },
{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 },
{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
{"mul.ob", "X,Y,Q", 0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
*************** const struct mips_opcode mips_builtin_op
*** 1209,1214 ****
--- 1260,1267 ----
{"xor.ob", "D,S,k", 0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
{"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, 0, I1 },
+ {"yield", "s", 0x7c000009, 0xfc1fffff, TRAP|RD_s, 0, MT32 },
+ {"yield", "d,s", 0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s, 0, MT32 },
/* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
instructions so they are here for the latters to take precedence. */
*************** const struct mips_opcode mips_builtin_op
*** 1352,1357 ****
--- 1405,1415 ----
{"subu_s.qb", "d,s,t", 0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"wrdsp", "s", 0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA, 0, D32 },
{"wrdsp", "s,8", 0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA, 0, D32 },
+ /* Move bc0* after mftr and mttr to avoid opcode collision. */
+ {"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1 },
+ {"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
+ {"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1 },
+ {"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
};
#define MIPS_NUM_OPCODES \
Index: opcodes/mips-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-dis.c,v
retrieving revision 1.53
diff -c -3 -p -r1.53 mips-dis.c
*** opcodes/mips-dis.c 25 Aug 2005 18:12:44 -0000 1.53
--- opcodes/mips-dis.c 31 Aug 2005 00:10:29 -0000
*************** const struct mips_arch_choice mips_arch_
*** 376,382 ****
mips_hwr_names_numeric },
{ "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
! ISA_MIPS32R2 | INSN_MIPS16 | INSN_DSP,
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_hwr_names_mips3264r2 },
--- 376,382 ----
mips_hwr_names_numeric },
{ "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
! ISA_MIPS32R2 | INSN_MIPS16 | INSN_DSP | INSN_MT,
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_hwr_names_mips3264r2 },
*************** print_insn_args (const char *d,
*** 771,776 ****
--- 771,804 ----
(*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
break;
+ case 't': /* Coprocessor 0 reg name */
+ (*info->fprintf_func) (info->stream, "%s",
+ mips_cp0_names[(l >> OP_SH_RT) &
+ OP_MASK_RT]);
+ break;
+
+ case 'T': /* Coprocessor 0 reg name */
+ {
+ const struct mips_cp0sel_name *n;
+ unsigned int cp0reg, sel;
+
+ cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
+ sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
+
+ /* CP0 register including 'sel' code for mftc0, to be
+ printed textually if known. If not known, print both
+ CP0 register name and sel numerically since CP0 register
+ with sel 0 may have a name unrelated to register being
+ printed. */
+ n = lookup_mips_cp0sel_name(mips_cp0sel_names,
+ mips_cp0sel_names_len, cp0reg, sel);
+ if (n != NULL)
+ (*info->fprintf_func) (info->stream, "%s", n->name);
+ else
+ (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
+ break;
+ }
+
default:
/* xgettext:c-format */
(*info->fprintf_func) (info->stream,
*************** print_insn_args (const char *d,
*** 841,846 ****
--- 869,900 ----
(*info->fprintf_func) (info->stream, "%d", delta);
break;
+ case '!':
+ (*info->fprintf_func) (info->stream, "%ld",
+ (l >> OP_SH_MT_U) & OP_MASK_MT_U);
+ break;
+
+ case '$':
+ (*info->fprintf_func) (info->stream, "%ld",
+ (l >> OP_SH_MT_H) & OP_MASK_MT_H);
+ break;
+
+ case '*':
+ (*info->fprintf_func) (info->stream, "$ac%ld",
+ (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
+ break;
+
+ case '&':
+ (*info->fprintf_func) (info->stream, "$ac%ld",
+ (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
+ break;
+
+ case 'g':
+ /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
+ (*info->fprintf_func) (info->stream, "$%ld",
+ (l >> OP_SH_RD) & OP_MASK_RD);
+ break;
+
case 's':
case 'b':
case 'r':
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.318
diff -c -3 -p -r1.318 tc-mips.c
*** gas/config/tc-mips.c 25 Aug 2005 18:17:36 -0000 1.318
--- gas/config/tc-mips.c 31 Aug 2005 00:10:31 -0000
*************** struct mips_set_options
*** 194,199 ****
--- 194,200 ----
int ase_mips3d;
int ase_mdmx;
int ase_dsp;
+ int ase_mt;
/* Whether we are assembling for the mips16 processor. 0 if we are
not, 1 if we are, and -1 if the value has not been initialized.
Changed by `.set mips16' and `.set nomips16', and the -mips16 and
*************** static int file_mips_fp32 = -1;
*** 244,250 ****
static struct mips_set_options mips_opts =
{
! ISA_UNKNOWN, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE
};
/* These variables are filled in with the masks of registers used.
--- 245,251 ----
static struct mips_set_options mips_opts =
{
! ISA_UNKNOWN, -1, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE
};
/* These variables are filled in with the masks of registers used.
*************** static int file_ase_mdmx;
*** 272,277 ****
--- 273,282 ----
command line (e.g., by -march). */
static int file_ase_dsp;
+ /* True if -mmt was passed or implied by arguments passed on the
+ command line (e.g., by -march). */
+ static int file_ase_mt;
+
/* The argument of the -march= flag. The architecture we are assembling. */
static int file_mips_arch = CPU_UNKNOWN;
static const char *mips_arch_string;
*************** static int mips_32bitmode = 0;
*** 374,379 ****
--- 379,388 ----
#define CPU_HAS_DSP(cpu) (FALSE \
)
+ /* Return true if the given CPU supports the MT ASE. */
+ #define CPU_HAS_MT(cpu) (FALSE \
+ )
+
/* True if CPU has a dror instruction. */
#define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
*************** validate_mips_insn (const struct mips_op
*** 7765,7770 ****
--- 7774,7782 ----
case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
case 'I': break;
+ case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
+ case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
+ USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
default:
as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
c, opc->name, opc->args);
*************** validate_mips_insn (const struct mips_op
*** 7837,7842 ****
--- 7849,7859 ----
case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
+ case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
+ case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
+ case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
+ case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
+ case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
default:
as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
c, opc->name, opc->args);
*************** mips_ip (char *str, struct mips_cl_insn
*** 7935,7940 ****
--- 7952,7958 ----
| (file_ase_mips16 ? INSN_MIPS16 : 0)
| (mips_opts.ase_mdmx ? INSN_MDMX : 0)
| (mips_opts.ase_dsp ? INSN_DSP : 0)
+ | (mips_opts.ase_mt ? INSN_MT : 0)
| (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
mips_opts.arch))
ok = TRUE;
*************** mips_ip (char *str, struct mips_cl_insn
*** 8156,8161 ****
--- 8174,8233 ----
s = expr_end;
continue;
+ case '!': /* mt 1-bit unsigned immediate in bit 5 */
+ my_getExpression (&imm_expr, s);
+ check_absolute_expr (ip, &imm_expr);
+ if (imm_expr.X_add_number & ~OP_MASK_MT_U)
+ {
+ as_warn (_("MT immediate not in range 0..%d (%lu)"),
+ OP_MASK_MT_U, (unsigned long) imm_expr.X_add_number);
+ imm_expr.X_add_number &= OP_MASK_MT_U;
+ }
+ ip->insn_opcode |= imm_expr.X_add_number << OP_SH_MT_U;
+ imm_expr.X_op = O_absent;
+ s = expr_end;
+ continue;
+
+ case '$': /* mt 1-bit unsigned immediate in bit 4 */
+ my_getExpression (&imm_expr, s);
+ check_absolute_expr (ip, &imm_expr);
+ if (imm_expr.X_add_number & ~OP_MASK_MT_H)
+ {
+ as_warn (_("MT immediate not in range 0..%d (%lu)"),
+ OP_MASK_MT_H, (unsigned long) imm_expr.X_add_number);
+ imm_expr.X_add_number &= OP_MASK_MT_H;
+ }
+ ip->insn_opcode |= imm_expr.X_add_number << OP_SH_MT_H;
+ imm_expr.X_op = O_absent;
+ s = expr_end;
+ continue;
+
+ case '*': /* four dsp accumulators in bits 18,19 */
+ if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
+ s[3] >= '0' && s[3] <= '3')
+ {
+ regno = s[3] - '0';
+ s += 4;
+ ip->insn_opcode |= regno << OP_SH_MTACC_T;
+ continue;
+ }
+ else
+ as_bad (_("Invalid dsp/smartmips acc register"));
+ break;
+
+ case '&': /* four dsp accumulators in bits 13,14 */
+ if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
+ s[3] >= '0' && s[3] <= '3')
+ {
+ regno = s[3] - '0';
+ s += 4;
+ ip->insn_opcode |= regno << OP_SH_MTACC_D;
+ continue;
+ }
+ else
+ as_bad (_("Invalid dsp/smartmips acc register"));
+ break;
+
case ',':
if (*s++ == *args)
continue;
*************** do_msbd:
*** 8308,8313 ****
--- 8380,8413 ----
s = expr_end;
continue;
+ case 'T': /* Coprocessor register */
+ /* +T is for disassembly only; never match. */
+ break;
+
+ case 't': /* Coprocessor register number */
+ if (s[0] == '$' && ISDIGIT (s[1]))
+ {
+ ++s;
+ regno = 0;
+ do
+ {
+ regno *= 10;
+ regno += *s - '0';
+ ++s;
+ }
+ while (ISDIGIT (*s));
+ if (regno > 31)
+ as_bad (_("Invalid register number (%d)"), regno);
+ else
+ {
+ ip->insn_opcode |= regno << OP_SH_RT;
+ continue;
+ }
+ }
+ else
+ as_bad (_("Invalid coprocessor 0 register number"));
+ break;
+
default:
as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
*args, insn->name, insn->args);
*************** do_msbd:
*** 8442,8447 ****
--- 8542,8548 ----
case 'x': /* ignore register name */
case 'z': /* must be zero register */
case 'U': /* destination register (clo/clz). */
+ case 'g': /* coprocessor destination register */
s_reset = s;
if (s[0] == '$')
{
*************** do_msbd:
*** 8566,8571 ****
--- 8667,8673 ----
case 'd':
case 'G':
case 'K':
+ case 'g':
INSERT_OPERAND (RD, *ip, regno);
break;
case 'U':
*************** do_msbd:
*** 8681,8687 ****
|| strcmp (str, "lwc1") == 0
|| strcmp (str, "swc1") == 0
|| strcmp (str, "l.s") == 0
! || strcmp (str, "s.s") == 0))
as_warn (_("Float register should be even, was %d"),
regno);
--- 8783,8795 ----
|| strcmp (str, "lwc1") == 0
|| strcmp (str, "swc1") == 0
|| strcmp (str, "l.s") == 0
! || strcmp (str, "s.s") == 0
! || strcmp (str, "mftc1") == 0
! || strcmp (str, "mfthc1") == 0
! || strcmp (str, "cftc1") == 0
! || strcmp (str, "mttc1") == 0
! || strcmp (str, "mtthc1") == 0
! || strcmp (str, "cttc1") == 0))
as_warn (_("Float register should be even, was %d"),
regno);
*************** struct option md_longopts[] =
*** 10222,10230 ****
{"mdsp", no_argument, NULL, OPTION_DSP},
#define OPTION_NO_DSP (OPTION_ASE_BASE + 7)
{"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
/* Old-style architecture options. Don't add more of these. */
! #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 8)
#define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
{"m4650", no_argument, NULL, OPTION_M4650},
#define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
--- 10330,10342 ----
{"mdsp", no_argument, NULL, OPTION_DSP},
#define OPTION_NO_DSP (OPTION_ASE_BASE + 7)
{"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
+ #define OPTION_MT (OPTION_ASE_BASE + 8)
+ {"mmt", no_argument, NULL, OPTION_MT},
+ #define OPTION_NO_MT (OPTION_ASE_BASE + 9)
+ {"mno-mt", no_argument, NULL, OPTION_NO_MT},
/* Old-style architecture options. Don't add more of these. */
! #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 10)
#define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
{"m4650", no_argument, NULL, OPTION_M4650},
#define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
*************** md_parse_option (int c, char *arg)
*** 10484,10489 ****
--- 10596,10609 ----
mips_opts.ase_dsp = 0;
break;
+ case OPTION_MT:
+ mips_opts.ase_mt = 1;
+ break;
+
+ case OPTION_NO_MT:
+ mips_opts.ase_mt = 0;
+ break;
+
case OPTION_MIPS16:
mips_opts.mips16 = 1;
mips_no_prev_insn ();
*************** mips_after_parse_args (void)
*** 10840,10851 ****
--- 10960,10974 ----
mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0;
if (mips_opts.ase_dsp == -1)
mips_opts.ase_dsp = (CPU_HAS_DSP (file_mips_arch)) ? 1 : 0;
+ if (mips_opts.ase_mt == -1)
+ mips_opts.ase_mt = (CPU_HAS_MT (file_mips_arch)) ? 1 : 0;
file_mips_isa = mips_opts.isa;
file_ase_mips16 = mips_opts.mips16;
file_ase_mips3d = mips_opts.ase_mips3d;
file_ase_mdmx = mips_opts.ase_mdmx;
file_ase_dsp = mips_opts.ase_dsp;
+ file_ase_mt = mips_opts.ase_mt;
mips_opts.gp32 = file_mips_gp32;
mips_opts.fp32 = file_mips_fp32;
*************** s_mipsset (int x ATTRIBUTE_UNUSED)
*** 11787,11792 ****
--- 11910,11919 ----
mips_opts.ase_dsp = 1;
else if (strcmp (name, "nodsp") == 0)
mips_opts.ase_dsp = 0;
+ else if (strcmp (name, "mt") == 0)
+ mips_opts.ase_mt = 1;
+ else if (strcmp (name, "nomt") == 0)
+ mips_opts.ase_mt = 0;
else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
{
int reset = 0;
*************** mips_elf_final_processing (void)
*** 13523,13528 ****
--- 13650,13657 ----
/* Set MIPS ELF flags for ASEs. */
/* We may need to define a new flag for DSP ASE, and set this flag when
file_ase_dsp is true. */
+ /* We may need to define a new flag for MT ASE, and set this flag when
+ file_ase_mt is true. */
if (file_ase_mips16)
elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
#if 0 /* XXX FIXME */
*************** MIPS options:\n\
*** 14230,14235 ****
--- 14359,14367 ----
-mdsp generate DSP instructions\n\
-mno-dsp do not generate DSP instructions\n"));
fprintf (stream, _("\
+ -mmt generate MT instructions\n\
+ -mno-mt do not generate MT instructions\n"));
+ fprintf (stream, _("\
-mfix-vr4120 work around certain VR4120 errata\n\
-mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
-mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.108
diff -c -3 -p -r1.108 mips.exp
*** gas/testsuite/gas/mips/mips.exp 25 Aug 2005 18:21:47 -0000 1.108
--- gas/testsuite/gas/mips/mips.exp 31 Aug 2005 00:10:31 -0000
*************** if { [istarget mips*-*-*] } then {
*** 763,768 ****
--- 763,769 ----
run_list_test "noat-7" ""
run_dump_test_arches "mips32-dsp" [mips_arch_list_matching mips32 !sb1]
+ run_dump_test_arches "mips32-mt" [mips_arch_list_matching mips32r2 !gpr64]
if { $elf && !$no_mips16 } {
run_dump_test "mips16-dwarf2"
[-- Attachment #3: mips32-mt.s --]
[-- Type: application/octet-stream, Size: 15991 bytes --]
# source file to test assembly of MIPS MT ASE for MIPS32 instructions
.set noreorder
.set noat
.text
text_label:
dmt
dmt $31
dvpe
dvpe $1
emt
emt $2
evpe
evpe $3
fork $4,$5,$6
yield $5
yield $6,$7
mftc0 $7,$8
mftc0 $8,$0,0
mftc0 $8,$0,1
mftc0 $8,$0,2
mftc0 $8,$0,3
mftc0 $8,$0,4
mftc0 $8,$0,5
mftc0 $8,$0,6
mftc0 $8,$0,7
mftc0 $8,$1,0
mftc0 $8,$1,1
mftc0 $8,$1,2
mftc0 $8,$1,3
mftc0 $8,$1,4
mftc0 $8,$1,5
mftc0 $8,$1,6
mftc0 $8,$1,7
mftc0 $8,$2,0
mftc0 $8,$2,1
mftc0 $8,$2,2
mftc0 $8,$2,3
mftc0 $8,$2,4
mftc0 $8,$2,5
mftc0 $8,$2,6
mftc0 $8,$2,7
mftc0 $8,$3,0
mftc0 $8,$3,1
mftc0 $8,$3,2
mftc0 $8,$3,3
mftc0 $8,$3,4
mftc0 $8,$3,5
mftc0 $8,$3,6
mftc0 $8,$3,7
mftc0 $8,$4,0
mftc0 $8,$4,1
mftc0 $8,$4,2
mftc0 $8,$4,3
mftc0 $8,$4,4
mftc0 $8,$4,5
mftc0 $8,$4,6
mftc0 $8,$4,7
mftc0 $8,$5,0
mftc0 $8,$5,1
mftc0 $8,$5,2
mftc0 $8,$5,3
mftc0 $8,$5,4
mftc0 $8,$5,5
mftc0 $8,$5,6
mftc0 $8,$5,7
mftc0 $8,$6,0
mftc0 $8,$6,1
mftc0 $8,$6,2
mftc0 $8,$6,3
mftc0 $8,$6,4
mftc0 $8,$6,5
mftc0 $8,$6,6
mftc0 $8,$6,7
mftc0 $8,$7,0
mftc0 $8,$7,1
mftc0 $8,$7,2
mftc0 $8,$7,3
mftc0 $8,$7,4
mftc0 $8,$7,5
mftc0 $8,$7,6
mftc0 $8,$7,7
mftc0 $8,$8,0
mftc0 $8,$8,1
mftc0 $8,$8,2
mftc0 $8,$8,3
mftc0 $8,$8,4
mftc0 $8,$8,5
mftc0 $8,$8,6
mftc0 $8,$8,7
mftc0 $8,$9,0
mftc0 $8,$9,1
mftc0 $8,$9,2
mftc0 $8,$9,3
mftc0 $8,$9,4
mftc0 $8,$9,5
mftc0 $8,$9,6
mftc0 $8,$9,7
mftc0 $8,$10,0
mftc0 $8,$10,1
mftc0 $8,$10,2
mftc0 $8,$10,3
mftc0 $8,$10,4
mftc0 $8,$10,5
mftc0 $8,$10,6
mftc0 $8,$10,7
mftc0 $8,$11,0
mftc0 $8,$11,1
mftc0 $8,$11,2
mftc0 $8,$11,3
mftc0 $8,$11,4
mftc0 $8,$11,5
mftc0 $8,$11,6
mftc0 $8,$11,7
mftc0 $8,$12,0
mftc0 $8,$12,1
mftc0 $8,$12,2
mftc0 $8,$12,3
mftc0 $8,$12,4
mftc0 $8,$12,5
mftc0 $8,$12,6
mftc0 $8,$12,7
mftc0 $8,$13,0
mftc0 $8,$13,1
mftc0 $8,$13,2
mftc0 $8,$13,3
mftc0 $8,$13,4
mftc0 $8,$13,5
mftc0 $8,$13,6
mftc0 $8,$13,7
mftc0 $8,$14,0
mftc0 $8,$14,1
mftc0 $8,$14,2
mftc0 $8,$14,3
mftc0 $8,$14,4
mftc0 $8,$14,5
mftc0 $8,$14,6
mftc0 $8,$14,7
mftc0 $8,$15,0
mftc0 $8,$15,1
mftc0 $8,$15,2
mftc0 $8,$15,3
mftc0 $8,$15,4
mftc0 $8,$15,5
mftc0 $8,$15,6
mftc0 $8,$15,7
mftc0 $8,$16,0
mftc0 $8,$16,1
mftc0 $8,$16,2
mftc0 $8,$16,3
mftc0 $8,$16,4
mftc0 $8,$16,5
mftc0 $8,$16,6
mftc0 $8,$16,7
mftc0 $8,$17,0
mftc0 $8,$17,1
mftc0 $8,$17,2
mftc0 $8,$17,3
mftc0 $8,$17,4
mftc0 $8,$17,5
mftc0 $8,$17,6
mftc0 $8,$17,7
mftc0 $8,$18,0
mftc0 $8,$18,1
mftc0 $8,$18,2
mftc0 $8,$18,3
mftc0 $8,$18,4
mftc0 $8,$18,5
mftc0 $8,$18,6
mftc0 $8,$18,7
mftc0 $8,$19,0
mftc0 $8,$19,1
mftc0 $8,$19,2
mftc0 $8,$19,3
mftc0 $8,$19,4
mftc0 $8,$19,5
mftc0 $8,$19,6
mftc0 $8,$19,7
mftc0 $8,$20,0
mftc0 $8,$20,1
mftc0 $8,$20,2
mftc0 $8,$20,3
mftc0 $8,$20,4
mftc0 $8,$20,5
mftc0 $8,$20,6
mftc0 $8,$20,7
mftc0 $8,$21,0
mftc0 $8,$21,1
mftc0 $8,$21,2
mftc0 $8,$21,3
mftc0 $8,$21,4
mftc0 $8,$21,5
mftc0 $8,$21,6
mftc0 $8,$21,7
mftc0 $8,$22,0
mftc0 $8,$22,1
mftc0 $8,$22,2
mftc0 $8,$22,3
mftc0 $8,$22,4
mftc0 $8,$22,5
mftc0 $8,$22,6
mftc0 $8,$22,7
mftc0 $8,$23,0
mftc0 $8,$23,1
mftc0 $8,$23,2
mftc0 $8,$23,3
mftc0 $8,$23,4
mftc0 $8,$23,5
mftc0 $8,$23,6
mftc0 $8,$23,7
mftc0 $8,$24,0
mftc0 $8,$24,1
mftc0 $8,$24,2
mftc0 $8,$24,3
mftc0 $8,$24,4
mftc0 $8,$24,5
mftc0 $8,$24,6
mftc0 $8,$24,7
mftc0 $8,$25,0
mftc0 $8,$25,1
mftc0 $8,$25,2
mftc0 $8,$25,3
mftc0 $8,$25,4
mftc0 $8,$25,5
mftc0 $8,$25,6
mftc0 $8,$25,7
mftc0 $8,$26,0
mftc0 $8,$26,1
mftc0 $8,$26,2
mftc0 $8,$26,3
mftc0 $8,$26,4
mftc0 $8,$26,5
mftc0 $8,$26,6
mftc0 $8,$26,7
mftc0 $8,$27,0
mftc0 $8,$27,1
mftc0 $8,$27,2
mftc0 $8,$27,3
mftc0 $8,$27,4
mftc0 $8,$27,5
mftc0 $8,$27,6
mftc0 $8,$27,7
mftc0 $8,$28,0
mftc0 $8,$28,1
mftc0 $8,$28,2
mftc0 $8,$28,3
mftc0 $8,$28,4
mftc0 $8,$28,5
mftc0 $8,$28,6
mftc0 $8,$28,7
mftc0 $8,$29,0
mftc0 $8,$29,1
mftc0 $8,$29,2
mftc0 $8,$29,3
mftc0 $8,$29,4
mftc0 $8,$29,5
mftc0 $8,$29,6
mftc0 $8,$29,7
mftc0 $8,$30,0
mftc0 $8,$30,1
mftc0 $8,$30,2
mftc0 $8,$30,3
mftc0 $8,$30,4
mftc0 $8,$30,5
mftc0 $8,$30,6
mftc0 $8,$30,7
mftc0 $8,$31,0
mftc0 $8,$31,1
mftc0 $8,$31,2
mftc0 $8,$31,3
mftc0 $8,$31,4
mftc0 $8,$31,5
mftc0 $8,$31,6
mftc0 $8,$31,7
mftgpr $9,$10
mftlo $10
mftlo $11,$ac0
mfthi $12
mfthi $13,$ac1
mftacx $14
mftacx $15,$ac2
mftdsp $16
mftc1 $17,$f18
mftc1 $18,$19
mfthc1 $19,$f20
mfthc1 $20,$22
cftc1 $21,$22
cftc1 $22,$f23
mftc2 $23,$24
mfthc2 $24,$25
cftc2 $25,$26
mttc0 $26,$27
mttc0 $27,$0,0
mttc0 $27,$0,1
mttc0 $27,$0,2
mttc0 $27,$0,3
mttc0 $27,$0,4
mttc0 $27,$0,5
mttc0 $27,$0,6
mttc0 $27,$0,7
mttc0 $27,$1,0
mttc0 $27,$1,1
mttc0 $27,$1,2
mttc0 $27,$1,3
mttc0 $27,$1,4
mttc0 $27,$1,5
mttc0 $27,$1,6
mttc0 $27,$1,7
mttc0 $27,$2,0
mttc0 $27,$2,1
mttc0 $27,$2,2
mttc0 $27,$2,3
mttc0 $27,$2,4
mttc0 $27,$2,5
mttc0 $27,$2,6
mttc0 $27,$2,7
mttc0 $27,$3,0
mttc0 $27,$3,1
mttc0 $27,$3,2
mttc0 $27,$3,3
mttc0 $27,$3,4
mttc0 $27,$3,5
mttc0 $27,$3,6
mttc0 $27,$3,7
mttc0 $27,$4,0
mttc0 $27,$4,1
mttc0 $27,$4,2
mttc0 $27,$4,3
mttc0 $27,$4,4
mttc0 $27,$4,5
mttc0 $27,$4,6
mttc0 $27,$4,7
mttc0 $27,$5,0
mttc0 $27,$5,1
mttc0 $27,$5,2
mttc0 $27,$5,3
mttc0 $27,$5,4
mttc0 $27,$5,5
mttc0 $27,$5,6
mttc0 $27,$5,7
mttc0 $27,$6,0
mttc0 $27,$6,1
mttc0 $27,$6,2
mttc0 $27,$6,3
mttc0 $27,$6,4
mttc0 $27,$6,5
mttc0 $27,$6,6
mttc0 $27,$6,7
mttc0 $27,$7,0
mttc0 $27,$7,1
mttc0 $27,$7,2
mttc0 $27,$7,3
mttc0 $27,$7,4
mttc0 $27,$7,5
mttc0 $27,$7,6
mttc0 $27,$7,7
mttc0 $27,$8,0
mttc0 $27,$8,1
mttc0 $27,$8,2
mttc0 $27,$8,3
mttc0 $27,$8,4
mttc0 $27,$8,5
mttc0 $27,$8,6
mttc0 $27,$8,7
mttc0 $27,$9,0
mttc0 $27,$9,1
mttc0 $27,$9,2
mttc0 $27,$9,3
mttc0 $27,$9,4
mttc0 $27,$9,5
mttc0 $27,$9,6
mttc0 $27,$9,7
mttc0 $27,$10,0
mttc0 $27,$10,1
mttc0 $27,$10,2
mttc0 $27,$10,3
mttc0 $27,$10,4
mttc0 $27,$10,5
mttc0 $27,$10,6
mttc0 $27,$10,7
mttc0 $27,$11,0
mttc0 $27,$11,1
mttc0 $27,$11,2
mttc0 $27,$11,3
mttc0 $27,$11,4
mttc0 $27,$11,5
mttc0 $27,$11,6
mttc0 $27,$11,7
mttc0 $27,$12,0
mttc0 $27,$12,1
mttc0 $27,$12,2
mttc0 $27,$12,3
mttc0 $27,$12,4
mttc0 $27,$12,5
mttc0 $27,$12,6
mttc0 $27,$12,7
mttc0 $27,$13,0
mttc0 $27,$13,1
mttc0 $27,$13,2
mttc0 $27,$13,3
mttc0 $27,$13,4
mttc0 $27,$13,5
mttc0 $27,$13,6
mttc0 $27,$13,7
mttc0 $27,$14,0
mttc0 $27,$14,1
mttc0 $27,$14,2
mttc0 $27,$14,3
mttc0 $27,$14,4
mttc0 $27,$14,5
mttc0 $27,$14,6
mttc0 $27,$14,7
mttc0 $27,$15,0
mttc0 $27,$15,1
mttc0 $27,$15,2
mttc0 $27,$15,3
mttc0 $27,$15,4
mttc0 $27,$15,5
mttc0 $27,$15,6
mttc0 $27,$15,7
mttc0 $27,$16,0
mttc0 $27,$16,1
mttc0 $27,$16,2
mttc0 $27,$16,3
mttc0 $27,$16,4
mttc0 $27,$16,5
mttc0 $27,$16,6
mttc0 $27,$16,7
mttc0 $27,$17,0
mttc0 $27,$17,1
mttc0 $27,$17,2
mttc0 $27,$17,3
mttc0 $27,$17,4
mttc0 $27,$17,5
mttc0 $27,$17,6
mttc0 $27,$17,7
mttc0 $27,$18,0
mttc0 $27,$18,1
mttc0 $27,$18,2
mttc0 $27,$18,3
mttc0 $27,$18,4
mttc0 $27,$18,5
mttc0 $27,$18,6
mttc0 $27,$18,7
mttc0 $27,$19,0
mttc0 $27,$19,1
mttc0 $27,$19,2
mttc0 $27,$19,3
mttc0 $27,$19,4
mttc0 $27,$19,5
mttc0 $27,$19,6
mttc0 $27,$19,7
mttc0 $27,$20,0
mttc0 $27,$20,1
mttc0 $27,$20,2
mttc0 $27,$20,3
mttc0 $27,$20,4
mttc0 $27,$20,5
mttc0 $27,$20,6
mttc0 $27,$20,7
mttc0 $27,$21,0
mttc0 $27,$21,1
mttc0 $27,$21,2
mttc0 $27,$21,3
mttc0 $27,$21,4
mttc0 $27,$21,5
mttc0 $27,$21,6
mttc0 $27,$21,7
mttc0 $27,$22,0
mttc0 $27,$22,1
mttc0 $27,$22,2
mttc0 $27,$22,3
mttc0 $27,$22,4
mttc0 $27,$22,5
mttc0 $27,$22,6
mttc0 $27,$22,7
mttc0 $27,$23,0
mttc0 $27,$23,1
mttc0 $27,$23,2
mttc0 $27,$23,3
mttc0 $27,$23,4
mttc0 $27,$23,5
mttc0 $27,$23,6
mttc0 $27,$23,7
mttc0 $27,$24,0
mttc0 $27,$24,1
mttc0 $27,$24,2
mttc0 $27,$24,3
mttc0 $27,$24,4
mttc0 $27,$24,5
mttc0 $27,$24,6
mttc0 $27,$24,7
mttc0 $27,$25,0
mttc0 $27,$25,1
mttc0 $27,$25,2
mttc0 $27,$25,3
mttc0 $27,$25,4
mttc0 $27,$25,5
mttc0 $27,$25,6
mttc0 $27,$25,7
mttc0 $27,$26,0
mttc0 $27,$26,1
mttc0 $27,$26,2
mttc0 $27,$26,3
mttc0 $27,$26,4
mttc0 $27,$26,5
mttc0 $27,$26,6
mttc0 $27,$26,7
mttc0 $27,$27,0
mttc0 $27,$27,1
mttc0 $27,$27,2
mttc0 $27,$27,3
mttc0 $27,$27,4
mttc0 $27,$27,5
mttc0 $27,$27,6
mttc0 $27,$27,7
mttc0 $27,$28,0
mttc0 $27,$28,1
mttc0 $27,$28,2
mttc0 $27,$28,3
mttc0 $27,$28,4
mttc0 $27,$28,5
mttc0 $27,$28,6
mttc0 $27,$28,7
mttc0 $27,$29,0
mttc0 $27,$29,1
mttc0 $27,$29,2
mttc0 $27,$29,3
mttc0 $27,$29,4
mttc0 $27,$29,5
mttc0 $27,$29,6
mttc0 $27,$29,7
mttc0 $27,$30,0
mttc0 $27,$30,1
mttc0 $27,$30,2
mttc0 $27,$30,3
mttc0 $27,$30,4
mttc0 $27,$30,5
mttc0 $27,$30,6
mttc0 $27,$30,7
mttc0 $27,$31,0
mttc0 $27,$31,1
mttc0 $27,$31,2
mttc0 $27,$31,3
mttc0 $27,$31,4
mttc0 $27,$31,5
mttc0 $27,$31,6
mttc0 $27,$31,7
mttgpr $28,$29
mttlo $29
mttlo $30,$ac3
mtthi $31
mtthi $0,$ac0
mttacx $1
mttacx $2,$ac1
mttdsp $3
mttc1 $4,$f5
mttc1 $5,$6
mtthc1 $6,$f8
mtthc1 $7,$10
cttc1 $8,$9
cttc1 $9,$f10
mttc2 $10,$11
mtthc2 $11,$12
cttc2 $12,$13
mftr $13,$14,-1,0,-1
mftr $13,$14,-1,1,-1
mftr $13,$14,-1,2,-1
mftr $13,$14,-1,3,-1
mftr $13,$14,-1,4,-1
mftr $13,$14,-1,5,-1
mftr $13,$14,-1,6,-1
mftr $13,$14,-1,7,-1
mftr $13,$14,-1,0,0
mftr $13,$14,-1,1,0
mftr $13,$14,-1,2,0
mftr $13,$14,-1,3,0
mftr $13,$14,-1,4,0
mftr $13,$14,-1,5,0
mftr $13,$14,-1,6,0
mftr $13,$14,-1,7,0
mftr $13,$14,-1,0,1
mftr $13,$14,-1,1,1
mftr $13,$14,-1,2,1
mftr $13,$14,-1,3,1
mftr $13,$14,-1,4,1
mftr $13,$14,-1,5,1
mftr $13,$14,-1,6,1
mftr $13,$14,-1,7,1
mftr $13,$14,-1,0,2
mftr $13,$14,-1,1,2
mftr $13,$14,-1,2,2
mftr $13,$14,-1,3,2
mftr $13,$14,-1,4,2
mftr $13,$14,-1,5,2
mftr $13,$14,-1,6,2
mftr $13,$14,-1,7,2
mftr $13,$14,0,0,-1
mftr $13,$14,0,1,-1
mftr $13,$14,0,2,-1
mftr $13,$14,0,3,-1
mftr $13,$14,0,4,-1
mftr $13,$14,0,5,-1
mftr $13,$14,0,6,-1
mftr $13,$14,0,7,-1
mftr $13,$14,0,0,0
mftr $13,$14,0,1,0
mftr $13,$14,0,2,0
mftr $13,$14,0,3,0
mftr $13,$14,0,4,0
mftr $13,$14,0,5,0
mftr $13,$14,0,6,0
mftr $13,$14,0,7,0
mftr $13,$14,0,0,1
mftr $13,$14,0,1,1
mftr $13,$14,0,2,1
mftr $13,$14,0,3,1
mftr $13,$14,0,4,1
mftr $13,$14,0,5,1
mftr $13,$14,0,6,1
mftr $13,$14,0,7,1
mftr $13,$14,0,0,2
mftr $13,$14,0,1,2
mftr $13,$14,0,2,2
mftr $13,$14,0,3,2
mftr $13,$14,0,4,2
mftr $13,$14,0,5,2
mftr $13,$14,0,6,2
mftr $13,$14,0,7,2
mftr $13,$14,1,0,-1
mftr $13,$14,1,1,-1
mftr $13,$14,1,2,-1
mftr $13,$14,1,3,-1
mftr $13,$14,1,4,-1
mftr $13,$14,1,5,-1
mftr $13,$14,1,6,-1
mftr $13,$14,1,7,-1
mftr $13,$14,1,0,0
mftr $13,$14,1,1,0
mftr $13,$14,1,2,0
mftr $13,$14,1,3,0
mftr $13,$14,1,4,0
mftr $13,$14,1,5,0
mftr $13,$14,1,6,0
mftr $13,$14,1,7,0
mftr $13,$14,1,0,1
mftr $13,$14,1,1,1
mftr $13,$14,1,2,1
mftr $13,$14,1,3,1
mftr $13,$14,1,4,1
mftr $13,$14,1,5,1
mftr $13,$14,1,6,1
mftr $13,$14,1,7,1
mftr $13,$14,1,0,2
mftr $13,$14,1,1,2
mftr $13,$14,1,2,2
mftr $13,$14,1,3,2
mftr $13,$14,1,4,2
mftr $13,$14,1,5,2
mftr $13,$14,1,6,2
mftr $13,$14,1,7,2
mftr $13,$14,2,0,-1
mftr $13,$14,2,1,-1
mftr $13,$14,2,2,-1
mftr $13,$14,2,3,-1
mftr $13,$14,2,4,-1
mftr $13,$14,2,5,-1
mftr $13,$14,2,6,-1
mftr $13,$14,2,7,-1
mftr $13,$14,2,0,0
mftr $13,$14,2,1,0
mftr $13,$14,2,2,0
mftr $13,$14,2,3,0
mftr $13,$14,2,4,0
mftr $13,$14,2,5,0
mftr $13,$14,2,6,0
mftr $13,$14,2,7,0
mftr $13,$14,2,0,1
mftr $13,$14,2,1,1
mftr $13,$14,2,2,1
mftr $13,$14,2,3,1
mftr $13,$14,2,4,1
mftr $13,$14,2,5,1
mftr $13,$14,2,6,1
mftr $13,$14,2,7,1
mftr $13,$14,2,0,2
mftr $13,$14,2,1,2
mftr $13,$14,2,2,2
mftr $13,$14,2,3,2
mftr $13,$14,2,4,2
mftr $13,$14,2,5,2
mftr $13,$14,2,6,2
mftr $13,$14,2,7,2
mttr $13,$14,-1,0,-1
mttr $13,$14,-1,1,-1
mttr $13,$14,-1,2,-1
mttr $13,$14,-1,3,-1
mttr $13,$14,-1,4,-1
mttr $13,$14,-1,5,-1
mttr $13,$14,-1,6,-1
mttr $13,$14,-1,7,-1
mttr $13,$14,-1,0,0
mttr $13,$14,-1,1,0
mttr $13,$14,-1,2,0
mttr $13,$14,-1,3,0
mttr $13,$14,-1,4,0
mttr $13,$14,-1,5,0
mttr $13,$14,-1,6,0
mttr $13,$14,-1,7,0
mttr $13,$14,-1,0,1
mttr $13,$14,-1,1,1
mttr $13,$14,-1,2,1
mttr $13,$14,-1,3,1
mttr $13,$14,-1,4,1
mttr $13,$14,-1,5,1
mttr $13,$14,-1,6,1
mttr $13,$14,-1,7,1
mttr $13,$14,-1,0,2
mttr $13,$14,-1,1,2
mttr $13,$14,-1,2,2
mttr $13,$14,-1,3,2
mttr $13,$14,-1,4,2
mttr $13,$14,-1,5,2
mttr $13,$14,-1,6,2
mttr $13,$14,-1,7,2
mttr $13,$14,0,0,-1
mttr $13,$14,0,1,-1
mttr $13,$14,0,2,-1
mttr $13,$14,0,3,-1
mttr $13,$14,0,4,-1
mttr $13,$14,0,5,-1
mttr $13,$14,0,6,-1
mttr $13,$14,0,7,-1
mttr $13,$14,0,0,0
mttr $13,$14,0,1,0
mttr $13,$14,0,2,0
mttr $13,$14,0,3,0
mttr $13,$14,0,4,0
mttr $13,$14,0,5,0
mttr $13,$14,0,6,0
mttr $13,$14,0,7,0
mttr $13,$14,0,0,1
mttr $13,$14,0,1,1
mttr $13,$14,0,2,1
mttr $13,$14,0,3,1
mttr $13,$14,0,4,1
mttr $13,$14,0,5,1
mttr $13,$14,0,6,1
mttr $13,$14,0,7,1
mttr $13,$14,0,0,2
mttr $13,$14,0,1,2
mttr $13,$14,0,2,2
mttr $13,$14,0,3,2
mttr $13,$14,0,4,2
mttr $13,$14,0,5,2
mttr $13,$14,0,6,2
mttr $13,$14,0,7,2
mttr $13,$14,1,0,-1
mttr $13,$14,1,1,-1
mttr $13,$14,1,2,-1
mttr $13,$14,1,3,-1
mttr $13,$14,1,4,-1
mttr $13,$14,1,5,-1
mttr $13,$14,1,6,-1
mttr $13,$14,1,7,-1
mttr $13,$14,1,0,0
mttr $13,$14,1,1,0
mttr $13,$14,1,2,0
mttr $13,$14,1,3,0
mttr $13,$14,1,4,0
mttr $13,$14,1,5,0
mttr $13,$14,1,6,0
mttr $13,$14,1,7,0
mttr $13,$14,1,0,1
mttr $13,$14,1,1,1
mttr $13,$14,1,2,1
mttr $13,$14,1,3,1
mttr $13,$14,1,4,1
mttr $13,$14,1,5,1
mttr $13,$14,1,6,1
mttr $13,$14,1,7,1
mttr $13,$14,1,0,2
mttr $13,$14,1,1,2
mttr $13,$14,1,2,2
mttr $13,$14,1,3,2
mttr $13,$14,1,4,2
mttr $13,$14,1,5,2
mttr $13,$14,1,6,2
mttr $13,$14,1,7,2
mttr $13,$14,2,0,-1
mttr $13,$14,2,1,-1
mttr $13,$14,2,2,-1
mttr $13,$14,2,3,-1
mttr $13,$14,2,4,-1
mttr $13,$14,2,5,-1
mttr $13,$14,2,6,-1
mttr $13,$14,2,7,-1
mttr $13,$14,2,0,0
mttr $13,$14,2,1,0
mttr $13,$14,2,2,0
mttr $13,$14,2,3,0
mttr $13,$14,2,4,0
mttr $13,$14,2,5,0
mttr $13,$14,2,6,0
mttr $13,$14,2,7,0
mttr $13,$14,2,0,1
mttr $13,$14,2,1,1
mttr $13,$14,2,2,1
mttr $13,$14,2,3,1
mttr $13,$14,2,4,1
mttr $13,$14,2,5,1
mttr $13,$14,2,6,1
mttr $13,$14,2,7,1
mttr $13,$14,2,0,2
mttr $13,$14,2,1,2
mttr $13,$14,2,2,2
mttr $13,$14,2,3,2
mttr $13,$14,2,4,2
mttr $13,$14,2,5,2
mttr $13,$14,2,6,2
mttr $13,$14,2,7,2
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8
[-- Attachment #4: mips32-mt.l --]
[-- Type: application/octet-stream, Size: 15257 bytes --]
.*: Assembler messages:
.*:568: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:568: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:569: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:569: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:570: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:570: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:571: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:571: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:572: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:572: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:573: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:573: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:574: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:574: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:575: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:575: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:576: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:577: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:578: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:579: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:580: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:581: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:582: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:583: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:584: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:585: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:586: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:587: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:588: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:589: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:590: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:591: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:592: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:592: Warning: MT immediate not in range 0..1 \(2\)
.*:593: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:593: Warning: MT immediate not in range 0..1 \(2\)
.*:594: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:594: Warning: MT immediate not in range 0..1 \(2\)
.*:595: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:595: Warning: MT immediate not in range 0..1 \(2\)
.*:596: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:596: Warning: MT immediate not in range 0..1 \(2\)
.*:597: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:597: Warning: MT immediate not in range 0..1 \(2\)
.*:598: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:598: Warning: MT immediate not in range 0..1 \(2\)
.*:599: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:599: Warning: MT immediate not in range 0..1 \(2\)
.*:600: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:601: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:602: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:603: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:604: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:605: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:606: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:607: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:624: Warning: MT immediate not in range 0..1 \(2\)
.*:625: Warning: MT immediate not in range 0..1 \(2\)
.*:626: Warning: MT immediate not in range 0..1 \(2\)
.*:627: Warning: MT immediate not in range 0..1 \(2\)
.*:628: Warning: MT immediate not in range 0..1 \(2\)
.*:629: Warning: MT immediate not in range 0..1 \(2\)
.*:630: Warning: MT immediate not in range 0..1 \(2\)
.*:631: Warning: MT immediate not in range 0..1 \(2\)
.*:632: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:633: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:634: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:635: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:636: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:637: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:638: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:639: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:656: Warning: MT immediate not in range 0..1 \(2\)
.*:657: Warning: MT immediate not in range 0..1 \(2\)
.*:658: Warning: MT immediate not in range 0..1 \(2\)
.*:659: Warning: MT immediate not in range 0..1 \(2\)
.*:660: Warning: MT immediate not in range 0..1 \(2\)
.*:661: Warning: MT immediate not in range 0..1 \(2\)
.*:662: Warning: MT immediate not in range 0..1 \(2\)
.*:663: Warning: MT immediate not in range 0..1 \(2\)
.*:664: Warning: MT immediate not in range 0..1 \(2\)
.*:664: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:665: Warning: MT immediate not in range 0..1 \(2\)
.*:665: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:666: Warning: MT immediate not in range 0..1 \(2\)
.*:666: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:667: Warning: MT immediate not in range 0..1 \(2\)
.*:667: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:668: Warning: MT immediate not in range 0..1 \(2\)
.*:668: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:669: Warning: MT immediate not in range 0..1 \(2\)
.*:669: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:670: Warning: MT immediate not in range 0..1 \(2\)
.*:670: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:671: Warning: MT immediate not in range 0..1 \(2\)
.*:671: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:672: Warning: MT immediate not in range 0..1 \(2\)
.*:673: Warning: MT immediate not in range 0..1 \(2\)
.*:674: Warning: MT immediate not in range 0..1 \(2\)
.*:675: Warning: MT immediate not in range 0..1 \(2\)
.*:676: Warning: MT immediate not in range 0..1 \(2\)
.*:677: Warning: MT immediate not in range 0..1 \(2\)
.*:678: Warning: MT immediate not in range 0..1 \(2\)
.*:679: Warning: MT immediate not in range 0..1 \(2\)
.*:680: Warning: MT immediate not in range 0..1 \(2\)
.*:681: Warning: MT immediate not in range 0..1 \(2\)
.*:682: Warning: MT immediate not in range 0..1 \(2\)
.*:683: Warning: MT immediate not in range 0..1 \(2\)
.*:684: Warning: MT immediate not in range 0..1 \(2\)
.*:685: Warning: MT immediate not in range 0..1 \(2\)
.*:686: Warning: MT immediate not in range 0..1 \(2\)
.*:687: Warning: MT immediate not in range 0..1 \(2\)
.*:688: Warning: MT immediate not in range 0..1 \(2\)
.*:688: Warning: MT immediate not in range 0..1 \(2\)
.*:689: Warning: MT immediate not in range 0..1 \(2\)
.*:689: Warning: MT immediate not in range 0..1 \(2\)
.*:690: Warning: MT immediate not in range 0..1 \(2\)
.*:690: Warning: MT immediate not in range 0..1 \(2\)
.*:691: Warning: MT immediate not in range 0..1 \(2\)
.*:691: Warning: MT immediate not in range 0..1 \(2\)
.*:692: Warning: MT immediate not in range 0..1 \(2\)
.*:692: Warning: MT immediate not in range 0..1 \(2\)
.*:693: Warning: MT immediate not in range 0..1 \(2\)
.*:693: Warning: MT immediate not in range 0..1 \(2\)
.*:694: Warning: MT immediate not in range 0..1 \(2\)
.*:694: Warning: MT immediate not in range 0..1 \(2\)
.*:695: Warning: MT immediate not in range 0..1 \(2\)
.*:695: Warning: MT immediate not in range 0..1 \(2\)
.*:696: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:696: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:697: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:697: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:698: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:698: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:699: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:699: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:700: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:700: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:701: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:701: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:702: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:702: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:703: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:703: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:704: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:705: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:706: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:707: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:708: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:709: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:710: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:711: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:712: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:713: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:714: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:715: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:716: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:717: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:718: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:719: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:720: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:720: Warning: MT immediate not in range 0..1 \(2\)
.*:721: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:721: Warning: MT immediate not in range 0..1 \(2\)
.*:722: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:722: Warning: MT immediate not in range 0..1 \(2\)
.*:723: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:723: Warning: MT immediate not in range 0..1 \(2\)
.*:724: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:724: Warning: MT immediate not in range 0..1 \(2\)
.*:725: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:725: Warning: MT immediate not in range 0..1 \(2\)
.*:726: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:726: Warning: MT immediate not in range 0..1 \(2\)
.*:727: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:727: Warning: MT immediate not in range 0..1 \(2\)
.*:728: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:729: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:730: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:731: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:732: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:733: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:734: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:735: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:752: Warning: MT immediate not in range 0..1 \(2\)
.*:753: Warning: MT immediate not in range 0..1 \(2\)
.*:754: Warning: MT immediate not in range 0..1 \(2\)
.*:755: Warning: MT immediate not in range 0..1 \(2\)
.*:756: Warning: MT immediate not in range 0..1 \(2\)
.*:757: Warning: MT immediate not in range 0..1 \(2\)
.*:758: Warning: MT immediate not in range 0..1 \(2\)
.*:759: Warning: MT immediate not in range 0..1 \(2\)
.*:760: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:761: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:762: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:763: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:764: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:765: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:766: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:767: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:784: Warning: MT immediate not in range 0..1 \(2\)
.*:785: Warning: MT immediate not in range 0..1 \(2\)
.*:786: Warning: MT immediate not in range 0..1 \(2\)
.*:787: Warning: MT immediate not in range 0..1 \(2\)
.*:788: Warning: MT immediate not in range 0..1 \(2\)
.*:789: Warning: MT immediate not in range 0..1 \(2\)
.*:790: Warning: MT immediate not in range 0..1 \(2\)
.*:791: Warning: MT immediate not in range 0..1 \(2\)
.*:792: Warning: MT immediate not in range 0..1 \(2\)
.*:792: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:793: Warning: MT immediate not in range 0..1 \(2\)
.*:793: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:794: Warning: MT immediate not in range 0..1 \(2\)
.*:794: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:795: Warning: MT immediate not in range 0..1 \(2\)
.*:795: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:796: Warning: MT immediate not in range 0..1 \(2\)
.*:796: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:797: Warning: MT immediate not in range 0..1 \(2\)
.*:797: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:798: Warning: MT immediate not in range 0..1 \(2\)
.*:798: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:799: Warning: MT immediate not in range 0..1 \(2\)
.*:799: Warning: MT immediate not in range 0..1 \(4294967295\)
.*:800: Warning: MT immediate not in range 0..1 \(2\)
.*:801: Warning: MT immediate not in range 0..1 \(2\)
.*:802: Warning: MT immediate not in range 0..1 \(2\)
.*:803: Warning: MT immediate not in range 0..1 \(2\)
.*:804: Warning: MT immediate not in range 0..1 \(2\)
.*:805: Warning: MT immediate not in range 0..1 \(2\)
.*:806: Warning: MT immediate not in range 0..1 \(2\)
.*:807: Warning: MT immediate not in range 0..1 \(2\)
.*:808: Warning: MT immediate not in range 0..1 \(2\)
.*:809: Warning: MT immediate not in range 0..1 \(2\)
.*:810: Warning: MT immediate not in range 0..1 \(2\)
.*:811: Warning: MT immediate not in range 0..1 \(2\)
.*:812: Warning: MT immediate not in range 0..1 \(2\)
.*:813: Warning: MT immediate not in range 0..1 \(2\)
.*:814: Warning: MT immediate not in range 0..1 \(2\)
.*:815: Warning: MT immediate not in range 0..1 \(2\)
.*:816: Warning: MT immediate not in range 0..1 \(2\)
.*:816: Warning: MT immediate not in range 0..1 \(2\)
.*:817: Warning: MT immediate not in range 0..1 \(2\)
.*:817: Warning: MT immediate not in range 0..1 \(2\)
.*:818: Warning: MT immediate not in range 0..1 \(2\)
.*:818: Warning: MT immediate not in range 0..1 \(2\)
.*:819: Warning: MT immediate not in range 0..1 \(2\)
.*:819: Warning: MT immediate not in range 0..1 \(2\)
.*:820: Warning: MT immediate not in range 0..1 \(2\)
.*:820: Warning: MT immediate not in range 0..1 \(2\)
.*:821: Warning: MT immediate not in range 0..1 \(2\)
.*:821: Warning: MT immediate not in range 0..1 \(2\)
.*:822: Warning: MT immediate not in range 0..1 \(2\)
.*:822: Warning: MT immediate not in range 0..1 \(2\)
.*:823: Warning: MT immediate not in range 0..1 \(2\)
.*:823: Warning: MT immediate not in range 0..1 \(2\)
[-- Attachment #5: mips32-mt.d --]
[-- Type: application/octet-stream, Size: 34712 bytes --]
#objdump: -dr --prefix-addresses --show-raw-insn -M cp0-names=mips32
#name: MIPS MT ASE for MIPS32
#as: -mmt
#stderr: mips32-mt.l
# Check MIPS MT ASE for MIPS32 Instruction Assembly
.*: +file format .*mips.*
Disassembly of section .text:
0+0000 <[^>]*> 41600bc1 dmt
0+0004 <[^>]*> 417f0bc1 dmt ra
0+0008 <[^>]*> 41600001 dvpe
0+000c <[^>]*> 41610001 dvpe at
0+0010 <[^>]*> 41600be1 emt
0+0014 <[^>]*> 41620be1 emt v0
0+0018 <[^>]*> 41600021 evpe
0+001c <[^>]*> 41630021 evpe v1
0+0020 <[^>]*> 7ca62008 fork a0,a1,a2
0+0024 <[^>]*> 7ca00009 yield a1
0+0028 <[^>]*> 7ce03009 yield a2,a3
0+002c <[^>]*> 41083800 mftc0 a3,c0_badvaddr
0+0030 <[^>]*> 41004000 mftc0 t0,c0_index
0+0034 <[^>]*> 41004001 mftc0 t0,\$0,1
0+0038 <[^>]*> 41004002 mftc0 t0,\$0,2
0+003c <[^>]*> 41004003 mftc0 t0,\$0,3
0+0040 <[^>]*> 41004004 mftc0 t0,\$0,4
0+0044 <[^>]*> 41004005 mftc0 t0,\$0,5
0+0048 <[^>]*> 41004006 mftc0 t0,\$0,6
0+004c <[^>]*> 41004007 mftc0 t0,\$0,7
0+0050 <[^>]*> 41014000 mftc0 t0,c0_random
0+0054 <[^>]*> 41014001 mftc0 t0,\$1,1
0+0058 <[^>]*> 41014002 mftc0 t0,\$1,2
0+005c <[^>]*> 41014003 mftc0 t0,\$1,3
0+0060 <[^>]*> 41014004 mftc0 t0,\$1,4
0+0064 <[^>]*> 41014005 mftc0 t0,\$1,5
0+0068 <[^>]*> 41014006 mftc0 t0,\$1,6
0+006c <[^>]*> 41014007 mftc0 t0,\$1,7
0+0070 <[^>]*> 41024000 mftc0 t0,c0_entrylo0
0+0074 <[^>]*> 41024001 mftc0 t0,\$2,1
0+0078 <[^>]*> 41024002 mftc0 t0,\$2,2
0+007c <[^>]*> 41024003 mftc0 t0,\$2,3
0+0080 <[^>]*> 41024004 mftc0 t0,\$2,4
0+0084 <[^>]*> 41024005 mftc0 t0,\$2,5
0+0088 <[^>]*> 41024006 mftc0 t0,\$2,6
0+008c <[^>]*> 41024007 mftc0 t0,\$2,7
0+0090 <[^>]*> 41034000 mftc0 t0,c0_entrylo1
0+0094 <[^>]*> 41034001 mftc0 t0,\$3,1
0+0098 <[^>]*> 41034002 mftc0 t0,\$3,2
0+009c <[^>]*> 41034003 mftc0 t0,\$3,3
0+00a0 <[^>]*> 41034004 mftc0 t0,\$3,4
0+00a4 <[^>]*> 41034005 mftc0 t0,\$3,5
0+00a8 <[^>]*> 41034006 mftc0 t0,\$3,6
0+00ac <[^>]*> 41034007 mftc0 t0,\$3,7
0+00b0 <[^>]*> 41044000 mftc0 t0,c0_context
0+00b4 <[^>]*> 41044001 mftc0 t0,\$4,1
0+00b8 <[^>]*> 41044002 mftc0 t0,\$4,2
0+00bc <[^>]*> 41044003 mftc0 t0,\$4,3
0+00c0 <[^>]*> 41044004 mftc0 t0,\$4,4
0+00c4 <[^>]*> 41044005 mftc0 t0,\$4,5
0+00c8 <[^>]*> 41044006 mftc0 t0,\$4,6
0+00cc <[^>]*> 41044007 mftc0 t0,\$4,7
0+00d0 <[^>]*> 41054000 mftc0 t0,c0_pagemask
0+00d4 <[^>]*> 41054001 mftc0 t0,\$5,1
0+00d8 <[^>]*> 41054002 mftc0 t0,\$5,2
0+00dc <[^>]*> 41054003 mftc0 t0,\$5,3
0+00e0 <[^>]*> 41054004 mftc0 t0,\$5,4
0+00e4 <[^>]*> 41054005 mftc0 t0,\$5,5
0+00e8 <[^>]*> 41054006 mftc0 t0,\$5,6
0+00ec <[^>]*> 41054007 mftc0 t0,\$5,7
0+00f0 <[^>]*> 41064000 mftc0 t0,c0_wired
0+00f4 <[^>]*> 41064001 mftc0 t0,\$6,1
0+00f8 <[^>]*> 41064002 mftc0 t0,\$6,2
0+00fc <[^>]*> 41064003 mftc0 t0,\$6,3
0+0100 <[^>]*> 41064004 mftc0 t0,\$6,4
0+0104 <[^>]*> 41064005 mftc0 t0,\$6,5
0+0108 <[^>]*> 41064006 mftc0 t0,\$6,6
0+010c <[^>]*> 41064007 mftc0 t0,\$6,7
0+0110 <[^>]*> 41074000 mftc0 t0,\$7
0+0114 <[^>]*> 41074001 mftc0 t0,\$7,1
0+0118 <[^>]*> 41074002 mftc0 t0,\$7,2
0+011c <[^>]*> 41074003 mftc0 t0,\$7,3
0+0120 <[^>]*> 41074004 mftc0 t0,\$7,4
0+0124 <[^>]*> 41074005 mftc0 t0,\$7,5
0+0128 <[^>]*> 41074006 mftc0 t0,\$7,6
0+012c <[^>]*> 41074007 mftc0 t0,\$7,7
0+0130 <[^>]*> 41084000 mftc0 t0,c0_badvaddr
0+0134 <[^>]*> 41084001 mftc0 t0,\$8,1
0+0138 <[^>]*> 41084002 mftc0 t0,\$8,2
0+013c <[^>]*> 41084003 mftc0 t0,\$8,3
0+0140 <[^>]*> 41084004 mftc0 t0,\$8,4
0+0144 <[^>]*> 41084005 mftc0 t0,\$8,5
0+0148 <[^>]*> 41084006 mftc0 t0,\$8,6
0+014c <[^>]*> 41084007 mftc0 t0,\$8,7
0+0150 <[^>]*> 41094000 mftc0 t0,c0_count
0+0154 <[^>]*> 41094001 mftc0 t0,\$9,1
0+0158 <[^>]*> 41094002 mftc0 t0,\$9,2
0+015c <[^>]*> 41094003 mftc0 t0,\$9,3
0+0160 <[^>]*> 41094004 mftc0 t0,\$9,4
0+0164 <[^>]*> 41094005 mftc0 t0,\$9,5
0+0168 <[^>]*> 41094006 mftc0 t0,\$9,6
0+016c <[^>]*> 41094007 mftc0 t0,\$9,7
0+0170 <[^>]*> 410a4000 mftc0 t0,c0_entryhi
0+0174 <[^>]*> 410a4001 mftc0 t0,\$10,1
0+0178 <[^>]*> 410a4002 mftc0 t0,\$10,2
0+017c <[^>]*> 410a4003 mftc0 t0,\$10,3
0+0180 <[^>]*> 410a4004 mftc0 t0,\$10,4
0+0184 <[^>]*> 410a4005 mftc0 t0,\$10,5
0+0188 <[^>]*> 410a4006 mftc0 t0,\$10,6
0+018c <[^>]*> 410a4007 mftc0 t0,\$10,7
0+0190 <[^>]*> 410b4000 mftc0 t0,c0_compare
0+0194 <[^>]*> 410b4001 mftc0 t0,\$11,1
0+0198 <[^>]*> 410b4002 mftc0 t0,\$11,2
0+019c <[^>]*> 410b4003 mftc0 t0,\$11,3
0+01a0 <[^>]*> 410b4004 mftc0 t0,\$11,4
0+01a4 <[^>]*> 410b4005 mftc0 t0,\$11,5
0+01a8 <[^>]*> 410b4006 mftc0 t0,\$11,6
0+01ac <[^>]*> 410b4007 mftc0 t0,\$11,7
0+01b0 <[^>]*> 410c4000 mftc0 t0,c0_status
0+01b4 <[^>]*> 410c4001 mftc0 t0,\$12,1
0+01b8 <[^>]*> 410c4002 mftc0 t0,\$12,2
0+01bc <[^>]*> 410c4003 mftc0 t0,\$12,3
0+01c0 <[^>]*> 410c4004 mftc0 t0,\$12,4
0+01c4 <[^>]*> 410c4005 mftc0 t0,\$12,5
0+01c8 <[^>]*> 410c4006 mftc0 t0,\$12,6
0+01cc <[^>]*> 410c4007 mftc0 t0,\$12,7
0+01d0 <[^>]*> 410d4000 mftc0 t0,c0_cause
0+01d4 <[^>]*> 410d4001 mftc0 t0,\$13,1
0+01d8 <[^>]*> 410d4002 mftc0 t0,\$13,2
0+01dc <[^>]*> 410d4003 mftc0 t0,\$13,3
0+01e0 <[^>]*> 410d4004 mftc0 t0,\$13,4
0+01e4 <[^>]*> 410d4005 mftc0 t0,\$13,5
0+01e8 <[^>]*> 410d4006 mftc0 t0,\$13,6
0+01ec <[^>]*> 410d4007 mftc0 t0,\$13,7
0+01f0 <[^>]*> 410e4000 mftc0 t0,c0_epc
0+01f4 <[^>]*> 410e4001 mftc0 t0,\$14,1
0+01f8 <[^>]*> 410e4002 mftc0 t0,\$14,2
0+01fc <[^>]*> 410e4003 mftc0 t0,\$14,3
0+0200 <[^>]*> 410e4004 mftc0 t0,\$14,4
0+0204 <[^>]*> 410e4005 mftc0 t0,\$14,5
0+0208 <[^>]*> 410e4006 mftc0 t0,\$14,6
0+020c <[^>]*> 410e4007 mftc0 t0,\$14,7
0+0210 <[^>]*> 410f4000 mftc0 t0,c0_prid
0+0214 <[^>]*> 410f4001 mftc0 t0,\$15,1
0+0218 <[^>]*> 410f4002 mftc0 t0,\$15,2
0+021c <[^>]*> 410f4003 mftc0 t0,\$15,3
0+0220 <[^>]*> 410f4004 mftc0 t0,\$15,4
0+0224 <[^>]*> 410f4005 mftc0 t0,\$15,5
0+0228 <[^>]*> 410f4006 mftc0 t0,\$15,6
0+022c <[^>]*> 410f4007 mftc0 t0,\$15,7
0+0230 <[^>]*> 41104000 mftc0 t0,c0_config
0+0234 <[^>]*> 41104001 mftc0 t0,c0_config1
0+0238 <[^>]*> 41104002 mftc0 t0,c0_config2
0+023c <[^>]*> 41104003 mftc0 t0,c0_config3
0+0240 <[^>]*> 41104004 mftc0 t0,\$16,4
0+0244 <[^>]*> 41104005 mftc0 t0,\$16,5
0+0248 <[^>]*> 41104006 mftc0 t0,\$16,6
0+024c <[^>]*> 41104007 mftc0 t0,\$16,7
0+0250 <[^>]*> 41114000 mftc0 t0,c0_lladdr
0+0254 <[^>]*> 41114001 mftc0 t0,\$17,1
0+0258 <[^>]*> 41114002 mftc0 t0,\$17,2
0+025c <[^>]*> 41114003 mftc0 t0,\$17,3
0+0260 <[^>]*> 41114004 mftc0 t0,\$17,4
0+0264 <[^>]*> 41114005 mftc0 t0,\$17,5
0+0268 <[^>]*> 41114006 mftc0 t0,\$17,6
0+026c <[^>]*> 41114007 mftc0 t0,\$17,7
0+0270 <[^>]*> 41124000 mftc0 t0,c0_watchlo
0+0274 <[^>]*> 41124001 mftc0 t0,c0_watchlo,1
0+0278 <[^>]*> 41124002 mftc0 t0,c0_watchlo,2
0+027c <[^>]*> 41124003 mftc0 t0,c0_watchlo,3
0+0280 <[^>]*> 41124004 mftc0 t0,c0_watchlo,4
0+0284 <[^>]*> 41124005 mftc0 t0,c0_watchlo,5
0+0288 <[^>]*> 41124006 mftc0 t0,c0_watchlo,6
0+028c <[^>]*> 41124007 mftc0 t0,c0_watchlo,7
0+0290 <[^>]*> 41134000 mftc0 t0,c0_watchhi
0+0294 <[^>]*> 41134001 mftc0 t0,c0_watchhi,1
0+0298 <[^>]*> 41134002 mftc0 t0,c0_watchhi,2
0+029c <[^>]*> 41134003 mftc0 t0,c0_watchhi,3
0+02a0 <[^>]*> 41134004 mftc0 t0,c0_watchhi,4
0+02a4 <[^>]*> 41134005 mftc0 t0,c0_watchhi,5
0+02a8 <[^>]*> 41134006 mftc0 t0,c0_watchhi,6
0+02ac <[^>]*> 41134007 mftc0 t0,c0_watchhi,7
0+02b0 <[^>]*> 41144000 mftc0 t0,c0_xcontext
0+02b4 <[^>]*> 41144001 mftc0 t0,\$20,1
0+02b8 <[^>]*> 41144002 mftc0 t0,\$20,2
0+02bc <[^>]*> 41144003 mftc0 t0,\$20,3
0+02c0 <[^>]*> 41144004 mftc0 t0,\$20,4
0+02c4 <[^>]*> 41144005 mftc0 t0,\$20,5
0+02c8 <[^>]*> 41144006 mftc0 t0,\$20,6
0+02cc <[^>]*> 41144007 mftc0 t0,\$20,7
0+02d0 <[^>]*> 41154000 mftc0 t0,\$21
0+02d4 <[^>]*> 41154001 mftc0 t0,\$21,1
0+02d8 <[^>]*> 41154002 mftc0 t0,\$21,2
0+02dc <[^>]*> 41154003 mftc0 t0,\$21,3
0+02e0 <[^>]*> 41154004 mftc0 t0,\$21,4
0+02e4 <[^>]*> 41154005 mftc0 t0,\$21,5
0+02e8 <[^>]*> 41154006 mftc0 t0,\$21,6
0+02ec <[^>]*> 41154007 mftc0 t0,\$21,7
0+02f0 <[^>]*> 41164000 mftc0 t0,\$22
0+02f4 <[^>]*> 41164001 mftc0 t0,\$22,1
0+02f8 <[^>]*> 41164002 mftc0 t0,\$22,2
0+02fc <[^>]*> 41164003 mftc0 t0,\$22,3
0+0300 <[^>]*> 41164004 mftc0 t0,\$22,4
0+0304 <[^>]*> 41164005 mftc0 t0,\$22,5
0+0308 <[^>]*> 41164006 mftc0 t0,\$22,6
0+030c <[^>]*> 41164007 mftc0 t0,\$22,7
0+0310 <[^>]*> 41174000 mftc0 t0,c0_debug
0+0314 <[^>]*> 41174001 mftc0 t0,\$23,1
0+0318 <[^>]*> 41174002 mftc0 t0,\$23,2
0+031c <[^>]*> 41174003 mftc0 t0,\$23,3
0+0320 <[^>]*> 41174004 mftc0 t0,\$23,4
0+0324 <[^>]*> 41174005 mftc0 t0,\$23,5
0+0328 <[^>]*> 41174006 mftc0 t0,\$23,6
0+032c <[^>]*> 41174007 mftc0 t0,\$23,7
0+0330 <[^>]*> 41184000 mftc0 t0,c0_depc
0+0334 <[^>]*> 41184001 mftc0 t0,\$24,1
0+0338 <[^>]*> 41184002 mftc0 t0,\$24,2
0+033c <[^>]*> 41184003 mftc0 t0,\$24,3
0+0340 <[^>]*> 41184004 mftc0 t0,\$24,4
0+0344 <[^>]*> 41184005 mftc0 t0,\$24,5
0+0348 <[^>]*> 41184006 mftc0 t0,\$24,6
0+034c <[^>]*> 41184007 mftc0 t0,\$24,7
0+0350 <[^>]*> 41194000 mftc0 t0,c0_perfcnt
0+0354 <[^>]*> 41194001 mftc0 t0,c0_perfcnt,1
0+0358 <[^>]*> 41194002 mftc0 t0,c0_perfcnt,2
0+035c <[^>]*> 41194003 mftc0 t0,c0_perfcnt,3
0+0360 <[^>]*> 41194004 mftc0 t0,c0_perfcnt,4
0+0364 <[^>]*> 41194005 mftc0 t0,c0_perfcnt,5
0+0368 <[^>]*> 41194006 mftc0 t0,c0_perfcnt,6
0+036c <[^>]*> 41194007 mftc0 t0,c0_perfcnt,7
0+0370 <[^>]*> 411a4000 mftc0 t0,c0_errctl
0+0374 <[^>]*> 411a4001 mftc0 t0,\$26,1
0+0378 <[^>]*> 411a4002 mftc0 t0,\$26,2
0+037c <[^>]*> 411a4003 mftc0 t0,\$26,3
0+0380 <[^>]*> 411a4004 mftc0 t0,\$26,4
0+0384 <[^>]*> 411a4005 mftc0 t0,\$26,5
0+0388 <[^>]*> 411a4006 mftc0 t0,\$26,6
0+038c <[^>]*> 411a4007 mftc0 t0,\$26,7
0+0390 <[^>]*> 411b4000 mftc0 t0,c0_cacheerr
0+0394 <[^>]*> 411b4001 mftc0 t0,c0_cacheerr,1
0+0398 <[^>]*> 411b4002 mftc0 t0,c0_cacheerr,2
0+039c <[^>]*> 411b4003 mftc0 t0,c0_cacheerr,3
0+03a0 <[^>]*> 411b4004 mftc0 t0,\$27,4
0+03a4 <[^>]*> 411b4005 mftc0 t0,\$27,5
0+03a8 <[^>]*> 411b4006 mftc0 t0,\$27,6
0+03ac <[^>]*> 411b4007 mftc0 t0,\$27,7
0+03b0 <[^>]*> 411c4000 mftc0 t0,c0_taglo
0+03b4 <[^>]*> 411c4001 mftc0 t0,c0_datalo
0+03b8 <[^>]*> 411c4002 mftc0 t0,\$28,2
0+03bc <[^>]*> 411c4003 mftc0 t0,\$28,3
0+03c0 <[^>]*> 411c4004 mftc0 t0,\$28,4
0+03c4 <[^>]*> 411c4005 mftc0 t0,\$28,5
0+03c8 <[^>]*> 411c4006 mftc0 t0,\$28,6
0+03cc <[^>]*> 411c4007 mftc0 t0,\$28,7
0+03d0 <[^>]*> 411d4000 mftc0 t0,c0_taghi
0+03d4 <[^>]*> 411d4001 mftc0 t0,c0_datahi
0+03d8 <[^>]*> 411d4002 mftc0 t0,\$29,2
0+03dc <[^>]*> 411d4003 mftc0 t0,\$29,3
0+03e0 <[^>]*> 411d4004 mftc0 t0,\$29,4
0+03e4 <[^>]*> 411d4005 mftc0 t0,\$29,5
0+03e8 <[^>]*> 411d4006 mftc0 t0,\$29,6
0+03ec <[^>]*> 411d4007 mftc0 t0,\$29,7
0+03f0 <[^>]*> 411e4000 mftc0 t0,c0_errorepc
0+03f4 <[^>]*> 411e4001 mftc0 t0,\$30,1
0+03f8 <[^>]*> 411e4002 mftc0 t0,\$30,2
0+03fc <[^>]*> 411e4003 mftc0 t0,\$30,3
0+0400 <[^>]*> 411e4004 mftc0 t0,\$30,4
0+0404 <[^>]*> 411e4005 mftc0 t0,\$30,5
0+0408 <[^>]*> 411e4006 mftc0 t0,\$30,6
0+040c <[^>]*> 411e4007 mftc0 t0,\$30,7
0+0410 <[^>]*> 411f4000 mftc0 t0,c0_desave
0+0414 <[^>]*> 411f4001 mftc0 t0,\$31,1
0+0418 <[^>]*> 411f4002 mftc0 t0,\$31,2
0+041c <[^>]*> 411f4003 mftc0 t0,\$31,3
0+0420 <[^>]*> 411f4004 mftc0 t0,\$31,4
0+0424 <[^>]*> 411f4005 mftc0 t0,\$31,5
0+0428 <[^>]*> 411f4006 mftc0 t0,\$31,6
0+042c <[^>]*> 411f4007 mftc0 t0,\$31,7
0+0430 <[^>]*> 410a4820 mftgpr t1,t2
0+0434 <[^>]*> 41005021 mftlo t2
0+0438 <[^>]*> 41005821 mftlo t3
0+043c <[^>]*> 41016021 mfthi t4
0+0440 <[^>]*> 41056821 mfthi t5,\$ac1
0+0444 <[^>]*> 41027021 mftacx t6
0+0448 <[^>]*> 410a7821 mftacx t7,\$ac2
0+044c <[^>]*> 41108021 mftdsp s0
0+0450 <[^>]*> 41128822 mftc1 s1,\$f18
0+0454 <[^>]*> 41139022 mftc1 s2,\$f19
0+0458 <[^>]*> 41149832 mfthc1 s3,\$f20
0+045c <[^>]*> 4116a032 mfthc1 s4,\$f22
0+0460 <[^>]*> 4116a823 cftc1 s5,\$22
0+0464 <[^>]*> 4117b023 cftc1 s6,\$23
0+0468 <[^>]*> 4118b824 mftc2 s7,\$24
0+046c <[^>]*> 4119c034 mfthc2 t8,\$25
0+0470 <[^>]*> 411ac825 cftc2 t9,\$26
0+0474 <[^>]*> 419ad800 mttc0 k0,c0_cacheerr
0+0478 <[^>]*> 419b0000 mttc0 k1,c0_index
0+047c <[^>]*> 419b0001 mttc0 k1,\$0,1
0+0480 <[^>]*> 419b0002 mttc0 k1,\$0,2
0+0484 <[^>]*> 419b0003 mttc0 k1,\$0,3
0+0488 <[^>]*> 419b0004 mttc0 k1,\$0,4
0+048c <[^>]*> 419b0005 mttc0 k1,\$0,5
0+0490 <[^>]*> 419b0006 mttc0 k1,\$0,6
0+0494 <[^>]*> 419b0007 mttc0 k1,\$0,7
0+0498 <[^>]*> 419b0800 mttc0 k1,c0_random
0+049c <[^>]*> 419b0801 mttc0 k1,\$1,1
0+04a0 <[^>]*> 419b0802 mttc0 k1,\$1,2
0+04a4 <[^>]*> 419b0803 mttc0 k1,\$1,3
0+04a8 <[^>]*> 419b0804 mttc0 k1,\$1,4
0+04ac <[^>]*> 419b0805 mttc0 k1,\$1,5
0+04b0 <[^>]*> 419b0806 mttc0 k1,\$1,6
0+04b4 <[^>]*> 419b0807 mttc0 k1,\$1,7
0+04b8 <[^>]*> 419b1000 mttc0 k1,c0_entrylo0
0+04bc <[^>]*> 419b1001 mttc0 k1,\$2,1
0+04c0 <[^>]*> 419b1002 mttc0 k1,\$2,2
0+04c4 <[^>]*> 419b1003 mttc0 k1,\$2,3
0+04c8 <[^>]*> 419b1004 mttc0 k1,\$2,4
0+04cc <[^>]*> 419b1005 mttc0 k1,\$2,5
0+04d0 <[^>]*> 419b1006 mttc0 k1,\$2,6
0+04d4 <[^>]*> 419b1007 mttc0 k1,\$2,7
0+04d8 <[^>]*> 419b1800 mttc0 k1,c0_entrylo1
0+04dc <[^>]*> 419b1801 mttc0 k1,\$3,1
0+04e0 <[^>]*> 419b1802 mttc0 k1,\$3,2
0+04e4 <[^>]*> 419b1803 mttc0 k1,\$3,3
0+04e8 <[^>]*> 419b1804 mttc0 k1,\$3,4
0+04ec <[^>]*> 419b1805 mttc0 k1,\$3,5
0+04f0 <[^>]*> 419b1806 mttc0 k1,\$3,6
0+04f4 <[^>]*> 419b1807 mttc0 k1,\$3,7
0+04f8 <[^>]*> 419b2000 mttc0 k1,c0_context
0+04fc <[^>]*> 419b2001 mttc0 k1,\$4,1
0+0500 <[^>]*> 419b2002 mttc0 k1,\$4,2
0+0504 <[^>]*> 419b2003 mttc0 k1,\$4,3
0+0508 <[^>]*> 419b2004 mttc0 k1,\$4,4
0+050c <[^>]*> 419b2005 mttc0 k1,\$4,5
0+0510 <[^>]*> 419b2006 mttc0 k1,\$4,6
0+0514 <[^>]*> 419b2007 mttc0 k1,\$4,7
0+0518 <[^>]*> 419b2800 mttc0 k1,c0_pagemask
0+051c <[^>]*> 419b2801 mttc0 k1,\$5,1
0+0520 <[^>]*> 419b2802 mttc0 k1,\$5,2
0+0524 <[^>]*> 419b2803 mttc0 k1,\$5,3
0+0528 <[^>]*> 419b2804 mttc0 k1,\$5,4
0+052c <[^>]*> 419b2805 mttc0 k1,\$5,5
0+0530 <[^>]*> 419b2806 mttc0 k1,\$5,6
0+0534 <[^>]*> 419b2807 mttc0 k1,\$5,7
0+0538 <[^>]*> 419b3000 mttc0 k1,c0_wired
0+053c <[^>]*> 419b3001 mttc0 k1,\$6,1
0+0540 <[^>]*> 419b3002 mttc0 k1,\$6,2
0+0544 <[^>]*> 419b3003 mttc0 k1,\$6,3
0+0548 <[^>]*> 419b3004 mttc0 k1,\$6,4
0+054c <[^>]*> 419b3005 mttc0 k1,\$6,5
0+0550 <[^>]*> 419b3006 mttc0 k1,\$6,6
0+0554 <[^>]*> 419b3007 mttc0 k1,\$6,7
0+0558 <[^>]*> 419b3800 mttc0 k1,\$7
0+055c <[^>]*> 419b3801 mttc0 k1,\$7,1
0+0560 <[^>]*> 419b3802 mttc0 k1,\$7,2
0+0564 <[^>]*> 419b3803 mttc0 k1,\$7,3
0+0568 <[^>]*> 419b3804 mttc0 k1,\$7,4
0+056c <[^>]*> 419b3805 mttc0 k1,\$7,5
0+0570 <[^>]*> 419b3806 mttc0 k1,\$7,6
0+0574 <[^>]*> 419b3807 mttc0 k1,\$7,7
0+0578 <[^>]*> 419b4000 mttc0 k1,c0_badvaddr
0+057c <[^>]*> 419b4001 mttc0 k1,\$8,1
0+0580 <[^>]*> 419b4002 mttc0 k1,\$8,2
0+0584 <[^>]*> 419b4003 mttc0 k1,\$8,3
0+0588 <[^>]*> 419b4004 mttc0 k1,\$8,4
0+058c <[^>]*> 419b4005 mttc0 k1,\$8,5
0+0590 <[^>]*> 419b4006 mttc0 k1,\$8,6
0+0594 <[^>]*> 419b4007 mttc0 k1,\$8,7
0+0598 <[^>]*> 419b4800 mttc0 k1,c0_count
0+059c <[^>]*> 419b4801 mttc0 k1,\$9,1
0+05a0 <[^>]*> 419b4802 mttc0 k1,\$9,2
0+05a4 <[^>]*> 419b4803 mttc0 k1,\$9,3
0+05a8 <[^>]*> 419b4804 mttc0 k1,\$9,4
0+05ac <[^>]*> 419b4805 mttc0 k1,\$9,5
0+05b0 <[^>]*> 419b4806 mttc0 k1,\$9,6
0+05b4 <[^>]*> 419b4807 mttc0 k1,\$9,7
0+05b8 <[^>]*> 419b5000 mttc0 k1,c0_entryhi
0+05bc <[^>]*> 419b5001 mttc0 k1,\$10,1
0+05c0 <[^>]*> 419b5002 mttc0 k1,\$10,2
0+05c4 <[^>]*> 419b5003 mttc0 k1,\$10,3
0+05c8 <[^>]*> 419b5004 mttc0 k1,\$10,4
0+05cc <[^>]*> 419b5005 mttc0 k1,\$10,5
0+05d0 <[^>]*> 419b5006 mttc0 k1,\$10,6
0+05d4 <[^>]*> 419b5007 mttc0 k1,\$10,7
0+05d8 <[^>]*> 419b5800 mttc0 k1,c0_compare
0+05dc <[^>]*> 419b5801 mttc0 k1,\$11,1
0+05e0 <[^>]*> 419b5802 mttc0 k1,\$11,2
0+05e4 <[^>]*> 419b5803 mttc0 k1,\$11,3
0+05e8 <[^>]*> 419b5804 mttc0 k1,\$11,4
0+05ec <[^>]*> 419b5805 mttc0 k1,\$11,5
0+05f0 <[^>]*> 419b5806 mttc0 k1,\$11,6
0+05f4 <[^>]*> 419b5807 mttc0 k1,\$11,7
0+05f8 <[^>]*> 419b6000 mttc0 k1,c0_status
0+05fc <[^>]*> 419b6001 mttc0 k1,\$12,1
0+0600 <[^>]*> 419b6002 mttc0 k1,\$12,2
0+0604 <[^>]*> 419b6003 mttc0 k1,\$12,3
0+0608 <[^>]*> 419b6004 mttc0 k1,\$12,4
0+060c <[^>]*> 419b6005 mttc0 k1,\$12,5
0+0610 <[^>]*> 419b6006 mttc0 k1,\$12,6
0+0614 <[^>]*> 419b6007 mttc0 k1,\$12,7
0+0618 <[^>]*> 419b6800 mttc0 k1,c0_cause
0+061c <[^>]*> 419b6801 mttc0 k1,\$13,1
0+0620 <[^>]*> 419b6802 mttc0 k1,\$13,2
0+0624 <[^>]*> 419b6803 mttc0 k1,\$13,3
0+0628 <[^>]*> 419b6804 mttc0 k1,\$13,4
0+062c <[^>]*> 419b6805 mttc0 k1,\$13,5
0+0630 <[^>]*> 419b6806 mttc0 k1,\$13,6
0+0634 <[^>]*> 419b6807 mttc0 k1,\$13,7
0+0638 <[^>]*> 419b7000 mttc0 k1,c0_epc
0+063c <[^>]*> 419b7001 mttc0 k1,\$14,1
0+0640 <[^>]*> 419b7002 mttc0 k1,\$14,2
0+0644 <[^>]*> 419b7003 mttc0 k1,\$14,3
0+0648 <[^>]*> 419b7004 mttc0 k1,\$14,4
0+064c <[^>]*> 419b7005 mttc0 k1,\$14,5
0+0650 <[^>]*> 419b7006 mttc0 k1,\$14,6
0+0654 <[^>]*> 419b7007 mttc0 k1,\$14,7
0+0658 <[^>]*> 419b7800 mttc0 k1,c0_prid
0+065c <[^>]*> 419b7801 mttc0 k1,\$15,1
0+0660 <[^>]*> 419b7802 mttc0 k1,\$15,2
0+0664 <[^>]*> 419b7803 mttc0 k1,\$15,3
0+0668 <[^>]*> 419b7804 mttc0 k1,\$15,4
0+066c <[^>]*> 419b7805 mttc0 k1,\$15,5
0+0670 <[^>]*> 419b7806 mttc0 k1,\$15,6
0+0674 <[^>]*> 419b7807 mttc0 k1,\$15,7
0+0678 <[^>]*> 419b8000 mttc0 k1,c0_config
0+067c <[^>]*> 419b8001 mttc0 k1,c0_config1
0+0680 <[^>]*> 419b8002 mttc0 k1,c0_config2
0+0684 <[^>]*> 419b8003 mttc0 k1,c0_config3
0+0688 <[^>]*> 419b8004 mttc0 k1,\$16,4
0+068c <[^>]*> 419b8005 mttc0 k1,\$16,5
0+0690 <[^>]*> 419b8006 mttc0 k1,\$16,6
0+0694 <[^>]*> 419b8007 mttc0 k1,\$16,7
0+0698 <[^>]*> 419b8800 mttc0 k1,c0_lladdr
0+069c <[^>]*> 419b8801 mttc0 k1,\$17,1
0+06a0 <[^>]*> 419b8802 mttc0 k1,\$17,2
0+06a4 <[^>]*> 419b8803 mttc0 k1,\$17,3
0+06a8 <[^>]*> 419b8804 mttc0 k1,\$17,4
0+06ac <[^>]*> 419b8805 mttc0 k1,\$17,5
0+06b0 <[^>]*> 419b8806 mttc0 k1,\$17,6
0+06b4 <[^>]*> 419b8807 mttc0 k1,\$17,7
0+06b8 <[^>]*> 419b9000 mttc0 k1,c0_watchlo
0+06bc <[^>]*> 419b9001 mttc0 k1,c0_watchlo,1
0+06c0 <[^>]*> 419b9002 mttc0 k1,c0_watchlo,2
0+06c4 <[^>]*> 419b9003 mttc0 k1,c0_watchlo,3
0+06c8 <[^>]*> 419b9004 mttc0 k1,c0_watchlo,4
0+06cc <[^>]*> 419b9005 mttc0 k1,c0_watchlo,5
0+06d0 <[^>]*> 419b9006 mttc0 k1,c0_watchlo,6
0+06d4 <[^>]*> 419b9007 mttc0 k1,c0_watchlo,7
0+06d8 <[^>]*> 419b9800 mttc0 k1,c0_watchhi
0+06dc <[^>]*> 419b9801 mttc0 k1,c0_watchhi,1
0+06e0 <[^>]*> 419b9802 mttc0 k1,c0_watchhi,2
0+06e4 <[^>]*> 419b9803 mttc0 k1,c0_watchhi,3
0+06e8 <[^>]*> 419b9804 mttc0 k1,c0_watchhi,4
0+06ec <[^>]*> 419b9805 mttc0 k1,c0_watchhi,5
0+06f0 <[^>]*> 419b9806 mttc0 k1,c0_watchhi,6
0+06f4 <[^>]*> 419b9807 mttc0 k1,c0_watchhi,7
0+06f8 <[^>]*> 419ba000 mttc0 k1,c0_xcontext
0+06fc <[^>]*> 419ba001 mttc0 k1,\$20,1
0+0700 <[^>]*> 419ba002 mttc0 k1,\$20,2
0+0704 <[^>]*> 419ba003 mttc0 k1,\$20,3
0+0708 <[^>]*> 419ba004 mttc0 k1,\$20,4
0+070c <[^>]*> 419ba005 mttc0 k1,\$20,5
0+0710 <[^>]*> 419ba006 mttc0 k1,\$20,6
0+0714 <[^>]*> 419ba007 mttc0 k1,\$20,7
0+0718 <[^>]*> 419ba800 mttc0 k1,\$21
0+071c <[^>]*> 419ba801 mttc0 k1,\$21,1
0+0720 <[^>]*> 419ba802 mttc0 k1,\$21,2
0+0724 <[^>]*> 419ba803 mttc0 k1,\$21,3
0+0728 <[^>]*> 419ba804 mttc0 k1,\$21,4
0+072c <[^>]*> 419ba805 mttc0 k1,\$21,5
0+0730 <[^>]*> 419ba806 mttc0 k1,\$21,6
0+0734 <[^>]*> 419ba807 mttc0 k1,\$21,7
0+0738 <[^>]*> 419bb000 mttc0 k1,\$22
0+073c <[^>]*> 419bb001 mttc0 k1,\$22,1
0+0740 <[^>]*> 419bb002 mttc0 k1,\$22,2
0+0744 <[^>]*> 419bb003 mttc0 k1,\$22,3
0+0748 <[^>]*> 419bb004 mttc0 k1,\$22,4
0+074c <[^>]*> 419bb005 mttc0 k1,\$22,5
0+0750 <[^>]*> 419bb006 mttc0 k1,\$22,6
0+0754 <[^>]*> 419bb007 mttc0 k1,\$22,7
0+0758 <[^>]*> 419bb800 mttc0 k1,c0_debug
0+075c <[^>]*> 419bb801 mttc0 k1,\$23,1
0+0760 <[^>]*> 419bb802 mttc0 k1,\$23,2
0+0764 <[^>]*> 419bb803 mttc0 k1,\$23,3
0+0768 <[^>]*> 419bb804 mttc0 k1,\$23,4
0+076c <[^>]*> 419bb805 mttc0 k1,\$23,5
0+0770 <[^>]*> 419bb806 mttc0 k1,\$23,6
0+0774 <[^>]*> 419bb807 mttc0 k1,\$23,7
0+0778 <[^>]*> 419bc000 mttc0 k1,c0_depc
0+077c <[^>]*> 419bc001 mttc0 k1,\$24,1
0+0780 <[^>]*> 419bc002 mttc0 k1,\$24,2
0+0784 <[^>]*> 419bc003 mttc0 k1,\$24,3
0+0788 <[^>]*> 419bc004 mttc0 k1,\$24,4
0+078c <[^>]*> 419bc005 mttc0 k1,\$24,5
0+0790 <[^>]*> 419bc006 mttc0 k1,\$24,6
0+0794 <[^>]*> 419bc007 mttc0 k1,\$24,7
0+0798 <[^>]*> 419bc800 mttc0 k1,c0_perfcnt
0+079c <[^>]*> 419bc801 mttc0 k1,c0_perfcnt,1
0+07a0 <[^>]*> 419bc802 mttc0 k1,c0_perfcnt,2
0+07a4 <[^>]*> 419bc803 mttc0 k1,c0_perfcnt,3
0+07a8 <[^>]*> 419bc804 mttc0 k1,c0_perfcnt,4
0+07ac <[^>]*> 419bc805 mttc0 k1,c0_perfcnt,5
0+07b0 <[^>]*> 419bc806 mttc0 k1,c0_perfcnt,6
0+07b4 <[^>]*> 419bc807 mttc0 k1,c0_perfcnt,7
0+07b8 <[^>]*> 419bd000 mttc0 k1,c0_errctl
0+07bc <[^>]*> 419bd001 mttc0 k1,\$26,1
0+07c0 <[^>]*> 419bd002 mttc0 k1,\$26,2
0+07c4 <[^>]*> 419bd003 mttc0 k1,\$26,3
0+07c8 <[^>]*> 419bd004 mttc0 k1,\$26,4
0+07cc <[^>]*> 419bd005 mttc0 k1,\$26,5
0+07d0 <[^>]*> 419bd006 mttc0 k1,\$26,6
0+07d4 <[^>]*> 419bd007 mttc0 k1,\$26,7
0+07d8 <[^>]*> 419bd800 mttc0 k1,c0_cacheerr
0+07dc <[^>]*> 419bd801 mttc0 k1,c0_cacheerr,1
0+07e0 <[^>]*> 419bd802 mttc0 k1,c0_cacheerr,2
0+07e4 <[^>]*> 419bd803 mttc0 k1,c0_cacheerr,3
0+07e8 <[^>]*> 419bd804 mttc0 k1,\$27,4
0+07ec <[^>]*> 419bd805 mttc0 k1,\$27,5
0+07f0 <[^>]*> 419bd806 mttc0 k1,\$27,6
0+07f4 <[^>]*> 419bd807 mttc0 k1,\$27,7
0+07f8 <[^>]*> 419be000 mttc0 k1,c0_taglo
0+07fc <[^>]*> 419be001 mttc0 k1,c0_datalo
0+0800 <[^>]*> 419be002 mttc0 k1,\$28,2
0+0804 <[^>]*> 419be003 mttc0 k1,\$28,3
0+0808 <[^>]*> 419be004 mttc0 k1,\$28,4
0+080c <[^>]*> 419be005 mttc0 k1,\$28,5
0+0810 <[^>]*> 419be006 mttc0 k1,\$28,6
0+0814 <[^>]*> 419be007 mttc0 k1,\$28,7
0+0818 <[^>]*> 419be800 mttc0 k1,c0_taghi
0+081c <[^>]*> 419be801 mttc0 k1,c0_datahi
0+0820 <[^>]*> 419be802 mttc0 k1,\$29,2
0+0824 <[^>]*> 419be803 mttc0 k1,\$29,3
0+0828 <[^>]*> 419be804 mttc0 k1,\$29,4
0+082c <[^>]*> 419be805 mttc0 k1,\$29,5
0+0830 <[^>]*> 419be806 mttc0 k1,\$29,6
0+0834 <[^>]*> 419be807 mttc0 k1,\$29,7
0+0838 <[^>]*> 419bf000 mttc0 k1,c0_errorepc
0+083c <[^>]*> 419bf001 mttc0 k1,\$30,1
0+0840 <[^>]*> 419bf002 mttc0 k1,\$30,2
0+0844 <[^>]*> 419bf003 mttc0 k1,\$30,3
0+0848 <[^>]*> 419bf004 mttc0 k1,\$30,4
0+084c <[^>]*> 419bf005 mttc0 k1,\$30,5
0+0850 <[^>]*> 419bf006 mttc0 k1,\$30,6
0+0854 <[^>]*> 419bf007 mttc0 k1,\$30,7
0+0858 <[^>]*> 419bf800 mttc0 k1,c0_desave
0+085c <[^>]*> 419bf801 mttc0 k1,\$31,1
0+0860 <[^>]*> 419bf802 mttc0 k1,\$31,2
0+0864 <[^>]*> 419bf803 mttc0 k1,\$31,3
0+0868 <[^>]*> 419bf804 mttc0 k1,\$31,4
0+086c <[^>]*> 419bf805 mttc0 k1,\$31,5
0+0870 <[^>]*> 419bf806 mttc0 k1,\$31,6
0+0874 <[^>]*> 419bf807 mttc0 k1,\$31,7
0+0878 <[^>]*> 419ce820 mttgpr gp,sp
0+087c <[^>]*> 419d0021 mttlo sp
0+0880 <[^>]*> 419e6021 mttlo s8,\$ac3
0+0884 <[^>]*> 419f0821 mtthi ra
0+0888 <[^>]*> 41800821 mtthi zero
0+088c <[^>]*> 41811021 mttacx at
0+0890 <[^>]*> 41823021 mttacx v0,\$ac1
0+0894 <[^>]*> 41838021 mttdsp v1
0+0898 <[^>]*> 41842822 mttc1 a0,\$f5
0+089c <[^>]*> 41853022 mttc1 a1,\$f6
0+08a0 <[^>]*> 41864032 mtthc1 a2,\$f8
0+08a4 <[^>]*> 41875032 mtthc1 a3,\$f10
0+08a8 <[^>]*> 41884823 cttc1 t0,\$9
0+08ac <[^>]*> 41895023 cttc1 t1,\$10
0+08b0 <[^>]*> 418a5824 mttc2 t2,\$11
0+08b4 <[^>]*> 418b6034 mtthc2 t3,\$12
0+08b8 <[^>]*> 418c6825 cttc2 t4,\$13
0+08bc <[^>]*> 410d7030 mftr t5,t6,1,0,1
0+08c0 <[^>]*> 410d7031 mftr t5,t6,1,1,1
0+08c4 <[^>]*> 410d7032 mfthc1 t6,\$f13
0+08c8 <[^>]*> 410d7033 mftr t5,t6,1,3,1
0+08cc <[^>]*> 410d7034 mfthc2 t6,\$13
0+08d0 <[^>]*> 410d7035 mftr t5,t6,1,5,1
0+08d4 <[^>]*> 410d7036 mftr t5,t6,1,6,1
0+08d8 <[^>]*> 410d7037 mftr t5,t6,1,7,1
0+08dc <[^>]*> 410d7020 mftgpr t6,t5
0+08e0 <[^>]*> 410d7021 mfthi t6,\$ac3
0+08e4 <[^>]*> 410d7022 mftc1 t6,\$f13
0+08e8 <[^>]*> 410d7023 cftc1 t6,\$13
0+08ec <[^>]*> 410d7024 mftc2 t6,\$13
0+08f0 <[^>]*> 410d7025 cftc2 t6,\$13
0+08f4 <[^>]*> 410d7026 mftr t5,t6,1,6,0
0+08f8 <[^>]*> 410d7027 mftr t5,t6,1,7,0
0+08fc <[^>]*> 410d7030 mftr t5,t6,1,0,1
0+0900 <[^>]*> 410d7031 mftr t5,t6,1,1,1
0+0904 <[^>]*> 410d7032 mfthc1 t6,\$f13
0+0908 <[^>]*> 410d7033 mftr t5,t6,1,3,1
0+090c <[^>]*> 410d7034 mfthc2 t6,\$13
0+0910 <[^>]*> 410d7035 mftr t5,t6,1,5,1
0+0914 <[^>]*> 410d7036 mftr t5,t6,1,6,1
0+0918 <[^>]*> 410d7037 mftr t5,t6,1,7,1
0+091c <[^>]*> 410d7020 mftgpr t6,t5
0+0920 <[^>]*> 410d7021 mfthi t6,\$ac3
0+0924 <[^>]*> 410d7022 mftc1 t6,\$f13
0+0928 <[^>]*> 410d7023 cftc1 t6,\$13
0+092c <[^>]*> 410d7024 mftc2 t6,\$13
0+0930 <[^>]*> 410d7025 cftc2 t6,\$13
0+0934 <[^>]*> 410d7026 mftr t5,t6,1,6,0
0+0938 <[^>]*> 410d7027 mftr t5,t6,1,7,0
0+093c <[^>]*> 410d7010 mftr t5,t6,0,0,1
0+0940 <[^>]*> 410d7011 mftr t5,t6,0,1,1
0+0944 <[^>]*> 410d7012 mftr t5,t6,0,2,1
0+0948 <[^>]*> 410d7013 mftr t5,t6,0,3,1
0+094c <[^>]*> 410d7014 mftr t5,t6,0,4,1
0+0950 <[^>]*> 410d7015 mftr t5,t6,0,5,1
0+0954 <[^>]*> 410d7016 mftr t5,t6,0,6,1
0+0958 <[^>]*> 410d7017 mftr t5,t6,0,7,1
0+095c <[^>]*> 410d7000 mftc0 t6,c0_cause
0+0960 <[^>]*> 410d7001 mftc0 t6,\$13,1
0+0964 <[^>]*> 410d7002 mftc0 t6,\$13,2
0+0968 <[^>]*> 410d7003 mftc0 t6,\$13,3
0+096c <[^>]*> 410d7004 mftc0 t6,\$13,4
0+0970 <[^>]*> 410d7005 mftc0 t6,\$13,5
0+0974 <[^>]*> 410d7006 mftc0 t6,\$13,6
0+0978 <[^>]*> 410d7007 mftc0 t6,\$13,7
0+097c <[^>]*> 410d7010 mftr t5,t6,0,0,1
0+0980 <[^>]*> 410d7011 mftr t5,t6,0,1,1
0+0984 <[^>]*> 410d7012 mftr t5,t6,0,2,1
0+0988 <[^>]*> 410d7013 mftr t5,t6,0,3,1
0+098c <[^>]*> 410d7014 mftr t5,t6,0,4,1
0+0990 <[^>]*> 410d7015 mftr t5,t6,0,5,1
0+0994 <[^>]*> 410d7016 mftr t5,t6,0,6,1
0+0998 <[^>]*> 410d7017 mftr t5,t6,0,7,1
0+099c <[^>]*> 410d7000 mftc0 t6,c0_cause
0+09a0 <[^>]*> 410d7001 mftc0 t6,\$13,1
0+09a4 <[^>]*> 410d7002 mftc0 t6,\$13,2
0+09a8 <[^>]*> 410d7003 mftc0 t6,\$13,3
0+09ac <[^>]*> 410d7004 mftc0 t6,\$13,4
0+09b0 <[^>]*> 410d7005 mftc0 t6,\$13,5
0+09b4 <[^>]*> 410d7006 mftc0 t6,\$13,6
0+09b8 <[^>]*> 410d7007 mftc0 t6,\$13,7
0+09bc <[^>]*> 410d7030 mftr t5,t6,1,0,1
0+09c0 <[^>]*> 410d7031 mftr t5,t6,1,1,1
0+09c4 <[^>]*> 410d7032 mfthc1 t6,\$f13
0+09c8 <[^>]*> 410d7033 mftr t5,t6,1,3,1
0+09cc <[^>]*> 410d7034 mfthc2 t6,\$13
0+09d0 <[^>]*> 410d7035 mftr t5,t6,1,5,1
0+09d4 <[^>]*> 410d7036 mftr t5,t6,1,6,1
0+09d8 <[^>]*> 410d7037 mftr t5,t6,1,7,1
0+09dc <[^>]*> 410d7020 mftgpr t6,t5
0+09e0 <[^>]*> 410d7021 mfthi t6,\$ac3
0+09e4 <[^>]*> 410d7022 mftc1 t6,\$f13
0+09e8 <[^>]*> 410d7023 cftc1 t6,\$13
0+09ec <[^>]*> 410d7024 mftc2 t6,\$13
0+09f0 <[^>]*> 410d7025 cftc2 t6,\$13
0+09f4 <[^>]*> 410d7026 mftr t5,t6,1,6,0
0+09f8 <[^>]*> 410d7027 mftr t5,t6,1,7,0
0+09fc <[^>]*> 410d7030 mftr t5,t6,1,0,1
0+0a00 <[^>]*> 410d7031 mftr t5,t6,1,1,1
0+0a04 <[^>]*> 410d7032 mfthc1 t6,\$f13
0+0a08 <[^>]*> 410d7033 mftr t5,t6,1,3,1
0+0a0c <[^>]*> 410d7034 mfthc2 t6,\$13
0+0a10 <[^>]*> 410d7035 mftr t5,t6,1,5,1
0+0a14 <[^>]*> 410d7036 mftr t5,t6,1,6,1
0+0a18 <[^>]*> 410d7037 mftr t5,t6,1,7,1
0+0a1c <[^>]*> 410d7020 mftgpr t6,t5
0+0a20 <[^>]*> 410d7021 mfthi t6,\$ac3
0+0a24 <[^>]*> 410d7022 mftc1 t6,\$f13
0+0a28 <[^>]*> 410d7023 cftc1 t6,\$13
0+0a2c <[^>]*> 410d7024 mftc2 t6,\$13
0+0a30 <[^>]*> 410d7025 cftc2 t6,\$13
0+0a34 <[^>]*> 410d7026 mftr t5,t6,1,6,0
0+0a38 <[^>]*> 410d7027 mftr t5,t6,1,7,0
0+0a3c <[^>]*> 410d7010 mftr t5,t6,0,0,1
0+0a40 <[^>]*> 410d7011 mftr t5,t6,0,1,1
0+0a44 <[^>]*> 410d7012 mftr t5,t6,0,2,1
0+0a48 <[^>]*> 410d7013 mftr t5,t6,0,3,1
0+0a4c <[^>]*> 410d7014 mftr t5,t6,0,4,1
0+0a50 <[^>]*> 410d7015 mftr t5,t6,0,5,1
0+0a54 <[^>]*> 410d7016 mftr t5,t6,0,6,1
0+0a58 <[^>]*> 410d7017 mftr t5,t6,0,7,1
0+0a5c <[^>]*> 410d7000 mftc0 t6,c0_cause
0+0a60 <[^>]*> 410d7001 mftc0 t6,\$13,1
0+0a64 <[^>]*> 410d7002 mftc0 t6,\$13,2
0+0a68 <[^>]*> 410d7003 mftc0 t6,\$13,3
0+0a6c <[^>]*> 410d7004 mftc0 t6,\$13,4
0+0a70 <[^>]*> 410d7005 mftc0 t6,\$13,5
0+0a74 <[^>]*> 410d7006 mftc0 t6,\$13,6
0+0a78 <[^>]*> 410d7007 mftc0 t6,\$13,7
0+0a7c <[^>]*> 410d7010 mftr t5,t6,0,0,1
0+0a80 <[^>]*> 410d7011 mftr t5,t6,0,1,1
0+0a84 <[^>]*> 410d7012 mftr t5,t6,0,2,1
0+0a88 <[^>]*> 410d7013 mftr t5,t6,0,3,1
0+0a8c <[^>]*> 410d7014 mftr t5,t6,0,4,1
0+0a90 <[^>]*> 410d7015 mftr t5,t6,0,5,1
0+0a94 <[^>]*> 410d7016 mftr t5,t6,0,6,1
0+0a98 <[^>]*> 410d7017 mftr t5,t6,0,7,1
0+0a9c <[^>]*> 410d7000 mftc0 t6,c0_cause
0+0aa0 <[^>]*> 410d7001 mftc0 t6,\$13,1
0+0aa4 <[^>]*> 410d7002 mftc0 t6,\$13,2
0+0aa8 <[^>]*> 410d7003 mftc0 t6,\$13,3
0+0aac <[^>]*> 410d7004 mftc0 t6,\$13,4
0+0ab0 <[^>]*> 410d7005 mftc0 t6,\$13,5
0+0ab4 <[^>]*> 410d7006 mftc0 t6,\$13,6
0+0ab8 <[^>]*> 410d7007 mftc0 t6,\$13,7
0+0abc <[^>]*> 418d7030 mttr t5,t6,1,0,1
0+0ac0 <[^>]*> 418d7031 mttr t5,t6,1,1,1
0+0ac4 <[^>]*> 418d7032 mtthc1 t5,\$f14
0+0ac8 <[^>]*> 418d7033 mttr t5,t6,1,3,1
0+0acc <[^>]*> 418d7034 mtthc2 t5,\$14
0+0ad0 <[^>]*> 418d7035 mttr t5,t6,1,5,1
0+0ad4 <[^>]*> 418d7036 mttr t5,t6,1,6,1
0+0ad8 <[^>]*> 418d7037 mttr t5,t6,1,7,1
0+0adc <[^>]*> 418d7020 mttgpr t5,t6
0+0ae0 <[^>]*> 418d7021 mttacx t5,\$ac3
0+0ae4 <[^>]*> 418d7022 mttc1 t5,\$f14
0+0ae8 <[^>]*> 418d7023 cttc1 t5,\$14
0+0aec <[^>]*> 418d7024 mttc2 t5,\$14
0+0af0 <[^>]*> 418d7025 cttc2 t5,\$14
0+0af4 <[^>]*> 418d7026 mttr t5,t6,1,6,0
0+0af8 <[^>]*> 418d7027 mttr t5,t6,1,7,0
0+0afc <[^>]*> 418d7030 mttr t5,t6,1,0,1
0+0b00 <[^>]*> 418d7031 mttr t5,t6,1,1,1
0+0b04 <[^>]*> 418d7032 mtthc1 t5,\$f14
0+0b08 <[^>]*> 418d7033 mttr t5,t6,1,3,1
0+0b0c <[^>]*> 418d7034 mtthc2 t5,\$14
0+0b10 <[^>]*> 418d7035 mttr t5,t6,1,5,1
0+0b14 <[^>]*> 418d7036 mttr t5,t6,1,6,1
0+0b18 <[^>]*> 418d7037 mttr t5,t6,1,7,1
0+0b1c <[^>]*> 418d7020 mttgpr t5,t6
0+0b20 <[^>]*> 418d7021 mttacx t5,\$ac3
0+0b24 <[^>]*> 418d7022 mttc1 t5,\$f14
0+0b28 <[^>]*> 418d7023 cttc1 t5,\$14
0+0b2c <[^>]*> 418d7024 mttc2 t5,\$14
0+0b30 <[^>]*> 418d7025 cttc2 t5,\$14
0+0b34 <[^>]*> 418d7026 mttr t5,t6,1,6,0
0+0b38 <[^>]*> 418d7027 mttr t5,t6,1,7,0
0+0b3c <[^>]*> 418d7010 mttr t5,t6,0,0,1
0+0b40 <[^>]*> 418d7011 mttr t5,t6,0,1,1
0+0b44 <[^>]*> 418d7012 mttr t5,t6,0,2,1
0+0b48 <[^>]*> 418d7013 mttr t5,t6,0,3,1
0+0b4c <[^>]*> 418d7014 mttr t5,t6,0,4,1
0+0b50 <[^>]*> 418d7015 mttr t5,t6,0,5,1
0+0b54 <[^>]*> 418d7016 mttr t5,t6,0,6,1
0+0b58 <[^>]*> 418d7017 mttr t5,t6,0,7,1
0+0b5c <[^>]*> 418d7000 mttc0 t5,c0_epc
0+0b60 <[^>]*> 418d7001 mttc0 t5,\$14,1
0+0b64 <[^>]*> 418d7002 mttc0 t5,\$14,2
0+0b68 <[^>]*> 418d7003 mttc0 t5,\$14,3
0+0b6c <[^>]*> 418d7004 mttc0 t5,\$14,4
0+0b70 <[^>]*> 418d7005 mttc0 t5,\$14,5
0+0b74 <[^>]*> 418d7006 mttc0 t5,\$14,6
0+0b78 <[^>]*> 418d7007 mttc0 t5,\$14,7
0+0b7c <[^>]*> 418d7010 mttr t5,t6,0,0,1
0+0b80 <[^>]*> 418d7011 mttr t5,t6,0,1,1
0+0b84 <[^>]*> 418d7012 mttr t5,t6,0,2,1
0+0b88 <[^>]*> 418d7013 mttr t5,t6,0,3,1
0+0b8c <[^>]*> 418d7014 mttr t5,t6,0,4,1
0+0b90 <[^>]*> 418d7015 mttr t5,t6,0,5,1
0+0b94 <[^>]*> 418d7016 mttr t5,t6,0,6,1
0+0b98 <[^>]*> 418d7017 mttr t5,t6,0,7,1
0+0b9c <[^>]*> 418d7000 mttc0 t5,c0_epc
0+0ba0 <[^>]*> 418d7001 mttc0 t5,\$14,1
0+0ba4 <[^>]*> 418d7002 mttc0 t5,\$14,2
0+0ba8 <[^>]*> 418d7003 mttc0 t5,\$14,3
0+0bac <[^>]*> 418d7004 mttc0 t5,\$14,4
0+0bb0 <[^>]*> 418d7005 mttc0 t5,\$14,5
0+0bb4 <[^>]*> 418d7006 mttc0 t5,\$14,6
0+0bb8 <[^>]*> 418d7007 mttc0 t5,\$14,7
0+0bbc <[^>]*> 418d7030 mttr t5,t6,1,0,1
0+0bc0 <[^>]*> 418d7031 mttr t5,t6,1,1,1
0+0bc4 <[^>]*> 418d7032 mtthc1 t5,\$f14
0+0bc8 <[^>]*> 418d7033 mttr t5,t6,1,3,1
0+0bcc <[^>]*> 418d7034 mtthc2 t5,\$14
0+0bd0 <[^>]*> 418d7035 mttr t5,t6,1,5,1
0+0bd4 <[^>]*> 418d7036 mttr t5,t6,1,6,1
0+0bd8 <[^>]*> 418d7037 mttr t5,t6,1,7,1
0+0bdc <[^>]*> 418d7020 mttgpr t5,t6
0+0be0 <[^>]*> 418d7021 mttacx t5,\$ac3
0+0be4 <[^>]*> 418d7022 mttc1 t5,\$f14
0+0be8 <[^>]*> 418d7023 cttc1 t5,\$14
0+0bec <[^>]*> 418d7024 mttc2 t5,\$14
0+0bf0 <[^>]*> 418d7025 cttc2 t5,\$14
0+0bf4 <[^>]*> 418d7026 mttr t5,t6,1,6,0
0+0bf8 <[^>]*> 418d7027 mttr t5,t6,1,7,0
0+0bfc <[^>]*> 418d7030 mttr t5,t6,1,0,1
0+0c00 <[^>]*> 418d7031 mttr t5,t6,1,1,1
0+0c04 <[^>]*> 418d7032 mtthc1 t5,\$f14
0+0c08 <[^>]*> 418d7033 mttr t5,t6,1,3,1
0+0c0c <[^>]*> 418d7034 mtthc2 t5,\$14
0+0c10 <[^>]*> 418d7035 mttr t5,t6,1,5,1
0+0c14 <[^>]*> 418d7036 mttr t5,t6,1,6,1
0+0c18 <[^>]*> 418d7037 mttr t5,t6,1,7,1
0+0c1c <[^>]*> 418d7020 mttgpr t5,t6
0+0c20 <[^>]*> 418d7021 mttacx t5,\$ac3
0+0c24 <[^>]*> 418d7022 mttc1 t5,\$f14
0+0c28 <[^>]*> 418d7023 cttc1 t5,\$14
0+0c2c <[^>]*> 418d7024 mttc2 t5,\$14
0+0c30 <[^>]*> 418d7025 cttc2 t5,\$14
0+0c34 <[^>]*> 418d7026 mttr t5,t6,1,6,0
0+0c38 <[^>]*> 418d7027 mttr t5,t6,1,7,0
0+0c3c <[^>]*> 418d7010 mttr t5,t6,0,0,1
0+0c40 <[^>]*> 418d7011 mttr t5,t6,0,1,1
0+0c44 <[^>]*> 418d7012 mttr t5,t6,0,2,1
0+0c48 <[^>]*> 418d7013 mttr t5,t6,0,3,1
0+0c4c <[^>]*> 418d7014 mttr t5,t6,0,4,1
0+0c50 <[^>]*> 418d7015 mttr t5,t6,0,5,1
0+0c54 <[^>]*> 418d7016 mttr t5,t6,0,6,1
0+0c58 <[^>]*> 418d7017 mttr t5,t6,0,7,1
0+0c5c <[^>]*> 418d7000 mttc0 t5,c0_epc
0+0c60 <[^>]*> 418d7001 mttc0 t5,\$14,1
0+0c64 <[^>]*> 418d7002 mttc0 t5,\$14,2
0+0c68 <[^>]*> 418d7003 mttc0 t5,\$14,3
0+0c6c <[^>]*> 418d7004 mttc0 t5,\$14,4
0+0c70 <[^>]*> 418d7005 mttc0 t5,\$14,5
0+0c74 <[^>]*> 418d7006 mttc0 t5,\$14,6
0+0c78 <[^>]*> 418d7007 mttc0 t5,\$14,7
0+0c7c <[^>]*> 418d7010 mttr t5,t6,0,0,1
0+0c80 <[^>]*> 418d7011 mttr t5,t6,0,1,1
0+0c84 <[^>]*> 418d7012 mttr t5,t6,0,2,1
0+0c88 <[^>]*> 418d7013 mttr t5,t6,0,3,1
0+0c8c <[^>]*> 418d7014 mttr t5,t6,0,4,1
0+0c90 <[^>]*> 418d7015 mttr t5,t6,0,5,1
0+0c94 <[^>]*> 418d7016 mttr t5,t6,0,6,1
0+0c98 <[^>]*> 418d7017 mttr t5,t6,0,7,1
0+0c9c <[^>]*> 418d7000 mttc0 t5,c0_epc
0+0ca0 <[^>]*> 418d7001 mttc0 t5,\$14,1
0+0ca4 <[^>]*> 418d7002 mttc0 t5,\$14,2
0+0ca8 <[^>]*> 418d7003 mttc0 t5,\$14,3
0+0cac <[^>]*> 418d7004 mttc0 t5,\$14,4
0+0cb0 <[^>]*> 418d7005 mttc0 t5,\$14,5
0+0cb4 <[^>]*> 418d7006 mttc0 t5,\$14,6
0+0cb8 <[^>]*> 418d7007 mttc0 t5,\$14,7
...
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [patch] GAS supports for MIPS32 MT ASE
2005-08-31 0:49 ` Chao-ying Fu
@ 2005-09-02 12:15 ` Thiemo Seufer
2005-09-02 15:43 ` Eric Christopher
0 siblings, 1 reply; 15+ messages in thread
From: Thiemo Seufer @ 2005-09-02 12:15 UTC (permalink / raw)
To: Chao-ying Fu
Cc: Eric Christopher, Daniel Jacobowitz, Maciej W. Rozycki, Thekkath,
Radhika, binutils
Chao-ying Fu wrote:
[snip]
> include/opcode/ChangeLog
> 2005-08-30 Chao-ying Fu <fu@mips.com>
>
> * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
> OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
> define.
> Document !, $, *, &, g, +t, +T operand formats for MT instructions.
> (INSN_ASE_MASK): Update to include INSN_MT.
> (INSN_MT): New define for MT ASE.
>
> opcodes/ChangeLog
> 2005-08-30 Chao-ying Fu <fu@mips.com>
>
> * mips-opc.c (MT32): New define.
> (mips_builtin_opcodes): Move "bc0f", "bc0fl", "bc0t", "bc0tl" to the
> bottom to avoid opcode collision with "mftr" and "mttr".
> Add MT instructions.
> * mips-dis.c (mips_arch_choices): Enable INSN_MT for mips32r2.
> (print_insn_args): Add supports for +t, +T, !, $, *, &, g operand
> formats.
>
> gas/ChangeLog
> 2005-08-30 Chao-ying Fu <fu@mips.com>
>
> * config/tc-mips.c (mips_set_options): Add ase_mt for MT instructions.
> (mips_opts): Add -1 to initialize ase_mt.
> (file_ase_mt): New variable for -mmt.
> (CPU_HAS_MT): New define.
> (validate_mips_insn): Add supports for +t, +T, !, $, *, &, g operand
> formats.
> (mips_ip): Check ase_mt to enable MT instructions.
> Handle !, $, *, &, +T, +t, g operand formats.
> For "mftc1", "mfthc1", "cftc1", "mttc1", "mtthc1", "cttc1", we allow
> odd float registers.
> (OPTION_MT, OPTION_NO_MT): New define.
> (OPTION_COMPAT_ARCH_BASE): Change because of inserting MT define.
> (md_parse_option): Parse OPTION_MT and OPTION_NO_MT.
> (mips_after_parse_args): Set ase_mt based on CPU.
> (s_mipsset): Handle ".set mt" and ".set nomt".
> (mips_elf_final_processing): Remind of adding new flag for MT ASE.
> (md_show_usage): Show usage of -mmt and -mno-mt.
>
> gas/testsuite/ChangeLog
> 2005-08-30 Chao-ying Fu <fu@mips.com>
>
> * gas/mips/mips.exp: Run MT test for mips32r2 only.
> * gas/mips/mips32-mt.[sdl]: New test.
Ok. Can you also update the assembler documentation for -mmt in a
followup patch?
Thiemo
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [patch] GAS supports for MIPS32 MT ASE
2005-09-02 12:15 ` Thiemo Seufer
@ 2005-09-02 15:43 ` Eric Christopher
2005-09-05 6:56 ` Chao-ying Fu
0 siblings, 1 reply; 15+ messages in thread
From: Eric Christopher @ 2005-09-02 15:43 UTC (permalink / raw)
To: Thiemo Seufer
Cc: Chao-ying Fu, Daniel Jacobowitz, Maciej W. Rozycki, Thekkath,
Radhika, binutils
>
> Ok. Can you also update the assembler documentation for -mmt in a
> followup patch?
>
It should be part of this patch.
-eric
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [patch] GAS supports for MIPS32 MT ASE
2005-09-02 15:43 ` Eric Christopher
@ 2005-09-05 6:56 ` Chao-ying Fu
2005-09-05 22:33 ` Thiemo Seufer
0 siblings, 1 reply; 15+ messages in thread
From: Chao-ying Fu @ 2005-09-05 6:56 UTC (permalink / raw)
To: Eric Christopher, Thiemo Seufer
Cc: Daniel Jacobowitz, Maciej W. Rozycki, Thekkath, Radhika, binutils
Sure. The document patch will be include with the previous patch.
Is it ok? Thanks!
Regards,
Chao-ying
gas/ChangeLog
2005-09-02 Chao-ying Fu <fu@mips.com>
* doc/as.texinfo: Document -mmt and -mno-mt options.
* doc/c-mips.texi: Likewise, and document ".set mt" and ".set nomt"
directives.
Index: as.texinfo
===================================================================
RCS file: /cvs/src/src/gas/doc/as.texinfo,v
retrieving revision 1.124
diff -c -3 -p -r1.124 as.texinfo
*** as.texinfo 11 Aug 2005 01:25:29 -0000 1.124
--- as.texinfo 2 Sep 2005 21:23:24 -0000
*************** gcc(1), ld(1), and the Info entries for
*** 368,373 ****
--- 368,374 ----
[@b{-mips16}] [@b{-no-mips16}]
[@b{-mips3d}] [@b{-no-mips3d}]
[@b{-mdmx}] [@b{-no-mdmx}]
+ [@b{-mmt}] [@b{-mno-mt}]
[@b{-mdebug}] [@b{-no-mdebug}]
[@b{-mpdr}] [@b{-mno-pdr}]
@end ifset
*************** Generate code for the MDMX Application S
*** 1000,1005 ****
--- 1001,1012 ----
This tells the assembler to accept MDMX instructions.
@samp{-no-mdmx} turns off this option.
+ @item -mmt
+ @itemx -mno-mt
+ Generate code for the MT Application Specific Extension.
+ This tells the assembler to accept MT instructions.
+ @samp{-mno-mt} turns off this option.
+
@item --construct-floats
@itemx --no-construct-floats
The @samp{--no-construct-floats} option disables the construction of
Index: c-mips.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/c-mips.texi,v
retrieving revision 1.34
diff -c -3 -p -r1.34 c-mips.texi
*** c-mips.texi 9 Mar 2005 09:53:49 -0000 1.34
--- c-mips.texi 2 Sep 2005 21:23:24 -0000
*************** Generate code for the MDMX Application S
*** 118,123 ****
--- 118,129 ----
This tells the assembler to accept MDMX instructions.
@samp{-no-mdmx} turns off this option.
+ @item -mmt
+ @itemx -mno-mt
+ Generate code for the MT Application Specific Extension.
+ This tells the assembler to accept MT instructions.
+ @samp{-mno-mt} turns off this option.
+
@item -mfix7000
@itemx -mno-fix7000
Cause nops to be inserted if the read of the destination register
*************** from the MDMX Application Specific Exten
*** 451,454 ****
--- 457,468 ----
in the assembly. The @code{.set nomdmx} directive prevents MDMX
instructions from being accepted.
+ @cindex MIPS MT instruction generation override
+ @kindex @code{.set mt}
+ @kindex @code{.set nomt}
+ The directive @code{.set mt} makes the assembler accept instructions
+ from the MT Application Specific Extension from that point on
+ in the assembly. The @code{.set nomt} directive prevents MT
+ instructions from being accepted.
+
Traditional @sc{mips} assemblers do not support these directives.
----- Original Message -----
From: "Eric Christopher" <echristo@apple.com>
To: "Thiemo Seufer" <ths@networkno.de>
Cc: "Chao-ying Fu" <fu@mips.com>; "Daniel Jacobowitz" <drow@false.org>;
"Maciej W. Rozycki" <macro@linux-mips.org>; "Thekkath, Radhika"
<radhika@mips.com>; <binutils@sourceware.org>
Sent: Friday, September 02, 2005 8:21 AM
Subject: Re: [patch] GAS supports for MIPS32 MT ASE
> >
> > Ok. Can you also update the assembler documentation for -mmt in a
> > followup patch?
> >
>
> It should be part of this patch.
>
> -eric
>
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [patch] GAS supports for MIPS32 MT ASE
2005-09-05 6:56 ` Chao-ying Fu
@ 2005-09-05 22:33 ` Thiemo Seufer
2005-09-06 16:19 ` Eric Christopher
0 siblings, 1 reply; 15+ messages in thread
From: Thiemo Seufer @ 2005-09-05 22:33 UTC (permalink / raw)
To: Chao-ying Fu
Cc: Eric Christopher, Daniel Jacobowitz, Maciej W. Rozycki, Thekkath,
Radhika, binutils
Chao-ying Fu wrote:
> Sure. The document patch will be include with the previous patch.
> Is it ok? Thanks!
I think so, yes. Eric, anything still left which isn't ok from your POV?
Thiemo
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [patch] GAS supports for MIPS32 MT ASE
2005-09-05 22:33 ` Thiemo Seufer
@ 2005-09-06 16:19 ` Eric Christopher
2005-09-06 21:51 ` Chao-ying Fu
0 siblings, 1 reply; 15+ messages in thread
From: Eric Christopher @ 2005-09-06 16:19 UTC (permalink / raw)
To: Thiemo Seufer
Cc: Chao-ying Fu, Daniel Jacobowitz, Maciej W. Rozycki, Thekkath,
Radhika, binutils
On Sep 5, 2005, at 12:24 AM, Thiemo Seufer wrote:
> Chao-ying Fu wrote:
>
>> Sure. The document patch will be include with the previous patch.
>> Is it ok? Thanks!
>>
>
> I think so, yes. Eric, anything still left which isn't ok from your
> POV?
Nah. I'm good.
-eric
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [patch] GAS supports for MIPS32 MT ASE
2005-09-06 16:19 ` Eric Christopher
@ 2005-09-06 21:51 ` Chao-ying Fu
0 siblings, 0 replies; 15+ messages in thread
From: Chao-ying Fu @ 2005-09-06 21:51 UTC (permalink / raw)
To: Eric Christopher, Thiemo Seufer
Cc: Daniel Jacobowitz, Maciej W. Rozycki, Thekkath, Radhika, binutils
Applied. Thanks a lot!
Regards,
Chao-ying
----- Original Message -----
From: "Eric Christopher" <echristo@apple.com>
To: "Thiemo Seufer" <ths@networkno.de>
Cc: "Chao-ying Fu" <fu@mips.com>; "Daniel Jacobowitz" <drow@false.org>;
"Maciej W. Rozycki" <macro@linux-mips.org>; "Thekkath, Radhika"
<radhika@mips.com>; <binutils@sourceware.org>
Sent: Tuesday, September 06, 2005 9:07 AM
Subject: Re: [patch] GAS supports for MIPS32 MT ASE
>
> On Sep 5, 2005, at 12:24 AM, Thiemo Seufer wrote:
>
> > Chao-ying Fu wrote:
> >
> >> Sure. The document patch will be include with the previous patch.
> >> Is it ok? Thanks!
> >>
> >
> > I think so, yes. Eric, anything still left which isn't ok from your
> > POV?
>
> Nah. I'm good.
>
> -eric
>
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2005-09-06 20:21 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2005-08-26 22:05 [patch] GAS supports for MIPS32 MT ASE Chao-ying Fu
2005-08-29 9:55 ` Maciej W. Rozycki
2005-08-29 23:23 ` Chao-ying Fu
2005-08-29 23:41 ` Thiemo Seufer
2005-08-30 22:54 ` Chao-ying Fu
2005-08-30 22:57 ` Eric Christopher
2005-08-30 23:01 ` Daniel Jacobowitz
2005-08-31 0:25 ` Eric Christopher
2005-08-31 0:49 ` Chao-ying Fu
2005-09-02 12:15 ` Thiemo Seufer
2005-09-02 15:43 ` Eric Christopher
2005-09-05 6:56 ` Chao-ying Fu
2005-09-05 22:33 ` Thiemo Seufer
2005-09-06 16:19 ` Eric Christopher
2005-09-06 21:51 ` Chao-ying Fu
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