* [patch gas] LDRD warnings for unpredictable behaviour.
@ 2011-06-08 15:12 James Greenhalgh
0 siblings, 0 replies; 3+ messages in thread
From: James Greenhalgh @ 2011-06-08 15:12 UTC (permalink / raw)
To: binutils
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This patch corrects the behaviour of do_ldrd to warn in
unpredictable cases and adds associated test cases. Previous code
checked against LOAD_BIT (mask 0x00100000) which is
not set for the LDRD instruction. This patch checks against
V4_STR_BIT (mask 0x00000020) to correctly distinguish between ldrd and
strd.
Tested using make check with no regression.
James Greenhalgh
gas/ChangeLog:
2011-05-25 James Greenhalgh <james.greenhalgh@arm.com>
* config/tc-arm.c (do_ldrd): Warn in unpredictable cases.
gas/testsuite/ChangeLog:
2011-05-25 James Greenhalgh <james.greenhalgh@arm.com>
* gas/arm/ldrd-unpredicatble.d: New testcase.
* gas/arm/ldrd-unpredicatble.s: Likewise.
* gas/arm/ldrd-unpredicatble.l: Likewise.
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0001-patch-gas-LDRD-warnings-for-unpredictable-behaviour.patch --]
[-- Type: text/x-patch; name=0001-patch-gas-LDRD-warnings-for-unpredictable-behaviour.patch, Size: 3458 bytes --]
diff --git gas/config/tc-arm.c gas/config/tc-arm.c
index 21ebdbe..d4262a9 100644
--- gas/config/tc-arm.c
+++ gas/config/tc-arm.c
@@ -7798,18 +7798,16 @@ static void
do_ldrd (void)
{
constraint (inst.operands[0].reg % 2 != 0,
- _("first destination register must be even"));
+ _("first transfer register must be even"));
constraint (inst.operands[1].present
&& inst.operands[1].reg != inst.operands[0].reg + 1,
- _("can only load two consecutive registers"));
+ _("can only transfer two consecutive registers"));
constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
constraint (!inst.operands[2].isreg, _("'[' expected"));
if (!inst.operands[1].present)
inst.operands[1].reg = inst.operands[0].reg + 1;
- if (inst.instruction & LOAD_BIT)
- {
/* encode_arm_addr_mode_3 will diagnose overlap between the base
register and the first register written; we have to diagnose
overlap between the base and the second register written here. */
@@ -7817,16 +7815,17 @@ do_ldrd (void)
if (inst.operands[2].reg == inst.operands[1].reg
&& (inst.operands[2].writeback || inst.operands[2].postind))
as_warn (_("base register written back, and overlaps "
- "second destination register"));
+ "second transfer register"));
+ if (!(inst.instruction & V4_STR_BIT))
+ {
/* For an index-register load, the index register must not overlap the
destination (even if not write-back). */
- else if (inst.operands[2].immisreg
+ if (inst.operands[2].immisreg
&& ((unsigned) inst.operands[2].imm == inst.operands[0].reg
|| (unsigned) inst.operands[2].imm == inst.operands[1].reg))
- as_warn (_("index register overlaps destination register"));
+ as_warn (_("index register overlaps transfer register"));
}
-
inst.instruction |= inst.operands[0].reg << 12;
encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
}
diff --git gas/testsuite/gas/arm/ldrd-unpredictable.d gas/testsuite/gas/arm/ldrd-unpredictable.d
new file mode 100644
index 0000000..10561b8
--- /dev/null
+++ gas/testsuite/gas/arm/ldrd-unpredictable.d
@@ -0,0 +1,2 @@
+# name: Unpredictable LDRD and STRD instructions. - ARM
+# error-output: ldrd-unpredictable.l
diff --git gas/testsuite/gas/arm/ldrd-unpredictable.l gas/testsuite/gas/arm/ldrd-unpredictable.l
new file mode 100644
index 0000000..3271714
--- /dev/null
+++ gas/testsuite/gas/arm/ldrd-unpredictable.l
@@ -0,0 +1,7 @@
+[^:]*: Assembler messages:
+[^:]*:6: Warning: index register overlaps transfer register
+[^:]*:7: Warning: index register overlaps transfer register
+[^:]*:8: Warning: source register same as write-back base
+[^:]*:9: Warning: base register written back, and overlaps second transfer register
+[^:]*:13: Warning: source register same as write-back base
+[^:]*:14: Warning: base register written back, and overlaps second transfer register
diff --git gas/testsuite/gas/arm/ldrd-unpredictable.s gas/testsuite/gas/arm/ldrd-unpredictable.s
new file mode 100644
index 0000000..1f67d74
--- /dev/null
+++ gas/testsuite/gas/arm/ldrd-unpredictable.s
@@ -0,0 +1,14 @@
+.syntax unified
+
+.arm
+
+@ LDRD
+ldrd r0,r1,[r0,r1] @ unpredictable
+ldrd r0,r1,[r1,r0] @ ditto
+ldrd r0,r1,[r0,r2]! @ ditto
+ldrd r0,r1,[r1,r2]! @ ditto
+
+@ STRD
+
+strd r0,r1,[r0,r2]! @ ditto
+strd r0,r1,[r1,r2]! @ ditto
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [patch gas] LDRD warnings for unpredictable behaviour.
2011-06-08 15:29 James Greenhalgh
@ 2011-06-09 10:02 ` Richard Earnshaw
0 siblings, 0 replies; 3+ messages in thread
From: Richard Earnshaw @ 2011-06-09 10:02 UTC (permalink / raw)
To: James Greenhalgh; +Cc: binutils
On 08/06/11 16:29, James Greenhalgh wrote:
> Apologies, I stripped the indentation changes with the previous send.
>
> James Greenhalgh
>
> ---
>
> This patch corrects the behaviour of do_ldrd to warn in
> unpredictable cases and adds associated test cases. Previous code
> checked against LOAD_BIT (mask 0x00100000) which is
> not set for the LDRD instruction. This patch checks against
> V4_STR_BIT (mask 0x00000020) to correctly distinguish between ldrd and
> strd.
>
> Tested using make check with no regression.
>
> James Greenhalgh
>
> gas/ChangeLog:
>
> 2011-05-25 James Greenhalgh <james.greenhalgh@arm.com>
>
> * config/tc-arm.c (do_ldrd): Warn in unpredictable cases.
>
> gas/testsuite/ChangeLog:
>
> 2011-05-25 James Greenhalgh <james.greenhalgh@arm.com>
>
> * gas/arm/ldrd-unpredicatble.d: New testcase.
> * gas/arm/ldrd-unpredicatble.s: Likewise.
> * gas/arm/ldrd-unpredicatble.l: Likewise.
>
>
Thanks, I've put this in.
I minor note. The final hunk (ldrd-unpredictable.s) did not apply
cleanly because the patch did not end with a new line and gnu patch
thought the hunk was thus corrupt. You might want to look at how you
generate your patches (there's a way of telling patch that the last line
doesn't have a terminator), but better still would be to ensure that
files end with a new-line marker.
R.
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [patch gas] LDRD warnings for unpredictable behaviour.
@ 2011-06-08 15:29 James Greenhalgh
2011-06-09 10:02 ` Richard Earnshaw
0 siblings, 1 reply; 3+ messages in thread
From: James Greenhalgh @ 2011-06-08 15:29 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 852 bytes --]
Apologies, I stripped the indentation changes with the previous send.
James Greenhalgh
---
This patch corrects the behaviour of do_ldrd to warn in
unpredictable cases and adds associated test cases. Previous code
checked against LOAD_BIT (mask 0x00100000) which is
not set for the LDRD instruction. This patch checks against
V4_STR_BIT (mask 0x00000020) to correctly distinguish between ldrd and
strd.
Tested using make check with no regression.
James Greenhalgh
gas/ChangeLog:
2011-05-25 James Greenhalgh <james.greenhalgh@arm.com>
* config/tc-arm.c (do_ldrd): Warn in unpredictable cases.
gas/testsuite/ChangeLog:
2011-05-25 James Greenhalgh <james.greenhalgh@arm.com>
* gas/arm/ldrd-unpredicatble.d: New testcase.
* gas/arm/ldrd-unpredicatble.s: Likewise.
* gas/arm/ldrd-unpredicatble.l: Likewise.
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0001-patch-gas-LDRD-warnings-for-unpredictable-behaviour.patch --]
[-- Type: text/x-patch; name=0001-patch-gas-LDRD-warnings-for-unpredictable-behaviour.patch, Size: 3999 bytes --]
diff --git gas/config/tc-arm.c gas/config/tc-arm.c
index 21ebdbe..d4262a9 100644
--- gas/config/tc-arm.c
+++ gas/config/tc-arm.c
@@ -7798,35 +7798,34 @@ static void
do_ldrd (void)
{
constraint (inst.operands[0].reg % 2 != 0,
- _("first destination register must be even"));
+ _("first transfer register must be even"));
constraint (inst.operands[1].present
&& inst.operands[1].reg != inst.operands[0].reg + 1,
- _("can only load two consecutive registers"));
+ _("can only transfer two consecutive registers"));
constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
constraint (!inst.operands[2].isreg, _("'[' expected"));
if (!inst.operands[1].present)
inst.operands[1].reg = inst.operands[0].reg + 1;
- if (inst.instruction & LOAD_BIT)
- {
- /* encode_arm_addr_mode_3 will diagnose overlap between the base
- register and the first register written; we have to diagnose
- overlap between the base and the second register written here. */
+ /* encode_arm_addr_mode_3 will diagnose overlap between the base
+ register and the first register written; we have to diagnose
+ overlap between the base and the second register written here. */
- if (inst.operands[2].reg == inst.operands[1].reg
- && (inst.operands[2].writeback || inst.operands[2].postind))
- as_warn (_("base register written back, and overlaps "
- "second destination register"));
+ if (inst.operands[2].reg == inst.operands[1].reg
+ && (inst.operands[2].writeback || inst.operands[2].postind))
+ as_warn (_("base register written back, and overlaps "
+ "second transfer register"));
+ if (!(inst.instruction & V4_STR_BIT))
+ {
/* For an index-register load, the index register must not overlap the
- destination (even if not write-back). */
- else if (inst.operands[2].immisreg
- && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
- || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
- as_warn (_("index register overlaps destination register"));
+ destination (even if not write-back). */
+ if (inst.operands[2].immisreg
+ && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
+ || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
+ as_warn (_("index register overlaps transfer register"));
}
-
inst.instruction |= inst.operands[0].reg << 12;
encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
}
diff --git gas/testsuite/gas/arm/ldrd-unpredictable.d gas/testsuite/gas/arm/ldrd-unpredictable.d
new file mode 100644
index 0000000..10561b8
--- /dev/null
+++ gas/testsuite/gas/arm/ldrd-unpredictable.d
@@ -0,0 +1,2 @@
+# name: Unpredictable LDRD and STRD instructions. - ARM
+# error-output: ldrd-unpredictable.l
diff --git gas/testsuite/gas/arm/ldrd-unpredictable.l gas/testsuite/gas/arm/ldrd-unpredictable.l
new file mode 100644
index 0000000..3271714
--- /dev/null
+++ gas/testsuite/gas/arm/ldrd-unpredictable.l
@@ -0,0 +1,7 @@
+[^:]*: Assembler messages:
+[^:]*:6: Warning: index register overlaps transfer register
+[^:]*:7: Warning: index register overlaps transfer register
+[^:]*:8: Warning: source register same as write-back base
+[^:]*:9: Warning: base register written back, and overlaps second transfer register
+[^:]*:13: Warning: source register same as write-back base
+[^:]*:14: Warning: base register written back, and overlaps second transfer register
diff --git gas/testsuite/gas/arm/ldrd-unpredictable.s gas/testsuite/gas/arm/ldrd-unpredictable.s
new file mode 100644
index 0000000..1f67d74
--- /dev/null
+++ gas/testsuite/gas/arm/ldrd-unpredictable.s
@@ -0,0 +1,14 @@
+.syntax unified
+
+.arm
+
+@ LDRD
+ldrd r0,r1,[r0,r1] @ unpredictable
+ldrd r0,r1,[r1,r0] @ ditto
+ldrd r0,r1,[r0,r2]! @ ditto
+ldrd r0,r1,[r1,r2]! @ ditto
+
+@ STRD
+
+strd r0,r1,[r0,r2]! @ ditto
+strd r0,r1,[r1,r2]! @ ditto
^ permalink raw reply [flat|nested] 3+ messages in thread
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2011-06-09 10:02 ` Richard Earnshaw
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