Hello, All,

  We want to contribute another GAS patch for MIPS32 MT ASE.  (This MT patch
is similar to the previous DSP patch, in terms of the code structure.)
The MT ASE defines 8 new instructions for multithreading as follows.

1. DMT: Disable multi-threaded execution
2. EMT: Enable multi-threaded execution
3. DVPE: Disable virtual processor execution
4. EVPE: Enable virtual processor execution
5. FORK: Allocate and schedule a new thread.
6. YIELD: Conditionally deschedule or deallocate the current thread.
7. MFTR: Move from thread context.
   (It has assembler idioms: MFTC0, MFTGPR, MFTLO, MFTHI, MFTACX,
    MFTDSP, MFTC1, MFTHC1, CFTC1, MFTC2, MFTHC2, CFTC2.)
8. MTTR: Move to thread context.
   (It has assembler idioms: MTTC0, MTTGPR, MTTLO, MTTHI, MTTACX,
    MTTDSP, MTTC1, MTTHC1, CTTC1, MTTC2, MTTHC2, CTTC2.)

  I built and tested with mipsisa64-elf and mipsisa32-elf.  No new
regressions.
Could you review this patch?  We will revise the patch, if there are issues.
Thanks a lot!

Regards,
Chao-ying

include/opcode/ChangeLog
2005-08-26  Chao-ying Fu  <fu@mips.com>

    * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
    OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
    define.
    Document !, $, *, &, g, +t, +T operand formats for MT instructions.
    (INSN_ASE_MASK): Update to include INSN_MT.
    (INSN_MT): New define for MT ASE.

opcodes/ChangeLog
2005-08-26  Chao-ying Fu  <fu@mips.com>

    * mips-opc.c (MT32): New define.
    (mips_builtin_opcodes): Add MT instructions.
    Move "bc0f", "bc0fl", "bc0t", "bc0tl" to the end to avoid opcode
    collision with "mftr" and "mttr".
    * mips-dis.c (mips_arch_choices): Enable INSN_MT for mips32r2.
    (print_insn_args): Add supports for +t, +T, !, $, *, &, g operand
    formats.

gas/ChangeLog
2005-08-26  Chao-ying Fu  <fu@mips.com>

    * config/tc-mips.c (mips_set_options): Add ase_mt for MT instructions.
    (mips_opts): Add -1 to initialize ase_mt.
    (file_ase_mt): New variable for -mt.
    (CPU_HAS_MT): New define.
    (validate_mips_insn): Add supports for +t, +T, !, $, *, &, g operand
    formats.
    (mips_ip): Check ase_mt to enable MT instructions.
    Handle !, $, *, &, +T, +t, g operand formats.
    For "mftc1", "mfthc1", "cftc1", "mttc1", "mtthc1", "cttc1", we allow
    odd float registers.
    (OPTION_MT, OPTION_NO_MT): New define.
    (OPTION_COMPAT_ARCH_BASE): Change because of inserting MT define.
    (md_parse_option): Parse OPTION_MT and OPTION_NO_MT.
    (mips_after_parse_args): Set ase_mt based on CPU.
    (s_mipsset): Handle ".set mt" and ".set nomt".
    (mips_elf_final_processing): Remind of adding new flag for MT ASE.
    (md_show_usage): Show usage of -mt and -mno-mt.

gas/testsuite/ChangeLog
2005-08-26  Chao-ying Fu  <fu@mips.com>

    * gas/mips/mips.exp: Run MT test for mips32r2 only.
    * gas/mips/mips32-mt.[sdl]: New test.