From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 28701 invoked by alias); 29 Aug 2005 23:23:06 -0000 Mailing-List: contact binutils-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sources.redhat.com Received: (qmail 28585 invoked by uid 22791); 29 Aug 2005 23:22:56 -0000 Received: from 209-232-97-206.ded.pacbell.net (HELO dns0.mips.com) (209.232.97.206) by sourceware.org (qpsmtpd/0.30-dev) with ESMTP; Mon, 29 Aug 2005 23:22:55 +0000 Received: from mercury.mips.com (sbcns-dmz [209.232.97.193]) by dns0.mips.com (8.12.11/8.12.11) with ESMTP id j7TNMY9c026609; Mon, 29 Aug 2005 16:22:35 -0700 (PDT) Received: from exchange.MIPS.COM (exchange [192.168.20.29]) by mercury.mips.com (8.12.9/8.12.11) with ESMTP id j7TNMVvU020077; Mon, 29 Aug 2005 16:22:31 -0700 (PDT) Received: from pcfu ([192.168.20.169]) by exchange.MIPS.COM with Microsoft SMTPSVC(6.0.3790.211); Mon, 29 Aug 2005 16:22:33 -0700 Message-ID: <002101c5acf0$8876c220$a914a8c0@MIPS.COM> Reply-To: "Chao-ying Fu" From: "Chao-ying Fu" To: "Maciej W. Rozycki" Cc: "Eric Christopher" , "Thekkath, Radhika" , "Thiemo Seufer" , References: <001401c5aa8a$3f2698b0$a914a8c0@MIPS.COM> Subject: Re: [patch] GAS supports for MIPS32 MT ASE Date: Mon, 29 Aug 2005 23:23:00 -0000 MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_NextPart_000_001E_01C5ACB5.DBFB3A60" X-SW-Source: 2005-08/txt/msg00397.txt.bz2 This is a multi-part message in MIME format. ------=_NextPart_000_001E_01C5ACB5.DBFB3A60 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-length: 5093 Ok. I fixed all the issues except the option name -mt/-mno-mt, because it seems redundant to have two "m"s (-mmt). Any suggestion? (I still attach the diff file to avoid the line-wrap problem from my email program.) Regards, Chao-ying include/opcode/ChangeLog 2005-08-29 Chao-ying Fu * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H, OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New define. Document !, $, *, &, g, +t, +T operand formats for MT instructions. (INSN_ASE_MASK): Update to include INSN_MT. (INSN_MT): New define for MT ASE. opcodes/ChangeLog 2005-08-29 Chao-ying Fu * mips-opc.c (MT32): New define. (mips_builtin_opcodes): Add MT instructions. Move "bc0f", "bc0fl", "bc0t", "bc0tl" to the end to avoid opcode collision with "mftr" and "mttr". * mips-dis.c (mips_arch_choices): Enable INSN_MT for mips32r2. (print_insn_args): Add supports for +t, +T, !, $, *, &, g operand formats. gas/ChangeLog 2005-08-29 Chao-ying Fu * config/tc-mips.c (mips_set_options): Add ase_mt for MT instructions. (mips_opts): Add -1 to initialize ase_mt. (file_ase_mt): New variable for -mt. (CPU_HAS_MT): New define. (validate_mips_insn): Add supports for +t, +T, !, $, *, &, g operand formats. (mips_ip): Check ase_mt to enable MT instructions. Handle !, $, *, &, +T, +t, g operand formats. For "mftc1", "mfthc1", "cftc1", "mttc1", "mtthc1", "cttc1", we allow odd float registers. (OPTION_MT, OPTION_NO_MT): New define. (OPTION_COMPAT_ARCH_BASE): Change because of inserting MT define. (md_parse_option): Parse OPTION_MT and OPTION_NO_MT. (mips_after_parse_args): Set ase_mt based on CPU. (s_mipsset): Handle ".set mt" and ".set nomt". (mips_elf_final_processing): Remind of adding new flag for MT ASE. (md_show_usage): Show usage of -mt and -mno-mt. gas/testsuite/ChangeLog 2005-08-29 Chao-ying Fu * gas/mips/mips.exp: Run MT test for mips32r2 only. * gas/mips/mips32-mt.[sdl]: New test. ----- Original Message ----- From: "Maciej W. Rozycki" To: "Chao-ying Fu" Cc: "Eric Christopher" ; "Thekkath, Radhika" ; "Thiemo Seufer" ; Sent: Monday, August 29, 2005 2:55 AM Subject: Re: [patch] GAS supports for MIPS32 MT ASE > On Fri, 26 Aug 2005, Chao-ying Fu wrote: > > > Could you review this patch? We will revise the patch, if there are issues. > > Posting patches inline helps commenting significantly... Cutting & > pasting for now. > > *** 220,229 **** > {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, > /* b is at the top of the table. */ > /* bal is at the top of the table. */ > - {"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, > - {"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, > - {"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, > - {"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, > {"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD|RD_CC|FP_S, 0, > {"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, 0, > {"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD|RD_CC|FP_S, 0, > --- 223,228 ---- > > A comment is missing about the instructions having been relocated (like > one for "b" and "bal" seen immediately above!). > > --- 1351,1415 ---- > {"subu_s.qb", "d,s,t", 0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t, > {"wrdsp", "s", 0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA, 0, > {"wrdsp", "s,8", 0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA, 0, > + /* MIPS MT ASE Instructions. */ > + {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, > + {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, > + {"dvpe", "", 0x41600001, 0xffffffff, TRAP, > > Note that the table is meant to be sorted alphabetically (except from > when conflicts arise)... > > --- 14359,14367 ---- > -mdsp generate DSP instructions\n\ > -mno-dsp do not generate DSP instructions\n")); > fprintf (stream, _("\ > + -mt generate MT instructions\n\ > + -mno-mt do not generate MT instructions\n")); > + fprintf (stream, _("\ > -mfix-vr4120 work around certain VR4120 errata\n\ > -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ > -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ > > Hmm, there is an inconsistency here -- I think "-mmt/-mno-mt" sounds > better than "-mt/-mno-t". > > dmt > dmt $0 > dvpe > dvpe $1 > > Testing "dmt" with a non-$0 argument might be a bit more useful to > assure `objdump' gets the disassembly right for the single-operand > variation. > > I'll leave the rest to the maintainers... > > Maciej > ------=_NextPart_000_001E_01C5ACB5.DBFB3A60 Content-Type: application/octet-stream; name="src.diff" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="src.diff" Content-length: 33474 Index: include/opcode/mips.h=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/include/opcode/mips.h,v=0A= retrieving revision 1.44=0A= diff -c -3 -p -r1.44 mips.h=0A= *** include/opcode/mips.h 25 Aug 2005 18:09:24 -0000 1.44=0A= --- include/opcode/mips.h 29 Aug 2005 23:00:09 -0000=0A= *************** Software Foundation, 51 Franklin Street=20=0A= *** 170,175 ****=0A= --- 170,185 ----=0A= #define OP_SH_RDDSP 16=0A= #define OP_MASK_RDDSP 0x3f=0A= =20=20=0A= + /* MIPS MT ASE */=0A= + #define OP_SH_MT_U 5=0A= + #define OP_MASK_MT_U 0x1=0A= + #define OP_SH_MT_H 4=0A= + #define OP_MASK_MT_H 0x1=0A= + #define OP_SH_MTACC_T 18=0A= + #define OP_MASK_MTACC_T 0x3=0A= + #define OP_SH_MTACC_D 13=0A= + #define OP_MASK_MTACC_D 0x3=0A= +=20=0A= #define OP_OP_COP0 0x10=0A= #define OP_OP_COP1 0x11=0A= #define OP_OP_COP2 0x12=0A= *************** struct mips_opcode=0A= *** 331,336 ****=0A= --- 341,355 ----=0A= "'" 6 bit unsigned immediate (OP_*_RDDSP)=0A= "@" 10 bit signed immediate (OP_*_IMM10)=0A= =20=20=0A= + MT ASE usage:=0A= + "!" 1 bit immediate at bit 5=0A= + "$" 1 bit immediate at bit 4=0A= + "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)=0A= + "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)=0A= + "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)=0A= + "+t" 5 bit coprocessor 0 destination register (OP_*_RT)=0A= + "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly = only=0A= +=20=0A= Other:=0A= "()" parens surrounding optional value=0A= "," separates operands=0A= *************** struct mips_opcode=0A= *** 339,351 ****=0A= =20=20=0A= Characters used so far, for quick reference when adding more:=0A= "34567890"=0A= ! "%[]<>(),+:'@"=0A= "ABCDEFGHIJKLMNOPQRSTUVWXYZ"=0A= ! "abcdefhijklopqrstuvwxz"=0A= =20=20=0A= Extension character sequences used so far ("+" followed by the=0A= following), for quick reference when adding more:=0A= ! "ABCDEFGHI"=0A= */=0A= =20=20=0A= /* These are the bits which may be set in the pinfo field of an=0A= --- 358,371 ----=0A= =20=20=0A= Characters used so far, for quick reference when adding more:=0A= "34567890"=0A= ! "%[]<>(),+:'@!$*&"=0A= "ABCDEFGHIJKLMNOPQRSTUVWXYZ"=0A= ! "abcdefghijklopqrstuvwxz"=0A= =20=20=0A= Extension character sequences used so far ("+" followed by the=0A= following), for quick reference when adding more:=0A= ! "ABCDEFGHIT"=0A= ! "t"=0A= */=0A= =20=20=0A= /* These are the bits which may be set in the pinfo field of an=0A= *************** struct mips_opcode=0A= *** 447,453 ****=0A= #define INSN_ISA64R2 0x00000100=0A= =20=20=0A= /* Masks used for MIPS-defined ASEs. */=0A= ! #define INSN_ASE_MASK 0x0000f000=0A= =20=20=0A= /* DSP ASE */=20=0A= #define INSN_DSP 0x00001000=0A= --- 467,473 ----=0A= #define INSN_ISA64R2 0x00000100=0A= =20=20=0A= /* Masks used for MIPS-defined ASEs. */=0A= ! #define INSN_ASE_MASK 0x0400f000=0A= =20=20=0A= /* DSP ASE */=20=0A= #define INSN_DSP 0x00001000=0A= *************** struct mips_opcode=0A= *** 480,485 ****=0A= --- 500,507 ----=0A= #define INSN_5400 0x01000000=0A= /* NEC VR5500 instruction. */=0A= #define INSN_5500 0x02000000=0A= + /* MT ASE */=0A= + #define INSN_MT 0x04000000=0A= =20=20=0A= /* MIPS ISA defines, use instead of hardcoding ISA level. */=0A= =20=20=0A= Index: opcodes/mips-opc.c=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/opcodes/mips-opc.c,v=0A= retrieving revision 1.52=0A= diff -c -3 -p -r1.52 mips-opc.c=0A= *** opcodes/mips-opc.c 25 Aug 2005 18:12:43 -0000 1.52=0A= --- opcodes/mips-opc.c 29 Aug 2005 23:00:10 -0000=0A= *************** Software Foundation, 51 Franklin Street=20=0A= *** 146,151 ****=0A= --- 146,154 ----=0A= #define DSP_VOLA INSN_TRAP=0A= #define D32 (INSN_DSP)=0A= =20=20=0A= + /* MIPS MT ASE support. */=0A= + #define MT32 (INSN_MT)=0A= +=20=0A= /* The order of overloaded instructions matters. Label arguments and=0A= register arguments look the same. Instructions that can have either=0A= for arguments must apear in the correct order in this table for the=0A= *************** const struct mips_opcode mips_builtin_op=0A= *** 220,229 ****=0A= {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 },=0A= /* b is at the top of the table. */=0A= /* bal is at the top of the table. */=0A= ! {"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1 },=0A= ! {"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },=0A= ! {"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1 },=0A= ! {"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },=0A= {"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },= =0A= {"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },= =0A= {"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },= =0A= --- 223,229 ----=0A= {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 },=0A= /* b is at the top of the table. */=0A= /* bal is at the top of the table. */=0A= ! /* bc0[tf]l? are at the bottom of the table. */=0A= {"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },= =0A= {"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },= =0A= {"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },= =0A= *************** const struct mips_opcode mips_builtin_op=0A= *** 469,474 ****=0A= --- 469,477 ----=0A= {"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 },= =0A= /* cfc2 is at the bottom of the table. */=0A= {"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 },=0A= + {"cftc1", "d,E", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, = MT32 },=0A= + {"cftc1", "d,T", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, = MT32 },=0A= + {"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 = },=0A= {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|= N55 },=0A= {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|= N55 },=0A= {"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },=0A= *************** const struct mips_opcode mips_builtin_op=0A= *** 476,481 ****=0A= --- 479,487 ----=0A= {"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 },= =0A= /* ctc2 is at the bottom of the table. */=0A= {"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },=0A= + {"cttc1", "t,g", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, = MT32 },=0A= + {"cttc1", "t,S", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, = MT32 },=0A= + {"cttc2", "t,g", 0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC, 0, MT32 = },=0A= {"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, 0, I3 },=0A= {"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_D|FP_S, 0, I1 },= =0A= {"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 },=0A= *************** const struct mips_opcode mips_builtin_op=0A= *** 556,561 ****=0A= --- 562,569 ----=0A= {"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3 },=0A= {"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 = },=0A= {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 = },=0A= + {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, MT32 },=0A= + {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },=0A= {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3 }= ,=0A= {"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0= , I64 },=0A= {"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0= , I64 },=0A= *************** const struct mips_opcode mips_builtin_op=0A= *** 620,628 ****=0A= --- 628,642 ----=0A= {"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3 },=0A= {"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },= =0A= {"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3 },=0A= + {"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, MT32 },=0A= + {"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 },=0A= {"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 },=0A= {"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 },=0A= + {"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 },=0A= + {"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },=0A= {"eret", "", 0x42000018, 0xffffffff, 0, 0, I3|I32 },= =0A= + {"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, MT32 },=0A= + {"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 },=0A= {"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33 = },=0A= {"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, 0, I3 },= =0A= {"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S, 0, I3 },= =0A= *************** const struct mips_opcode mips_builtin_op=0A= *** 719,724 ****=0A= --- 733,739 ----=0A= {"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 },=0A= {"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /= * same */=0A= {"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I2 }, /* as = lwr */=0A= + {"fork", "d,s,t", 0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t, 0, MT3= 2 },=0A= {"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 },= =0A= {"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3 },=0A= {"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, 0, I4 = },=0A= *************** const struct mips_opcode mips_builtin_op=0A= *** 755,760 ****=0A= --- 770,793 ----=0A= {"max.qh", "X,Y,Q", 0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX = },=0A= {"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 },= =0A= {"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 },= =0A= + {"mftacx", "d", 0x41020021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },=0A= + {"mftacx", "d,*", 0x41020021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },= =0A= + {"mftc0", "d,+t", 0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0, 0, MT32= },=0A= + {"mftc0", "d,+T", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32= },=0A= + {"mftc0", "d,E,H", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT3= 2 },=0A= + {"mftc1", "d,T", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, M= T32 },=0A= + {"mftc1", "d,E", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, M= T32 },=0A= + {"mftc2", "d,E", 0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 = },=0A= + {"mftdsp", "d", 0x41100021, 0xffff07ff, TRAP|WR_d, 0, MT32 },=0A= + {"mftgpr", "d,t", 0x41000020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 },= =0A= + {"mfthc1", "d,T", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, M= T32 },=0A= + {"mfthc1", "d,E", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, M= T32 },=0A= + {"mfthc2", "d,E", 0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 = },=0A= + {"mfthi", "d", 0x41010021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },=0A= + {"mfthi", "d,*", 0x41010021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },= =0A= + {"mftlo", "d", 0x41000021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },=0A= + {"mftlo", "d,*", 0x41000021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },= =0A= + {"mftr", "t,d,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d, 0, MT32 },= =0A= {"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 },=0A= {"mfc0", "t,+D", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 = },=0A= {"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 = },=0A= *************** const struct mips_opcode mips_builtin_op=0A= *** 836,841 ****=0A= --- 869,892 ----=0A= {"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_s|WR_HI, 0, D32 },=0A= {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 },=0A= {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_s|WR_LO, 0, D32 },=0A= + {"mttc0", "t,G", 0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0, = MT32 },=0A= + {"mttc0", "t,+D", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0,= MT32 },=0A= + {"mttc0", "t,G,H", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0= , MT32 },=0A= + {"mttc1", "t,S", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, M= T32 },=0A= + {"mttc1", "t,G", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, M= T32 },=0A= + {"mttc2", "t,g", 0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, = MT32 },=0A= + {"mttacx", "t", 0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },=0A= + {"mttacx", "t,&", 0x41801021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },= =0A= + {"mttdsp", "t", 0x41808021, 0xffe0ffff, TRAP|RD_t, 0, MT32 },=0A= + {"mttgpr", "t,d", 0x41800020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 },= =0A= + {"mtthc1", "t,S", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, M= T32 },=0A= + {"mtthc1", "t,G", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, M= T32 },=0A= + {"mtthc2", "t,g", 0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, = MT32 },=0A= + {"mtthi", "t", 0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },=0A= + {"mtthi", "t,&", 0x41800821, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },= =0A= + {"mttlo", "t", 0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },=0A= + {"mttlo", "t,&", 0x41800021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },= =0A= + {"mttr", "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t, 0, MT32 },= =0A= {"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 = },=0A= {"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 = },=0A= {"mul.ob", "X,Y,Q", 0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|= SB1 },=0A= *************** const struct mips_opcode mips_builtin_op=0A= *** 1209,1214 ****=0A= --- 1260,1267 ----=0A= {"xor.ob", "D,S,k", 0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },= =0A= {"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX = },=0A= {"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, 0, I1 },=0A= + {"yield", "s", 0x7c000009, 0xfc1fffff, TRAP|RD_s, 0, MT32 },=0A= + {"yield", "d,s", 0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s, 0, MT32 },= =0A= =20=20=0A= /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format=0A= instructions so they are here for the latters to take precedence. */= =0A= *************** const struct mips_opcode mips_builtin_op=0A= *** 1352,1357 ****=0A= --- 1405,1415 ----=0A= {"subu_s.qb", "d,s,t", 0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }= ,=0A= {"wrdsp", "s", 0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA, 0, D32 },=0A= {"wrdsp", "s,8", 0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA, 0, D32 },=0A= + /* Move bc0* after mftr and mttr to avoid opcode collision. */=0A= + {"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1 },=0A= + {"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },=0A= + {"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1 },=0A= + {"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },=0A= };=0A= =20=20=0A= #define MIPS_NUM_OPCODES \=0A= Index: opcodes/mips-dis.c=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/opcodes/mips-dis.c,v=0A= retrieving revision 1.53=0A= diff -c -3 -p -r1.53 mips-dis.c=0A= *** opcodes/mips-dis.c 25 Aug 2005 18:12:44 -0000 1.53=0A= --- opcodes/mips-dis.c 29 Aug 2005 23:00:10 -0000=0A= *************** const struct mips_arch_choice mips_arch_=0A= *** 376,382 ****=0A= mips_hwr_names_numeric },=0A= =20=20=0A= { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,=0A= ! ISA_MIPS32R2 | INSN_MIPS16 | INSN_DSP,=0A= mips_cp0_names_mips3264r2,=0A= mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r= 2),=0A= mips_hwr_names_mips3264r2 },=0A= --- 376,382 ----=0A= mips_hwr_names_numeric },=0A= =20=20=0A= { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,=0A= ! ISA_MIPS32R2 | INSN_MIPS16 | INSN_DSP | INSN_MT,=0A= mips_cp0_names_mips3264r2,=0A= mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r= 2),=0A= mips_hwr_names_mips3264r2 },=0A= *************** print_insn_args (const char *d,=0A= *** 771,776 ****=0A= --- 771,804 ----=0A= (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);=0A= break;=0A= =20=20=0A= + case 't': /* Coprocessor 0 reg name */=0A= + (*info->fprintf_func) (info->stream, "%s",=0A= + mips_cp0_names[(l >> OP_SH_RT) &=0A= + OP_MASK_RT]);=0A= + break;=0A= +=20=0A= + case 'T': /* Coprocessor 0 reg name */=0A= + {=0A= + const struct mips_cp0sel_name *n;=0A= + unsigned int cp0reg, sel;=0A= +=20=0A= + cp0reg =3D (l >> OP_SH_RT) & OP_MASK_RT;=0A= + sel =3D (l >> OP_SH_SEL) & OP_MASK_SEL;=0A= +=20=0A= + /* CP0 register including 'sel' code for mftc0, to be=0A= + printed textually if known. If not known, print both=0A= + CP0 register name and sel numerically since CP0 register=0A= + with sel 0 may have a name unrelated to register being=0A= + printed. */=0A= + n =3D lookup_mips_cp0sel_name(mips_cp0sel_names,=0A= + mips_cp0sel_names_len, cp0reg, sel);=0A= + if (n !=3D NULL)=0A= + (*info->fprintf_func) (info->stream, "%s", n->name);=0A= + else=0A= + (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);=0A= + break;=0A= + }=0A= +=20=0A= default:=0A= /* xgettext:c-format */=0A= (*info->fprintf_func) (info->stream,=0A= *************** print_insn_args (const char *d,=0A= *** 841,846 ****=0A= --- 869,900 ----=0A= (*info->fprintf_func) (info->stream, "%d", delta);=0A= break;=0A= =20=20=0A= + case '!':=0A= + (*info->fprintf_func) (info->stream, "%ld",=0A= + (l >> OP_SH_MT_U) & OP_MASK_MT_U);=0A= + break;=0A= +=20=0A= + case '$':=0A= + (*info->fprintf_func) (info->stream, "%ld",=0A= + (l >> OP_SH_MT_H) & OP_MASK_MT_H);=0A= + break;=0A= +=20=0A= + case '*':=0A= + (*info->fprintf_func) (info->stream, "$ac%ld",=0A= + (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);=0A= + break;=0A= +=20=0A= + case '&':=0A= + (*info->fprintf_func) (info->stream, "$ac%ld",=0A= + (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);=0A= + break;=0A= +=20=0A= + case 'g':=0A= + /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */=0A= + (*info->fprintf_func) (info->stream, "$%ld",=0A= + (l >> OP_SH_RD) & OP_MASK_RD);=0A= + break;=0A= +=20=0A= case 's':=0A= case 'b':=0A= case 'r':=0A= Index: gas/config/tc-mips.c=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/gas/config/tc-mips.c,v=0A= retrieving revision 1.318=0A= diff -c -3 -p -r1.318 tc-mips.c=0A= *** gas/config/tc-mips.c 25 Aug 2005 18:17:36 -0000 1.318=0A= --- gas/config/tc-mips.c 29 Aug 2005 23:00:12 -0000=0A= *************** struct mips_set_options=0A= *** 194,199 ****=0A= --- 194,200 ----=0A= int ase_mips3d;=0A= int ase_mdmx;=0A= int ase_dsp;=0A= + int ase_mt;=0A= /* Whether we are assembling for the mips16 processor. 0 if we are=0A= not, 1 if we are, and -1 if the value has not been initialized.=0A= Changed by `.set mips16' and `.set nomips16', and the -mips16 and=0A= *************** static int file_mips_fp32 =3D -1;=0A= *** 244,250 ****=0A= =20=20=0A= static struct mips_set_options mips_opts =3D=0A= {=0A= ! ISA_UNKNOWN, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE= =0A= };=0A= =20=20=0A= /* These variables are filled in with the masks of registers used.=0A= --- 245,251 ----=0A= =20=20=0A= static struct mips_set_options mips_opts =3D=0A= {=0A= ! ISA_UNKNOWN, -1, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, F= ALSE=0A= };=0A= =20=20=0A= /* These variables are filled in with the masks of registers used.=0A= *************** static int file_ase_mdmx;=0A= *** 272,277 ****=0A= --- 273,282 ----=0A= command line (e.g., by -march). */=0A= static int file_ase_dsp;=0A= =20=20=0A= + /* True if -mt was passed or implied by arguments passed on the=0A= + command line (e.g., by -march). */=0A= + static int file_ase_mt;=0A= +=20=0A= /* The argument of the -march=3D flag. The architecture we are assemblin= g. */=0A= static int file_mips_arch =3D CPU_UNKNOWN;=0A= static const char *mips_arch_string;=0A= *************** static int mips_32bitmode =3D 0;=0A= *** 374,379 ****=0A= --- 379,388 ----=0A= #define CPU_HAS_DSP(cpu) (FALSE \=0A= )=0A= =20=20=0A= + /* Return true if the given CPU supports the MT ASE. */=0A= + #define CPU_HAS_MT(cpu) (FALSE \=0A= + )=0A= +=20=0A= /* True if CPU has a dror instruction. */=0A= #define CPU_HAS_DROR(CPU) ((CPU) =3D=3D CPU_VR5400 || (CPU) =3D=3D CPU_VR= 5500)=0A= =20=20=0A= *************** validate_mips_insn (const struct mips_op=0A= *** 7765,7770 ****=0A= --- 7774,7782 ----=0A= case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;=0A= case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;=0A= case 'I': break;=0A= + case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;=0A= + case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);=0A= + USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;=0A= default:=0A= as_bad (_("internal: bad mips opcode (unknown extension operand type= `+%c'): %s %s"),=0A= c, opc->name, opc->args);=0A= *************** validate_mips_insn (const struct mips_op=0A= *** 7837,7842 ****=0A= --- 7849,7859 ----=0A= case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;=0A= case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;=0A= case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;=0A= + case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;=0A= + case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;=0A= + case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;=0A= + case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;=0A= + case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;=0A= default:=0A= as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"= ),=0A= c, opc->name, opc->args);=0A= *************** mips_ip (char *str, struct mips_cl_insn=20=0A= *** 7935,7940 ****=0A= --- 7952,7958 ----=0A= | (file_ase_mips16 ? INSN_MIPS16 : 0)=0A= | (mips_opts.ase_mdmx ? INSN_MDMX : 0)=0A= | (mips_opts.ase_dsp ? INSN_DSP : 0)=0A= + | (mips_opts.ase_mt ? INSN_MT : 0)=0A= | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),=0A= mips_opts.arch))=0A= ok =3D TRUE;=0A= *************** mips_ip (char *str, struct mips_cl_insn=20=0A= *** 8156,8161 ****=0A= --- 8174,8233 ----=0A= s =3D expr_end;=0A= continue;=0A= =20=20=0A= + case '!': /* mt 1-bit unsigned immediate in bit 5 */=0A= + my_getExpression (&imm_expr, s);=0A= + check_absolute_expr (ip, &imm_expr);=0A= + if (imm_expr.X_add_number & ~OP_MASK_MT_U)=0A= + {=0A= + as_warn (_("MT immediate not in range 0..%d (%lu)"),=0A= + OP_MASK_MT_U, (unsigned long) imm_expr.X_add_number);=0A= + imm_expr.X_add_number &=3D OP_MASK_MT_U;=0A= + }=0A= + ip->insn_opcode |=3D imm_expr.X_add_number << OP_SH_MT_U;=0A= + imm_expr.X_op =3D O_absent;=0A= + s =3D expr_end;=0A= + continue;=0A= +=20=0A= + case '$': /* mt 1-bit unsigned immediate in bit 4 */=0A= + my_getExpression (&imm_expr, s);=0A= + check_absolute_expr (ip, &imm_expr);=0A= + if (imm_expr.X_add_number & ~OP_MASK_MT_H)=0A= + {=0A= + as_warn (_("MT immediate not in range 0..%d (%lu)"),=0A= + OP_MASK_MT_H, (unsigned long) imm_expr.X_add_number);=0A= + imm_expr.X_add_number &=3D OP_MASK_MT_H;=0A= + }=0A= + ip->insn_opcode |=3D imm_expr.X_add_number << OP_SH_MT_H;=0A= + imm_expr.X_op =3D O_absent;=0A= + s =3D expr_end;=0A= + continue;=0A= +=20=0A= + case '*': /* four dsp accumulators in bits 18,19 */=20=0A= + if (s[0] =3D=3D '$' && s[1] =3D=3D 'a' && s[2] =3D=3D 'c' &&=0A= + s[3] >=3D '0' && s[3] <=3D '3')=0A= + {=0A= + regno =3D s[3] - '0';=0A= + s +=3D 4;=0A= + ip->insn_opcode |=3D regno << OP_SH_MTACC_T;=0A= + continue;=0A= + }=0A= + else=0A= + as_bad (_("Invalid dsp/smartmips acc register"));=0A= + break;=0A= +=20=0A= + case '&': /* four dsp accumulators in bits 13,14 */=20=0A= + if (s[0] =3D=3D '$' && s[1] =3D=3D 'a' && s[2] =3D=3D 'c' &&=0A= + s[3] >=3D '0' && s[3] <=3D '3')=0A= + {=0A= + regno =3D s[3] - '0';=0A= + s +=3D 4;=0A= + ip->insn_opcode |=3D regno << OP_SH_MTACC_D;=0A= + continue;=0A= + }=0A= + else=0A= + as_bad (_("Invalid dsp/smartmips acc register"));=0A= + break;=0A= +=20=0A= case ',':=0A= if (*s++ =3D=3D *args)=0A= continue;=0A= *************** do_msbd:=0A= *** 8308,8313 ****=0A= --- 8380,8413 ----=0A= s =3D expr_end;=0A= continue;=0A= =20=20=0A= + case 'T': /* Coprocessor register */=0A= + /* +T is for disassembly only; never match. */=0A= + break;=0A= +=20=0A= + case 't': /* Coprocessor register number */=0A= + if (s[0] =3D=3D '$' && ISDIGIT (s[1]))=0A= + {=0A= + ++s;=0A= + regno =3D 0;=0A= + do=0A= + {=0A= + regno *=3D 10;=0A= + regno +=3D *s - '0';=0A= + ++s;=0A= + }=0A= + while (ISDIGIT (*s));=0A= + if (regno > 31)=0A= + as_bad (_("Invalid register number (%d)"), regno);=0A= + else=0A= + {=0A= + ip->insn_opcode |=3D regno << OP_SH_RT;=0A= + continue;=0A= + }=0A= + }=0A= + else=0A= + as_bad (_("Invalid coprocessor 0 register number"));=0A= + break;=0A= +=20=0A= default:=0A= as_bad (_("internal: bad mips opcode (unknown extension operand type = `+%c'): %s %s"),=0A= *args, insn->name, insn->args);=0A= *************** do_msbd:=0A= *** 8442,8447 ****=0A= --- 8542,8548 ----=0A= case 'x': /* ignore register name */=0A= case 'z': /* must be zero register */=0A= case 'U': /* destination register (clo/clz). */=0A= + case 'g': /* coprocessor destination register */=0A= s_reset =3D s;=0A= if (s[0] =3D=3D '$')=0A= {=0A= *************** do_msbd:=0A= *** 8566,8571 ****=0A= --- 8667,8673 ----=0A= case 'd':=0A= case 'G':=0A= case 'K':=0A= + case 'g':=0A= INSERT_OPERAND (RD, *ip, regno);=0A= break;=0A= case 'U':=0A= *************** do_msbd:=0A= *** 8681,8687 ****=0A= || strcmp (str, "lwc1") =3D=3D 0=0A= || strcmp (str, "swc1") =3D=3D 0=0A= || strcmp (str, "l.s") =3D=3D 0=0A= ! || strcmp (str, "s.s") =3D=3D 0))=0A= as_warn (_("Float register should be even, was %d"),=0A= regno);=0A= =20=20=0A= --- 8783,8795 ----=0A= || strcmp (str, "lwc1") =3D=3D 0=0A= || strcmp (str, "swc1") =3D=3D 0=0A= || strcmp (str, "l.s") =3D=3D 0=0A= ! || strcmp (str, "s.s") =3D=3D 0=0A= ! || strcmp (str, "mftc1") =3D=3D 0=0A= ! || strcmp (str, "mfthc1") =3D=3D 0=0A= ! || strcmp (str, "cftc1") =3D=3D 0=0A= ! || strcmp (str, "mttc1") =3D=3D 0=0A= ! || strcmp (str, "mtthc1") =3D=3D 0=0A= ! || strcmp (str, "cttc1") =3D=3D 0))=0A= as_warn (_("Float register should be even, was %d"),=0A= regno);=0A= =20=20=0A= *************** struct option md_longopts[] =3D=0A= *** 10222,10230 ****=0A= {"mdsp", no_argument, NULL, OPTION_DSP},=0A= #define OPTION_NO_DSP (OPTION_ASE_BASE + 7)=0A= {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},=0A= =20=20=0A= /* Old-style architecture options. Don't add more of these. */=0A= ! #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 8)=0A= #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)=0A= {"m4650", no_argument, NULL, OPTION_M4650},=0A= #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)=0A= --- 10330,10342 ----=0A= {"mdsp", no_argument, NULL, OPTION_DSP},=0A= #define OPTION_NO_DSP (OPTION_ASE_BASE + 7)=0A= {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},=0A= + #define OPTION_MT (OPTION_ASE_BASE + 8)=0A= + {"mt", no_argument, NULL, OPTION_MT},=0A= + #define OPTION_NO_MT (OPTION_ASE_BASE + 9)=0A= + {"mno-mt", no_argument, NULL, OPTION_NO_MT},=0A= =20=20=0A= /* Old-style architecture options. Don't add more of these. */=0A= ! #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 10)=0A= #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)=0A= {"m4650", no_argument, NULL, OPTION_M4650},=0A= #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)=0A= *************** md_parse_option (int c, char *arg)=0A= *** 10484,10489 ****=0A= --- 10596,10609 ----=0A= mips_opts.ase_dsp =3D 0;=0A= break;=0A= =20=20=0A= + case OPTION_MT:=0A= + mips_opts.ase_mt =3D 1;=0A= + break;=0A= +=20=0A= + case OPTION_NO_MT:=0A= + mips_opts.ase_mt =3D 0;=0A= + break;=0A= +=20=0A= case OPTION_MIPS16:=0A= mips_opts.mips16 =3D 1;=0A= mips_no_prev_insn ();=0A= *************** mips_after_parse_args (void)=0A= *** 10840,10851 ****=0A= --- 10960,10974 ----=0A= mips_opts.ase_mdmx =3D (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0;=0A= if (mips_opts.ase_dsp =3D=3D -1)=0A= mips_opts.ase_dsp =3D (CPU_HAS_DSP (file_mips_arch)) ? 1 : 0;=0A= + if (mips_opts.ase_mt =3D=3D -1)=0A= + mips_opts.ase_mt =3D (CPU_HAS_MT (file_mips_arch)) ? 1 : 0;=0A= =20=20=0A= file_mips_isa =3D mips_opts.isa;=0A= file_ase_mips16 =3D mips_opts.mips16;=0A= file_ase_mips3d =3D mips_opts.ase_mips3d;=0A= file_ase_mdmx =3D mips_opts.ase_mdmx;=0A= file_ase_dsp =3D mips_opts.ase_dsp;=0A= + file_ase_mt =3D mips_opts.ase_mt;=0A= mips_opts.gp32 =3D file_mips_gp32;=0A= mips_opts.fp32 =3D file_mips_fp32;=0A= =20=20=0A= *************** s_mipsset (int x ATTRIBUTE_UNUSED)=0A= *** 11787,11792 ****=0A= --- 11910,11919 ----=0A= mips_opts.ase_dsp =3D 1;=0A= else if (strcmp (name, "nodsp") =3D=3D 0)=0A= mips_opts.ase_dsp =3D 0;=0A= + else if (strcmp (name, "mt") =3D=3D 0)=0A= + mips_opts.ase_mt =3D 1;=0A= + else if (strcmp (name, "nomt") =3D=3D 0)=0A= + mips_opts.ase_mt =3D 0;=0A= else if (strncmp (name, "mips", 4) =3D=3D 0 || strncmp (name, "arch=3D"= , 5) =3D=3D 0)=0A= {=0A= int reset =3D 0;=0A= *************** mips_elf_final_processing (void)=0A= *** 13523,13528 ****=0A= --- 13650,13657 ----=0A= /* Set MIPS ELF flags for ASEs. */=0A= /* We may need to define a new flag for DSP ASE, and set this flag when= =0A= file_ase_dsp is true. */=0A= + /* We may need to define a new flag for MT ASE, and set this flag when= =0A= + file_ase_mt is true. */=0A= if (file_ase_mips16)=0A= elf_elfheader (stdoutput)->e_flags |=3D EF_MIPS_ARCH_ASE_M16;=0A= #if 0 /* XXX FIXME */=0A= *************** MIPS options:\n\=0A= *** 14230,14235 ****=0A= --- 14359,14367 ----=0A= -mdsp generate DSP instructions\n\=0A= -mno-dsp do not generate DSP instructions\n"));=0A= fprintf (stream, _("\=0A= + -mt generate MT instructions\n\=0A= + -mno-mt do not generate MT instructions\n"));=0A= + fprintf (stream, _("\=0A= -mfix-vr4120 work around certain VR4120 errata\n\=0A= -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\=0A= -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\=0A= Index: gas/testsuite/gas/mips/mips.exp=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v=0A= retrieving revision 1.108=0A= diff -c -3 -p -r1.108 mips.exp=0A= *** gas/testsuite/gas/mips/mips.exp 25 Aug 2005 18:21:47 -0000 1.108=0A= --- gas/testsuite/gas/mips/mips.exp 29 Aug 2005 23:00:12 -0000=0A= *************** if { [istarget mips*-*-*] } then {=0A= *** 763,768 ****=0A= --- 763,769 ----=0A= run_list_test "noat-7" ""=0A= =20=20=0A= run_dump_test_arches "mips32-dsp" [mips_arch_list_matching mips32 !sb= 1]=0A= + run_dump_test_arches "mips32-mt" [mips_arch_list_matching mips32r2 !g= pr64]=0A= =20=20=0A= if { $elf && !$no_mips16 } {=0A= run_dump_test "mips16-dwarf2"=0A= ------=_NextPart_000_001E_01C5ACB5.DBFB3A60 Content-Type: application/octet-stream; name="mips32-mt.s" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="mips32-mt.s" Content-length: 18471 # source file to test assembly of MIPS MT ASE for MIPS32 instructions=0A= =0A= .set noreorder=0A= .set noat=0A= =0A= .text=0A= text_label:=0A= =0A= dmt=0A= dmt $31=0A= dvpe=0A= dvpe $1=0A= emt=0A= emt $2=0A= evpe=0A= evpe $3=0A= fork $4,$5,$6=0A= yield $5=0A= yield $6,$7=0A= mftc0 $7,$8=0A= mftc0 $8,$0,0=0A= mftc0 $8,$0,1=0A= mftc0 $8,$0,2=0A= mftc0 $8,$0,3=0A= mftc0 $8,$0,4=0A= mftc0 $8,$0,5=0A= mftc0 $8,$0,6=0A= mftc0 $8,$0,7=0A= mftc0 $8,$1,0=0A= mftc0 $8,$1,1=0A= mftc0 $8,$1,2=0A= mftc0 $8,$1,3=0A= mftc0 $8,$1,4=0A= mftc0 $8,$1,5=0A= mftc0 $8,$1,6=0A= mftc0 $8,$1,7=0A= mftc0 $8,$2,0=0A= mftc0 $8,$2,1=0A= mftc0 $8,$2,2=0A= mftc0 $8,$2,3=0A= mftc0 $8,$2,4=0A= mftc0 $8,$2,5=0A= mftc0 $8,$2,6=0A= mftc0 $8,$2,7=0A= mftc0 $8,$3,0=0A= mftc0 $8,$3,1=0A= mftc0 $8,$3,2=0A= mftc0 $8,$3,3=0A= mftc0 $8,$3,4=0A= mftc0 $8,$3,5=0A= mftc0 $8,$3,6=0A= mftc0 $8,$3,7=0A= mftc0 $8,$4,0=0A= mftc0 $8,$4,1=0A= mftc0 $8,$4,2=0A= mftc0 $8,$4,3=0A= mftc0 $8,$4,4=0A= mftc0 $8,$4,5=0A= mftc0 $8,$4,6=0A= mftc0 $8,$4,7=0A= mftc0 $8,$5,0=0A= mftc0 $8,$5,1=0A= mftc0 $8,$5,2=0A= mftc0 $8,$5,3=0A= mftc0 $8,$5,4=0A= mftc0 $8,$5,5=0A= mftc0 $8,$5,6=0A= mftc0 $8,$5,7=0A= mftc0 $8,$6,0=0A= mftc0 $8,$6,1=0A= mftc0 $8,$6,2=0A= mftc0 $8,$6,3=0A= mftc0 $8,$6,4=0A= mftc0 $8,$6,5=0A= mftc0 $8,$6,6=0A= mftc0 $8,$6,7=0A= mftc0 $8,$7,0=0A= mftc0 $8,$7,1=0A= mftc0 $8,$7,2=0A= mftc0 $8,$7,3=0A= mftc0 $8,$7,4=0A= mftc0 $8,$7,5=0A= mftc0 $8,$7,6=0A= mftc0 $8,$7,7=0A= mftc0 $8,$8,0=0A= mftc0 $8,$8,1=0A= mftc0 $8,$8,2=0A= mftc0 $8,$8,3=0A= mftc0 $8,$8,4=0A= mftc0 $8,$8,5=0A= mftc0 $8,$8,6=0A= mftc0 $8,$8,7=0A= mftc0 $8,$9,0=0A= mftc0 $8,$9,1=0A= mftc0 $8,$9,2=0A= mftc0 $8,$9,3=0A= mftc0 $8,$9,4=0A= mftc0 $8,$9,5=0A= mftc0 $8,$9,6=0A= mftc0 $8,$9,7=0A= mftc0 $8,$10,0=0A= mftc0 $8,$10,1=0A= mftc0 $8,$10,2=0A= mftc0 $8,$10,3=0A= mftc0 $8,$10,4=0A= mftc0 $8,$10,5=0A= mftc0 $8,$10,6=0A= mftc0 $8,$10,7=0A= mftc0 $8,$11,0=0A= mftc0 $8,$11,1=0A= mftc0 $8,$11,2=0A= mftc0 $8,$11,3=0A= mftc0 $8,$11,4=0A= mftc0 $8,$11,5=0A= mftc0 $8,$11,6=0A= mftc0 $8,$11,7=0A= mftc0 $8,$12,0=0A= mftc0 $8,$12,1=0A= mftc0 $8,$12,2=0A= mftc0 $8,$12,3=0A= mftc0 $8,$12,4=0A= mftc0 $8,$12,5=0A= mftc0 $8,$12,6=0A= mftc0 $8,$12,7=0A= mftc0 $8,$13,0=0A= mftc0 $8,$13,1=0A= mftc0 $8,$13,2=0A= mftc0 $8,$13,3=0A= mftc0 $8,$13,4=0A= mftc0 $8,$13,5=0A= mftc0 $8,$13,6=0A= mftc0 $8,$13,7=0A= mftc0 $8,$14,0=0A= mftc0 $8,$14,1=0A= mftc0 $8,$14,2=0A= mftc0 $8,$14,3=0A= mftc0 $8,$14,4=0A= mftc0 $8,$14,5=0A= mftc0 $8,$14,6=0A= mftc0 $8,$14,7=0A= mftc0 $8,$15,0=0A= mftc0 $8,$15,1=0A= mftc0 $8,$15,2=0A= mftc0 $8,$15,3=0A= mftc0 $8,$15,4=0A= mftc0 $8,$15,5=0A= mftc0 $8,$15,6=0A= mftc0 $8,$15,7=0A= mftc0 $8,$16,0=0A= mftc0 $8,$16,1=0A= mftc0 $8,$16,2=0A= mftc0 $8,$16,3=0A= mftc0 $8,$16,4=0A= mftc0 $8,$16,5=0A= mftc0 $8,$16,6=0A= mftc0 $8,$16,7=0A= mftc0 $8,$17,0=0A= mftc0 $8,$17,1=0A= mftc0 $8,$17,2=0A= mftc0 $8,$17,3=0A= mftc0 $8,$17,4=0A= mftc0 $8,$17,5=0A= mftc0 $8,$17,6=0A= mftc0 $8,$17,7=0A= mftc0 $8,$18,0=0A= mftc0 $8,$18,1=0A= mftc0 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$27,$29,1=0A= mttc0 $27,$29,2=0A= mttc0 $27,$29,3=0A= mttc0 $27,$29,4=0A= mttc0 $27,$29,5=0A= mttc0 $27,$29,6=0A= mttc0 $27,$29,7=0A= mttc0 $27,$30,0=0A= mttc0 $27,$30,1=0A= mttc0 $27,$30,2=0A= mttc0 $27,$30,3=0A= mttc0 $27,$30,4=0A= mttc0 $27,$30,5=0A= mttc0 $27,$30,6=0A= mttc0 $27,$30,7=0A= mttc0 $27,$31,0=0A= mttc0 $27,$31,1=0A= mttc0 $27,$31,2=0A= mttc0 $27,$31,3=0A= mttc0 $27,$31,4=0A= mttc0 $27,$31,5=0A= mttc0 $27,$31,6=0A= mttc0 $27,$31,7=0A= mttgpr $28,$29=0A= mttlo $29=0A= mttlo $30,$ac3=0A= mtthi $31=0A= mtthi $0,$ac0=0A= mttacx $1=0A= mttacx $2,$ac1=0A= mttdsp $3=0A= mttc1 $4,$f5=0A= mttc1 $5,$6=0A= mtthc1 $6,$f8=0A= mtthc1 $7,$10=0A= cttc1 $8,$9=0A= cttc1 $9,$f10=0A= mttc2 $10,$11=0A= mtthc2 $11,$12=0A= cttc2 $12,$13=0A= mftr $13,$14,-1,0,-1=0A= mftr $13,$14,-1,1,-1=0A= mftr $13,$14,-1,2,-1=0A= mftr $13,$14,-1,3,-1=0A= mftr $13,$14,-1,4,-1=0A= mftr $13,$14,-1,5,-1=0A= mftr $13,$14,-1,6,-1=0A= mftr $13,$14,-1,7,-1=0A= mftr $13,$14,-1,0,0=0A= mftr $13,$14,-1,1,0=0A= mftr $13,$14,-1,2,0=0A= mftr $13,$14,-1,3,0=0A= mftr $13,$14,-1,4,0=0A= mftr $13,$14,-1,5,0=0A= mftr $13,$14,-1,6,0=0A= mftr $13,$14,-1,7,0=0A= mftr $13,$14,-1,0,1=0A= mftr $13,$14,-1,1,1=0A= mftr $13,$14,-1,2,1=0A= mftr $13,$14,-1,3,1=0A= mftr $13,$14,-1,4,1=0A= mftr $13,$14,-1,5,1=0A= mftr $13,$14,-1,6,1=0A= mftr $13,$14,-1,7,1=0A= mftr $13,$14,-1,0,2=0A= mftr $13,$14,-1,1,2=0A= mftr $13,$14,-1,2,2=0A= mftr $13,$14,-1,3,2=0A= mftr $13,$14,-1,4,2=0A= mftr $13,$14,-1,5,2=0A= mftr $13,$14,-1,6,2=0A= mftr $13,$14,-1,7,2=0A= mftr $13,$14,0,0,-1=0A= mftr $13,$14,0,1,-1=0A= mftr $13,$14,0,2,-1=0A= mftr $13,$14,0,3,-1=0A= mftr $13,$14,0,4,-1=0A= mftr $13,$14,0,5,-1=0A= mftr $13,$14,0,6,-1=0A= mftr $13,$14,0,7,-1=0A= mftr $13,$14,0,0,0=0A= mftr $13,$14,0,1,0=0A= mftr $13,$14,0,2,0=0A= mftr $13,$14,0,3,0=0A= mftr $13,$14,0,4,0=0A= mftr $13,$14,0,5,0=0A= mftr $13,$14,0,6,0=0A= mftr $13,$14,0,7,0=0A= mftr $13,$14,0,0,1=0A= mftr $13,$14,0,1,1=0A= mftr $13,$14,0,2,1=0A= mftr $13,$14,0,3,1=0A= mftr $13,$14,0,4,1=0A= mftr $13,$14,0,5,1=0A= mftr $13,$14,0,6,1=0A= mftr $13,$14,0,7,1=0A= mftr $13,$14,0,0,2=0A= mftr $13,$14,0,1,2=0A= mftr $13,$14,0,2,2=0A= mftr $13,$14,0,3,2=0A= mftr $13,$14,0,4,2=0A= mftr $13,$14,0,5,2=0A= mftr $13,$14,0,6,2=0A= mftr $13,$14,0,7,2=0A= mftr $13,$14,1,0,-1=0A= mftr $13,$14,1,1,-1=0A= mftr $13,$14,1,2,-1=0A= mftr $13,$14,1,3,-1=0A= mftr $13,$14,1,4,-1=0A= mftr $13,$14,1,5,-1=0A= mftr $13,$14,1,6,-1=0A= mftr $13,$14,1,7,-1=0A= mftr $13,$14,1,0,0=0A= mftr $13,$14,1,1,0=0A= mftr $13,$14,1,2,0=0A= mftr $13,$14,1,3,0=0A= mftr $13,$14,1,4,0=0A= mftr $13,$14,1,5,0=0A= mftr $13,$14,1,6,0=0A= mftr $13,$14,1,7,0=0A= mftr $13,$14,1,0,1=0A= mftr $13,$14,1,1,1=0A= mftr $13,$14,1,2,1=0A= mftr $13,$14,1,3,1=0A= mftr $13,$14,1,4,1=0A= mftr $13,$14,1,5,1=0A= mftr $13,$14,1,6,1=0A= mftr $13,$14,1,7,1=0A= mftr $13,$14,1,0,2=0A= mftr $13,$14,1,1,2=0A= mftr $13,$14,1,2,2=0A= mftr $13,$14,1,3,2=0A= mftr $13,$14,1,4,2=0A= mftr $13,$14,1,5,2=0A= mftr $13,$14,1,6,2=0A= mftr $13,$14,1,7,2=0A= mftr $13,$14,2,0,-1=0A= mftr $13,$14,2,1,-1=0A= mftr $13,$14,2,2,-1=0A= mftr $13,$14,2,3,-1=0A= mftr $13,$14,2,4,-1=0A= mftr $13,$14,2,5,-1=0A= mftr $13,$14,2,6,-1=0A= mftr $13,$14,2,7,-1=0A= mftr $13,$14,2,0,0=0A= mftr $13,$14,2,1,0=0A= mftr $13,$14,2,2,0=0A= mftr $13,$14,2,3,0=0A= mftr $13,$14,2,4,0=0A= mftr $13,$14,2,5,0=0A= mftr $13,$14,2,6,0=0A= mftr $13,$14,2,7,0=0A= mftr $13,$14,2,0,1=0A= mftr $13,$14,2,1,1=0A= mftr $13,$14,2,2,1=0A= mftr $13,$14,2,3,1=0A= mftr $13,$14,2,4,1=0A= mftr $13,$14,2,5,1=0A= mftr $13,$14,2,6,1=0A= mftr $13,$14,2,7,1=0A= mftr $13,$14,2,0,2=0A= mftr $13,$14,2,1,2=0A= mftr $13,$14,2,2,2=0A= mftr $13,$14,2,3,2=0A= mftr $13,$14,2,4,2=0A= mftr $13,$14,2,5,2=0A= mftr $13,$14,2,6,2=0A= mftr $13,$14,2,7,2=0A= mttr $13,$14,-1,0,-1=0A= mttr $13,$14,-1,1,-1=0A= mttr $13,$14,-1,2,-1=0A= mttr $13,$14,-1,3,-1=0A= mttr $13,$14,-1,4,-1=0A= mttr $13,$14,-1,5,-1=0A= mttr $13,$14,-1,6,-1=0A= mttr $13,$14,-1,7,-1=0A= mttr $13,$14,-1,0,0=0A= mttr $13,$14,-1,1,0=0A= mttr $13,$14,-1,2,0=0A= mttr $13,$14,-1,3,0=0A= mttr $13,$14,-1,4,0=0A= mttr $13,$14,-1,5,0=0A= mttr $13,$14,-1,6,0=0A= mttr $13,$14,-1,7,0=0A= mttr $13,$14,-1,0,1=0A= mttr $13,$14,-1,1,1=0A= mttr $13,$14,-1,2,1=0A= mttr $13,$14,-1,3,1=0A= mttr $13,$14,-1,4,1=0A= mttr $13,$14,-1,5,1=0A= mttr $13,$14,-1,6,1=0A= mttr $13,$14,-1,7,1=0A= mttr $13,$14,-1,0,2=0A= mttr $13,$14,-1,1,2=0A= mttr $13,$14,-1,2,2=0A= mttr $13,$14,-1,3,2=0A= mttr $13,$14,-1,4,2=0A= mttr $13,$14,-1,5,2=0A= mttr $13,$14,-1,6,2=0A= mttr $13,$14,-1,7,2=0A= mttr $13,$14,0,0,-1=0A= mttr $13,$14,0,1,-1=0A= mttr $13,$14,0,2,-1=0A= mttr $13,$14,0,3,-1=0A= mttr $13,$14,0,4,-1=0A= mttr $13,$14,0,5,-1=0A= mttr $13,$14,0,6,-1=0A= mttr $13,$14,0,7,-1=0A= mttr $13,$14,0,0,0=0A= mttr $13,$14,0,1,0=0A= mttr $13,$14,0,2,0=0A= mttr $13,$14,0,3,0=0A= mttr $13,$14,0,4,0=0A= mttr $13,$14,0,5,0=0A= mttr $13,$14,0,6,0=0A= mttr $13,$14,0,7,0=0A= mttr $13,$14,0,0,1=0A= mttr $13,$14,0,1,1=0A= mttr $13,$14,0,2,1=0A= mttr $13,$14,0,3,1=0A= mttr $13,$14,0,4,1=0A= mttr $13,$14,0,5,1=0A= mttr $13,$14,0,6,1=0A= mttr $13,$14,0,7,1=0A= mttr $13,$14,0,0,2=0A= mttr $13,$14,0,1,2=0A= mttr $13,$14,0,2,2=0A= mttr $13,$14,0,3,2=0A= mttr $13,$14,0,4,2=0A= mttr $13,$14,0,5,2=0A= mttr $13,$14,0,6,2=0A= mttr $13,$14,0,7,2=0A= mttr $13,$14,1,0,-1=0A= mttr $13,$14,1,1,-1=0A= mttr $13,$14,1,2,-1=0A= mttr $13,$14,1,3,-1=0A= mttr $13,$14,1,4,-1=0A= mttr $13,$14,1,5,-1=0A= mttr $13,$14,1,6,-1=0A= mttr $13,$14,1,7,-1=0A= mttr $13,$14,1,0,0=0A= mttr $13,$14,1,1,0=0A= mttr $13,$14,1,2,0=0A= mttr $13,$14,1,3,0=0A= mttr $13,$14,1,4,0=0A= mttr $13,$14,1,5,0=0A= mttr $13,$14,1,6,0=0A= mttr $13,$14,1,7,0=0A= mttr $13,$14,1,0,1=0A= mttr $13,$14,1,1,1=0A= mttr $13,$14,1,2,1=0A= mttr $13,$14,1,3,1=0A= mttr $13,$14,1,4,1=0A= mttr $13,$14,1,5,1=0A= mttr $13,$14,1,6,1=0A= mttr $13,$14,1,7,1=0A= mttr $13,$14,1,0,2=0A= mttr $13,$14,1,1,2=0A= mttr $13,$14,1,2,2=0A= mttr $13,$14,1,3,2=0A= mttr $13,$14,1,4,2=0A= mttr $13,$14,1,5,2=0A= mttr $13,$14,1,6,2=0A= mttr $13,$14,1,7,2=0A= mttr $13,$14,2,0,-1=0A= mttr $13,$14,2,1,-1=0A= mttr $13,$14,2,2,-1=0A= mttr $13,$14,2,3,-1=0A= mttr $13,$14,2,4,-1=0A= mttr $13,$14,2,5,-1=0A= mttr $13,$14,2,6,-1=0A= mttr $13,$14,2,7,-1=0A= mttr $13,$14,2,0,0=0A= mttr $13,$14,2,1,0=0A= mttr $13,$14,2,2,0=0A= mttr $13,$14,2,3,0=0A= mttr $13,$14,2,4,0=0A= mttr $13,$14,2,5,0=0A= mttr $13,$14,2,6,0=0A= mttr $13,$14,2,7,0=0A= mttr $13,$14,2,0,1=0A= mttr $13,$14,2,1,1=0A= mttr $13,$14,2,2,1=0A= mttr $13,$14,2,3,1=0A= mttr $13,$14,2,4,1=0A= mttr $13,$14,2,5,1=0A= mttr $13,$14,2,6,1=0A= mttr $13,$14,2,7,1=0A= mttr $13,$14,2,0,2=0A= mttr $13,$14,2,1,2=0A= mttr $13,$14,2,2,2=0A= mttr $13,$14,2,3,2=0A= mttr $13,$14,2,4,2=0A= mttr $13,$14,2,5,2=0A= mttr $13,$14,2,6,2=0A= mttr $13,$14,2,7,2=0A= =0A= # Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...= =0A= .space 8=0A= ------=_NextPart_000_001E_01C5ACB5.DBFB3A60 Content-Type: application/octet-stream; name="mips32-mt.l" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="mips32-mt.l" Content-length: 16028 .*: Assembler messages:=0A= .*:568: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:568: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:569: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:569: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:570: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:570: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:571: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:571: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:572: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:572: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:573: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:573: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:574: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:574: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:575: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:575: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:576: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:577: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:578: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:579: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:580: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:581: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:582: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:583: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:584: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:585: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:586: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:587: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:588: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:589: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:590: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:591: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:592: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:592: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:593: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:593: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:594: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:594: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:595: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:595: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:596: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:596: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:597: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:597: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:598: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:598: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:599: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:599: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:600: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:601: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:602: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:603: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:604: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:605: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:606: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:607: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:624: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:625: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:626: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:627: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:628: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:629: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:630: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:631: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:632: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:633: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:634: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:635: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:636: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:637: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:638: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:639: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:656: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:657: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:658: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:659: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:660: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:661: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:662: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:663: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:664: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:664: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:665: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:665: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:666: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:666: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:667: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:667: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:668: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:668: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:669: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:669: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:670: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:670: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:671: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:671: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:672: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:673: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:674: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:675: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:676: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:677: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:678: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:679: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:680: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:681: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:682: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:683: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:684: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:685: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:686: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:687: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:688: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:688: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:689: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:689: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:690: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:690: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:691: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:691: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:692: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:692: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:693: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:693: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:694: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:694: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:695: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:695: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:696: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:696: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:697: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:697: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:698: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:698: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:699: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:699: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:700: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:700: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:701: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:701: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:702: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:702: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:703: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:703: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:704: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:705: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:706: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:707: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:708: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:709: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:710: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:711: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:712: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:713: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:714: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:715: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:716: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:717: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:718: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:719: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:720: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:720: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:721: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:721: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:722: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:722: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:723: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:723: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:724: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:724: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:725: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:725: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:726: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:726: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:727: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:727: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:728: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:729: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:730: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:731: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:732: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:733: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:734: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:735: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:752: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:753: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:754: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:755: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:756: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:757: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:758: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:759: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:760: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:761: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:762: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:763: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:764: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:765: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:766: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:767: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:784: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:785: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:786: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:787: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:788: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:789: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:790: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:791: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:792: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:792: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:793: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:793: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:794: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:794: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:795: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:795: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:796: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:796: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:797: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:797: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:798: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:798: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:799: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:799: Warning: MT immediate not in range 0..1 \(4294967295\)=0A= .*:800: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:801: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:802: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:803: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:804: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:805: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:806: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:807: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:808: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:809: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:810: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:811: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:812: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:813: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:814: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:815: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:816: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:816: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:817: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:817: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:818: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:818: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:819: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:819: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:820: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:820: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:821: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:821: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:822: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:822: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:823: Warning: MT immediate not in range 0..1 \(2\)=0A= .*:823: Warning: MT immediate not in range 0..1 \(2\)=0A= ------=_NextPart_000_001E_01C5ACB5.DBFB3A60 Content-Type: application/octet-stream; name="mips32-mt.d" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="mips32-mt.d" Content-length: 37191 #objdump: -dr --prefix-addresses --show-raw-insn -M cp0-names=3Dmips32=0A= #name: MIPS MT ASE for MIPS32=0A= #as: -mt=0A= #stderr: mips32-mt.l=0A= =0A= # Check MIPS MT ASE for MIPS32 Instruction Assembly=0A= =0A= .*: +file format .*mips.*=0A= =0A= Disassembly of section .text:=0A= 0+0000 <[^>]*> 41600bc1 dmt=0A= 0+0004 <[^>]*> 417f0bc1 dmt ra=0A= 0+0008 <[^>]*> 41600001 dvpe=0A= 0+000c <[^>]*> 41610001 dvpe at=0A= 0+0010 <[^>]*> 41600be1 emt=0A= 0+0014 <[^>]*> 41620be1 emt v0=0A= 0+0018 <[^>]*> 41600021 evpe=0A= 0+001c <[^>]*> 41630021 evpe v1=0A= 0+0020 <[^>]*> 7ca62008 fork a0,a1,a2=0A= 0+0024 <[^>]*> 7ca00009 yield a1=0A= 0+0028 <[^>]*> 7ce03009 yield a2,a3=0A= 0+002c <[^>]*> 41083800 mftc0 a3,c0_badvaddr=0A= 0+0030 <[^>]*> 41004000 mftc0 t0,c0_index=0A= 0+0034 <[^>]*> 41004001 mftc0 t0,\$0,1=0A= 0+0038 <[^>]*> 41004002 mftc0 t0,\$0,2=0A= 0+003c <[^>]*> 41004003 mftc0 t0,\$0,3=0A= 0+0040 <[^>]*> 41004004 mftc0 t0,\$0,4=0A= 0+0044 <[^>]*> 41004005 mftc0 t0,\$0,5=0A= 0+0048 <[^>]*> 41004006 mftc0 t0,\$0,6=0A= 0+004c <[^>]*> 41004007 mftc0 t0,\$0,7=0A= 0+0050 <[^>]*> 41014000 mftc0 t0,c0_random=0A= 0+0054 <[^>]*> 41014001 mftc0 t0,\$1,1=0A= 0+0058 <[^>]*> 41014002 mftc0 t0,\$1,2=0A= 0+005c <[^>]*> 41014003 mftc0 t0,\$1,3=0A= 0+0060 <[^>]*> 41014004 mftc0 t0,\$1,4=0A= 0+0064 <[^>]*> 41014005 mftc0 t0,\$1,5=0A= 0+0068 <[^>]*> 41014006 mftc0 t0,\$1,6=0A= 0+006c <[^>]*> 41014007 mftc0 t0,\$1,7=0A= 0+0070 <[^>]*> 41024000 mftc0 t0,c0_entrylo0=0A= 0+0074 <[^>]*> 41024001 mftc0 t0,\$2,1=0A= 0+0078 <[^>]*> 41024002 mftc0 t0,\$2,2=0A= 0+007c <[^>]*> 41024003 mftc0 t0,\$2,3=0A= 0+0080 <[^>]*> 41024004 mftc0 t0,\$2,4=0A= 0+0084 <[^>]*> 41024005 mftc0 t0,\$2,5=0A= 0+0088 <[^>]*> 41024006 mftc0 t0,\$2,6=0A= 0+008c <[^>]*> 41024007 mftc0 t0,\$2,7=0A= 0+0090 <[^>]*> 41034000 mftc0 t0,c0_entrylo1=0A= 0+0094 <[^>]*> 41034001 mftc0 t0,\$3,1=0A= 0+0098 <[^>]*> 41034002 mftc0 t0,\$3,2=0A= 0+009c <[^>]*> 41034003 mftc0 t0,\$3,3=0A= 0+00a0 <[^>]*> 41034004 mftc0 t0,\$3,4=0A= 0+00a4 <[^>]*> 41034005 mftc0 t0,\$3,5=0A= 0+00a8 <[^>]*> 41034006 mftc0 t0,\$3,6=0A= 0+00ac <[^>]*> 41034007 mftc0 t0,\$3,7=0A= 0+00b0 <[^>]*> 41044000 mftc0 t0,c0_context=0A= 0+00b4 <[^>]*> 41044001 mftc0 t0,\$4,1=0A= 0+00b8 <[^>]*> 41044002 mftc0 t0,\$4,2=0A= 0+00bc <[^>]*> 41044003 mftc0 t0,\$4,3=0A= 0+00c0 <[^>]*> 41044004 mftc0 t0,\$4,4=0A= 0+00c4 <[^>]*> 41044005 mftc0 t0,\$4,5=0A= 0+00c8 <[^>]*> 41044006 mftc0 t0,\$4,6=0A= 0+00cc <[^>]*> 41044007 mftc0 t0,\$4,7=0A= 0+00d0 <[^>]*> 41054000 mftc0 t0,c0_pagemask=0A= 0+00d4 <[^>]*> 41054001 mftc0 t0,\$5,1=0A= 0+00d8 <[^>]*> 41054002 mftc0 t0,\$5,2=0A= 0+00dc <[^>]*> 41054003 mftc0 t0,\$5,3=0A= 0+00e0 <[^>]*> 41054004 mftc0 t0,\$5,4=0A= 0+00e4 <[^>]*> 41054005 mftc0 t0,\$5,5=0A= 0+00e8 <[^>]*> 41054006 mftc0 t0,\$5,6=0A= 0+00ec <[^>]*> 41054007 mftc0 t0,\$5,7=0A= 0+00f0 <[^>]*> 41064000 mftc0 t0,c0_wired=0A= 0+00f4 <[^>]*> 41064001 mftc0 t0,\$6,1=0A= 0+00f8 <[^>]*> 41064002 mftc0 t0,\$6,2=0A= 0+00fc <[^>]*> 41064003 mftc0 t0,\$6,3=0A= 0+0100 <[^>]*> 41064004 mftc0 t0,\$6,4=0A= 0+0104 <[^>]*> 41064005 mftc0 t0,\$6,5=0A= 0+0108 <[^>]*> 41064006 mftc0 t0,\$6,6=0A= 0+010c <[^>]*> 41064007 mftc0 t0,\$6,7=0A= 0+0110 <[^>]*> 41074000 mftc0 t0,\$7=0A= 0+0114 <[^>]*> 41074001 mftc0 t0,\$7,1=0A= 0+0118 <[^>]*> 41074002 mftc0 t0,\$7,2=0A= 0+011c <[^>]*> 41074003 mftc0 t0,\$7,3=0A= 0+0120 <[^>]*> 41074004 mftc0 t0,\$7,4=0A= 0+0124 <[^>]*> 41074005 mftc0 t0,\$7,5=0A= 0+0128 <[^>]*> 41074006 mftc0 t0,\$7,6=0A= 0+012c <[^>]*> 41074007 mftc0 t0,\$7,7=0A= 0+0130 <[^>]*> 41084000 mftc0 t0,c0_badvaddr=0A= 0+0134 <[^>]*> 41084001 mftc0 t0,\$8,1=0A= 0+0138 <[^>]*> 41084002 mftc0 t0,\$8,2=0A= 0+013c <[^>]*> 41084003 mftc0 t0,\$8,3=0A= 0+0140 <[^>]*> 41084004 mftc0 t0,\$8,4=0A= 0+0144 <[^>]*> 41084005 mftc0 t0,\$8,5=0A= 0+0148 <[^>]*> 41084006 mftc0 t0,\$8,6=0A= 0+014c <[^>]*> 41084007 mftc0 t0,\$8,7=0A= 0+0150 <[^>]*> 41094000 mftc0 t0,c0_count=0A= 0+0154 <[^>]*> 41094001 mftc0 t0,\$9,1=0A= 0+0158 <[^>]*> 41094002 mftc0 t0,\$9,2=0A= 0+015c <[^>]*> 41094003 mftc0 t0,\$9,3=0A= 0+0160 <[^>]*> 41094004 mftc0 t0,\$9,4=0A= 0+0164 <[^>]*> 41094005 mftc0 t0,\$9,5=0A= 0+0168 <[^>]*> 41094006 mftc0 t0,\$9,6=0A= 0+016c <[^>]*> 41094007 mftc0 t0,\$9,7=0A= 0+0170 <[^>]*> 410a4000 mftc0 t0,c0_entryhi=0A= 0+0174 <[^>]*> 410a4001 mftc0 t0,\$10,1=0A= 0+0178 <[^>]*> 410a4002 mftc0 t0,\$10,2=0A= 0+017c <[^>]*> 410a4003 mftc0 t0,\$10,3=0A= 0+0180 <[^>]*> 410a4004 mftc0 t0,\$10,4=0A= 0+0184 <[^>]*> 410a4005 mftc0 t0,\$10,5=0A= 0+0188 <[^>]*> 410a4006 mftc0 t0,\$10,6=0A= 0+018c <[^>]*> 410a4007 mftc0 t0,\$10,7=0A= 0+0190 <[^>]*> 410b4000 mftc0 t0,c0_compare=0A= 0+0194 <[^>]*> 410b4001 mftc0 t0,\$11,1=0A= 0+0198 <[^>]*> 410b4002 mftc0 t0,\$11,2=0A= 0+019c <[^>]*> 410b4003 mftc0 t0,\$11,3=0A= 0+01a0 <[^>]*> 410b4004 mftc0 t0,\$11,4=0A= 0+01a4 <[^>]*> 410b4005 mftc0 t0,\$11,5=0A= 0+01a8 <[^>]*> 410b4006 mftc0 t0,\$11,6=0A= 0+01ac <[^>]*> 410b4007 mftc0 t0,\$11,7=0A= 0+01b0 <[^>]*> 410c4000 mftc0 t0,c0_status=0A= 0+01b4 <[^>]*> 410c4001 mftc0 t0,\$12,1=0A= 0+01b8 <[^>]*> 410c4002 mftc0 t0,\$12,2=0A= 0+01bc <[^>]*> 410c4003 mftc0 t0,\$12,3=0A= 0+01c0 <[^>]*> 410c4004 mftc0 t0,\$12,4=0A= 0+01c4 <[^>]*> 410c4005 mftc0 t0,\$12,5=0A= 0+01c8 <[^>]*> 410c4006 mftc0 t0,\$12,6=0A= 0+01cc <[^>]*> 410c4007 mftc0 t0,\$12,7=0A= 0+01d0 <[^>]*> 410d4000 mftc0 t0,c0_cause=0A= 0+01d4 <[^>]*> 410d4001 mftc0 t0,\$13,1=0A= 0+01d8 <[^>]*> 410d4002 mftc0 t0,\$13,2=0A= 0+01dc <[^>]*> 410d4003 mftc0 t0,\$13,3=0A= 0+01e0 <[^>]*> 410d4004 mftc0 t0,\$13,4=0A= 0+01e4 <[^>]*> 410d4005 mftc0 t0,\$13,5=0A= 0+01e8 <[^>]*> 410d4006 mftc0 t0,\$13,6=0A= 0+01ec <[^>]*> 410d4007 mftc0 t0,\$13,7=0A= 0+01f0 <[^>]*> 410e4000 mftc0 t0,c0_epc=0A= 0+01f4 <[^>]*> 410e4001 mftc0 t0,\$14,1=0A= 0+01f8 <[^>]*> 410e4002 mftc0 t0,\$14,2=0A= 0+01fc <[^>]*> 410e4003 mftc0 t0,\$14,3=0A= 0+0200 <[^>]*> 410e4004 mftc0 t0,\$14,4=0A= 0+0204 <[^>]*> 410e4005 mftc0 t0,\$14,5=0A= 0+0208 <[^>]*> 410e4006 mftc0 t0,\$14,6=0A= 0+020c <[^>]*> 410e4007 mftc0 t0,\$14,7=0A= 0+0210 <[^>]*> 410f4000 mftc0 t0,c0_prid=0A= 0+0214 <[^>]*> 410f4001 mftc0 t0,\$15,1=0A= 0+0218 <[^>]*> 410f4002 mftc0 t0,\$15,2=0A= 0+021c <[^>]*> 410f4003 mftc0 t0,\$15,3=0A= 0+0220 <[^>]*> 410f4004 mftc0 t0,\$15,4=0A= 0+0224 <[^>]*> 410f4005 mftc0 t0,\$15,5=0A= 0+0228 <[^>]*> 410f4006 mftc0 t0,\$15,6=0A= 0+022c <[^>]*> 410f4007 mftc0 t0,\$15,7=0A= 0+0230 <[^>]*> 41104000 mftc0 t0,c0_config=0A= 0+0234 <[^>]*> 41104001 mftc0 t0,c0_config1=0A= 0+0238 <[^>]*> 41104002 mftc0 t0,c0_config2=0A= 0+023c <[^>]*> 41104003 mftc0 t0,c0_config3=0A= 0+0240 <[^>]*> 41104004 mftc0 t0,\$16,4=0A= 0+0244 <[^>]*> 41104005 mftc0 t0,\$16,5=0A= 0+0248 <[^>]*> 41104006 mftc0 t0,\$16,6=0A= 0+024c <[^>]*> 41104007 mftc0 t0,\$16,7=0A= 0+0250 <[^>]*> 41114000 mftc0 t0,c0_lladdr=0A= 0+0254 <[^>]*> 41114001 mftc0 t0,\$17,1=0A= 0+0258 <[^>]*> 41114002 mftc0 t0,\$17,2=0A= 0+025c <[^>]*> 41114003 mftc0 t0,\$17,3=0A= 0+0260 <[^>]*> 41114004 mftc0 t0,\$17,4=0A= 0+0264 <[^>]*> 41114005 mftc0 t0,\$17,5=0A= 0+0268 <[^>]*> 41114006 mftc0 t0,\$17,6=0A= 0+026c <[^>]*> 41114007 mftc0 t0,\$17,7=0A= 0+0270 <[^>]*> 41124000 mftc0 t0,c0_watchlo=0A= 0+0274 <[^>]*> 41124001 mftc0 t0,c0_watchlo,1=0A= 0+0278 <[^>]*> 41124002 mftc0 t0,c0_watchlo,2=0A= 0+027c <[^>]*> 41124003 mftc0 t0,c0_watchlo,3=0A= 0+0280 <[^>]*> 41124004 mftc0 t0,c0_watchlo,4=0A= 0+0284 <[^>]*> 41124005 mftc0 t0,c0_watchlo,5=0A= 0+0288 <[^>]*> 41124006 mftc0 t0,c0_watchlo,6=0A= 0+028c <[^>]*> 41124007 mftc0 t0,c0_watchlo,7=0A= 0+0290 <[^>]*> 41134000 mftc0 t0,c0_watchhi=0A= 0+0294 <[^>]*> 41134001 mftc0 t0,c0_watchhi,1=0A= 0+0298 <[^>]*> 41134002 mftc0 t0,c0_watchhi,2=0A= 0+029c <[^>]*> 41134003 mftc0 t0,c0_watchhi,3=0A= 0+02a0 <[^>]*> 41134004 mftc0 t0,c0_watchhi,4=0A= 0+02a4 <[^>]*> 41134005 mftc0 t0,c0_watchhi,5=0A= 0+02a8 <[^>]*> 41134006 mftc0 t0,c0_watchhi,6=0A= 0+02ac <[^>]*> 41134007 mftc0 t0,c0_watchhi,7=0A= 0+02b0 <[^>]*> 41144000 mftc0 t0,c0_xcontext=0A= 0+02b4 <[^>]*> 41144001 mftc0 t0,\$20,1=0A= 0+02b8 <[^>]*> 41144002 mftc0 t0,\$20,2=0A= 0+02bc <[^>]*> 41144003 mftc0 t0,\$20,3=0A= 0+02c0 <[^>]*> 41144004 mftc0 t0,\$20,4=0A= 0+02c4 <[^>]*> 41144005 mftc0 t0,\$20,5=0A= 0+02c8 <[^>]*> 41144006 mftc0 t0,\$20,6=0A= 0+02cc <[^>]*> 41144007 mftc0 t0,\$20,7=0A= 0+02d0 <[^>]*> 41154000 mftc0 t0,\$21=0A= 0+02d4 <[^>]*> 41154001 mftc0 t0,\$21,1=0A= 0+02d8 <[^>]*> 41154002 mftc0 t0,\$21,2=0A= 0+02dc <[^>]*> 41154003 mftc0 t0,\$21,3=0A= 0+02e0 <[^>]*> 41154004 mftc0 t0,\$21,4=0A= 0+02e4 <[^>]*> 41154005 mftc0 t0,\$21,5=0A= 0+02e8 <[^>]*> 41154006 mftc0 t0,\$21,6=0A= 0+02ec <[^>]*> 41154007 mftc0 t0,\$21,7=0A= 0+02f0 <[^>]*> 41164000 mftc0 t0,\$22=0A= 0+02f4 <[^>]*> 41164001 mftc0 t0,\$22,1=0A= 0+02f8 <[^>]*> 41164002 mftc0 t0,\$22,2=0A= 0+02fc <[^>]*> 41164003 mftc0 t0,\$22,3=0A= 0+0300 <[^>]*> 41164004 mftc0 t0,\$22,4=0A= 0+0304 <[^>]*> 41164005 mftc0 t0,\$22,5=0A= 0+0308 <[^>]*> 41164006 mftc0 t0,\$22,6=0A= 0+030c <[^>]*> 41164007 mftc0 t0,\$22,7=0A= 0+0310 <[^>]*> 41174000 mftc0 t0,c0_debug=0A= 0+0314 <[^>]*> 41174001 mftc0 t0,\$23,1=0A= 0+0318 <[^>]*> 41174002 mftc0 t0,\$23,2=0A= 0+031c <[^>]*> 41174003 mftc0 t0,\$23,3=0A= 0+0320 <[^>]*> 41174004 mftc0 t0,\$23,4=0A= 0+0324 <[^>]*> 41174005 mftc0 t0,\$23,5=0A= 0+0328 <[^>]*> 41174006 mftc0 t0,\$23,6=0A= 0+032c <[^>]*> 41174007 mftc0 t0,\$23,7=0A= 0+0330 <[^>]*> 41184000 mftc0 t0,c0_depc=0A= 0+0334 <[^>]*> 41184001 mftc0 t0,\$24,1=0A= 0+0338 <[^>]*> 41184002 mftc0 t0,\$24,2=0A= 0+033c <[^>]*> 41184003 mftc0 t0,\$24,3=0A= 0+0340 <[^>]*> 41184004 mftc0 t0,\$24,4=0A= 0+0344 <[^>]*> 41184005 mftc0 t0,\$24,5=0A= 0+0348 <[^>]*> 41184006 mftc0 t0,\$24,6=0A= 0+034c <[^>]*> 41184007 mftc0 t0,\$24,7=0A= 0+0350 <[^>]*> 41194000 mftc0 t0,c0_perfcnt=0A= 0+0354 <[^>]*> 41194001 mftc0 t0,c0_perfcnt,1=0A= 0+0358 <[^>]*> 41194002 mftc0 t0,c0_perfcnt,2=0A= 0+035c <[^>]*> 41194003 mftc0 t0,c0_perfcnt,3=0A= 0+0360 <[^>]*> 41194004 mftc0 t0,c0_perfcnt,4=0A= 0+0364 <[^>]*> 41194005 mftc0 t0,c0_perfcnt,5=0A= 0+0368 <[^>]*> 41194006 mftc0 t0,c0_perfcnt,6=0A= 0+036c <[^>]*> 41194007 mftc0 t0,c0_perfcnt,7=0A= 0+0370 <[^>]*> 411a4000 mftc0 t0,c0_errctl=0A= 0+0374 <[^>]*> 411a4001 mftc0 t0,\$26,1=0A= 0+0378 <[^>]*> 411a4002 mftc0 t0,\$26,2=0A= 0+037c <[^>]*> 411a4003 mftc0 t0,\$26,3=0A= 0+0380 <[^>]*> 411a4004 mftc0 t0,\$26,4=0A= 0+0384 <[^>]*> 411a4005 mftc0 t0,\$26,5=0A= 0+0388 <[^>]*> 411a4006 mftc0 t0,\$26,6=0A= 0+038c <[^>]*> 411a4007 mftc0 t0,\$26,7=0A= 0+0390 <[^>]*> 411b4000 mftc0 t0,c0_cacheerr=0A= 0+0394 <[^>]*> 411b4001 mftc0 t0,c0_cacheerr,1=0A= 0+0398 <[^>]*> 411b4002 mftc0 t0,c0_cacheerr,2=0A= 0+039c <[^>]*> 411b4003 mftc0 t0,c0_cacheerr,3=0A= 0+03a0 <[^>]*> 411b4004 mftc0 t0,\$27,4=0A= 0+03a4 <[^>]*> 411b4005 mftc0 t0,\$27,5=0A= 0+03a8 <[^>]*> 411b4006 mftc0 t0,\$27,6=0A= 0+03ac <[^>]*> 411b4007 mftc0 t0,\$27,7=0A= 0+03b0 <[^>]*> 411c4000 mftc0 t0,c0_taglo=0A= 0+03b4 <[^>]*> 411c4001 mftc0 t0,c0_datalo=0A= 0+03b8 <[^>]*> 411c4002 mftc0 t0,\$28,2=0A= 0+03bc <[^>]*> 411c4003 mftc0 t0,\$28,3=0A= 0+03c0 <[^>]*> 411c4004 mftc0 t0,\$28,4=0A= 0+03c4 <[^>]*> 411c4005 mftc0 t0,\$28,5=0A= 0+03c8 <[^>]*> 411c4006 mftc0 t0,\$28,6=0A= 0+03cc <[^>]*> 411c4007 mftc0 t0,\$28,7=0A= 0+03d0 <[^>]*> 411d4000 mftc0 t0,c0_taghi=0A= 0+03d4 <[^>]*> 411d4001 mftc0 t0,c0_datahi=0A= 0+03d8 <[^>]*> 411d4002 mftc0 t0,\$29,2=0A= 0+03dc <[^>]*> 411d4003 mftc0 t0,\$29,3=0A= 0+03e0 <[^>]*> 411d4004 mftc0 t0,\$29,4=0A= 0+03e4 <[^>]*> 411d4005 mftc0 t0,\$29,5=0A= 0+03e8 <[^>]*> 411d4006 mftc0 t0,\$29,6=0A= 0+03ec <[^>]*> 411d4007 mftc0 t0,\$29,7=0A= 0+03f0 <[^>]*> 411e4000 mftc0 t0,c0_errorepc=0A= 0+03f4 <[^>]*> 411e4001 mftc0 t0,\$30,1=0A= 0+03f8 <[^>]*> 411e4002 mftc0 t0,\$30,2=0A= 0+03fc <[^>]*> 411e4003 mftc0 t0,\$30,3=0A= 0+0400 <[^>]*> 411e4004 mftc0 t0,\$30,4=0A= 0+0404 <[^>]*> 411e4005 mftc0 t0,\$30,5=0A= 0+0408 <[^>]*> 411e4006 mftc0 t0,\$30,6=0A= 0+040c <[^>]*> 411e4007 mftc0 t0,\$30,7=0A= 0+0410 <[^>]*> 411f4000 mftc0 t0,c0_desave=0A= 0+0414 <[^>]*> 411f4001 mftc0 t0,\$31,1=0A= 0+0418 <[^>]*> 411f4002 mftc0 t0,\$31,2=0A= 0+041c <[^>]*> 411f4003 mftc0 t0,\$31,3=0A= 0+0420 <[^>]*> 411f4004 mftc0 t0,\$31,4=0A= 0+0424 <[^>]*> 411f4005 mftc0 t0,\$31,5=0A= 0+0428 <[^>]*> 411f4006 mftc0 t0,\$31,6=0A= 0+042c <[^>]*> 411f4007 mftc0 t0,\$31,7=0A= 0+0430 <[^>]*> 410a4820 mftgpr t1,t2=0A= 0+0434 <[^>]*> 41005021 mftlo t2=0A= 0+0438 <[^>]*> 41005821 mftlo t3=0A= 0+043c <[^>]*> 41016021 mfthi t4=0A= 0+0440 <[^>]*> 41056821 mfthi t5,\$ac1=0A= 0+0444 <[^>]*> 41027021 mftacx t6=0A= 0+0448 <[^>]*> 410a7821 mftacx t7,\$ac2=0A= 0+044c <[^>]*> 41108021 mftdsp s0=0A= 0+0450 <[^>]*> 41128822 mftc1 s1,\$f18=0A= 0+0454 <[^>]*> 41139022 mftc1 s2,\$f19=0A= 0+0458 <[^>]*> 41149832 mfthc1 s3,\$f20=0A= 0+045c <[^>]*> 4116a032 mfthc1 s4,\$f22=0A= 0+0460 <[^>]*> 4116a823 cftc1 s5,\$22=0A= 0+0464 <[^>]*> 4117b023 cftc1 s6,\$23=0A= 0+0468 <[^>]*> 4118b824 mftc2 s7,\$24=0A= 0+046c <[^>]*> 4119c034 mfthc2 t8,\$25=0A= 0+0470 <[^>]*> 411ac825 cftc2 t9,\$26=0A= 0+0474 <[^>]*> 419ad800 mttc0 k0,c0_cacheerr=0A= 0+0478 <[^>]*> 419b0000 mttc0 k1,c0_index=0A= 0+047c <[^>]*> 419b0001 mttc0 k1,\$0,1=0A= 0+0480 <[^>]*> 419b0002 mttc0 k1,\$0,2=0A= 0+0484 <[^>]*> 419b0003 mttc0 k1,\$0,3=0A= 0+0488 <[^>]*> 419b0004 mttc0 k1,\$0,4=0A= 0+048c <[^>]*> 419b0005 mttc0 k1,\$0,5=0A= 0+0490 <[^>]*> 419b0006 mttc0 k1,\$0,6=0A= 0+0494 <[^>]*> 419b0007 mttc0 k1,\$0,7=0A= 0+0498 <[^>]*> 419b0800 mttc0 k1,c0_random=0A= 0+049c <[^>]*> 419b0801 mttc0 k1,\$1,1=0A= 0+04a0 <[^>]*> 419b0802 mttc0 k1,\$1,2=0A= 0+04a4 <[^>]*> 419b0803 mttc0 k1,\$1,3=0A= 0+04a8 <[^>]*> 419b0804 mttc0 k1,\$1,4=0A= 0+04ac <[^>]*> 419b0805 mttc0 k1,\$1,5=0A= 0+04b0 <[^>]*> 419b0806 mttc0 k1,\$1,6=0A= 0+04b4 <[^>]*> 419b0807 mttc0 k1,\$1,7=0A= 0+04b8 <[^>]*> 419b1000 mttc0 k1,c0_entrylo0=0A= 0+04bc <[^>]*> 419b1001 mttc0 k1,\$2,1=0A= 0+04c0 <[^>]*> 419b1002 mttc0 k1,\$2,2=0A= 0+04c4 <[^>]*> 419b1003 mttc0 k1,\$2,3=0A= 0+04c8 <[^>]*> 419b1004 mttc0 k1,\$2,4=0A= 0+04cc <[^>]*> 419b1005 mttc0 k1,\$2,5=0A= 0+04d0 <[^>]*> 419b1006 mttc0 k1,\$2,6=0A= 0+04d4 <[^>]*> 419b1007 mttc0 k1,\$2,7=0A= 0+04d8 <[^>]*> 419b1800 mttc0 k1,c0_entrylo1=0A= 0+04dc <[^>]*> 419b1801 mttc0 k1,\$3,1=0A= 0+04e0 <[^>]*> 419b1802 mttc0 k1,\$3,2=0A= 0+04e4 <[^>]*> 419b1803 mttc0 k1,\$3,3=0A= 0+04e8 <[^>]*> 419b1804 mttc0 k1,\$3,4=0A= 0+04ec <[^>]*> 419b1805 mttc0 k1,\$3,5=0A= 0+04f0 <[^>]*> 419b1806 mttc0 k1,\$3,6=0A= 0+04f4 <[^>]*> 419b1807 mttc0 k1,\$3,7=0A= 0+04f8 <[^>]*> 419b2000 mttc0 k1,c0_context=0A= 0+04fc <[^>]*> 419b2001 mttc0 k1,\$4,1=0A= 0+0500 <[^>]*> 419b2002 mttc0 k1,\$4,2=0A= 0+0504 <[^>]*> 419b2003 mttc0 k1,\$4,3=0A= 0+0508 <[^>]*> 419b2004 mttc0 k1,\$4,4=0A= 0+050c <[^>]*> 419b2005 mttc0 k1,\$4,5=0A= 0+0510 <[^>]*> 419b2006 mttc0 k1,\$4,6=0A= 0+0514 <[^>]*> 419b2007 mttc0 k1,\$4,7=0A= 0+0518 <[^>]*> 419b2800 mttc0 k1,c0_pagemask=0A= 0+051c <[^>]*> 419b2801 mttc0 k1,\$5,1=0A= 0+0520 <[^>]*> 419b2802 mttc0 k1,\$5,2=0A= 0+0524 <[^>]*> 419b2803 mttc0 k1,\$5,3=0A= 0+0528 <[^>]*> 419b2804 mttc0 k1,\$5,4=0A= 0+052c <[^>]*> 419b2805 mttc0 k1,\$5,5=0A= 0+0530 <[^>]*> 419b2806 mttc0 k1,\$5,6=0A= 0+0534 <[^>]*> 419b2807 mttc0 k1,\$5,7=0A= 0+0538 <[^>]*> 419b3000 mttc0 k1,c0_wired=0A= 0+053c <[^>]*> 419b3001 mttc0 k1,\$6,1=0A= 0+0540 <[^>]*> 419b3002 mttc0 k1,\$6,2=0A= 0+0544 <[^>]*> 419b3003 mttc0 k1,\$6,3=0A= 0+0548 <[^>]*> 419b3004 mttc0 k1,\$6,4=0A= 0+054c <[^>]*> 419b3005 mttc0 k1,\$6,5=0A= 0+0550 <[^>]*> 419b3006 mttc0 k1,\$6,6=0A= 0+0554 <[^>]*> 419b3007 mttc0 k1,\$6,7=0A= 0+0558 <[^>]*> 419b3800 mttc0 k1,\$7=0A= 0+055c <[^>]*> 419b3801 mttc0 k1,\$7,1=0A= 0+0560 <[^>]*> 419b3802 mttc0 k1,\$7,2=0A= 0+0564 <[^>]*> 419b3803 mttc0 k1,\$7,3=0A= 0+0568 <[^>]*> 419b3804 mttc0 k1,\$7,4=0A= 0+056c <[^>]*> 419b3805 mttc0 k1,\$7,5=0A= 0+0570 <[^>]*> 419b3806 mttc0 k1,\$7,6=0A= 0+0574 <[^>]*> 419b3807 mttc0 k1,\$7,7=0A= 0+0578 <[^>]*> 419b4000 mttc0 k1,c0_badvaddr=0A= 0+057c <[^>]*> 419b4001 mttc0 k1,\$8,1=0A= 0+0580 <[^>]*> 419b4002 mttc0 k1,\$8,2=0A= 0+0584 <[^>]*> 419b4003 mttc0 k1,\$8,3=0A= 0+0588 <[^>]*> 419b4004 mttc0 k1,\$8,4=0A= 0+058c <[^>]*> 419b4005 mttc0 k1,\$8,5=0A= 0+0590 <[^>]*> 419b4006 mttc0 k1,\$8,6=0A= 0+0594 <[^>]*> 419b4007 mttc0 k1,\$8,7=0A= 0+0598 <[^>]*> 419b4800 mttc0 k1,c0_count=0A= 0+059c <[^>]*> 419b4801 mttc0 k1,\$9,1=0A= 0+05a0 <[^>]*> 419b4802 mttc0 k1,\$9,2=0A= 0+05a4 <[^>]*> 419b4803 mttc0 k1,\$9,3=0A= 0+05a8 <[^>]*> 419b4804 mttc0 k1,\$9,4=0A= 0+05ac <[^>]*> 419b4805 mttc0 k1,\$9,5=0A= 0+05b0 <[^>]*> 419b4806 mttc0 k1,\$9,6=0A= 0+05b4 <[^>]*> 419b4807 mttc0 k1,\$9,7=0A= 0+05b8 <[^>]*> 419b5000 mttc0 k1,c0_entryhi=0A= 0+05bc <[^>]*> 419b5001 mttc0 k1,\$10,1=0A= 0+05c0 <[^>]*> 419b5002 mttc0 k1,\$10,2=0A= 0+05c4 <[^>]*> 419b5003 mttc0 k1,\$10,3=0A= 0+05c8 <[^>]*> 419b5004 mttc0 k1,\$10,4=0A= 0+05cc <[^>]*> 419b5005 mttc0 k1,\$10,5=0A= 0+05d0 <[^>]*> 419b5006 mttc0 k1,\$10,6=0A= 0+05d4 <[^>]*> 419b5007 mttc0 k1,\$10,7=0A= 0+05d8 <[^>]*> 419b5800 mttc0 k1,c0_compare=0A= 0+05dc <[^>]*> 419b5801 mttc0 k1,\$11,1=0A= 0+05e0 <[^>]*> 419b5802 mttc0 k1,\$11,2=0A= 0+05e4 <[^>]*> 419b5803 mttc0 k1,\$11,3=0A= 0+05e8 <[^>]*> 419b5804 mttc0 k1,\$11,4=0A= 0+05ec <[^>]*> 419b5805 mttc0 k1,\$11,5=0A= 0+05f0 <[^>]*> 419b5806 mttc0 k1,\$11,6=0A= 0+05f4 <[^>]*> 419b5807 mttc0 k1,\$11,7=0A= 0+05f8 <[^>]*> 419b6000 mttc0 k1,c0_status=0A= 0+05fc <[^>]*> 419b6001 mttc0 k1,\$12,1=0A= 0+0600 <[^>]*> 419b6002 mttc0 k1,\$12,2=0A= 0+0604 <[^>]*> 419b6003 mttc0 k1,\$12,3=0A= 0+0608 <[^>]*> 419b6004 mttc0 k1,\$12,4=0A= 0+060c <[^>]*> 419b6005 mttc0 k1,\$12,5=0A= 0+0610 <[^>]*> 419b6006 mttc0 k1,\$12,6=0A= 0+0614 <[^>]*> 419b6007 mttc0 k1,\$12,7=0A= 0+0618 <[^>]*> 419b6800 mttc0 k1,c0_cause=0A= 0+061c <[^>]*> 419b6801 mttc0 k1,\$13,1=0A= 0+0620 <[^>]*> 419b6802 mttc0 k1,\$13,2=0A= 0+0624 <[^>]*> 419b6803 mttc0 k1,\$13,3=0A= 0+0628 <[^>]*> 419b6804 mttc0 k1,\$13,4=0A= 0+062c <[^>]*> 419b6805 mttc0 k1,\$13,5=0A= 0+0630 <[^>]*> 419b6806 mttc0 k1,\$13,6=0A= 0+0634 <[^>]*> 419b6807 mttc0 k1,\$13,7=0A= 0+0638 <[^>]*> 419b7000 mttc0 k1,c0_epc=0A= 0+063c <[^>]*> 419b7001 mttc0 k1,\$14,1=0A= 0+0640 <[^>]*> 419b7002 mttc0 k1,\$14,2=0A= 0+0644 <[^>]*> 419b7003 mttc0 k1,\$14,3=0A= 0+0648 <[^>]*> 419b7004 mttc0 k1,\$14,4=0A= 0+064c <[^>]*> 419b7005 mttc0 k1,\$14,5=0A= 0+0650 <[^>]*> 419b7006 mttc0 k1,\$14,6=0A= 0+0654 <[^>]*> 419b7007 mttc0 k1,\$14,7=0A= 0+0658 <[^>]*> 419b7800 mttc0 k1,c0_prid=0A= 0+065c <[^>]*> 419b7801 mttc0 k1,\$15,1=0A= 0+0660 <[^>]*> 419b7802 mttc0 k1,\$15,2=0A= 0+0664 <[^>]*> 419b7803 mttc0 k1,\$15,3=0A= 0+0668 <[^>]*> 419b7804 mttc0 k1,\$15,4=0A= 0+066c <[^>]*> 419b7805 mttc0 k1,\$15,5=0A= 0+0670 <[^>]*> 419b7806 mttc0 k1,\$15,6=0A= 0+0674 <[^>]*> 419b7807 mttc0 k1,\$15,7=0A= 0+0678 <[^>]*> 419b8000 mttc0 k1,c0_config=0A= 0+067c <[^>]*> 419b8001 mttc0 k1,c0_config1=0A= 0+0680 <[^>]*> 419b8002 mttc0 k1,c0_config2=0A= 0+0684 <[^>]*> 419b8003 mttc0 k1,c0_config3=0A= 0+0688 <[^>]*> 419b8004 mttc0 k1,\$16,4=0A= 0+068c <[^>]*> 419b8005 mttc0 k1,\$16,5=0A= 0+0690 <[^>]*> 419b8006 mttc0 k1,\$16,6=0A= 0+0694 <[^>]*> 419b8007 mttc0 k1,\$16,7=0A= 0+0698 <[^>]*> 419b8800 mttc0 k1,c0_lladdr=0A= 0+069c <[^>]*> 419b8801 mttc0 k1,\$17,1=0A= 0+06a0 <[^>]*> 419b8802 mttc0 k1,\$17,2=0A= 0+06a4 <[^>]*> 419b8803 mttc0 k1,\$17,3=0A= 0+06a8 <[^>]*> 419b8804 mttc0 k1,\$17,4=0A= 0+06ac <[^>]*> 419b8805 mttc0 k1,\$17,5=0A= 0+06b0 <[^>]*> 419b8806 mttc0 k1,\$17,6=0A= 0+06b4 <[^>]*> 419b8807 mttc0 k1,\$17,7=0A= 0+06b8 <[^>]*> 419b9000 mttc0 k1,c0_watchlo=0A= 0+06bc <[^>]*> 419b9001 mttc0 k1,c0_watchlo,1=0A= 0+06c0 <[^>]*> 419b9002 mttc0 k1,c0_watchlo,2=0A= 0+06c4 <[^>]*> 419b9003 mttc0 k1,c0_watchlo,3=0A= 0+06c8 <[^>]*> 419b9004 mttc0 k1,c0_watchlo,4=0A= 0+06cc <[^>]*> 419b9005 mttc0 k1,c0_watchlo,5=0A= 0+06d0 <[^>]*> 419b9006 mttc0 k1,c0_watchlo,6=0A= 0+06d4 <[^>]*> 419b9007 mttc0 k1,c0_watchlo,7=0A= 0+06d8 <[^>]*> 419b9800 mttc0 k1,c0_watchhi=0A= 0+06dc <[^>]*> 419b9801 mttc0 k1,c0_watchhi,1=0A= 0+06e0 <[^>]*> 419b9802 mttc0 k1,c0_watchhi,2=0A= 0+06e4 <[^>]*> 419b9803 mttc0 k1,c0_watchhi,3=0A= 0+06e8 <[^>]*> 419b9804 mttc0 k1,c0_watchhi,4=0A= 0+06ec <[^>]*> 419b9805 mttc0 k1,c0_watchhi,5=0A= 0+06f0 <[^>]*> 419b9806 mttc0 k1,c0_watchhi,6=0A= 0+06f4 <[^>]*> 419b9807 mttc0 k1,c0_watchhi,7=0A= 0+06f8 <[^>]*> 419ba000 mttc0 k1,c0_xcontext=0A= 0+06fc <[^>]*> 419ba001 mttc0 k1,\$20,1=0A= 0+0700 <[^>]*> 419ba002 mttc0 k1,\$20,2=0A= 0+0704 <[^>]*> 419ba003 mttc0 k1,\$20,3=0A= 0+0708 <[^>]*> 419ba004 mttc0 k1,\$20,4=0A= 0+070c <[^>]*> 419ba005 mttc0 k1,\$20,5=0A= 0+0710 <[^>]*> 419ba006 mttc0 k1,\$20,6=0A= 0+0714 <[^>]*> 419ba007 mttc0 k1,\$20,7=0A= 0+0718 <[^>]*> 419ba800 mttc0 k1,\$21=0A= 0+071c <[^>]*> 419ba801 mttc0 k1,\$21,1=0A= 0+0720 <[^>]*> 419ba802 mttc0 k1,\$21,2=0A= 0+0724 <[^>]*> 419ba803 mttc0 k1,\$21,3=0A= 0+0728 <[^>]*> 419ba804 mttc0 k1,\$21,4=0A= 0+072c <[^>]*> 419ba805 mttc0 k1,\$21,5=0A= 0+0730 <[^>]*> 419ba806 mttc0 k1,\$21,6=0A= 0+0734 <[^>]*> 419ba807 mttc0 k1,\$21,7=0A= 0+0738 <[^>]*> 419bb000 mttc0 k1,\$22=0A= 0+073c <[^>]*> 419bb001 mttc0 k1,\$22,1=0A= 0+0740 <[^>]*> 419bb002 mttc0 k1,\$22,2=0A= 0+0744 <[^>]*> 419bb003 mttc0 k1,\$22,3=0A= 0+0748 <[^>]*> 419bb004 mttc0 k1,\$22,4=0A= 0+074c <[^>]*> 419bb005 mttc0 k1,\$22,5=0A= 0+0750 <[^>]*> 419bb006 mttc0 k1,\$22,6=0A= 0+0754 <[^>]*> 419bb007 mttc0 k1,\$22,7=0A= 0+0758 <[^>]*> 419bb800 mttc0 k1,c0_debug=0A= 0+075c <[^>]*> 419bb801 mttc0 k1,\$23,1=0A= 0+0760 <[^>]*> 419bb802 mttc0 k1,\$23,2=0A= 0+0764 <[^>]*> 419bb803 mttc0 k1,\$23,3=0A= 0+0768 <[^>]*> 419bb804 mttc0 k1,\$23,4=0A= 0+076c <[^>]*> 419bb805 mttc0 k1,\$23,5=0A= 0+0770 <[^>]*> 419bb806 mttc0 k1,\$23,6=0A= 0+0774 <[^>]*> 419bb807 mttc0 k1,\$23,7=0A= 0+0778 <[^>]*> 419bc000 mttc0 k1,c0_depc=0A= 0+077c <[^>]*> 419bc001 mttc0 k1,\$24,1=0A= 0+0780 <[^>]*> 419bc002 mttc0 k1,\$24,2=0A= 0+0784 <[^>]*> 419bc003 mttc0 k1,\$24,3=0A= 0+0788 <[^>]*> 419bc004 mttc0 k1,\$24,4=0A= 0+078c <[^>]*> 419bc005 mttc0 k1,\$24,5=0A= 0+0790 <[^>]*> 419bc006 mttc0 k1,\$24,6=0A= 0+0794 <[^>]*> 419bc007 mttc0 k1,\$24,7=0A= 0+0798 <[^>]*> 419bc800 mttc0 k1,c0_perfcnt=0A= 0+079c <[^>]*> 419bc801 mttc0 k1,c0_perfcnt,1=0A= 0+07a0 <[^>]*> 419bc802 mttc0 k1,c0_perfcnt,2=0A= 0+07a4 <[^>]*> 419bc803 mttc0 k1,c0_perfcnt,3=0A= 0+07a8 <[^>]*> 419bc804 mttc0 k1,c0_perfcnt,4=0A= 0+07ac <[^>]*> 419bc805 mttc0 k1,c0_perfcnt,5=0A= 0+07b0 <[^>]*> 419bc806 mttc0 k1,c0_perfcnt,6=0A= 0+07b4 <[^>]*> 419bc807 mttc0 k1,c0_perfcnt,7=0A= 0+07b8 <[^>]*> 419bd000 mttc0 k1,c0_errctl=0A= 0+07bc <[^>]*> 419bd001 mttc0 k1,\$26,1=0A= 0+07c0 <[^>]*> 419bd002 mttc0 k1,\$26,2=0A= 0+07c4 <[^>]*> 419bd003 mttc0 k1,\$26,3=0A= 0+07c8 <[^>]*> 419bd004 mttc0 k1,\$26,4=0A= 0+07cc <[^>]*> 419bd005 mttc0 k1,\$26,5=0A= 0+07d0 <[^>]*> 419bd006 mttc0 k1,\$26,6=0A= 0+07d4 <[^>]*> 419bd007 mttc0 k1,\$26,7=0A= 0+07d8 <[^>]*> 419bd800 mttc0 k1,c0_cacheerr=0A= 0+07dc <[^>]*> 419bd801 mttc0 k1,c0_cacheerr,1=0A= 0+07e0 <[^>]*> 419bd802 mttc0 k1,c0_cacheerr,2=0A= 0+07e4 <[^>]*> 419bd803 mttc0 k1,c0_cacheerr,3=0A= 0+07e8 <[^>]*> 419bd804 mttc0 k1,\$27,4=0A= 0+07ec <[^>]*> 419bd805 mttc0 k1,\$27,5=0A= 0+07f0 <[^>]*> 419bd806 mttc0 k1,\$27,6=0A= 0+07f4 <[^>]*> 419bd807 mttc0 k1,\$27,7=0A= 0+07f8 <[^>]*> 419be000 mttc0 k1,c0_taglo=0A= 0+07fc <[^>]*> 419be001 mttc0 k1,c0_datalo=0A= 0+0800 <[^>]*> 419be002 mttc0 k1,\$28,2=0A= 0+0804 <[^>]*> 419be003 mttc0 k1,\$28,3=0A= 0+0808 <[^>]*> 419be004 mttc0 k1,\$28,4=0A= 0+080c <[^>]*> 419be005 mttc0 k1,\$28,5=0A= 0+0810 <[^>]*> 419be006 mttc0 k1,\$28,6=0A= 0+0814 <[^>]*> 419be007 mttc0 k1,\$28,7=0A= 0+0818 <[^>]*> 419be800 mttc0 k1,c0_taghi=0A= 0+081c <[^>]*> 419be801 mttc0 k1,c0_datahi=0A= 0+0820 <[^>]*> 419be802 mttc0 k1,\$29,2=0A= 0+0824 <[^>]*> 419be803 mttc0 k1,\$29,3=0A= 0+0828 <[^>]*> 419be804 mttc0 k1,\$29,4=0A= 0+082c <[^>]*> 419be805 mttc0 k1,\$29,5=0A= 0+0830 <[^>]*> 419be806 mttc0 k1,\$29,6=0A= 0+0834 <[^>]*> 419be807 mttc0 k1,\$29,7=0A= 0+0838 <[^>]*> 419bf000 mttc0 k1,c0_errorepc=0A= 0+083c <[^>]*> 419bf001 mttc0 k1,\$30,1=0A= 0+0840 <[^>]*> 419bf002 mttc0 k1,\$30,2=0A= 0+0844 <[^>]*> 419bf003 mttc0 k1,\$30,3=0A= 0+0848 <[^>]*> 419bf004 mttc0 k1,\$30,4=0A= 0+084c <[^>]*> 419bf005 mttc0 k1,\$30,5=0A= 0+0850 <[^>]*> 419bf006 mttc0 k1,\$30,6=0A= 0+0854 <[^>]*> 419bf007 mttc0 k1,\$30,7=0A= 0+0858 <[^>]*> 419bf800 mttc0 k1,c0_desave=0A= 0+085c <[^>]*> 419bf801 mttc0 k1,\$31,1=0A= 0+0860 <[^>]*> 419bf802 mttc0 k1,\$31,2=0A= 0+0864 <[^>]*> 419bf803 mttc0 k1,\$31,3=0A= 0+0868 <[^>]*> 419bf804 mttc0 k1,\$31,4=0A= 0+086c <[^>]*> 419bf805 mttc0 k1,\$31,5=0A= 0+0870 <[^>]*> 419bf806 mttc0 k1,\$31,6=0A= 0+0874 <[^>]*> 419bf807 mttc0 k1,\$31,7=0A= 0+0878 <[^>]*> 419ce820 mttgpr gp,sp=0A= 0+087c <[^>]*> 419d0021 mttlo sp=0A= 0+0880 <[^>]*> 419e6021 mttlo s8,\$ac3=0A= 0+0884 <[^>]*> 419f0821 mtthi ra=0A= 0+0888 <[^>]*> 41800821 mtthi zero=0A= 0+088c <[^>]*> 41811021 mttacx at=0A= 0+0890 <[^>]*> 41823021 mttacx v0,\$ac1=0A= 0+0894 <[^>]*> 41838021 mttdsp v1=0A= 0+0898 <[^>]*> 41842822 mttc1 a0,\$f5=0A= 0+089c <[^>]*> 41853022 mttc1 a1,\$f6=0A= 0+08a0 <[^>]*> 41864032 mtthc1 a2,\$f8=0A= 0+08a4 <[^>]*> 41875032 mtthc1 a3,\$f10=0A= 0+08a8 <[^>]*> 41884823 cttc1 t0,\$9=0A= 0+08ac <[^>]*> 41895023 cttc1 t1,\$10=0A= 0+08b0 <[^>]*> 418a5824 mttc2 t2,\$11=0A= 0+08b4 <[^>]*> 418b6034 mtthc2 t3,\$12=0A= 0+08b8 <[^>]*> 418c6825 cttc2 t4,\$13=0A= 0+08bc <[^>]*> 410d7030 mftr t5,t6,1,0,1=0A= 0+08c0 <[^>]*> 410d7031 mftr t5,t6,1,1,1=0A= 0+08c4 <[^>]*> 410d7032 mfthc1 t6,\$f13=0A= 0+08c8 <[^>]*> 410d7033 mftr t5,t6,1,3,1=0A= 0+08cc <[^>]*> 410d7034 mfthc2 t6,\$13=0A= 0+08d0 <[^>]*> 410d7035 mftr t5,t6,1,5,1=0A= 0+08d4 <[^>]*> 410d7036 mftr t5,t6,1,6,1=0A= 0+08d8 <[^>]*> 410d7037 mftr t5,t6,1,7,1=0A= 0+08dc <[^>]*> 410d7020 mftgpr t6,t5=0A= 0+08e0 <[^>]*> 410d7021 mfthi t6,\$ac3=0A= 0+08e4 <[^>]*> 410d7022 mftc1 t6,\$f13=0A= 0+08e8 <[^>]*> 410d7023 cftc1 t6,\$13=0A= 0+08ec <[^>]*> 410d7024 mftc2 t6,\$13=0A= 0+08f0 <[^>]*> 410d7025 cftc2 t6,\$13=0A= 0+08f4 <[^>]*> 410d7026 mftr t5,t6,1,6,0=0A= 0+08f8 <[^>]*> 410d7027 mftr t5,t6,1,7,0=0A= 0+08fc <[^>]*> 410d7030 mftr t5,t6,1,0,1=0A= 0+0900 <[^>]*> 410d7031 mftr t5,t6,1,1,1=0A= 0+0904 <[^>]*> 410d7032 mfthc1 t6,\$f13=0A= 0+0908 <[^>]*> 410d7033 mftr t5,t6,1,3,1=0A= 0+090c <[^>]*> 410d7034 mfthc2 t6,\$13=0A= 0+0910 <[^>]*> 410d7035 mftr t5,t6,1,5,1=0A= 0+0914 <[^>]*> 410d7036 mftr t5,t6,1,6,1=0A= 0+0918 <[^>]*> 410d7037 mftr t5,t6,1,7,1=0A= 0+091c <[^>]*> 410d7020 mftgpr t6,t5=0A= 0+0920 <[^>]*> 410d7021 mfthi t6,\$ac3=0A= 0+0924 <[^>]*> 410d7022 mftc1 t6,\$f13=0A= 0+0928 <[^>]*> 410d7023 cftc1 t6,\$13=0A= 0+092c <[^>]*> 410d7024 mftc2 t6,\$13=0A= 0+0930 <[^>]*> 410d7025 cftc2 t6,\$13=0A= 0+0934 <[^>]*> 410d7026 mftr t5,t6,1,6,0=0A= 0+0938 <[^>]*> 410d7027 mftr t5,t6,1,7,0=0A= 0+093c <[^>]*> 410d7010 mftr t5,t6,0,0,1=0A= 0+0940 <[^>]*> 410d7011 mftr t5,t6,0,1,1=0A= 0+0944 <[^>]*> 410d7012 mftr t5,t6,0,2,1=0A= 0+0948 <[^>]*> 410d7013 mftr t5,t6,0,3,1=0A= 0+094c <[^>]*> 410d7014 mftr t5,t6,0,4,1=0A= 0+0950 <[^>]*> 410d7015 mftr t5,t6,0,5,1=0A= 0+0954 <[^>]*> 410d7016 mftr t5,t6,0,6,1=0A= 0+0958 <[^>]*> 410d7017 mftr t5,t6,0,7,1=0A= 0+095c <[^>]*> 410d7000 mftc0 t6,c0_cause=0A= 0+0960 <[^>]*> 410d7001 mftc0 t6,\$13,1=0A= 0+0964 <[^>]*> 410d7002 mftc0 t6,\$13,2=0A= 0+0968 <[^>]*> 410d7003 mftc0 t6,\$13,3=0A= 0+096c <[^>]*> 410d7004 mftc0 t6,\$13,4=0A= 0+0970 <[^>]*> 410d7005 mftc0 t6,\$13,5=0A= 0+0974 <[^>]*> 410d7006 mftc0 t6,\$13,6=0A= 0+0978 <[^>]*> 410d7007 mftc0 t6,\$13,7=0A= 0+097c <[^>]*> 410d7010 mftr t5,t6,0,0,1=0A= 0+0980 <[^>]*> 410d7011 mftr t5,t6,0,1,1=0A= 0+0984 <[^>]*> 410d7012 mftr t5,t6,0,2,1=0A= 0+0988 <[^>]*> 410d7013 mftr t5,t6,0,3,1=0A= 0+098c <[^>]*> 410d7014 mftr t5,t6,0,4,1=0A= 0+0990 <[^>]*> 410d7015 mftr t5,t6,0,5,1=0A= 0+0994 <[^>]*> 410d7016 mftr t5,t6,0,6,1=0A= 0+0998 <[^>]*> 410d7017 mftr t5,t6,0,7,1=0A= 0+099c <[^>]*> 410d7000 mftc0 t6,c0_cause=0A= 0+09a0 <[^>]*> 410d7001 mftc0 t6,\$13,1=0A= 0+09a4 <[^>]*> 410d7002 mftc0 t6,\$13,2=0A= 0+09a8 <[^>]*> 410d7003 mftc0 t6,\$13,3=0A= 0+09ac <[^>]*> 410d7004 mftc0 t6,\$13,4=0A= 0+09b0 <[^>]*> 410d7005 mftc0 t6,\$13,5=0A= 0+09b4 <[^>]*> 410d7006 mftc0 t6,\$13,6=0A= 0+09b8 <[^>]*> 410d7007 mftc0 t6,\$13,7=0A= 0+09bc <[^>]*> 410d7030 mftr t5,t6,1,0,1=0A= 0+09c0 <[^>]*> 410d7031 mftr t5,t6,1,1,1=0A= 0+09c4 <[^>]*> 410d7032 mfthc1 t6,\$f13=0A= 0+09c8 <[^>]*> 410d7033 mftr t5,t6,1,3,1=0A= 0+09cc <[^>]*> 410d7034 mfthc2 t6,\$13=0A= 0+09d0 <[^>]*> 410d7035 mftr t5,t6,1,5,1=0A= 0+09d4 <[^>]*> 410d7036 mftr t5,t6,1,6,1=0A= 0+09d8 <[^>]*> 410d7037 mftr t5,t6,1,7,1=0A= 0+09dc <[^>]*> 410d7020 mftgpr t6,t5=0A= 0+09e0 <[^>]*> 410d7021 mfthi t6,\$ac3=0A= 0+09e4 <[^>]*> 410d7022 mftc1 t6,\$f13=0A= 0+09e8 <[^>]*> 410d7023 cftc1 t6,\$13=0A= 0+09ec <[^>]*> 410d7024 mftc2 t6,\$13=0A= 0+09f0 <[^>]*> 410d7025 cftc2 t6,\$13=0A= 0+09f4 <[^>]*> 410d7026 mftr t5,t6,1,6,0=0A= 0+09f8 <[^>]*> 410d7027 mftr t5,t6,1,7,0=0A= 0+09fc <[^>]*> 410d7030 mftr t5,t6,1,0,1=0A= 0+0a00 <[^>]*> 410d7031 mftr t5,t6,1,1,1=0A= 0+0a04 <[^>]*> 410d7032 mfthc1 t6,\$f13=0A= 0+0a08 <[^>]*> 410d7033 mftr t5,t6,1,3,1=0A= 0+0a0c <[^>]*> 410d7034 mfthc2 t6,\$13=0A= 0+0a10 <[^>]*> 410d7035 mftr t5,t6,1,5,1=0A= 0+0a14 <[^>]*> 410d7036 mftr t5,t6,1,6,1=0A= 0+0a18 <[^>]*> 410d7037 mftr t5,t6,1,7,1=0A= 0+0a1c <[^>]*> 410d7020 mftgpr t6,t5=0A= 0+0a20 <[^>]*> 410d7021 mfthi t6,\$ac3=0A= 0+0a24 <[^>]*> 410d7022 mftc1 t6,\$f13=0A= 0+0a28 <[^>]*> 410d7023 cftc1 t6,\$13=0A= 0+0a2c <[^>]*> 410d7024 mftc2 t6,\$13=0A= 0+0a30 <[^>]*> 410d7025 cftc2 t6,\$13=0A= 0+0a34 <[^>]*> 410d7026 mftr t5,t6,1,6,0=0A= 0+0a38 <[^>]*> 410d7027 mftr t5,t6,1,7,0=0A= 0+0a3c <[^>]*> 410d7010 mftr t5,t6,0,0,1=0A= 0+0a40 <[^>]*> 410d7011 mftr t5,t6,0,1,1=0A= 0+0a44 <[^>]*> 410d7012 mftr t5,t6,0,2,1=0A= 0+0a48 <[^>]*> 410d7013 mftr t5,t6,0,3,1=0A= 0+0a4c <[^>]*> 410d7014 mftr t5,t6,0,4,1=0A= 0+0a50 <[^>]*> 410d7015 mftr t5,t6,0,5,1=0A= 0+0a54 <[^>]*> 410d7016 mftr t5,t6,0,6,1=0A= 0+0a58 <[^>]*> 410d7017 mftr t5,t6,0,7,1=0A= 0+0a5c <[^>]*> 410d7000 mftc0 t6,c0_cause=0A= 0+0a60 <[^>]*> 410d7001 mftc0 t6,\$13,1=0A= 0+0a64 <[^>]*> 410d7002 mftc0 t6,\$13,2=0A= 0+0a68 <[^>]*> 410d7003 mftc0 t6,\$13,3=0A= 0+0a6c <[^>]*> 410d7004 mftc0 t6,\$13,4=0A= 0+0a70 <[^>]*> 410d7005 mftc0 t6,\$13,5=0A= 0+0a74 <[^>]*> 410d7006 mftc0 t6,\$13,6=0A= 0+0a78 <[^>]*> 410d7007 mftc0 t6,\$13,7=0A= 0+0a7c <[^>]*> 410d7010 mftr t5,t6,0,0,1=0A= 0+0a80 <[^>]*> 410d7011 mftr t5,t6,0,1,1=0A= 0+0a84 <[^>]*> 410d7012 mftr t5,t6,0,2,1=0A= 0+0a88 <[^>]*> 410d7013 mftr t5,t6,0,3,1=0A= 0+0a8c <[^>]*> 410d7014 mftr t5,t6,0,4,1=0A= 0+0a90 <[^>]*> 410d7015 mftr t5,t6,0,5,1=0A= 0+0a94 <[^>]*> 410d7016 mftr t5,t6,0,6,1=0A= 0+0a98 <[^>]*> 410d7017 mftr t5,t6,0,7,1=0A= 0+0a9c <[^>]*> 410d7000 mftc0 t6,c0_cause=0A= 0+0aa0 <[^>]*> 410d7001 mftc0 t6,\$13,1=0A= 0+0aa4 <[^>]*> 410d7002 mftc0 t6,\$13,2=0A= 0+0aa8 <[^>]*> 410d7003 mftc0 t6,\$13,3=0A= 0+0aac <[^>]*> 410d7004 mftc0 t6,\$13,4=0A= 0+0ab0 <[^>]*> 410d7005 mftc0 t6,\$13,5=0A= 0+0ab4 <[^>]*> 410d7006 mftc0 t6,\$13,6=0A= 0+0ab8 <[^>]*> 410d7007 mftc0 t6,\$13,7=0A= 0+0abc <[^>]*> 418d7030 mttr t5,t6,1,0,1=0A= 0+0ac0 <[^>]*> 418d7031 mttr t5,t6,1,1,1=0A= 0+0ac4 <[^>]*> 418d7032 mtthc1 t5,\$f14=0A= 0+0ac8 <[^>]*> 418d7033 mttr t5,t6,1,3,1=0A= 0+0acc <[^>]*> 418d7034 mtthc2 t5,\$14=0A= 0+0ad0 <[^>]*> 418d7035 mttr t5,t6,1,5,1=0A= 0+0ad4 <[^>]*> 418d7036 mttr t5,t6,1,6,1=0A= 0+0ad8 <[^>]*> 418d7037 mttr t5,t6,1,7,1=0A= 0+0adc <[^>]*> 418d7020 mttgpr t5,t6=0A= 0+0ae0 <[^>]*> 418d7021 mttacx t5,\$ac3=0A= 0+0ae4 <[^>]*> 418d7022 mttc1 t5,\$f14=0A= 0+0ae8 <[^>]*> 418d7023 cttc1 t5,\$14=0A= 0+0aec <[^>]*> 418d7024 mttc2 t5,\$14=0A= 0+0af0 <[^>]*> 418d7025 cttc2 t5,\$14=0A= 0+0af4 <[^>]*> 418d7026 mttr t5,t6,1,6,0=0A= 0+0af8 <[^>]*> 418d7027 mttr t5,t6,1,7,0=0A= 0+0afc <[^>]*> 418d7030 mttr t5,t6,1,0,1=0A= 0+0b00 <[^>]*> 418d7031 mttr t5,t6,1,1,1=0A= 0+0b04 <[^>]*> 418d7032 mtthc1 t5,\$f14=0A= 0+0b08 <[^>]*> 418d7033 mttr t5,t6,1,3,1=0A= 0+0b0c <[^>]*> 418d7034 mtthc2 t5,\$14=0A= 0+0b10 <[^>]*> 418d7035 mttr t5,t6,1,5,1=0A= 0+0b14 <[^>]*> 418d7036 mttr t5,t6,1,6,1=0A= 0+0b18 <[^>]*> 418d7037 mttr t5,t6,1,7,1=0A= 0+0b1c <[^>]*> 418d7020 mttgpr t5,t6=0A= 0+0b20 <[^>]*> 418d7021 mttacx t5,\$ac3=0A= 0+0b24 <[^>]*> 418d7022 mttc1 t5,\$f14=0A= 0+0b28 <[^>]*> 418d7023 cttc1 t5,\$14=0A= 0+0b2c <[^>]*> 418d7024 mttc2 t5,\$14=0A= 0+0b30 <[^>]*> 418d7025 cttc2 t5,\$14=0A= 0+0b34 <[^>]*> 418d7026 mttr t5,t6,1,6,0=0A= 0+0b38 <[^>]*> 418d7027 mttr t5,t6,1,7,0=0A= 0+0b3c <[^>]*> 418d7010 mttr t5,t6,0,0,1=0A= 0+0b40 <[^>]*> 418d7011 mttr t5,t6,0,1,1=0A= 0+0b44 <[^>]*> 418d7012 mttr t5,t6,0,2,1=0A= 0+0b48 <[^>]*> 418d7013 mttr t5,t6,0,3,1=0A= 0+0b4c <[^>]*> 418d7014 mttr t5,t6,0,4,1=0A= 0+0b50 <[^>]*> 418d7015 mttr t5,t6,0,5,1=0A= 0+0b54 <[^>]*> 418d7016 mttr t5,t6,0,6,1=0A= 0+0b58 <[^>]*> 418d7017 mttr t5,t6,0,7,1=0A= 0+0b5c <[^>]*> 418d7000 mttc0 t5,c0_epc=0A= 0+0b60 <[^>]*> 418d7001 mttc0 t5,\$14,1=0A= 0+0b64 <[^>]*> 418d7002 mttc0 t5,\$14,2=0A= 0+0b68 <[^>]*> 418d7003 mttc0 t5,\$14,3=0A= 0+0b6c <[^>]*> 418d7004 mttc0 t5,\$14,4=0A= 0+0b70 <[^>]*> 418d7005 mttc0 t5,\$14,5=0A= 0+0b74 <[^>]*> 418d7006 mttc0 t5,\$14,6=0A= 0+0b78 <[^>]*> 418d7007 mttc0 t5,\$14,7=0A= 0+0b7c <[^>]*> 418d7010 mttr t5,t6,0,0,1=0A= 0+0b80 <[^>]*> 418d7011 mttr t5,t6,0,1,1=0A= 0+0b84 <[^>]*> 418d7012 mttr t5,t6,0,2,1=0A= 0+0b88 <[^>]*> 418d7013 mttr t5,t6,0,3,1=0A= 0+0b8c <[^>]*> 418d7014 mttr t5,t6,0,4,1=0A= 0+0b90 <[^>]*> 418d7015 mttr t5,t6,0,5,1=0A= 0+0b94 <[^>]*> 418d7016 mttr t5,t6,0,6,1=0A= 0+0b98 <[^>]*> 418d7017 mttr t5,t6,0,7,1=0A= 0+0b9c <[^>]*> 418d7000 mttc0 t5,c0_epc=0A= 0+0ba0 <[^>]*> 418d7001 mttc0 t5,\$14,1=0A= 0+0ba4 <[^>]*> 418d7002 mttc0 t5,\$14,2=0A= 0+0ba8 <[^>]*> 418d7003 mttc0 t5,\$14,3=0A= 0+0bac <[^>]*> 418d7004 mttc0 t5,\$14,4=0A= 0+0bb0 <[^>]*> 418d7005 mttc0 t5,\$14,5=0A= 0+0bb4 <[^>]*> 418d7006 mttc0 t5,\$14,6=0A= 0+0bb8 <[^>]*> 418d7007 mttc0 t5,\$14,7=0A= 0+0bbc <[^>]*> 418d7030 mttr t5,t6,1,0,1=0A= 0+0bc0 <[^>]*> 418d7031 mttr t5,t6,1,1,1=0A= 0+0bc4 <[^>]*> 418d7032 mtthc1 t5,\$f14=0A= 0+0bc8 <[^>]*> 418d7033 mttr t5,t6,1,3,1=0A= 0+0bcc <[^>]*> 418d7034 mtthc2 t5,\$14=0A= 0+0bd0 <[^>]*> 418d7035 mttr t5,t6,1,5,1=0A= 0+0bd4 <[^>]*> 418d7036 mttr t5,t6,1,6,1=0A= 0+0bd8 <[^>]*> 418d7037 mttr t5,t6,1,7,1=0A= 0+0bdc <[^>]*> 418d7020 mttgpr t5,t6=0A= 0+0be0 <[^>]*> 418d7021 mttacx t5,\$ac3=0A= 0+0be4 <[^>]*> 418d7022 mttc1 t5,\$f14=0A= 0+0be8 <[^>]*> 418d7023 cttc1 t5,\$14=0A= 0+0bec <[^>]*> 418d7024 mttc2 t5,\$14=0A= 0+0bf0 <[^>]*> 418d7025 cttc2 t5,\$14=0A= 0+0bf4 <[^>]*> 418d7026 mttr t5,t6,1,6,0=0A= 0+0bf8 <[^>]*> 418d7027 mttr t5,t6,1,7,0=0A= 0+0bfc <[^>]*> 418d7030 mttr t5,t6,1,0,1=0A= 0+0c00 <[^>]*> 418d7031 mttr t5,t6,1,1,1=0A= 0+0c04 <[^>]*> 418d7032 mtthc1 t5,\$f14=0A= 0+0c08 <[^>]*> 418d7033 mttr t5,t6,1,3,1=0A= 0+0c0c <[^>]*> 418d7034 mtthc2 t5,\$14=0A= 0+0c10 <[^>]*> 418d7035 mttr t5,t6,1,5,1=0A= 0+0c14 <[^>]*> 418d7036 mttr t5,t6,1,6,1=0A= 0+0c18 <[^>]*> 418d7037 mttr t5,t6,1,7,1=0A= 0+0c1c <[^>]*> 418d7020 mttgpr t5,t6=0A= 0+0c20 <[^>]*> 418d7021 mttacx t5,\$ac3=0A= 0+0c24 <[^>]*> 418d7022 mttc1 t5,\$f14=0A= 0+0c28 <[^>]*> 418d7023 cttc1 t5,\$14=0A= 0+0c2c <[^>]*> 418d7024 mttc2 t5,\$14=0A= 0+0c30 <[^>]*> 418d7025 cttc2 t5,\$14=0A= 0+0c34 <[^>]*> 418d7026 mttr t5,t6,1,6,0=0A= 0+0c38 <[^>]*> 418d7027 mttr t5,t6,1,7,0=0A= 0+0c3c <[^>]*> 418d7010 mttr t5,t6,0,0,1=0A= 0+0c40 <[^>]*> 418d7011 mttr t5,t6,0,1,1=0A= 0+0c44 <[^>]*> 418d7012 mttr t5,t6,0,2,1=0A= 0+0c48 <[^>]*> 418d7013 mttr t5,t6,0,3,1=0A= 0+0c4c <[^>]*> 418d7014 mttr t5,t6,0,4,1=0A= 0+0c50 <[^>]*> 418d7015 mttr t5,t6,0,5,1=0A= 0+0c54 <[^>]*> 418d7016 mttr t5,t6,0,6,1=0A= 0+0c58 <[^>]*> 418d7017 mttr t5,t6,0,7,1=0A= 0+0c5c <[^>]*> 418d7000 mttc0 t5,c0_epc=0A= 0+0c60 <[^>]*> 418d7001 mttc0 t5,\$14,1=0A= 0+0c64 <[^>]*> 418d7002 mttc0 t5,\$14,2=0A= 0+0c68 <[^>]*> 418d7003 mttc0 t5,\$14,3=0A= 0+0c6c <[^>]*> 418d7004 mttc0 t5,\$14,4=0A= 0+0c70 <[^>]*> 418d7005 mttc0 t5,\$14,5=0A= 0+0c74 <[^>]*> 418d7006 mttc0 t5,\$14,6=0A= 0+0c78 <[^>]*> 418d7007 mttc0 t5,\$14,7=0A= 0+0c7c <[^>]*> 418d7010 mttr t5,t6,0,0,1=0A= 0+0c80 <[^>]*> 418d7011 mttr t5,t6,0,1,1=0A= 0+0c84 <[^>]*> 418d7012 mttr t5,t6,0,2,1=0A= 0+0c88 <[^>]*> 418d7013 mttr t5,t6,0,3,1=0A= 0+0c8c <[^>]*> 418d7014 mttr t5,t6,0,4,1=0A= 0+0c90 <[^>]*> 418d7015 mttr t5,t6,0,5,1=0A= 0+0c94 <[^>]*> 418d7016 mttr t5,t6,0,6,1=0A= 0+0c98 <[^>]*> 418d7017 mttr t5,t6,0,7,1=0A= 0+0c9c <[^>]*> 418d7000 mttc0 t5,c0_epc=0A= 0+0ca0 <[^>]*> 418d7001 mttc0 t5,\$14,1=0A= 0+0ca4 <[^>]*> 418d7002 mttc0 t5,\$14,2=0A= 0+0ca8 <[^>]*> 418d7003 mttc0 t5,\$14,3=0A= 0+0cac <[^>]*> 418d7004 mttc0 t5,\$14,4=0A= 0+0cb0 <[^>]*> 418d7005 mttc0 t5,\$14,5=0A= 0+0cb4 <[^>]*> 418d7006 mttc0 t5,\$14,6=0A= 0+0cb8 <[^>]*> 418d7007 mttc0 t5,\$14,7=0A= ...=0A= ------=_NextPart_000_001E_01C5ACB5.DBFB3A60--