From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 7838 invoked by alias); 6 Jan 2005 11:28:11 -0000 Mailing-List: contact binutils-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sources.redhat.com Received: (qmail 7738 invoked from network); 6 Jan 2005 11:28:02 -0000 Received: from unknown (HELO lon-del-01.spheriq.net) (195.46.50.97) by sourceware.org with SMTP; 6 Jan 2005 11:28:02 -0000 Received: from lon-inc-06.spheriq.net ([195.46.50.70]) by lon-del-01.spheriq.net with ESMTP id j06BRwwO002440 for ; Thu, 6 Jan 2005 11:27:58 GMT Received: from lon-out-02.spheriq.net (lon-out-02.spheriq.net [195.46.50.130]) by lon-inc-06.spheriq.net with ESMTP id j06BRwws006952 for ; Thu, 6 Jan 2005 11:27:58 GMT Received: from lon-cus-02.spheriq.net (lon-cus-02.spheriq.net [195.46.50.38]) by lon-out-02.spheriq.net with ESMTP id j06BRuNX018587 for ; Thu, 6 Jan 2005 11:27:57 GMT Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by lon-cus-02.spheriq.net with ESMTP id j06BRtsV010545 (version=TLSv1/SSLv3 cipher=EDH-RSA-DES-CBC3-SHA bits=168 verify=OK); Thu, 6 Jan 2005 11:27:56 GMT Received: from zeta.dmz-eu.st.com (ns2.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 5C0D8DA41; Thu, 6 Jan 2005 11:27:55 +0000 (GMT) Received: by zeta.dmz-eu.st.com (STMicroelectronics, from userid 60012) id D03BF471CA; Thu, 6 Jan 2005 11:28:32 +0000 (GMT) Received: from zeta.dmz-eu.st.com (localhost [127.0.0.1]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A72147599B; Thu, 6 Jan 2005 11:28:32 +0000 (UTC) Received: from mail1.bri.st.com (mail1.bri.st.com [164.129.8.218]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id B1772471B9; Thu, 6 Jan 2005 11:28:31 +0000 (GMT) Received: from terrorhawk (terrorhawk.bri.st.com [164.129.15.13]) by mail1.bri.st.com (MOS 3.4.4-GR) with ESMTP id ARW00882 (AUTH "andrew stubbs"); Thu, 6 Jan 2005 11:27:52 GMT From: Andrew STUBBS To: "'Nick Clifton'" Cc: "'Alexandre Oliva'" , , "'Joern RENNECKE'" Subject: RE: Broken SH2a patches Date: Thu, 06 Jan 2005 11:28:00 -0000 Organization: STMicroelectronics Message-ID: <017c01c4f3e2$ecb09350$0d0f81a4@uk.w2k.superh.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable In-Reply-To: <41C70ABC.8050903@redhat.com> X-O-Virus-Status: No X-O-URL-Status: Not Scanned X-O-CSpam-Status: Not Scanned X-O-Spam-Status: Not scanned X-O-Image-Status: Not Scanned X-O-Att-Status: No X-SpheriQ-Ver: 1.8.3 X-SW-Source: 2005-01/txt/msg00058.txt.bz2 There appears to be another mistake in the inheritance. The SH4 descends from the SH2A-nofpu which can't be right. Here is a corrected tree: SH1 | SH2 .------------'|`--------------------------------. / | \ SH-DSP SH3-nommu/SH2A-nofpu SH2E | | |`--------------------. | | | | \| | SH3-nommu SH4-nm-nf/SH2A-nofpu SH3E/SH2A | |\ | | | | | | `------. | SH2A-nofpu | SH4/SH2A | | \| \ | | | | SH3 SH4-nommu-nofpu `---------+--. | | | /|\ | | \| | | .-----------' | `--------+---------------------. | SH2A | |/ | / \| | | | .-------' | | | |/ | | SH3-dsp SH4-nofpu SH3E | | |`-------------------------------. | .-----' | | \|/ | SH4A-nofpu SH4 | .------------' `-------------------------------. | |/ \| SH4AL-dsp SH4A */ /* Central branches. */ #define arch_sh1_up (arch_sh1 \ | arch_sh2_up) #define arch_sh2_up (arch_sh2 \ | arch_sh2e_up \ | arch_sh2a_nofpu_or_sh3_nommu_up \ | arch_sh_dsp_up) #define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \ | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \ | arch_sh2a_or_sh3e_up \ | arch_sh3_nommu_up) #define arch_sh2a_nofpu_or_sh4_nommu_nofpu_up (arch_sh2a_nofpu_or_sh4_nommu_nofpu \ | arch_sh2a_nofpu_up \ | arch_sh4_nommu_nofpu_up) #define arch_sh2a_nofpu_up (arch_sh2a_nofpu \ | arch_sh2a_up) #define arch_sh3_nommu_up (arch_sh3_nommu \ | arch_sh3_up \ | arch_sh4_nommu_nofpu_up) #define arch_sh3_up (arch_sh3 \ | arch_sh3e_up \ | arch_sh3_dsp_up \ | arch_sh4_nofp_up) #define arch_sh4_nommu_nofpu_up (arch_sh4_nommu_nofpu \ | arch_sh4_nofp_up) #define arch_sh4_nofp_up (arch_sh4_nofpu \ | arch_sh4_up \ | arch_sh4a_nofp_up) #define arch_sh4a_nofp_up (arch_sh4a_nofpu \ | arch_sh4a_up \ | arch_sh4al_dsp_up) /* Right branches. */ #define arch_sh2e_up (arch_sh2e \ | arch_sh2a_or_sh3e_up) #define arch_sh2a_or_sh3e_up (arch_sh2a_or_sh3e \ | arch_sh2a_or_sh4_up \ | arch_sh3e_up) #define arch_sh2a_or_sh4_up (arch_sh2a_or_sh4 \ | arch_sh2a_up \ | arch_sh4_up) #define arch_sh2a_up (arch_sh2a) #define arch_sh3e_up (arch_sh3e \ | arch_sh4_up) #define arch_sh4_up (arch_sh4 \ | arch_sh4a_up) #define arch_sh4a_up (arch_sh4a) /* Left branch. */ #define arch_sh_dsp_up (arch_sh_dsp \ | arch_sh3_dsp_up) #define arch_sh3_dsp_up (arch_sh3_dsp \ | arch_sh4al_dsp_up) #define arch_sh4al_dsp_up (arch_sh4al_dsp) -- Andrew Stubbs andrew.stubbs@st.com andrew.stubbs@superh.com