* Broken SH2a patches @ 2004-10-13 17:00 Andrew STUBBS 2004-10-28 20:33 ` Alexandre Oliva 0 siblings, 1 reply; 26+ messages in thread From: Andrew STUBBS @ 2004-10-13 17:00 UTC (permalink / raw) To: 'Alexandre Oliva'; +Cc: binutils Hi Alexandre, A (long) while back you send this message: http://sources.redhat.com/ml/binutils/2004-07/msg00439.html Have you made any progress with this problem yet? It would be better if this were fixed before a numbered release is made. Thanks -- Andrew Stubbs STMicroelectronics ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Broken SH2a patches 2004-10-13 17:00 Broken SH2a patches Andrew STUBBS @ 2004-10-28 20:33 ` Alexandre Oliva 2004-10-29 10:39 ` Nick Clifton 0 siblings, 1 reply; 26+ messages in thread From: Alexandre Oliva @ 2004-10-28 20:33 UTC (permalink / raw) To: Andrew STUBBS, nickc; +Cc: binutils On Oct 13, 2004, Andrew STUBBS <andrew.stubbs@st.com> wrote: > Hi Alexandre, > A (long) while back you send this message: > http://sources.redhat.com/ml/binutils/2004-07/msg00439.html > Have you made any progress with this problem yet? Erhm... Sort of. I got Nick to promise to look into the issues, and then didn't worry about them any more. Nick, I take it that you didn't make any progress on them? -- Alexandre Oliva http://www.ic.unicamp.br/~oliva/ Red Hat Compiler Engineer aoliva@{redhat.com, gcc.gnu.org} Free Software Evangelist oliva@{lsd.ic.unicamp.br, gnu.org} ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Broken SH2a patches 2004-10-28 20:33 ` Alexandre Oliva @ 2004-10-29 10:39 ` Nick Clifton 2004-10-29 12:11 ` Andrew STUBBS 0 siblings, 1 reply; 26+ messages in thread From: Nick Clifton @ 2004-10-29 10:39 UTC (permalink / raw) To: Alexandre Oliva; +Cc: Andrew STUBBS, binutils Hi Alex, Hi Andrew, >>Hi Alexandre, >>A (long) while back you send this message: >>http://sources.redhat.com/ml/binutils/2004-07/msg00439.html >>Have you made any progress with this problem yet? > Erhm... Sort of. I got Nick to promise to look into the issues, and > then didn't worry about them any more. Err, you did ? It must have been while I was drunk... > Nick, I take it that you didn't make any progress on them? That would be correct. Anyway as I understand it the problem is that the inheritance tree in sh-opc.h does not include the SH2A, right ? Judging from Alex's and Andrew's comments there are two possible fixes for this, a simple one that just adds the SH2A-nofpu and SH2A inheritance off the SH2E: ----------------------------------------------------------------------- /* Below are the 'architecture sets'. They describe the following inheritance graph: SH1 | SH2 .------------'|`--------------------. / | \ SH-DSP SH3-nommu SH2E | |`--------. |`--------. | | \ | \ | SH3 SH4-nommu-nofpu | | | | | | | | .------------'|`----------+---------. | | |/ / \| | | | .-------' | | | |/ | | SH3-dsp SH4-nofpu SH3E SH2A-nofpu | |`--------------------. | | | | \| | | SH4A-nofpu SH4 SH2A | .------------' `--------------------. | |/ \| SH4AL-dsp SH4A ------------------------------------------------------------------------- And a complex one that invents a fake intermediate architecture to show the fact that the SH4, SH4A and SH2A share some instructions. To my mind however there is no satisfactory way of showing this, and instead I would like to suggest using a dotted line to show partial inheritance: ------------------------------------------------------------------------- /* Below are the 'architecture sets'. They describe the following inheritance graph: (The .... between SH4A and SH2A-nofpu is a partial inheritance). SH1 | SH2 .------------'|`--------------------. / | \ SH-DSP SH3-nommu SH2E | |`--------. |`------. | | \ | \ | SH3 SH4-nommu-nofpu | | | | | | | | .------------'|`----------+---------. | | |/ / \| | | | .-------' | | | |/ | | SH3-dsp SH4-nofpu SH3E | | |`--------------------. | | | | \| | | SH4A-nofpu SH4 | | .------------' `--------------------. | | |/ \| | SH4AL-dsp SH4A | . | ......... | . | SH2A-no-fpu | SH2A ----------------------------------------------------------------------- What do you think ? Cheers Nick ^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: Broken SH2a patches 2004-10-29 10:39 ` Nick Clifton @ 2004-10-29 12:11 ` Andrew STUBBS 2004-10-29 12:28 ` [OT] " Dave Korn ` (2 more replies) 0 siblings, 3 replies; 26+ messages in thread From: Andrew STUBBS @ 2004-10-29 12:11 UTC (permalink / raw) To: 'Nick Clifton', 'Alexandre Oliva'; +Cc: binutils > > Nick, I take it that you didn't make any progress on them? > > That would be correct. > > Anyway as I understand it the problem is that the inheritance tree in > sh-opc.h does not include the SH2A, right ? Judging from Alex's and > Andrew's comments there are two possible fixes for this, a simple one > that just adds the SH2A-nofpu and SH2A inheritance off the SH2E: > -------------------------------------------------------------- > --------- > /* Below are the 'architecture sets'. > They describe the following inheritance graph: > > SH1 > | > SH2 > .------------'|`--------------------. > / | \ > SH-DSP SH3-nommu SH2E > | |`--------. |`--------. > | | \ | \ > | SH3 SH4-nommu-nofpu | | > | | | | | > | .------------'|`----------+---------. | | > |/ / \| | > | | .-------' | | > | |/ | | > SH3-dsp SH4-nofpu SH3E SH2A-nofpu > | |`--------------------. | | > | | \| | > | SH4A-nofpu SH4 SH2A > | .------------' `--------------------. | > |/ \| > SH4AL-dsp SH4A > -------------------------------------------------------------- No. This is wrong. There is _no_way_ a no-fpu variant can descend from an fpu variant - it would inherit the fpu! > And a complex one that invents a fake intermediate > architecture to show > the fact that the SH4, SH4A and SH2A share some instructions. To my > mind however there is no satisfactory way of showing this, > and instead I > would like to suggest using a dotted line to show partial inheritance: > -------------------------------------------------------------- > ----------- > /* Below are the 'architecture sets'. > They describe the following inheritance graph: > (The .... between SH4A and SH2A-nofpu is a partial inheritance). > > SH1 > | > SH2 > .------------'|`--------------------. > / | \ > SH-DSP SH3-nommu SH2E > | |`--------. |`------. > | | \ | \ > | SH3 SH4-nommu-nofpu | | > | | | | | > | .------------'|`----------+---------. | | > |/ / \| | > | | .-------' | | > | |/ | | > SH3-dsp SH4-nofpu SH3E | > | |`--------------------. | | > | | \| | > | SH4A-nofpu SH4 | > | .------------' `--------------------. | | > |/ \| | > SH4AL-dsp SH4A | > . | > ......... | > . | > SH2A-no-fpu > | > SH2A > -------------------------------------------------------------- I agree that there may be some problem inserting it into the diagram, but the important ting is that it must be inserted into the inheritance tree in the code and that the |s (ors) are removed from the instruction table (the op32 stuff may be ok, but the others have to go). Each and every instruction has to be introduced in one single architecture (albeit imaginary) and then be inherited by each and every one of its descendents. If this condition is not met then the algorithms in cpu-sh.c won't work and you find yourself forced to use the --isa option to sort out the mess. With the |s in place as they are the assembler _may_ work ok, but when it comes to save the file it has to translate that into an elf flag. When there are actually two architectures chosen (using | in the opcode table) then it can only choose one and the other information is lost. Therefore, when the file is loaded, the linker will not believe that it can link it against half the architectures it actually could link against. This is why you are forced to tell it which half manually using the -isa option. So lets consider the rules as I understand them (I haven't examined the opcodes table too carefully - this is just a thought experiment): - The sh2a_nofpu contains everything in sh2, some things from sh3_nommu, and some things of its own: SH2 | SH2A-nofpu-1 | \ SH3-nommu SH2A-nofpu - The sh2a contains everything from sh2a_nofpu, some things from sh3e, some things from sh4 and some things of its own: SH2A-nofpu | `--. SH2A-1 SH2A-2 | \ / | SH3E SH2A | | | `----. .----' SH4 I have omitted the SH3-* and SH4-* intermediates but you get the idea (you will need to consider if there any clashes with those as well). The SH2A-*-[12] variants contain those instructions which are present in both descendents - i.e. they are the common ancestor to which those instructions can be traced. I do not claim that the rules above are actually correct - I have gleaned them from memory of emails rather than solid facts - nor am I suggesting that the intermediate names are suitable. These are intended as a tutorial only. My other concern is the arch_op32 thingy. I don't know what it is for, or what the affect on the architecture code is, but you should be aware that it will not be encoded into the elf flags and, therefore, will not be available at link time. If it is only intended to be for the assembler then it may be ok. Once this is done you should create a small assembler file for each architecture the assembler and linker can produce (fake or real - they will all need elf codes assigned) and put it in the 'arch' testsuite directory (there is one under both the assembler and linker). If the architecture permutation test script produces the correct result then you know you have done the job right (but it will take some manual effort to verify the results first time). I hope that helps. I have tried to make sense but it isn't easy. It would be much easier if we forced the people who invented the SH family to maintain this themselves - sort of like house training. It does demonstrate why the old merge macro was doomed to failure. Good luck -- Andrew Stubbs andrew.stubbs@st.com andrew.stubbs@superh.com ^ permalink raw reply [flat|nested] 26+ messages in thread
* [OT] RE: Broken SH2a patches 2004-10-29 12:11 ` Andrew STUBBS @ 2004-10-29 12:28 ` Dave Korn 2004-10-29 12:59 ` Andrew STUBBS 2004-10-29 13:59 ` Ian Lance Taylor 2004-11-08 9:04 ` Nick Clifton 2 siblings, 1 reply; 26+ messages in thread From: Dave Korn @ 2004-10-29 12:28 UTC (permalink / raw) To: binutils > -----Original Message----- > From: binutils-owner On Behalf Of Andrew STUBBS > Sent: 29 October 2004 13:13 > No. This is wrong. There is _no_way_ a no-fpu variant can > descend from an fpu variant - it would inherit the fpu! Homo Sapiens descended from apes, but we no longer have tails! cheers, DaveK -- Can't think of a witty .sigline today.... ^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: [OT] RE: Broken SH2a patches 2004-10-29 12:28 ` [OT] " Dave Korn @ 2004-10-29 12:59 ` Andrew STUBBS 2004-10-29 13:03 ` Dave Korn 0 siblings, 1 reply; 26+ messages in thread From: Andrew STUBBS @ 2004-10-29 12:59 UTC (permalink / raw) To: 'Dave Korn', binutils > > No. This is wrong. There is _no_way_ a no-fpu variant can > > descend from an fpu variant - it would inherit the fpu! > > > Homo Sapiens descended from apes, but we no longer have tails! Apes don't have tails. ^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: [OT] RE: Broken SH2a patches 2004-10-29 12:59 ` Andrew STUBBS @ 2004-10-29 13:03 ` Dave Korn 2004-10-29 13:21 ` Andrew STUBBS 0 siblings, 1 reply; 26+ messages in thread From: Dave Korn @ 2004-10-29 13:03 UTC (permalink / raw) To: binutils > -----Original Message----- > From: Andrew STUBBS > Sent: 29 October 2004 14:01 > To: 'Dave Korn'; binutils > Subject: RE: [OT] RE: Broken SH2a patches > > > > No. This is wrong. There is _no_way_ a no-fpu variant can > > > descend from an fpu variant - it would inherit the fpu! > > > > > > Homo Sapiens descended from apes, but we no longer have tails! > > Apes don't have tails. > Ok, Ok. Let me re-word that: Homo Sapiens descended from apes, which descended from monkeys, but we no longer have tails! Is that better? The point that things that are inherited can also be not-inherited remains valid. cheers, DaveK -- Can't think of a witty .sigline today.... ^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: [OT] RE: Broken SH2a patches 2004-10-29 13:03 ` Dave Korn @ 2004-10-29 13:21 ` Andrew STUBBS 0 siblings, 0 replies; 26+ messages in thread From: Andrew STUBBS @ 2004-10-29 13:21 UTC (permalink / raw) To: 'Dave Korn', binutils > > > > No. This is wrong. There is _no_way_ a no-fpu variant > can descend > > > > from an fpu variant - it would inherit the fpu! > > > > > > > > > Homo Sapiens descended from apes, but we no longer have tails! > > > > Apes don't have tails. > > > > Ok, Ok. Let me re-word that: > > Homo Sapiens descended from apes, which descended from > monkeys, but we no longer have tails! > > Is that better? > > The point that things that are inherited can also be not-inherited > remains valid. I suppose that if we tried to represent this in C++ classes we would still end up with a vestigial tail - much like Homo Sapiens. My original point was that non-inheritance is not allowed in this case. It would rather defeat the object. Much like paleontologists, when a processor is unearthed with fuzzy parentage we can invent a missing link. One day we may even find one of them! Andrew ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Broken SH2a patches 2004-10-29 12:11 ` Andrew STUBBS 2004-10-29 12:28 ` [OT] " Dave Korn @ 2004-10-29 13:59 ` Ian Lance Taylor 2004-10-29 14:35 ` Andrew STUBBS 2004-11-08 9:04 ` Nick Clifton 2 siblings, 1 reply; 26+ messages in thread From: Ian Lance Taylor @ 2004-10-29 13:59 UTC (permalink / raw) To: Andrew STUBBS; +Cc: 'Nick Clifton', 'Alexandre Oliva', binutils Andrew STUBBS <andrew.stubbs@st.com> writes: > Each and every instruction has to be introduced in one single architecture > (albeit imaginary) and then be inherited by each and every one of its > descendents. If this condition is not met then the algorithms in cpu-sh.c > won't work and you find yourself forced to use the --isa option to sort out > the mess. > > With the |s in place as they are the assembler _may_ work ok, but when it > comes to save the file it has to translate that into an elf flag. When there > are actually two architectures chosen (using | in the opcode table) then it > can only choose one and the other information is lost. Therefore, when the > file is loaded, the linker will not believe that it can link it against half > the architectures it actually could link against. This is why you are forced > to tell it which half manually using the -isa option. To make this work, it sounds like you will need to change the ELF header flags, and thus will lose some degree of backward compatibility. If you have to do that anyhow, why not change the ELF flags to more appropriately reflect the situation? Instead of trying to represent all information with a single processor field, partition the instruction set into groups, and use bitfields to indicate which groups are represented in the object file. It would probably be appropriate to continue to have a processor field, to capture certain large groups in a single number. Then add a bit for, e.g., FPU instructions. I don't know how the SH architecture has evolved. Would this sort of approach be possible? Ian ^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: Broken SH2a patches 2004-10-29 13:59 ` Ian Lance Taylor @ 2004-10-29 14:35 ` Andrew STUBBS 2004-10-29 14:58 ` Ian Lance Taylor 0 siblings, 1 reply; 26+ messages in thread From: Andrew STUBBS @ 2004-10-29 14:35 UTC (permalink / raw) To: 'Ian Lance Taylor' Cc: 'Nick Clifton', 'Alexandre Oliva', binutils > To make this work, it sounds like you will need to change the > ELF header flags, and thus will lose some degree of backward > compatibility. If you have to do that anyhow, why not change > the ELF flags to more appropriately reflect the situation? > Instead of trying to represent all information with a single > processor field, partition the instruction set into groups, > and use bitfields to indicate which groups are represented in > the object file. It would probably be appropriate to > continue to have a processor field, to capture certain large > groups in a single number. Then add a bit for, e.g., FPU > instructions. > > I don't know how the SH architecture has evolved. Would this > sort of approach be possible? The way you describe is, more or less what we used to have. The problem was that the range of architectures outgrew the representation. It became impossible to insert new architectures with less features than older ones because there were no numbers in the correct range left. Simultaneously, the internal representation, in which each architecture had its own bit in an integer, was extending at an unsustainable rate (given that each new variant may also come with nofpu, nommu, nofpu-nommu, and dsp variants). Therefore, about six months ago now IIRC, we did an overhaul of the way the architecture detection and recording worked. The values of the pre-existing elf flags have not changed, but newer architectures no longer follow the same conventions as the old - i.e. there is no longer any significance to the value beyond its being a reference into a table. This change meant that older tools might make incorrect assumptions about files created for new architectures, but newer tools are totally backward compatible. The internal representation, used by the assembler and linker etc., now has a set of flags denoting what features are available, much as you suggest. This representation is entirely internal to the code so there can never be any compatibility issues. In the course of this work the inheritance tree was properly updated and, as a result, the sh3-nommu imaginary architecture invented - it was a missing link in the hierarchy. This system already did work. It is just the new SH2A architecture patches which have broken it. The algorithm for determining what the most general architecture a file will execute on, based on the instruction used within that file, requires that individual instructions are only introduced to the inheritance graph in one place, and that once introduced they do not disappear from the descendents. It is difficult to think of any general algorithm that can cope with any other arrangement. The main problem is that, because the system is so new, the only people who currently have much experience with the stuff is Joern and myself. It might have been easier if the next architecture to come along had not been such an evil mix of all the others. -- Andrew Stubbs andrew.stubbs@st.com andrew.stubbs@superh.com ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Broken SH2a patches 2004-10-29 14:35 ` Andrew STUBBS @ 2004-10-29 14:58 ` Ian Lance Taylor 2004-10-29 15:44 ` Andrew STUBBS 0 siblings, 1 reply; 26+ messages in thread From: Ian Lance Taylor @ 2004-10-29 14:58 UTC (permalink / raw) To: Andrew STUBBS; +Cc: 'Nick Clifton', 'Alexandre Oliva', binutils Andrew STUBBS <andrew.stubbs@st.com> writes: > The way you describe is, more or less what we used to have. I see. Thanks. > This system already did work. It is just the new SH2A architecture patches > which have broken it. The algorithm for determining what the most general > architecture a file will execute on, based on the instruction used within > that file, requires that individual instructions are only introduced to the > inheritance graph in one place, and that once introduced they do not > disappear from the descendents. It is difficult to think of any general > algorithm that can cope with any other arrangement. That's a tough restriction to impose, though. In my experience new variants of processors do borrow instructions from one another. Requiring that each instruction be a member of a (possibly pseudo) processor which is an ancestor of each processor which implements that instruction is likely to be quite difficult going forward. As new processors come out, you will have to reshuffle the graph, introducing new pseudo parent processors. I gather that the goal is to precisely identify which processors may execute a specific executable, based on the set of instructions which appear in that executable. Is having that precise information especially useful for users in practice? Would users be OK with knowing "this was compiled for chip X, and will run on any chip which supports this minimal ABI" even if it might run on some other chips also? Ian ^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: Broken SH2a patches 2004-10-29 14:58 ` Ian Lance Taylor @ 2004-10-29 15:44 ` Andrew STUBBS 0 siblings, 0 replies; 26+ messages in thread From: Andrew STUBBS @ 2004-10-29 15:44 UTC (permalink / raw) To: 'Ian Lance Taylor' Cc: 'Nick Clifton', 'Alexandre Oliva', binutils > That's a tough restriction to impose, though. In my > experience new variants of processors do borrow instructions > from one another. Requiring that each instruction be a member > of a (possibly pseudo) processor which is an ancestor of each > processor which implements that instruction is likely to be > quite difficult going forward. As new processors come out, > you will have to reshuffle the graph, introducing new pseudo > parent processors. That's the plan. So far it has been workable. The SH2A shouldn't be a problem with proper thought. It is conceivable that a change might occur that is so horrible that we have to think about something else in future, but the previous changes to the elf flags mean that such a reorganisation ought to be totally internal and transparent to the user. > I gather that the goal is to precisely identify which > processors may execute a specific executable, based on the > set of instructions which appear in that executable. Is > having that precise information especially useful for users > in practice? Would users be OK with knowing "this was > compiled for chip X, and will run on any chip which supports > this minimal ABI" even if it might run on some other chips also? The main reason for doing this is that it is the way it has always been done. Another reason is that, if the assembler does not infer the architecture from the contents then how does it know. The only other possibility is that the user always specify the architecture explicitly, or implicitly by means of a default. This may be ok when you consider that this is already true for the compiler. The assembler does have such an option, but traditionally it has only been used to ensure the correct relaxation optimisations were performed. Until my patch, this option did not even allow most architecture variants - only those that had been interesting to somebody or other down the years. There is a similar problem with the linker. Given that different architecture files _can_ be linked together the linker must have some technique for identifying the output architecture. Of course, if this were banned there would be no issue. However there is one major application: The gcc/newlib multilibs are shared for the various processors that are the same to the compiler (and share the same ABI) using the MULTILIB_MATCHES mechanism. The libraries are assigned the most general architecture, but are linkable against all the descendent, more specific, architectures. (Aside: Ideally I would like the linker to be able to identify and reject incompatible ABIs, but at present this is not checked). When you consider that SH users are used to it as is, I think that there are more reasons to leave it alone than change it. I hope this answers your question. -- Andrew Stubbs andrew.stubbs@st.com andrew.stubbs@superh.com ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Broken SH2a patches 2004-10-29 12:11 ` Andrew STUBBS 2004-10-29 12:28 ` [OT] " Dave Korn 2004-10-29 13:59 ` Ian Lance Taylor @ 2004-11-08 9:04 ` Nick Clifton 2004-11-08 15:12 ` Andrew STUBBS 2 siblings, 1 reply; 26+ messages in thread From: Nick Clifton @ 2004-11-08 9:04 UTC (permalink / raw) To: Andrew STUBBS, 'Alexandre Oliva'; +Cc: binutils [-- Attachment #1: Type: text/plain, Size: 2283 bytes --] Hi Andrew, Sorry that this is later than advertised... > I agree that there may be some problem inserting it into the diagram, but > the important ting is that it must be inserted into the inheritance tree in > the code and that the |s (ors) are removed from the instruction table (the > op32 stuff may be ok, but the others have to go). Ok, here is a patch that I think fixes up the diagram and removes the |'s from the opcodes table. What do you think ? > My other concern is the arch_op32 thingy. I don't know what it is for, or > what the affect on the architecture code is, but you should be aware that it > will not be encoded into the elf flags and, therefore, will not be available > at link time. If it is only intended to be for the assembler then it may be > ok. It is intended for the assembler and disassembler. It has no affect on architecture selection. Cheers Nick bfd/ChangeLog 2004-11-08 Nick Clifton <nickc@redhat.com> * archures.c: Add fake SH2A architectures. * bfd-in2.h: Regenerate. * cpu-sh.c: Add entries for fake SH2A architectures. binutils/ChangeLog 2004-11-08 Nick Clifton <nickc@redhat.com> * readelf.c: Add support for fake SH2A architectures. gas/testsuite/ChangeLog 2004-11-08 Nick Clifton <nickc@redhat.com> * gas/sh/arch/arch_expected.txt: Replace expected sh3e architectures with sh2a_(fake2). * gas/sh/arch/sh4.s: Replace fabs with frchg as the fabs instructions is used by SH2A as well. include/elf/ChangeLog 2004-11-08 Nick Clifton <nickc@redhat.com> * sh.h: Use hex constants for the EF flags to better demonstrate how the masking works. (EF_SH2A_FAKE1, EF_SH2A_FAKE2, EF_SH2A_FAKE3, EF_SH2A_FAKE4): Define. (EF_SH_BFD_TABLE): Add fake SH2A architectures. ld/testsuite/ChangeLog 2004-11-08 Nick Clifton <nickc@redhat.com> * ld-sh/arch/arch_expected.txt: Replace expected sh3e architectures with sh2a_(fake2). * ld-sh/arch/sh4.s: Replace fabs with frchg as the fabs instructions is used by SH2A as well. opcodes/ChangeLog 2004-11-08 Nick Clifton <nickc@redhat.com> * sh-opc.h (sh_table): Create fake SH2A architectures so that every SH opcode has exactly one associated base architecture. Update the SH architecture relationship diagram to add nodes for these fake architectures. [-- Attachment #2: sh.patch --] [-- Type: text/plain, Size: 45104 bytes --] Index: bfd/archures.c =================================================================== RCS file: /cvs/src/src/bfd/archures.c,v retrieving revision 1.98 diff -c -3 -p -r1.98 archures.c *** bfd/archures.c 4 Nov 2004 14:58:13 -0000 1.98 --- bfd/archures.c 8 Nov 2004 08:52:54 -0000 *************** DESCRIPTION *** 234,239 **** --- 234,243 ---- .#define bfd_mach_sh_dsp 0x2d .#define bfd_mach_sh2a 0x2a .#define bfd_mach_sh2a_nofpu 0x2b + .#define bfd_mach_sh2a_fake1 0x2a1 + .#define bfd_mach_sh2a_fake2 0x2a2 + .#define bfd_mach_sh2a_fake3 0x2a3 + .#define bfd_mach_sh2a_fake4 0x2a4 .#define bfd_mach_sh2e 0x2e .#define bfd_mach_sh3 0x30 .#define bfd_mach_sh3_nommu 0x31 Index: bfd/cpu-sh.c =================================================================== RCS file: /cvs/src/src/bfd/cpu-sh.c,v retrieving revision 1.17 diff -c -3 -p -r1.17 cpu-sh.c *** bfd/cpu-sh.c 13 Aug 2004 03:15:56 -0000 1.17 --- bfd/cpu-sh.c 8 Nov 2004 08:52:56 -0000 *************** *** 24,46 **** #include "libbfd.h" #include "../opcodes/sh-opc.h" ! #define SH_NEXT &arch_info_struct[0] ! #define SH2_NEXT &arch_info_struct[1] ! #define SH2E_NEXT &arch_info_struct[2] ! #define SH_DSP_NEXT &arch_info_struct[3] ! #define SH3_NEXT &arch_info_struct[4] ! #define SH3_NOMMU_NEXT &arch_info_struct[5] ! #define SH3_DSP_NEXT &arch_info_struct[6] ! #define SH3E_NEXT &arch_info_struct[7] ! #define SH4_NEXT &arch_info_struct[8] ! #define SH4A_NEXT &arch_info_struct[9] ! #define SH4AL_DSP_NEXT &arch_info_struct[10] ! #define SH4_NOFPU_NEXT &arch_info_struct[11] ! #define SH4_NOMMU_NOFPU_NEXT &arch_info_struct[12] ! #define SH4A_NOFPU_NEXT &arch_info_struct[13] ! #define SH2A_NEXT &arch_info_struct[14] ! #define SH2A_NOFPU_NEXT &arch_info_struct[15] ! #define SH64_NEXT NULL static const bfd_arch_info_type arch_info_struct[] = { --- 24,50 ---- #include "libbfd.h" #include "../opcodes/sh-opc.h" ! #define SH_NEXT arch_info_struct + 0 ! #define SH2_NEXT arch_info_struct + 1 ! #define SH2E_NEXT arch_info_struct + 2 ! #define SH_DSP_NEXT arch_info_struct + 3 ! #define SH3_NEXT arch_info_struct + 4 ! #define SH3_NOMMU_NEXT arch_info_struct + 5 ! #define SH3_DSP_NEXT arch_info_struct + 6 ! #define SH3E_NEXT arch_info_struct + 7 ! #define SH4_NEXT arch_info_struct + 8 ! #define SH4A_NEXT arch_info_struct + 9 ! #define SH4AL_DSP_NEXT arch_info_struct + 10 ! #define SH4_NOFPU_NEXT arch_info_struct + 11 ! #define SH4_NOMMU_NOFPU_NEXT arch_info_struct + 12 ! #define SH4A_NOFPU_NEXT arch_info_struct + 13 ! #define SH2A_NEXT arch_info_struct + 14 ! #define SH2A_NOFPU_NEXT arch_info_struct + 15 ! #define SH64_NEXT arch_info_struct + 16 ! #define SH2A_FAKE1_NEXT arch_info_struct + 17 ! #define SH2A_FAKE2_NEXT arch_info_struct + 18 ! #define SH2A_FAKE3_NEXT arch_info_struct + 19 ! #define SH2A_FAKE4_NEXT NULL static const bfd_arch_info_type arch_info_struct[] = { *************** static const bfd_arch_info_type arch_inf *** 268,273 **** --- 272,333 ---- bfd_default_scan, SH64_NEXT }, + { + 32, /* 32 bits in a word. */ + 32, /* 32 bits in an address. */ + 8, /* 8 bits in a byte. */ + bfd_arch_sh, + bfd_mach_sh2a_fake1, + "sh", /* Arch_name. */ + "sh2a_(fake1)", /* Printable name. */ + 1, + FALSE, /* Not the default. */ + bfd_default_compatible, + bfd_default_scan, + SH2A_FAKE1_NEXT + }, + { + 32, /* 32 bits in a word. */ + 32, /* 32 bits in an address. */ + 8, /* 8 bits in a byte. */ + bfd_arch_sh, + bfd_mach_sh2a_fake2, + "sh", /* Arch_name. */ + "sh2a_(fake2)", /* Printable name. */ + 1, + FALSE, /* Not the default. */ + bfd_default_compatible, + bfd_default_scan, + SH2A_FAKE2_NEXT + }, + { + 32, /* 32 bits in a word. */ + 32, /* 32 bits in an address. */ + 8, /* 8 bits in a byte. */ + bfd_arch_sh, + bfd_mach_sh2a_fake3, + "sh", /* Arch_name. */ + "sh2a_(fake3)", /* Printable name. */ + 1, + FALSE, /* Not the default. */ + bfd_default_compatible, + bfd_default_scan, + SH2A_FAKE3_NEXT + }, + { + 32, /* 32 bits in a word. */ + 32, /* 32 bits in an address. */ + 8, /* 8 bits in a byte. */ + bfd_arch_sh, + bfd_mach_sh2a_fake4, + "sh", /* Arch_name. */ + "sh2a_(fake4)", /* Printable name. */ + 1, + FALSE, /* Not the default. */ + bfd_default_compatible, + bfd_default_scan, + SH2A_FAKE4_NEXT + }, }; const bfd_arch_info_type bfd_sh_arch = *************** const bfd_arch_info_type bfd_sh_arch = *** 293,299 **** The prototypes for these SH specific functions are found in sh-opc.h . */ ! static struct { unsigned long bfd_mach, arch, arch_up; } bfd_to_arch_table[] = { { bfd_mach_sh, arch_sh1, arch_sh1_up }, { bfd_mach_sh2, arch_sh2, arch_sh2_up }, --- 353,365 ---- The prototypes for these SH specific functions are found in sh-opc.h . */ ! static struct ! { ! unsigned long bfd_mach; ! unsigned long arch; ! unsigned long arch_up; ! } ! bfd_to_arch_table[] = { { bfd_mach_sh, arch_sh1, arch_sh1_up }, { bfd_mach_sh2, arch_sh2, arch_sh2_up }, *************** static struct { unsigned long bfd_mach, *** 311,316 **** --- 377,388 ---- { bfd_mach_sh4_nofpu, arch_sh4_nofpu, arch_sh4_nofp_up }, { bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up }, { bfd_mach_sh4a_nofpu, arch_sh4a_nofpu, arch_sh4a_nofp_up }, + + { bfd_mach_sh2a_fake1, arch_sh2a_nofpu_fake1, arch_sh2a_nofpu_sh3_nommu_up }, + { bfd_mach_sh2a_fake2, arch_sh2a_fake2, arch_sh2a_sh3e_up }, + { bfd_mach_sh2a_fake3, arch_sh2a_nofpu_fake3, arch_sh2a_nofpu_sh4_nommu_up }, + { bfd_mach_sh2a_fake4, arch_sh2a_fake4, arch_sh2a_sh4_up }, + { 0, 0, 0 } /* Terminator. */ }; Index: binutils/readelf.c =================================================================== RCS file: /cvs/src/src/binutils/readelf.c,v retrieving revision 1.264 diff -c -3 -p -r1.264 readelf.c *** binutils/readelf.c 3 Nov 2004 10:44:43 -0000 1.264 --- binutils/readelf.c 8 Nov 2004 08:52:59 -0000 *************** get_machine_flags (unsigned e_flags, uns *** 2081,2088 **** case EF_SH2A: strcat (buf, ", sh2a"); break; case EF_SH4_NOFPU: strcat (buf, ", sh4-nofpu"); break; case EF_SH4A_NOFPU: strcat (buf, ", sh4a-nofpu"); break; case EF_SH2A_NOFPU: strcat (buf, ", sh2a-nofpu"); break; ! default: strcat (buf, ", unknown ISA"); break; } break; --- 2081,2094 ---- case EF_SH2A: strcat (buf, ", sh2a"); break; case EF_SH4_NOFPU: strcat (buf, ", sh4-nofpu"); break; case EF_SH4A_NOFPU: strcat (buf, ", sh4a-nofpu"); break; + case EF_SH4_NOMMU_NOFPU: strcat (buf,", sh4-nommu-nofpu"); break; case EF_SH2A_NOFPU: strcat (buf, ", sh2a-nofpu"); break; ! case EF_SH3_NOMMU: strcat (buf, ", sh3-nommu"); break; ! case EF_SH2A_FAKE1: strcat (buf, ", sh2a (fake1)"); break; ! case EF_SH2A_FAKE2: strcat (buf, ", sh2a (fake2)"); break; ! case EF_SH2A_FAKE3: strcat (buf, ", sh2a (fake3)"); break; ! case EF_SH2A_FAKE4: strcat (buf, ", sh2a (fake4)"); break; ! default: strcat (buf, ", unknown ISA: "); break; } break; Index: gas/testsuite/gas/sh/arch/arch_expected.txt =================================================================== RCS file: /cvs/src/src/gas/testsuite/gas/sh/arch/arch_expected.txt,v retrieving revision 1.1 diff -c -3 -p -r1.1 arch_expected.txt *** gas/testsuite/gas/sh/arch/arch_expected.txt 29 Jun 2004 16:35:05 -0000 1.1 --- gas/testsuite/gas/sh/arch/arch_expected.txt 8 Nov 2004 08:53:01 -0000 *************** sh3.s -isa=sh4a *** 241,259 **** sh3.s -isa=sh4a-up sh4a sh3.s -isa=sh4al-dsp sh4al-dsp sh3.s -isa=sh4al-dsp-up sh4al-dsp ! sh3e.s default-options sh3e sh3e.s -dsp ERROR ! sh3e.s -isa=any sh3e sh3e.s -isa=dsp ERROR ! sh3e.s -isa=fp sh3e sh3e.s -isa=sh-dsp ERROR sh3e.s -isa=sh-dsp-up ERROR sh3e.s -isa=sh ERROR ! sh3e.s -isa=sh-up sh3e sh3e.s -isa=sh2 ERROR ! sh3e.s -isa=sh2-up sh3e ! sh3e.s -isa=sh2e ERROR ! sh3e.s -isa=sh2e-up sh3e sh3e.s -isa=sh3-dsp ERROR sh3e.s -isa=sh3-dsp-up ERROR sh3e.s -isa=sh3-nommu ERROR --- 241,259 ---- sh3.s -isa=sh4a-up sh4a sh3.s -isa=sh4al-dsp sh4al-dsp sh3.s -isa=sh4al-dsp-up sh4al-dsp ! sh3e.s default-options sh2a_(fake2) sh3e.s -dsp ERROR ! sh3e.s -isa=any sh2a_(fake2) sh3e.s -isa=dsp ERROR ! sh3e.s -isa=fp sh2a_(fake2) sh3e.s -isa=sh-dsp ERROR sh3e.s -isa=sh-dsp-up ERROR sh3e.s -isa=sh ERROR ! sh3e.s -isa=sh-up sh2a_(fake2) sh3e.s -isa=sh2 ERROR ! sh3e.s -isa=sh2-up sh2a_(fake2) ! sh3e.s -isa=sh2e sh2a_(fake2) ! sh3e.s -isa=sh2e-up sh2a_(fake2) sh3e.s -isa=sh3-dsp ERROR sh3e.s -isa=sh3-dsp-up ERROR sh3e.s -isa=sh3-nommu ERROR Index: gas/testsuite/gas/sh/arch/sh4.s =================================================================== RCS file: /cvs/src/src/gas/testsuite/gas/sh/arch/sh4.s,v retrieving revision 1.1 diff -c -3 -p -r1.1 sh4.s *** gas/testsuite/gas/sh/arch/sh4.s 29 Jun 2004 16:35:05 -0000 1.1 --- gas/testsuite/gas/sh/arch/sh4.s 8 Nov 2004 08:53:01 -0000 *************** *** 1,3 **** .section .text sh4: ! fabs dr0 --- 1,3 ---- .section .text sh4: ! frchg Index: include/elf/sh.h =================================================================== RCS file: /cvs/src/src/include/elf/sh.h,v retrieving revision 1.19 diff -c -3 -p -r1.19 sh.h *** include/elf/sh.h 29 Jul 2004 05:17:37 -0000 1.19 --- include/elf/sh.h 8 Nov 2004 08:53:01 -0000 *************** *** 22,49 **** /* Processor specific flags for the ELF header e_flags field. */ ! #define EF_SH_MACH_MASK 0x1f ! #define EF_SH_UNKNOWN 0 /* For backwards compatibility. */ ! #define EF_SH1 1 ! #define EF_SH2 2 ! #define EF_SH3 3 ! #define EF_SH_DSP 4 ! #define EF_SH3_DSP 5 ! #define EF_SH4AL_DSP 6 ! #define EF_SH3E 8 ! #define EF_SH4 9 ! #define EF_SH2E 11 ! #define EF_SH4A 12 ! #define EF_SH2A 13 ! ! #define EF_SH4_NOFPU 16 ! #define EF_SH4A_NOFPU 17 ! #define EF_SH4_NOMMU_NOFPU 18 ! #define EF_SH2A_NOFPU 19 ! #define EF_SH3_NOMMU 20 /* This one can only mix in objects from other EF_SH5 objects. */ ! #define EF_SH5 10 /* Define the mapping from ELF to bfd mach numbers. bfd_mach_* are defined in bfd_in2.h (generated from --- 22,56 ---- /* Processor specific flags for the ELF header e_flags field. */ ! #define EF_SH_MACH_MASK 0x1f ! #define EF_SH_UNKNOWN 0x00 /* For backwards compatibility. */ ! #define EF_SH1 0x01 ! #define EF_SH2 0x02 ! #define EF_SH3 0x03 ! #define EF_SH_DSP 0x04 ! #define EF_SH3_DSP 0x05 ! #define EF_SH4AL_DSP 0x06 ! #define EF_SH3E 0x08 ! #define EF_SH4 0x09 /* This one can only mix in objects from other EF_SH5 objects. */ ! #define EF_SH5 0x0a ! ! #define EF_SH2E 0x0b ! #define EF_SH4A 0x0c ! #define EF_SH2A 0x0d ! ! #define EF_SH4_NOFPU 0x10 ! #define EF_SH4A_NOFPU 0x11 ! #define EF_SH4_NOMMU_NOFPU 0x12 ! #define EF_SH2A_NOFPU 0x13 ! #define EF_SH3_NOMMU 0x14 ! ! #define EF_SH2A_FAKE1 0x15 ! #define EF_SH2A_FAKE2 0x16 ! #define EF_SH2A_FAKE3 0x17 ! #define EF_SH2A_FAKE4 0x18 ! /* Define the mapping from ELF to bfd mach numbers. bfd_mach_* are defined in bfd_in2.h (generated from *************** *** 68,74 **** /* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \ /* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \ /* EF_SH2A_NOFPU */ bfd_mach_sh2a_nofpu , \ ! /* EF_SH3_NOMMU */ bfd_mach_sh3_nommu /* Convert arch_sh* into EF_SH*. */ int sh_find_elf_flags (unsigned int arch_set); --- 75,85 ---- /* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \ /* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \ /* EF_SH2A_NOFPU */ bfd_mach_sh2a_nofpu , \ ! /* EF_SH3_NOMMU */ bfd_mach_sh3_nommu ,\ ! /* EF_SH2A_FAKE1 */ bfd_mach_sh2a_fake1 , \ ! /* EF_SH2A_FAKE2 */ bfd_mach_sh2a_fake2 , \ ! /* EF_SH2A_FAKE3 */ bfd_mach_sh2a_fake3 , \ ! /* EF_SH2A_FAKE4 */ bfd_mach_sh2a_fake4 /* Convert arch_sh* into EF_SH*. */ int sh_find_elf_flags (unsigned int arch_set); Index: ld/testsuite/ld-sh/arch/arch_expected.txt =================================================================== RCS file: /cvs/src/src/ld/testsuite/ld-sh/arch/arch_expected.txt,v retrieving revision 1.1 diff -c -3 -p -r1.1 arch_expected.txt *** ld/testsuite/ld-sh/arch/arch_expected.txt 29 Jun 2004 16:35:05 -0000 1.1 --- ld/testsuite/ld-sh/arch/arch_expected.txt 8 Nov 2004 08:53:01 -0000 *************** sh.o sh2e.o *** 32,38 **** sh.o sh3-dsp.o sh3-dsp sh.o sh3-nommu.o sh3-nommu sh.o sh3.o sh3 ! sh.o sh3e.o sh3e sh.o sh4-nofpu.o sh4-nofpu sh.o sh4-nommu-nofpu.o sh4-nommu-nofpu sh.o sh4.o sh4 --- 32,38 ---- sh.o sh3-dsp.o sh3-dsp sh.o sh3-nommu.o sh3-nommu sh.o sh3.o sh3 ! sh.o sh3e.o sh2a_(fake2) sh.o sh4-nofpu.o sh4-nofpu sh.o sh4-nommu-nofpu.o sh4-nommu-nofpu sh.o sh4.o sh4 *************** sh2.o sh2e.o *** 47,53 **** sh2.o sh3-dsp.o sh3-dsp sh2.o sh3-nommu.o sh3-nommu sh2.o sh3.o sh3 ! sh2.o sh3e.o sh3e sh2.o sh4-nofpu.o sh4-nofpu sh2.o sh4-nommu-nofpu.o sh4-nommu-nofpu sh2.o sh4.o sh4 --- 47,53 ---- sh2.o sh3-dsp.o sh3-dsp sh2.o sh3-nommu.o sh3-nommu sh2.o sh3.o sh3 ! sh2.o sh3e.o sh2a_(fake2) sh2.o sh4-nofpu.o sh4-nofpu sh2.o sh4-nommu-nofpu.o sh4-nommu-nofpu sh2.o sh4.o sh4 *************** sh2e.o sh2e.o *** 62,68 **** sh2e.o sh3-dsp.o ERROR sh2e.o sh3-nommu.o sh3e sh2e.o sh3.o sh3e ! sh2e.o sh3e.o sh3e sh2e.o sh4-nofpu.o sh4 sh2e.o sh4-nommu-nofpu.o sh4 sh2e.o sh4.o sh4 --- 62,68 ---- sh2e.o sh3-dsp.o ERROR sh2e.o sh3-nommu.o sh3e sh2e.o sh3.o sh3e ! sh2e.o sh3e.o sh2a_(fake2) sh2e.o sh4-nofpu.o sh4 sh2e.o sh4-nommu-nofpu.o sh4 sh2e.o sh4.o sh4 *************** sh3.o sh4a.o *** 116,128 **** sh3.o sh4al-dsp.o sh4al-dsp sh3.o sh-unknown.o sh3 sh3e.o sh-dsp.o ERROR ! sh3e.o sh.o sh3e ! sh3e.o sh2.o sh3e ! sh3e.o sh2e.o sh3e sh3e.o sh3-dsp.o ERROR sh3e.o sh3-nommu.o sh3e sh3e.o sh3.o sh3e ! sh3e.o sh3e.o sh3e sh3e.o sh4-nofpu.o sh4 sh3e.o sh4-nommu-nofpu.o sh4 sh3e.o sh4.o sh4 --- 116,128 ---- sh3.o sh4al-dsp.o sh4al-dsp sh3.o sh-unknown.o sh3 sh3e.o sh-dsp.o ERROR ! sh3e.o sh.o sh2a_(fake2) ! sh3e.o sh2.o sh2a_(fake2) ! sh3e.o sh2e.o sh2a_(fake2) sh3e.o sh3-dsp.o ERROR sh3e.o sh3-nommu.o sh3e sh3e.o sh3.o sh3e ! sh3e.o sh3e.o sh2a_(fake2) sh3e.o sh4-nofpu.o sh4 sh3e.o sh4-nommu-nofpu.o sh4 sh3e.o sh4.o sh4 Index: ld/testsuite/ld-sh/arch/sh4.s =================================================================== RCS file: /cvs/src/src/ld/testsuite/ld-sh/arch/sh4.s,v retrieving revision 1.1 diff -c -3 -p -r1.1 sh4.s *** ld/testsuite/ld-sh/arch/sh4.s 29 Jun 2004 16:35:05 -0000 1.1 --- ld/testsuite/ld-sh/arch/sh4.s 8 Nov 2004 08:53:01 -0000 *************** *** 1,3 **** .section .text sh4: ! fabs dr0 --- 1,3 ---- .section .text sh4: ! frchg Index: opcodes/sh-opc.h =================================================================== RCS file: /cvs/src/src/opcodes/sh-opc.h,v retrieving revision 1.22 diff -c -3 -p -r1.22 sh-opc.h *** opcodes/sh-opc.h 29 Jul 2004 05:19:27 -0000 1.22 --- opcodes/sh-opc.h 8 Nov 2004 08:53:02 -0000 *************** typedef enum *** 198,244 **** } sh_dsp_reg_nums; - #define arch_sh1_base 0x0001 - #define arch_sh2_base 0x0002 - #define arch_sh3_base 0x0004 - #define arch_sh4_base 0x0008 - #define arch_sh4a_base 0x0010 - #define arch_sh2a_base 0x0020 - - /* This is an annotation on instruction types, but we abuse the arch - field in instructions to denote it. */ - #define arch_op32 0x00100000 /* This is a 32-bit opcode. */ - - #define arch_sh_no_mmu 0x04000000 - #define arch_sh_has_mmu 0x08000000 - #define arch_sh_no_co 0x10000000 /* neither FPU nor DSP co-processor */ - #define arch_sh_sp_fpu 0x20000000 /* single precision FPU */ - #define arch_sh_dp_fpu 0x40000000 /* double precision FPU */ - #define arch_sh_has_dsp 0x80000000 - - #define arch_sh_base_mask 0x0000003f ! #define arch_opann_mask 0x00100000 #define arch_sh_mmu_mask 0x0c000000 #define arch_sh_co_mask 0xf0000000 ! #define arch_sh1 (arch_sh1_base|arch_sh_no_mmu|arch_sh_no_co) ! #define arch_sh2 (arch_sh2_base|arch_sh_no_mmu|arch_sh_no_co) ! #define arch_sh2a (arch_sh2a_base|arch_sh_no_mmu|arch_sh_dp_fpu) ! #define arch_sh2a_nofpu (arch_sh2a_base|arch_sh_no_mmu|arch_sh_no_co) ! #define arch_sh2e (arch_sh2_base|arch_sh2a_base|arch_sh_no_mmu|arch_sh_sp_fpu) ! #define arch_sh_dsp (arch_sh2_base|arch_sh_no_mmu|arch_sh_has_dsp) ! #define arch_sh3_nommu (arch_sh3_base|arch_sh_no_mmu|arch_sh_no_co) ! #define arch_sh3 (arch_sh3_base|arch_sh_has_mmu|arch_sh_no_co) ! #define arch_sh3e (arch_sh3_base|arch_sh_has_mmu|arch_sh_sp_fpu) ! #define arch_sh3_dsp (arch_sh3_base|arch_sh_has_mmu|arch_sh_has_dsp) ! #define arch_sh4 (arch_sh4_base|arch_sh_has_mmu|arch_sh_dp_fpu) ! #define arch_sh4a (arch_sh4a_base|arch_sh_has_mmu|arch_sh_dp_fpu) ! #define arch_sh4al_dsp (arch_sh4a_base|arch_sh_has_mmu|arch_sh_has_dsp) ! #define arch_sh4_nofpu (arch_sh4_base|arch_sh_has_mmu|arch_sh_no_co) ! #define arch_sh4a_nofpu (arch_sh4a_base|arch_sh_has_mmu|arch_sh_no_co) ! #define arch_sh4_nommu_nofpu (arch_sh4_base|arch_sh_no_mmu|arch_sh_no_co) #define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2)) #define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0) --- 198,248 ---- } sh_dsp_reg_nums; #define arch_sh_base_mask 0x0000003f ! #define arch_sh1_base 0x00000001 ! #define arch_sh2_base 0x00000002 ! #define arch_sh3_base 0x00000004 ! #define arch_sh4_base 0x00000008 ! #define arch_sh4a_base 0x00000010 ! #define arch_sh2a_base 0x00000020 ! #define arch_sh_mmu_mask 0x0c000000 + #define arch_sh_no_mmu 0x04000000 + #define arch_sh_has_mmu 0x08000000 + #define arch_sh_co_mask 0xf0000000 + #define arch_sh_no_co 0x10000000 /* Neither FPU nor DSP co-processor. */ + #define arch_sh_sp_fpu 0x20000000 /* Single precision FPU. */ + #define arch_sh_dp_fpu 0x40000000 /* Double precision FPU. */ + #define arch_sh_has_dsp 0x80000000 + + /* This is an annotation on instruction types, but we + abuse the arch field in instructions to denote it. */ + #define arch_opann_mask 0x00100000 + #define arch_op32 0x00100000 /* This is a 32-bit opcode. */ ! #define arch_sh1 (arch_sh1_base |arch_sh_no_mmu|arch_sh_no_co) ! #define arch_sh2 (arch_sh2_base |arch_sh_no_mmu|arch_sh_no_co) ! #define arch_sh2a (arch_sh2a_base|arch_sh_no_mmu|arch_sh_dp_fpu) ! #define arch_sh2a_nofpu (arch_sh2a_base|arch_sh_no_mmu|arch_sh_no_co) ! #define arch_sh2e (arch_sh2_base |arch_sh2a_base|arch_sh_no_mmu|arch_sh_sp_fpu) ! #define arch_sh_dsp (arch_sh2_base |arch_sh_no_mmu|arch_sh_has_dsp) ! #define arch_sh3_nommu (arch_sh3_base |arch_sh_no_mmu|arch_sh_no_co) ! #define arch_sh3 (arch_sh3_base |arch_sh_has_mmu|arch_sh_no_co) ! #define arch_sh3e (arch_sh3_base |arch_sh_has_mmu|arch_sh_sp_fpu) ! #define arch_sh3_dsp (arch_sh3_base |arch_sh_has_mmu|arch_sh_has_dsp) ! #define arch_sh4 (arch_sh4_base |arch_sh_has_mmu|arch_sh_dp_fpu) ! #define arch_sh4a (arch_sh4a_base|arch_sh_has_mmu|arch_sh_dp_fpu) ! #define arch_sh4al_dsp (arch_sh4a_base|arch_sh_has_mmu|arch_sh_has_dsp) ! #define arch_sh4_nofpu (arch_sh4_base |arch_sh_has_mmu|arch_sh_no_co) ! #define arch_sh4a_nofpu (arch_sh4a_base|arch_sh_has_mmu|arch_sh_no_co) ! #define arch_sh4_nommu_nofpu (arch_sh4_base |arch_sh_no_mmu|arch_sh_no_co) ! ! #define arch_sh2a_nofpu_fake1 (arch_sh2_base |arch_sh2a_base|arch_sh_no_mmu|arch_sh_no_co) ! #define arch_sh2a_fake2 (arch_sh2a_base|arch_sh_no_mmu|arch_sh_sp_fpu) ! #define arch_sh2a_nofpu_fake3 (arch_sh2a_base|arch_sh_no_mmu|arch_sh_no_co) ! #define arch_sh2a_fake4 (arch_sh2a_base|arch_sh_no_mmu|arch_sh_dp_fpu) #define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2)) #define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0) *************** bfd_boolean sh_merge_bfd_arch (bfd *ibfd *** 276,323 **** SH2 .------------'|`--------------------. / | \ ! SH-DSP SH3-nommu SH2E ! | |`--------. | ! | | \ | ! | SH3 SH4-nommu-nofpu | ! | | | | ! | .------------'|`----------+---------. | ! |/ / \| ! | | .-------' | ! | |/ | ! SH3-dsp SH4-nofpu SH3E ! | |`--------------------. | ! | | \| ! | SH4A-nofpu SH4 ! | .------------' `--------------------. | ! |/ \| ! SH4AL-dsp SH4A ! */ ! /* Central branches */ ! #define arch_sh1_up (arch_sh1 | arch_sh2_up) ! #define arch_sh2_up (arch_sh2 | arch_sh2e_up | arch_sh2a_nofpu_up | arch_sh3_nommu_up | arch_sh_dsp_up) ! #define arch_sh3_nommu_up (arch_sh3_nommu | arch_sh3_up | arch_sh4_nommu_nofpu_up) ! #define arch_sh3_up (arch_sh3 | arch_sh3e_up | arch_sh3_dsp_up | arch_sh4_nofp_up) ! #define arch_sh4_nommu_nofpu_up (arch_sh4_nommu_nofpu | arch_sh4_nofp_up) ! #define arch_sh4_nofp_up (arch_sh4_nofpu | arch_sh4_up | arch_sh4a_nofp_up) ! #define arch_sh4a_nofp_up (arch_sh4a_nofpu | arch_sh4a_up | arch_sh4al_dsp_up) ! ! /* Right branch */ ! #define arch_sh2e_up (arch_sh2e | arch_sh2a_up | arch_sh3e_up) ! #define arch_sh3e_up (arch_sh3e | arch_sh4_up) ! #define arch_sh4_up (arch_sh4 | arch_sh4a_up) ! #define arch_sh4a_up (arch_sh4a) ! ! /* Left branch */ ! #define arch_sh_dsp_up (arch_sh_dsp | arch_sh3_dsp_up) ! #define arch_sh3_dsp_up (arch_sh3_dsp | arch_sh4al_dsp_up) ! #define arch_sh4al_dsp_up (arch_sh4al_dsp) ! ! /* SH 2a branched off SH2e, adding a lot but not all of SH4 and SH4a. */ ! #define arch_sh2a_up (arch_sh2a) ! #define arch_sh2a_nofpu_up (arch_sh2a_nofpu | arch_sh2a_up) typedef struct --- 280,341 ---- SH2 .------------'|`--------------------. / | \ ! SH2 SH2A SH2E ! (dsp) (fake1) | ! | /\ | ! | / \ | ! | / \ | ! | .----' SH3 SH2A ! | / (nommu) (fake2) ! | | /\ /\ ! | | / \ / \ ! | | / \ / \ ! | | SH2A SH3 / | ! | | (fake3) /|\ / | ! | | /\ / | \ / | ! | | ----' \ .../ | ----. / | ! | | / . \ | \/ | ! | SH2A . SH4 | SH3E | ! | (nofpu) . (nommu) | | | ! | | . (nofpu) | | | ! | ...+..... | .--' | | ! | / | . | / | | ! SH3 | SH4 SH2A | ! (dsp) | (nofpu) (fake4) | ! | | /\ /\ | ! | | / '---. .--'. \ .-----' ! | | / \ / \/ ! -+---- . SH4A SH4 SH2A <------.... ! | (nofpu) | ! | / \ .-' ! | .--------' '---. / ! | / \/ ! SH4AL SH4A ! (dsp) */ ! #define arch_sh1_up (arch_sh1 | arch_sh2_up) ! #define arch_sh2_up (arch_sh2 | arch_sh2e_up | arch_sh2a_nofpu_up | arch_sh3_nommu_up | arch_sh_dsp_up) ! #define arch_sh3_nommu_up (arch_sh3_nommu | arch_sh3_up | arch_sh4_nommu_nofpu_up) ! #define arch_sh3_up (arch_sh3 | arch_sh3e_up | arch_sh3_dsp_up | arch_sh4_nofp_up) ! #define arch_sh4_nommu_nofpu_up (arch_sh4_nommu_nofpu | arch_sh4_nofp_up) ! #define arch_sh4_nofp_up (arch_sh4_nofpu | arch_sh4_up | arch_sh4a_nofp_up) ! #define arch_sh4a_nofp_up (arch_sh4a_nofpu | arch_sh4a_up | arch_sh4al_dsp_up) ! #define arch_sh2e_up (arch_sh2e | arch_sh2a_up | arch_sh3e_up) ! #define arch_sh3e_up (arch_sh3e | arch_sh4_up) ! #define arch_sh4_up (arch_sh4 | arch_sh4a_up) ! #define arch_sh4a_up (arch_sh4a) ! #define arch_sh_dsp_up (arch_sh_dsp | arch_sh3_dsp_up) ! #define arch_sh3_dsp_up (arch_sh3_dsp | arch_sh4al_dsp_up) ! #define arch_sh4al_dsp_up (arch_sh4al_dsp) ! /* SH2a branched off SH2e, adding a lot but not all of SH4 and SH4a. */ ! #define arch_sh2a_up (arch_sh2a) ! #define arch_sh2a_nofpu_up (arch_sh2a_nofpu | arch_sh2a_up) ! ! #define arch_sh2a_nofpu_sh3_nommu_up (arch_sh2a_nofpu_fake1 | arch_sh2_up) ! #define arch_sh2a_sh3e_up (arch_sh2a_fake2 | arch_sh3e_up) ! #define arch_sh2a_nofpu_sh4_nommu_up (arch_sh2a_nofpu_fake3 | arch_sh4_nommu_nofpu_up) ! #define arch_sh2a_sh4_up (arch_sh2a_fake4 | arch_sh3e_up) typedef struct *************** const sh_opcode_info sh_table[] = *** 634,640 **** /* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh1_up}, ! /* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh4_nommu_nofpu_up | arch_sh2a_nofpu_up}, /* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofp_up}, --- 652,658 ---- /* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh1_up}, ! /* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_sh4_nommu_up}, /* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofp_up}, *************** const sh_opcode_info sh_table[] = *** 664,672 **** /* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}, ! /* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh3_nommu_up | arch_sh2a_nofpu_up}, ! /* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh3_nommu_up | arch_sh2a_nofpu_up}, /* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh1_up}, --- 682,690 ---- /* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}, ! /* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_sh3_nommu_up}, ! /* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_sh3_nommu_up}, /* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh1_up}, *************** const sh_opcode_info sh_table[] = *** 985,1007 **** {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}, /* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}, ! /* 1111nnn001011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}, ! /* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}, ! /* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}, ! /* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh4_up | arch_sh2a_up}, ! /* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh4_up | arch_sh2a_up}, ! /* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}, ! /* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh4_up | arch_sh2a_up}, /* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up}, --- 1003,1025 ---- {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}, /* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}, ! /* 1111nnn001011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2a_sh4_up}, /* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}, ! /* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2a_sh4_up}, /* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}, ! /* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_sh4_up}, /* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}, ! /* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_sh4_up}, ! /* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh2a_sh4_up}, ! /* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh2a_sh4_up}, /* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}, ! /* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2a_sh4_up}, /* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up}, *************** const sh_opcode_info sh_table[] = *** 1012,1053 **** /* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}, /* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}, ! /* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}, /* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}, ! /* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}, ! /* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}, ! /* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}, ! /* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}, ! /* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}, ! /* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}, ! /* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up | arch_sh2a_up}, ! /* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up | arch_sh2a_up}, ! /* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up | arch_sh2a_up}, ! /* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up | arch_sh2a_up}, ! /* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up | arch_sh2a_up}, ! /* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up | arch_sh2a_up}, ! /* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up | arch_sh2a_up}, /* 0011nnnnmmmm0001 0011dddddddddddd fmov.d <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.d",{DX_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY8}, arch_sh2a_up | arch_op32}, /* 0011nnnnmmmm0001 0111dddddddddddd fmov.d @(<DISP12>,<REG_M>),F_REG_N */ --- 1030,1071 ---- /* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}, /* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}, ! /* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2a_sh4_up}, /* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}, /* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}, ! /* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2a_sh4_up}, /* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}, ! /* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_sh4_up}, /* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}, ! /* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_sh4_up}, /* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}, ! /* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_sh4_up}, /* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}, ! /* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_sh4_up}, /* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}, ! /* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_sh4_up}, /* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}, ! /* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_sh4_up}, ! /* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_sh4_up}, ! /* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_sh4_up}, ! /* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_sh4_up}, ! /* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_sh4_up}, ! /* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_sh4_up}, ! /* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_sh4_up}, /* 0011nnnnmmmm0001 0011dddddddddddd fmov.d <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.d",{DX_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY8}, arch_sh2a_up | arch_op32}, /* 0011nnnnmmmm0001 0111dddddddddddd fmov.d @(<DISP12>,<REG_M>),F_REG_N */ *************** const sh_opcode_info sh_table[] = *** 1070,1079 **** {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}, /* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}, ! /* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}, ! /* 1111nnn001001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh4_up | arch_sh2a_up}, /* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}, --- 1088,1097 ---- {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}, /* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}, ! /* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2a_sh4_up}, /* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}, ! /* 1111nnn001001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2a_sh4_up}, /* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}, *************** const sh_opcode_info sh_table[] = *** 1081,1100 **** /* 1111nnn011111101 fsca FPUL,<D_REG_N> */{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_F,HEX_D}, arch_sh4_up}, ! /* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh4_up | arch_sh2a_up}, ! /* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh3e_up | arch_sh2a_up}, ! /* 1111nnn001101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}, /* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}, /* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}, ! /* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}, ! /* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh4_up | arch_sh2a_up}, /* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}, --- 1099,1118 ---- /* 1111nnn011111101 fsca FPUL,<D_REG_N> */{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_F,HEX_D}, arch_sh4_up}, ! /* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh2a_sh4_up}, ! /* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_sh3e_up}, ! /* 1111nnn001101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_sh4_up}, /* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}, /* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}, /* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}, ! /* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_sh4_up}, /* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}, ! /* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_sh4_up}, /* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}, ^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: Broken SH2a patches 2004-11-08 9:04 ` Nick Clifton @ 2004-11-08 15:12 ` Andrew STUBBS 2004-11-08 16:27 ` Joern RENNECKE ` (2 more replies) 0 siblings, 3 replies; 26+ messages in thread From: Andrew STUBBS @ 2004-11-08 15:12 UTC (permalink / raw) To: 'Nick Clifton', 'Alexandre Oliva' Cc: binutils, Joern RENNECKE > > I agree that there may be some problem inserting it into > the diagram, but > > the important ting is that it must be inserted into the > inheritance tree in > > the code and that the |s (ors) are removed from the > instruction table (the > > op32 stuff may be ok, but the others have to go). > > Ok, here is a patch that I think fixes up the diagram and removes the > |'s from the opcodes table. What do you think ? It does address most of the problems I was talking about, but unfortunately there are a number of problems with it. 1. Although you have adjusted the test results for the existing tests you have not added new tests for the six new architectures. I think it would reveal some worry results ... 2. What does this mean? #define arch_sh2a_nofpu_fake1 (arch_sh2_base| arch_sh2a_base \ |arch_sh_no_mmu|arch_sh_no_co) How can it have two bases? 3. The diagram: SH2 .------------'|`--------------------. / | \ ! SH2 SH2A SH2E ! (dsp) (fake1) | ! | /\ | ! | / \ | ! | / \ | ! | .----' SH3 SH2A ! | / (nommu) (fake2) ! | | /\ /\ ! | | / \ / \ ! | | / \ / \ ! | | SH2A SH3 / | ! | | (fake3) /|\ / | ! | | /\ / | \ / | ! | | ----' \ .../ | ----. / | ! | | / . \ | \/ | ! | SH2A . SH4 | SH3E | ! | (nofpu) . (nommu) | | | ! | | . (nofpu) | | | ! | ...+..... | .--' | | ! | / | . | / | | ! SH3 | SH4 SH2A | ! (dsp) | (nofpu) (fake4) | ! | | /\ /\ | ! | | / '---. .--'. \ .-----' ! | | / \ / \/ ! -+---- . SH4A SH4 SH2A <------.... ! | (nofpu) | ! | / \ .-' ! | .--------' '---. / ! | / \/ ! SH4AL SH4A ! (dsp) The sh3_nommu introduces a number of instructions, including 'ldc <REG_N>,SSR' etc., which are not present in the sh2a (according to the manual from the Renesas website). Yet your diagram shows sh2a inheriting these instructions. As far as I can tell fake3 should descend from fake1, while sh4_nommu_nofpu descends from both fake3 and sh3nommu. Similarly fake4 looks like it should descend from fake2, not sh3e. fake2 should also descend from fake1, in addition to sh2e, since it also has the shifts. You need to look at these inhertances carefully. I assume fake1 and fake2 genuinely can descend from sh2 and sh2e (but please check), but fake3 and fake4 cannot descend from anything sh3. It is a brave attempt at ASCII line routing! Too bad it had lost its former clarity though :-( 4. This is wrong: #define arch_sh2a_nofpu_sh3_nommu_up \ (arch_sh2a_nofpu_fake1 | arch_sh2_up) #define arch_sh2a_sh3e_up \ (arch_sh2a_fake2 | arch_sh3e_up) #define arch_sh2a_nofpu_sh4_nommu_up \ (arch_sh2a_nofpu_fake3 | arch_sh4_nommu_nofpu_up) #define arch_sh2a_sh4_up \ (arch_sh2a_fake4 | arch_sh3e_up) The first and fourth are upside down somehow and all of them are incomplete. It should be (according to the diagram): #define arch_sh2a_fake1_up \ (arch_sh2a_nofpu_fake1 | arch_sh2a_nofpu_up | sh3_nommu_up) #define arch_sh2a_fake2_up \ (arch_sh2a_fake2 | arch_sh3e_up | arch_sh2a_up) #define arch_sh2a_fake3_up \ (arch_sh2a_nofpu_fake3 | arch_sh4_nommu_nofpu_up \ | sh2a_nofpu_up) #define arch_sh2a_fake4_up \ (arch_sh2a_fake4 | arch_sh4_up | arch_sh2a_up) That is, itself plus _all_ its immediate descendents. I have changed the names to help me understand it. The way you had two names for the same thing was confusing. The second names were perhaps preferable (if more wordy) over 'fake' but perhaps also less future proof? Strictly speaking it may not be necessary to list arch_sh2a_up in arch_fake2_up because it is implied by arch_sh3e_up, but it provides documentation. Of course, what I have put above is wrong because the diagram it is based upon is wrong, but I did not want to confuse the matter any further. Additionally you have not updated the entries for the other architectures. E.g. arch_sh3e_up needs to include arch_sh2a_up, according to the diagram. I don't like the name 'fake', but I'm not sure what else to suggest. Perhaps sh2+, sh2e+, sh2++ and sh2e++ (or sh2+shift, sh2e+shift+fsqrt, sh2+shift+pref and sh2e+double). Of course '+' won't work in C ... hmmm. Unfortunately a lot of libraries etc. will end up labelled with these 'fake' architectures so it is important that the name means something. > > My other concern is the arch_op32 thingy. I don't know what > it is for, or > > what the affect on the architecture code is, but you should > be aware that it > > will not be encoded into the elf flags and, therefore, will > not be available > > at link time. If it is only intended to be for the > assembler then it may be > > ok. > > It is intended for the assembler and disassembler. It has no > affect on > architecture selection. Ah I see, this is something about the instruction encoding that has leaked into the wrong field. Should this not be encoded into the 'nibbles' somehow? If not, this is something that should be documented in the file. It does say it is an 'abuse' but not why. -- Andrew Stubbs andrew.stubbs@st.com andrew.stubbs@superh.com ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Broken SH2a patches 2004-11-08 15:12 ` Andrew STUBBS @ 2004-11-08 16:27 ` Joern RENNECKE 2004-11-08 16:36 ` Joern RENNECKE 2004-12-15 17:11 ` Nick Clifton 2 siblings, 0 replies; 26+ messages in thread From: Joern RENNECKE @ 2004-11-08 16:27 UTC (permalink / raw) To: Andrew STUBBS; +Cc: 'Nick Clifton', 'Alexandre Oliva', binutils > I don't like the name 'fake', but I'm not sure what else to suggest. Perhaps >sh2+, sh2e+, sh2++ and sh2e++ (or sh2+shift, sh2e+shift+fsqrt, >sh2+shift+pref and sh2e+double). Of course '+' won't work in C ... hmmm. > >Unfortunately a lot of libraries etc. will end up labelled with these 'fake' >architectures so it is important that the name means something. > When there are only one ot two simple features added, it seems most future-proof to just enumerate them. I.e. the 'fake1' adds dynamic shift to SH2, 'fake2' adds dynamic shift and fsqrt.s to SH2E, 'fake3' adds dynamic shift and prefetch to SH2. 'fake4', however, adds dynamic shift, fsqrt.s, prefetch, and a plethora of double precision arithmetic instructions and ancillary instructions to that. So I think we better name that one from the intersection that generates it, i.e. SH4_SH2A . You can probably draw this more nicely... SH2 .------------'|`--------------------. / | \ SH2 SH2_dshift SH2E (dsp) / \ \ | | / \ \_____________ | | / \ \ | | / \ \ | | / SH3 \ | | / (nommu) SH2E_dshift_sqrt | SH2_dshift_pref |\ /| | | \ | \ / | | | \ | \ / | | | \ | SH3 / | | | \ | /|\ / | | | \ | / | \ / | | | \ .!./ | \ / | | | . \ | | \ / | | SH2A . SH4 | \ / SH4_SH2A | (nofpu) . (nommu) | SH3E / | | | . (nofpu) | /\ / | | ...+..... | .--' | \ / | | / | | / | \ / | SH3 | SH4 | X | (dsp) | (nofpu) | / \ | | | /\ | / \ | | | / '---. | / \ / | | / \ |/ \/ -+---- . SH4A SH4 SH2A <------.... | (nofpu) | | / \ .-' | .--------' '---. / | / \/ SH4AL SH4A (dsp) ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Broken SH2a patches 2004-11-08 15:12 ` Andrew STUBBS 2004-11-08 16:27 ` Joern RENNECKE @ 2004-11-08 16:36 ` Joern RENNECKE 2004-12-15 17:11 ` Nick Clifton 2 siblings, 0 replies; 26+ messages in thread From: Joern RENNECKE @ 2004-11-08 16:36 UTC (permalink / raw) To: Andrew STUBBS; +Cc: 'Nick Clifton', 'Alexandre Oliva', binutils P.S.: You need another vertex from SH2_dshift_pref to SH4_SH2A . ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Broken SH2a patches 2004-11-08 15:12 ` Andrew STUBBS 2004-11-08 16:27 ` Joern RENNECKE 2004-11-08 16:36 ` Joern RENNECKE @ 2004-12-15 17:11 ` Nick Clifton 2004-12-16 13:24 ` Andrew STUBBS 2 siblings, 1 reply; 26+ messages in thread From: Nick Clifton @ 2004-12-15 17:11 UTC (permalink / raw) To: Andrew STUBBS; +Cc: 'Alexandre Oliva', binutils, Joern RENNECKE [-- Attachment #1: Type: text/plain, Size: 2408 bytes --] Hi Andrew, Sorry it is so late, but here is another attempt at resolving this problem. Features of this patch include: * I did not try to update the ASCII art in sh-opc.h with the new relationships. In my opinion it just makes the diagram too cluttered to be useful anymore. * I have tried to use more meaningful names for the new machine values. * I have added tests for the new machine values to the SH specific parts of the GAS and LD testsuites. What do you think ? Cheers Nick bfd/ChangeLog 2004-12-15 Nick Clifton <nickc@redhat.com> * archures.c: Rename fake SH2A machine numbers to more helpful versions: bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, bfd_mach_sh2a_nofpu_or_sh3_nommu, bfd_mach_sh2a_or_sh4, bfd_mach_sh2a_or_sh3e. * bfd-in2.h: Regenerate. * cpu-sh.c (arch_info_struct): Add entries for the fake SH2A machine values. (bfd_to_arch_table): Likewise. opcodes/ChangeLog 2004-12-15 Nick Clifton <nickc@redhat.com> * sh-opc.h (arch_sh2a_nofpu_or_sh4_nommu_nofpu, arch_sh2a_nofpu_or_sh3_nommu, arch_sh2a_or_sh4, arch_sh2a_or_sh3e, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up, arch_sh2a_nofpu_or_sh3_nommu_up, arch_sh2a_or_sh4_up, arch_sh2a_or_sh3e_up): New defines. (sh_table): Use the new arch defines to replace entries which previously combined two different arches. include/elf/ChangeLog 2004-12-15 Nick Clifton <nickc@redhat.com> * sh.h (EF_SH2A_SH4_NOFPU, EF_SH2A_SH3_NOFPU, EF_SH2A_SH4, EF_SH2A_SH3E): New flags for fake SH2A machine values. (EF_SH_BFD_TABLE): Add the flags to the table. gas/testsuite/ChangeLog 2004-12-15 Nick Clifton <nickc@redhat.com> * gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s: New test file. * gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s: New test file. * gas/sh/arch/sh2a-or-sh4.s: New test file. * gas/sh/arch/sh2a-or-sh3e.s: New test file. * gas/sh/arch/sh4.s: Fix to use an SH4 only instruction. * gas/sh/arch/arch_expected.txt: Update with new expected test results. ld/testsuite/ChangeLog 2004-12-15 Nick Clifton <nickc@redhat.com> * ld/ld-sh/sh/arch/sh2a-nofpu-or-sh3-nommu.s: New test file. * ld/ld-sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s: New test file. * ld/ld-sh/arch/sh2a-or-sh4.s: New test file. * ld/ld-sh/arch/sh2a-or-sh3e.s: New test file. * ld/ld-sh/arch/sh4.s: Fix to use an SH4 only instruction. * ld/ld-sh/arch/arch_expected.txt: Update with new expected test results. [-- Attachment #2: sh.patch.2 --] [-- Type: text/x-troff-man, Size: 105279 bytes --] Index: bfd/archures.c =================================================================== RCS file: /cvs/src/src/bfd/archures.c,v retrieving revision 1.100 diff -c -3 -p -r1.100 archures.c *** bfd/archures.c 9 Dec 2004 06:08:45 -0000 1.100 --- bfd/archures.c 15 Dec 2004 16:36:28 -0000 *************** DESCRIPTION *** 235,244 **** .#define bfd_mach_sh_dsp 0x2d .#define bfd_mach_sh2a 0x2a .#define bfd_mach_sh2a_nofpu 0x2b ! .#define bfd_mach_sh2a_fake1 0x2a1 ! .#define bfd_mach_sh2a_fake2 0x2a2 ! .#define bfd_mach_sh2a_fake3 0x2a3 ! .#define bfd_mach_sh2a_fake4 0x2a4 .#define bfd_mach_sh2e 0x2e .#define bfd_mach_sh3 0x30 .#define bfd_mach_sh3_nommu 0x31 --- 235,244 ---- .#define bfd_mach_sh_dsp 0x2d .#define bfd_mach_sh2a 0x2a .#define bfd_mach_sh2a_nofpu 0x2b ! .#define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1 ! .#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2 ! .#define bfd_mach_sh2a_or_sh4 0x2a3 ! .#define bfd_mach_sh2a_or_sh3e 0x2a4 .#define bfd_mach_sh2e 0x2e .#define bfd_mach_sh3 0x30 .#define bfd_mach_sh3_nommu 0x31 Index: bfd/bfd-in2.h =================================================================== RCS file: /cvs/src/src/bfd/bfd-in2.h,v retrieving revision 1.309 diff -c -3 -p -r1.309 bfd-in2.h *** bfd/bfd-in2.h 9 Dec 2004 06:08:45 -0000 1.309 --- bfd/bfd-in2.h 15 Dec 2004 16:36:29 -0000 *************** enum bfd_architecture *** 1686,1695 **** #define bfd_mach_sh_dsp 0x2d #define bfd_mach_sh2a 0x2a #define bfd_mach_sh2a_nofpu 0x2b ! #define bfd_mach_sh2a_fake1 0x2a1 ! #define bfd_mach_sh2a_fake2 0x2a2 ! #define bfd_mach_sh2a_fake3 0x2a3 ! #define bfd_mach_sh2a_fake4 0x2a4 #define bfd_mach_sh2e 0x2e #define bfd_mach_sh3 0x30 #define bfd_mach_sh3_nommu 0x31 --- 1686,1695 ---- #define bfd_mach_sh_dsp 0x2d #define bfd_mach_sh2a 0x2a #define bfd_mach_sh2a_nofpu 0x2b ! #define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1 ! #define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2 ! #define bfd_mach_sh2a_or_sh4 0x2a3 ! #define bfd_mach_sh2a_or_sh3e 0x2a4 #define bfd_mach_sh2e 0x2e #define bfd_mach_sh3 0x30 #define bfd_mach_sh3_nommu 0x31 Index: bfd/cpu-sh.c =================================================================== RCS file: /cvs/src/src/bfd/cpu-sh.c,v retrieving revision 1.17 diff -c -3 -p -r1.17 cpu-sh.c *** bfd/cpu-sh.c 13 Aug 2004 03:15:56 -0000 1.17 --- bfd/cpu-sh.c 15 Dec 2004 16:36:29 -0000 *************** *** 24,46 **** #include "libbfd.h" #include "../opcodes/sh-opc.h" ! #define SH_NEXT &arch_info_struct[0] ! #define SH2_NEXT &arch_info_struct[1] ! #define SH2E_NEXT &arch_info_struct[2] ! #define SH_DSP_NEXT &arch_info_struct[3] ! #define SH3_NEXT &arch_info_struct[4] ! #define SH3_NOMMU_NEXT &arch_info_struct[5] ! #define SH3_DSP_NEXT &arch_info_struct[6] ! #define SH3E_NEXT &arch_info_struct[7] ! #define SH4_NEXT &arch_info_struct[8] ! #define SH4A_NEXT &arch_info_struct[9] ! #define SH4AL_DSP_NEXT &arch_info_struct[10] ! #define SH4_NOFPU_NEXT &arch_info_struct[11] ! #define SH4_NOMMU_NOFPU_NEXT &arch_info_struct[12] ! #define SH4A_NOFPU_NEXT &arch_info_struct[13] ! #define SH2A_NEXT &arch_info_struct[14] ! #define SH2A_NOFPU_NEXT &arch_info_struct[15] ! #define SH64_NEXT NULL static const bfd_arch_info_type arch_info_struct[] = { --- 24,50 ---- #include "libbfd.h" #include "../opcodes/sh-opc.h" ! #define SH_NEXT arch_info_struct + 0 ! #define SH2_NEXT arch_info_struct + 1 ! #define SH2E_NEXT arch_info_struct + 2 ! #define SH_DSP_NEXT arch_info_struct + 3 ! #define SH3_NEXT arch_info_struct + 4 ! #define SH3_NOMMU_NEXT arch_info_struct + 5 ! #define SH3_DSP_NEXT arch_info_struct + 6 ! #define SH3E_NEXT arch_info_struct + 7 ! #define SH4_NEXT arch_info_struct + 8 ! #define SH4A_NEXT arch_info_struct + 9 ! #define SH4AL_DSP_NEXT arch_info_struct + 10 ! #define SH4_NOFPU_NEXT arch_info_struct + 11 ! #define SH4_NOMMU_NOFPU_NEXT arch_info_struct + 12 ! #define SH4A_NOFPU_NEXT arch_info_struct + 13 ! #define SH2A_NEXT arch_info_struct + 14 ! #define SH2A_NOFPU_NEXT arch_info_struct + 15 ! #define SH2A_NOFPU_OR_SH4_NOMMU_NOFPU_NEXT arch_info_struct + 16 ! #define SH2A_NOFPU_OR_SH3_NOMMU_NEXT arch_info_struct + 17 ! #define SH2A_OR_SH4_NEXT arch_info_struct + 18 ! #define SH2A_OR_SH3E_NEXT arch_info_struct + 19 ! #define SH64_NEXT NULL static const bfd_arch_info_type arch_info_struct[] = { *************** static const bfd_arch_info_type arch_inf *** 255,260 **** --- 259,320 ---- SH2A_NOFPU_NEXT }, { + 32, /* 32 bits in a word. */ + 32, /* 32 bits in an address. */ + 8, /* 8 bits in a byte. */ + bfd_arch_sh, + bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, + "sh", /* Arch_name. */ + "sh2a-nofpu-or-sh4-nommu-nofpu", /* Printable name. */ + 1, + FALSE, /* Not the default. */ + bfd_default_compatible, + bfd_default_scan, + SH2A_NOFPU_OR_SH4_NOMMU_NOFPU_NEXT + }, + { + 32, /* 32 bits in a word. */ + 32, /* 32 bits in an address. */ + 8, /* 8 bits in a byte. */ + bfd_arch_sh, + bfd_mach_sh2a_nofpu_or_sh3_nommu, + "sh", /* Arch_name. */ + "sh2a-nofpu-or-sh3-nommu", /* Printable name. */ + 1, + FALSE, /* Not the default. */ + bfd_default_compatible, + bfd_default_scan, + SH2A_NOFPU_OR_SH3_NOMMU_NEXT + }, + { + 32, /* 32 bits in a word. */ + 32, /* 32 bits in an address. */ + 8, /* 8 bits in a byte. */ + bfd_arch_sh, + bfd_mach_sh2a_or_sh4, + "sh", /* Arch_name. */ + "sh2a-or-sh4", /* Printable name. */ + 1, + FALSE, /* Not the default. */ + bfd_default_compatible, + bfd_default_scan, + SH2A_OR_SH4_NEXT + }, + { + 32, /* 32 bits in a word. */ + 32, /* 32 bits in an address. */ + 8, /* 8 bits in a byte. */ + bfd_arch_sh, + bfd_mach_sh2a_or_sh3e, + "sh", /* Arch_name. */ + "sh2a-or-sh3e", /* Printable name. */ + 1, + FALSE, /* Not the default. */ + bfd_default_compatible, + bfd_default_scan, + SH2A_OR_SH3E_NEXT + }, + { 64, /* 64 bits in a word */ 64, /* 64 bits in an address */ 8, /* 8 bits in a byte */ *************** static struct { unsigned long bfd_mach, *** 301,306 **** --- 361,372 ---- { bfd_mach_sh_dsp, arch_sh_dsp, arch_sh_dsp_up }, { bfd_mach_sh2a, arch_sh2a, arch_sh2a_up }, { bfd_mach_sh2a_nofpu, arch_sh2a_nofpu, arch_sh2a_nofpu_up }, + + { bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, arch_sh2a_nofpu_or_sh4_nommu_nofpu, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up }, + { bfd_mach_sh2a_nofpu_or_sh3_nommu, arch_sh2a_nofpu_or_sh3_nommu, arch_sh2a_nofpu_or_sh3_nommu_up }, + { bfd_mach_sh2a_or_sh4, arch_sh2a_or_sh4, arch_sh2a_or_sh4_up }, + { bfd_mach_sh2a_or_sh3e, arch_sh2a_or_sh3e, arch_sh2a_or_sh3e_up }, + { bfd_mach_sh3, arch_sh3, arch_sh3_up }, { bfd_mach_sh3_nommu, arch_sh3_nommu, arch_sh3_nommu_up }, { bfd_mach_sh3_dsp, arch_sh3_dsp, arch_sh3_dsp_up }, Index: opcodes/sh-opc.h =================================================================== RCS file: /cvs/src/src/opcodes/sh-opc.h,v retrieving revision 1.22 diff -c -3 -p -r1.22 sh-opc.h *** opcodes/sh-opc.h 29 Jul 2004 05:19:27 -0000 1.22 --- opcodes/sh-opc.h 15 Dec 2004 16:36:31 -0000 *************** sh_dsp_reg_nums; *** 223,244 **** #define arch_sh_co_mask 0xf0000000 ! #define arch_sh1 (arch_sh1_base|arch_sh_no_mmu|arch_sh_no_co) ! #define arch_sh2 (arch_sh2_base|arch_sh_no_mmu|arch_sh_no_co) ! #define arch_sh2a (arch_sh2a_base|arch_sh_no_mmu|arch_sh_dp_fpu) ! #define arch_sh2a_nofpu (arch_sh2a_base|arch_sh_no_mmu|arch_sh_no_co) ! #define arch_sh2e (arch_sh2_base|arch_sh2a_base|arch_sh_no_mmu|arch_sh_sp_fpu) ! #define arch_sh_dsp (arch_sh2_base|arch_sh_no_mmu|arch_sh_has_dsp) ! #define arch_sh3_nommu (arch_sh3_base|arch_sh_no_mmu|arch_sh_no_co) ! #define arch_sh3 (arch_sh3_base|arch_sh_has_mmu|arch_sh_no_co) ! #define arch_sh3e (arch_sh3_base|arch_sh_has_mmu|arch_sh_sp_fpu) ! #define arch_sh3_dsp (arch_sh3_base|arch_sh_has_mmu|arch_sh_has_dsp) ! #define arch_sh4 (arch_sh4_base|arch_sh_has_mmu|arch_sh_dp_fpu) ! #define arch_sh4a (arch_sh4a_base|arch_sh_has_mmu|arch_sh_dp_fpu) ! #define arch_sh4al_dsp (arch_sh4a_base|arch_sh_has_mmu|arch_sh_has_dsp) ! #define arch_sh4_nofpu (arch_sh4_base|arch_sh_has_mmu|arch_sh_no_co) ! #define arch_sh4a_nofpu (arch_sh4a_base|arch_sh_has_mmu|arch_sh_no_co) ! #define arch_sh4_nommu_nofpu (arch_sh4_base|arch_sh_no_mmu|arch_sh_no_co) #define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2)) #define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0) --- 223,248 ---- #define arch_sh_co_mask 0xf0000000 ! #define arch_sh1 (arch_sh1_base | arch_sh_no_mmu |arch_sh_no_co) ! #define arch_sh2 (arch_sh2_base | arch_sh_no_mmu |arch_sh_no_co) ! #define arch_sh2a (arch_sh2a_base| arch_sh_no_mmu |arch_sh_dp_fpu) ! #define arch_sh2a_nofpu (arch_sh2a_base| arch_sh_no_mmu |arch_sh_no_co) ! #define arch_sh2e (arch_sh2_base |arch_sh2a_base|arch_sh_no_mmu |arch_sh_sp_fpu) ! #define arch_sh_dsp (arch_sh2_base | arch_sh_no_mmu |arch_sh_has_dsp) ! #define arch_sh3_nommu (arch_sh3_base | arch_sh_no_mmu |arch_sh_no_co) ! #define arch_sh3 (arch_sh3_base | arch_sh_has_mmu|arch_sh_no_co) ! #define arch_sh3e (arch_sh3_base | arch_sh_has_mmu|arch_sh_sp_fpu) ! #define arch_sh3_dsp (arch_sh3_base | arch_sh_has_mmu|arch_sh_has_dsp) ! #define arch_sh4 (arch_sh4_base | arch_sh_has_mmu|arch_sh_dp_fpu) ! #define arch_sh4a (arch_sh4a_base| arch_sh_has_mmu|arch_sh_dp_fpu) ! #define arch_sh4al_dsp (arch_sh4a_base| arch_sh_has_mmu|arch_sh_has_dsp) ! #define arch_sh4_nofpu (arch_sh4_base | arch_sh_has_mmu|arch_sh_no_co) ! #define arch_sh4a_nofpu (arch_sh4a_base| arch_sh_has_mmu|arch_sh_no_co) ! #define arch_sh4_nommu_nofpu (arch_sh4_base | arch_sh_no_mmu |arch_sh_no_co) ! #define arch_sh2a_nofpu_or_sh4_nommu_nofpu (arch_sh2a_base|arch_sh4_base |arch_sh_no_mmu |arch_sh_no_co) ! #define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_base|arch_sh3_base |arch_sh_no_mmu |arch_sh_no_co) ! #define arch_sh2a_or_sh4 (arch_sh4_base |arch_sh4_base | arch_sh_dp_fpu) ! #define arch_sh2a_or_sh3e (arch_sh2a_base|arch_sh3_base) #define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2)) #define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0) *************** SH3-dsp SH4-nofpu *** 293,323 **** |/ \| SH4AL-dsp SH4A */ ! /* Central branches */ ! #define arch_sh1_up (arch_sh1 | arch_sh2_up) ! #define arch_sh2_up (arch_sh2 | arch_sh2e_up | arch_sh2a_nofpu_up | arch_sh3_nommu_up | arch_sh_dsp_up) ! #define arch_sh3_nommu_up (arch_sh3_nommu | arch_sh3_up | arch_sh4_nommu_nofpu_up) ! #define arch_sh3_up (arch_sh3 | arch_sh3e_up | arch_sh3_dsp_up | arch_sh4_nofp_up) ! #define arch_sh4_nommu_nofpu_up (arch_sh4_nommu_nofpu | arch_sh4_nofp_up) ! #define arch_sh4_nofp_up (arch_sh4_nofpu | arch_sh4_up | arch_sh4a_nofp_up) ! #define arch_sh4a_nofp_up (arch_sh4a_nofpu | arch_sh4a_up | arch_sh4al_dsp_up) ! ! /* Right branch */ ! #define arch_sh2e_up (arch_sh2e | arch_sh2a_up | arch_sh3e_up) ! #define arch_sh3e_up (arch_sh3e | arch_sh4_up) ! #define arch_sh4_up (arch_sh4 | arch_sh4a_up) ! #define arch_sh4a_up (arch_sh4a) ! ! /* Left branch */ ! #define arch_sh_dsp_up (arch_sh_dsp | arch_sh3_dsp_up) ! #define arch_sh3_dsp_up (arch_sh3_dsp | arch_sh4al_dsp_up) ! #define arch_sh4al_dsp_up (arch_sh4al_dsp) ! /* SH 2a branched off SH2e, adding a lot but not all of SH4 and SH4a. */ ! #define arch_sh2a_up (arch_sh2a) ! #define arch_sh2a_nofpu_up (arch_sh2a_nofpu | arch_sh2a_up) typedef struct --- 297,330 ---- |/ \| SH4AL-dsp SH4A + Note: The branches for the SH2A are not shown on this + diagram as they would needlessly complicate it. */ ! /* Central branches. */ ! #define arch_sh1_up (arch_sh1 | arch_sh2_up) ! #define arch_sh2_up (arch_sh2 | arch_sh2e_up | arch_sh2a_nofpu_or_sh3_nommu_up | arch_sh_dsp_up) ! #define arch_sh3_nommu_up (arch_sh3_nommu | arch_sh3_up | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up) ! #define arch_sh3_up (arch_sh3 | arch_sh2a_or_sh3e_up | arch_sh3_dsp_up | arch_sh4_nofp_up) ! #define arch_sh4_nommu_nofpu_up (arch_sh4_nommu_nofpu | arch_sh4_nofp_up) ! #define arch_sh4_nofp_up (arch_sh4_nofpu | arch_sh4_up | arch_sh4a_nofp_up) ! #define arch_sh4a_nofp_up (arch_sh4a_nofpu | arch_sh4a_up | arch_sh4al_dsp_up) ! /* Right branch. */ ! #define arch_sh2e_up (arch_sh2e | arch_sh2a_or_sh3e_up) ! #define arch_sh3e_up (arch_sh3e | arch_sh2a_or_sh4_up) ! #define arch_sh4_up (arch_sh4 | arch_sh4a_up) ! #define arch_sh4a_up (arch_sh4a) ! /* Left branch. */ ! #define arch_sh_dsp_up (arch_sh_dsp | arch_sh3_dsp_up) ! #define arch_sh3_dsp_up (arch_sh3_dsp | arch_sh4al_dsp_up) ! #define arch_sh4al_dsp_up (arch_sh4al_dsp) /* SH 2a branched off SH2e, adding a lot but not all of SH4 and SH4a. */ ! #define arch_sh2a_up (arch_sh2a) ! #define arch_sh2a_nofpu_up (arch_sh2a_nofpu | arch_sh2a_up) ! #define arch_sh2a_nofpu_or_sh4_nommu_nofpu_up (arch_sh2a_nofpu_or_sh4_nommu_nofpu | arch_sh2a_nofpu_up | arch_sh4_nommu_nofpu_up) ! #define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu | arch_sh2a_nofpu_up | arch_sh3_nommu_up) ! #define arch_sh2a_or_sh4_up (arch_sh2a_or_sh4 | arch_sh2a_up | arch_sh4_up) ! #define arch_sh2a_or_sh3e_up (arch_sh2a_or_sh3e | arch_sh2a_up | arch_sh3e_up) typedef struct *************** const sh_opcode_info sh_table[] = *** 634,640 **** /* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh1_up}, ! /* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh4_nommu_nofpu_up | arch_sh2a_nofpu_up}, /* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofp_up}, --- 641,647 ---- /* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh1_up}, ! /* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}, /* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofp_up}, *************** const sh_opcode_info sh_table[] = *** 664,672 **** /* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}, ! /* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh3_nommu_up | arch_sh2a_nofpu_up}, ! /* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh3_nommu_up | arch_sh2a_nofpu_up}, /* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh1_up}, --- 671,679 ---- /* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}, ! /* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}, ! /* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}, /* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh1_up}, *************** const sh_opcode_info sh_table[] = *** 985,1007 **** {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}, /* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}, ! /* 1111nnn001011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}, ! /* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}, ! /* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}, ! /* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh4_up | arch_sh2a_up}, ! /* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh4_up | arch_sh2a_up}, ! /* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}, ! /* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh4_up | arch_sh2a_up}, /* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up}, --- 992,1014 ---- {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}, /* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}, ! /* 1111nnn001011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2a_or_sh4_up}, /* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}, ! /* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2a_or_sh4_up}, /* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}, ! /* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up}, /* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}, ! /* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_or_sh4_up}, ! /* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh2a_or_sh4_up}, ! /* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh2a_or_sh4_up}, /* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}, ! /* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2a_or_sh4_up}, /* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up}, *************** const sh_opcode_info sh_table[] = *** 1012,1053 **** /* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}, /* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}, ! /* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}, /* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}, ! /* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}, ! /* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}, ! /* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}, ! /* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}, ! /* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}, ! /* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}, ! /* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up | arch_sh2a_up}, ! ! /* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up | arch_sh2a_up}, ! ! /* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up | arch_sh2a_up}, ! ! /* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up | arch_sh2a_up}, ! ! /* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up | arch_sh2a_up}, ! ! /* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up | arch_sh2a_up}, ! /* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up | arch_sh2a_up}, /* 0011nnnnmmmm0001 0011dddddddddddd fmov.d <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.d",{DX_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY8}, arch_sh2a_up | arch_op32}, /* 0011nnnnmmmm0001 0111dddddddddddd fmov.d @(<DISP12>,<REG_M>),F_REG_N */ --- 1019,1055 ---- /* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}, /* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}, ! /* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2a_or_sh4_up}, /* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}, /* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}, ! /* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2a_or_sh4_up}, /* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}, ! /* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}, /* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}, ! /* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}, /* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}, ! /* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}, /* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}, ! /* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}, /* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}, ! /* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}, /* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}, ! /* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}, ! /* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}, ! /* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}, ! /* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}, ! /* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}, ! /* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}, ! /* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}, /* 0011nnnnmmmm0001 0011dddddddddddd fmov.d <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.d",{DX_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY8}, arch_sh2a_up | arch_op32}, /* 0011nnnnmmmm0001 0111dddddddddddd fmov.d @(<DISP12>,<REG_M>),F_REG_N */ *************** const sh_opcode_info sh_table[] = *** 1070,1079 **** {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}, /* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}, ! /* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}, ! /* 1111nnn001001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh4_up | arch_sh2a_up}, /* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}, --- 1072,1081 ---- {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}, /* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}, ! /* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2a_or_sh4_up}, /* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}, ! /* 1111nnn001001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2a_or_sh4_up}, /* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}, *************** const sh_opcode_info sh_table[] = *** 1081,1100 **** /* 1111nnn011111101 fsca FPUL,<D_REG_N> */{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_F,HEX_D}, arch_sh4_up}, ! /* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh4_up | arch_sh2a_up}, ! /* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh3e_up | arch_sh2a_up}, ! /* 1111nnn001101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}, /* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}, /* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}, ! /* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}, ! /* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh4_up | arch_sh2a_up}, /* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}, --- 1083,1102 ---- /* 1111nnn011111101 fsca FPUL,<D_REG_N> */{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_F,HEX_D}, arch_sh4_up}, ! /* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh2a_or_sh4_up}, ! /* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}, ! /* 1111nnn001101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh4_up}, /* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}, /* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}, /* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}, ! /* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}, /* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}, ! /* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}, /* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}, Index: include/elf/sh.h =================================================================== RCS file: /cvs/src/src/include/elf/sh.h,v retrieving revision 1.19 diff -c -3 -p -r1.19 sh.h *** include/elf/sh.h 29 Jul 2004 05:17:37 -0000 1.19 --- include/elf/sh.h 15 Dec 2004 16:36:31 -0000 *************** *** 42,47 **** --- 42,52 ---- #define EF_SH2A_NOFPU 19 #define EF_SH3_NOMMU 20 + #define EF_SH2A_SH4_NOFPU 21 + #define EF_SH2A_SH3_NOFPU 22 + #define EF_SH2A_SH4 23 + #define EF_SH2A_SH3E 24 + /* This one can only mix in objects from other EF_SH5 objects. */ #define EF_SH5 10 *************** *** 68,74 **** /* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \ /* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \ /* EF_SH2A_NOFPU */ bfd_mach_sh2a_nofpu , \ ! /* EF_SH3_NOMMU */ bfd_mach_sh3_nommu /* Convert arch_sh* into EF_SH*. */ int sh_find_elf_flags (unsigned int arch_set); --- 73,83 ---- /* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \ /* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \ /* EF_SH2A_NOFPU */ bfd_mach_sh2a_nofpu , \ ! /* EF_SH3_NOMMU */ bfd_mach_sh3_nommu , \ ! /* EF_SH2A_SH4_NOFPU */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \ ! /* EF_SH2A_SH3_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \ ! /* EF_SH2A_SH4 */ bfd_mach_sh2a_or_sh4 , \ ! /* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e /* Convert arch_sh* into EF_SH*. */ int sh_find_elf_flags (unsigned int arch_set); *** /dev/null 2004-06-24 19:04:38.000000000 +0100 --- gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2004-12-15 15:43:37.000000000 +0000 *************** *** 0 **** --- 1,3 ---- + .section .text + sh2a_nofpu_or_sh3_nommu: + shad r3, r4 *** /dev/null 2004-06-24 19:04:38.000000000 +0100 --- gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2004-12-15 15:45:26.000000000 +0000 *************** *** 0 **** --- 1,3 ---- + .section .text + sh2a_nofpu_or_sh4_nommu_nofpu: + pref @r3 *** /dev/null 2004-06-24 19:04:38.000000000 +0100 --- gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2004-12-15 15:46:02.000000000 +0000 *************** *** 0 **** --- 1,3 ---- + .section .text + sh2a_or_sh3e: + fsqrt fr3 *** /dev/null 2004-06-24 19:04:38.000000000 +0100 --- gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2004-12-15 15:46:26.000000000 +0000 *************** *** 0 **** --- 1,3 ---- + .section .text + sh2a_or_sh4: + fcnvsd fpul, dr4 *** /dev/null 2004-06-24 19:04:38.000000000 +0100 --- ld/testsuite/ld-sh/arch/sh2a-nofpu-or-sh3-nommu.s 2004-12-15 15:49:55.000000000 +0000 *************** *** 0 **** --- 1,3 ---- + .section .text + sh2a_nofpu_or_sh3_nommu: + shad r3, r4 *** /dev/null 2004-06-24 19:04:38.000000000 +0100 --- ld/testsuite/ld-sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2004-12-15 15:49:55.000000000 +0000 *************** *** 0 **** --- 1,3 ---- + .section .text + sh2a_nofpu_or_sh4_nommu_nofpu: + pref @r3 *** /dev/null 2004-06-24 19:04:38.000000000 +0100 --- ld/testsuite/ld-sh/arch/sh2a-or-sh3e.s 2004-12-15 15:49:55.000000000 +0000 *************** *** 0 **** --- 1,3 ---- + .section .text + sh2a_or_sh3e: + fsqrt fr3 *** /dev/null 2004-06-24 19:04:38.000000000 +0100 --- ld/testsuite/ld-sh/arch/sh2a-or-sh4.s 2004-12-15 15:49:55.000000000 +0000 *************** *** 0 **** --- 1,3 ---- + .section .text + sh2a_or_sh4: + fcnvsd fpul, dr4 Index: gas/testsuite/gas/sh/arch/arch_expected.txt =================================================================== RCS file: /cvs/src/src/gas/testsuite/gas/sh/arch/arch_expected.txt,v retrieving revision 1.1 diff -c -3 -p -r1.1 arch_expected.txt *** gas/testsuite/gas/sh/arch/arch_expected.txt 29 Jun 2004 16:35:05 -0000 1.1 --- gas/testsuite/gas/sh/arch/arch_expected.txt 15 Dec 2004 16:36:27 -0000 *************** sh-dsp.s -isa=sh *** 21,26 **** --- 21,34 ---- sh-dsp.s -isa=sh-up sh-dsp sh-dsp.s -isa=sh2 ERROR sh-dsp.s -isa=sh2-up sh-dsp + sh-dsp.s -isa=sh2a-nofpu-or-sh3-nommu ERROR + sh-dsp.s -isa=sh2a-nofpu-or-sh3-nommu-up sh3-dsp + sh-dsp.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR + sh-dsp.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4al-dsp + sh-dsp.s -isa=sh2a-or-sh3e ERROR + sh-dsp.s -isa=sh2a-or-sh3e-up ERROR + sh-dsp.s -isa=sh2a-or-sh4 ERROR + sh-dsp.s -isa=sh2a-or-sh4-up ERROR sh-dsp.s -isa=sh2e ERROR sh-dsp.s -isa=sh2e-up ERROR sh-dsp.s -isa=sh3-dsp sh3-dsp *************** sh.s -isa=sh *** 54,69 **** sh.s -isa=sh-up sh sh.s -isa=sh2 sh2 sh.s -isa=sh2-up sh2 sh.s -isa=sh2e sh2e sh.s -isa=sh2e-up sh2e sh.s -isa=sh3-dsp sh3-dsp sh.s -isa=sh3-dsp-up sh3-dsp ! sh.s -isa=sh3-nommu sh3-nommu ! sh.s -isa=sh3-nommu-up sh3-nommu ! sh.s -isa=sh3 sh3 ! sh.s -isa=sh3-up sh3 ! sh.s -isa=sh3e sh3e ! sh.s -isa=sh3e-up sh3e sh.s -isa=sh4-nofpu sh4-nofpu sh.s -isa=sh4-nofpu-up sh4-nofpu sh.s -isa=sh4-nommu-nofpu sh4-nommu-nofpu --- 62,85 ---- sh.s -isa=sh-up sh sh.s -isa=sh2 sh2 sh.s -isa=sh2-up sh2 + sh.s -isa=sh2a-nofpu-or-sh3-nommu sh2a-nofpu + sh.s -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-nofpu-or-sh3-nommu + sh.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu sh2a-nofpu + sh.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-nofpu-or-sh4-nommu-nofpu + sh.s -isa=sh2a-or-sh3e ERROR + sh.s -isa=sh2a-or-sh3e-up sh2a-or-sh3e + sh.s -isa=sh2a-or-sh4 ERROR + sh.s -isa=sh2a-or-sh4-up sh2a-or-sh4 sh.s -isa=sh2e sh2e sh.s -isa=sh2e-up sh2e sh.s -isa=sh3-dsp sh3-dsp sh.s -isa=sh3-dsp-up sh3-dsp ! sh.s -isa=sh3-nommu sh2a-nofpu-or-sh3-nommu ! sh.s -isa=sh3-nommu-up sh2a-nofpu-or-sh3-nommu ! sh.s -isa=sh3 sh2a-nofpu-or-sh3-nommu ! sh.s -isa=sh3-up sh2a-nofpu-or-sh3-nommu ! sh.s -isa=sh3e sh2a-or-sh3e ! sh.s -isa=sh3e-up sh2a-or-sh3e sh.s -isa=sh4-nofpu sh4-nofpu sh.s -isa=sh4-nofpu-up sh4-nofpu sh.s -isa=sh4-nommu-nofpu sh4-nommu-nofpu *************** sh2.s -isa=sh *** 87,102 **** sh2.s -isa=sh-up sh2 sh2.s -isa=sh2 sh2 sh2.s -isa=sh2-up sh2 sh2.s -isa=sh2e sh2e sh2.s -isa=sh2e-up sh2e sh2.s -isa=sh3-dsp sh3-dsp sh2.s -isa=sh3-dsp-up sh3-dsp ! sh2.s -isa=sh3-nommu sh3-nommu ! sh2.s -isa=sh3-nommu-up sh3-nommu ! sh2.s -isa=sh3 sh3 ! sh2.s -isa=sh3-up sh3 ! sh2.s -isa=sh3e sh3e ! sh2.s -isa=sh3e-up sh3e sh2.s -isa=sh4-nofpu sh4-nofpu sh2.s -isa=sh4-nofpu-up sh4-nofpu sh2.s -isa=sh4-nommu-nofpu sh4-nommu-nofpu --- 103,126 ---- sh2.s -isa=sh-up sh2 sh2.s -isa=sh2 sh2 sh2.s -isa=sh2-up sh2 + sh2.s -isa=sh2a-nofpu-or-sh3-nommu sh2a-nofpu + sh2.s -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-nofpu-or-sh3-nommu + sh2.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu sh2a-nofpu + sh2.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-nofpu-or-sh4-nommu-nofpu + sh2.s -isa=sh2a-or-sh3e ERROR + sh2.s -isa=sh2a-or-sh3e-up sh2a-or-sh3e + sh2.s -isa=sh2a-or-sh4 ERROR + sh2.s -isa=sh2a-or-sh4-up sh2a-or-sh4 sh2.s -isa=sh2e sh2e sh2.s -isa=sh2e-up sh2e sh2.s -isa=sh3-dsp sh3-dsp sh2.s -isa=sh3-dsp-up sh3-dsp ! sh2.s -isa=sh3-nommu sh2a-nofpu-or-sh3-nommu ! sh2.s -isa=sh3-nommu-up sh2a-nofpu-or-sh3-nommu ! sh2.s -isa=sh3 sh2a-nofpu-or-sh3-nommu ! sh2.s -isa=sh3-up sh2a-nofpu-or-sh3-nommu ! sh2.s -isa=sh3e sh2a-or-sh3e ! sh2.s -isa=sh3e-up sh2a-or-sh3e sh2.s -isa=sh4-nofpu sh4-nofpu sh2.s -isa=sh4-nofpu-up sh4-nofpu sh2.s -isa=sh4-nommu-nofpu sh4-nommu-nofpu *************** sh2.s -isa=sh4a *** 109,114 **** --- 133,302 ---- sh2.s -isa=sh4a-up sh4a sh2.s -isa=sh4al-dsp sh4al-dsp sh2.s -isa=sh4al-dsp-up sh4al-dsp + sh2a-nofpu-or-sh3-nommu.s default-options sh2a-nofpu-or-sh3-nommu + sh2a-nofpu-or-sh3-nommu.s -dsp sh2a-nofpu-or-sh3-nommu + sh2a-nofpu-or-sh3-nommu.s -isa=any sh2a-nofpu-or-sh3-nommu + sh2a-nofpu-or-sh3-nommu.s -isa=dsp sh2a-nofpu-or-sh3-nommu + sh2a-nofpu-or-sh3-nommu.s -isa=fp sh2a-nofpu-or-sh3-nommu + sh2a-nofpu-or-sh3-nommu.s -isa=sh-dsp ERROR + sh2a-nofpu-or-sh3-nommu.s -isa=sh-dsp-up sh3-dsp + sh2a-nofpu-or-sh3-nommu.s -isa=sh ERROR + sh2a-nofpu-or-sh3-nommu.s -isa=sh-up sh2a-nofpu-or-sh3-nommu + sh2a-nofpu-or-sh3-nommu.s -isa=sh2 ERROR + sh2a-nofpu-or-sh3-nommu.s -isa=sh2-up sh2a-nofpu-or-sh3-nommu + sh2a-nofpu-or-sh3-nommu.s -isa=sh2a-nofpu-or-sh3-nommu sh2a-nofpu + sh2a-nofpu-or-sh3-nommu.s -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-nofpu-or-sh3-nommu + sh2a-nofpu-or-sh3-nommu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu sh2a-nofpu + sh2a-nofpu-or-sh3-nommu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-nofpu-or-sh4-nommu-nofpu + sh2a-nofpu-or-sh3-nommu.s -isa=sh2a-or-sh3e ERROR + sh2a-nofpu-or-sh3-nommu.s -isa=sh2a-or-sh3e-up sh2a-or-sh3e + sh2a-nofpu-or-sh3-nommu.s -isa=sh2a-or-sh4 ERROR + sh2a-nofpu-or-sh3-nommu.s -isa=sh2a-or-sh4-up sh2a-or-sh4 + sh2a-nofpu-or-sh3-nommu.s -isa=sh2e sh2a-or-sh3e + sh2a-nofpu-or-sh3-nommu.s -isa=sh2e-up sh2a-or-sh3e + sh2a-nofpu-or-sh3-nommu.s -isa=sh3-dsp sh3-dsp + sh2a-nofpu-or-sh3-nommu.s -isa=sh3-dsp-up sh3-dsp + sh2a-nofpu-or-sh3-nommu.s -isa=sh3-nommu sh2a-nofpu-or-sh3-nommu + sh2a-nofpu-or-sh3-nommu.s -isa=sh3-nommu-up sh2a-nofpu-or-sh3-nommu + sh2a-nofpu-or-sh3-nommu.s -isa=sh3 sh2a-nofpu-or-sh3-nommu + sh2a-nofpu-or-sh3-nommu.s -isa=sh3-up sh2a-nofpu-or-sh3-nommu + sh2a-nofpu-or-sh3-nommu.s -isa=sh3e sh2a-or-sh3e + sh2a-nofpu-or-sh3-nommu.s -isa=sh3e-up sh2a-or-sh3e + sh2a-nofpu-or-sh3-nommu.s -isa=sh4-nofpu sh4-nofpu + sh2a-nofpu-or-sh3-nommu.s -isa=sh4-nofpu-up sh4-nofpu + sh2a-nofpu-or-sh3-nommu.s -isa=sh4-nommu-nofpu sh4-nommu-nofpu + sh2a-nofpu-or-sh3-nommu.s -isa=sh4-nommu-nofpu-up sh4-nommu-nofpu + sh2a-nofpu-or-sh3-nommu.s -isa=sh4 sh4 + sh2a-nofpu-or-sh3-nommu.s -isa=sh4-up sh4 + sh2a-nofpu-or-sh3-nommu.s -isa=sh4a-nofpu sh4a-nofpu + sh2a-nofpu-or-sh3-nommu.s -isa=sh4a-nofpu-up sh4a-nofpu + sh2a-nofpu-or-sh3-nommu.s -isa=sh4a sh4a + sh2a-nofpu-or-sh3-nommu.s -isa=sh4a-up sh4a + sh2a-nofpu-or-sh3-nommu.s -isa=sh4al-dsp sh4al-dsp + sh2a-nofpu-or-sh3-nommu.s -isa=sh4al-dsp-up sh4al-dsp + sh2a-nofpu-or-sh4-nommu-nofpu.s default-options sh2a-nofpu-or-sh4-nommu-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -dsp sh2a-nofpu-or-sh4-nommu-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=any sh2a-nofpu-or-sh4-nommu-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=dsp sh2a-nofpu-or-sh4-nommu-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=fp sh2a-nofpu-or-sh4-nommu-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh-dsp ERROR + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh-dsp-up sh4al-dsp + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh ERROR + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh-up sh2a-nofpu-or-sh4-nommu-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2 ERROR + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2-up sh2a-nofpu-or-sh4-nommu-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a-nofpu-or-sh3-nommu sh2a-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-nofpu-or-sh4-nommu-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu sh2a-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-nofpu-or-sh4-nommu-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a-or-sh3e ERROR + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a-or-sh3e-up sh2a-or-sh4 + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a-or-sh4 ERROR + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a-or-sh4-up sh2a-or-sh4 + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2e ERROR + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2e-up sh2a-or-sh4 + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh3-dsp ERROR + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh3-dsp-up sh4al-dsp + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh3-nommu ERROR + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh3-nommu-up sh2a-nofpu-or-sh4-nommu-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh3 ERROR + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh3-up sh2a-nofpu-or-sh4-nommu-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh3e ERROR + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh3e-up sh2a-or-sh4 + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4-nofpu sh4-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4-nofpu-up sh4-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4-nommu-nofpu sh4-nommu-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4-nommu-nofpu-up sh4-nommu-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4 sh4 + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4-up sh4 + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4a-nofpu sh4a-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4a-nofpu-up sh4a-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4a sh4a + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4a-up sh4a + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4al-dsp sh4al-dsp + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4al-dsp-up sh4al-dsp + sh2a-or-sh3e.s default-options sh2a-or-sh3e + sh2a-or-sh3e.s -dsp ERROR + sh2a-or-sh3e.s -isa=any sh2a-or-sh3e + sh2a-or-sh3e.s -isa=dsp ERROR + sh2a-or-sh3e.s -isa=fp sh2a-or-sh3e + sh2a-or-sh3e.s -isa=sh-dsp ERROR + sh2a-or-sh3e.s -isa=sh-dsp-up ERROR + sh2a-or-sh3e.s -isa=sh ERROR + sh2a-or-sh3e.s -isa=sh-up sh2a-or-sh3e + sh2a-or-sh3e.s -isa=sh2 ERROR + sh2a-or-sh3e.s -isa=sh2-up sh2a-or-sh3e + sh2a-or-sh3e.s -isa=sh2a-nofpu-or-sh3-nommu ERROR + sh2a-or-sh3e.s -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-or-sh3e + sh2a-or-sh3e.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR + sh2a-or-sh3e.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-or-sh4 + sh2a-or-sh3e.s -isa=sh2a-or-sh3e ERROR + sh2a-or-sh3e.s -isa=sh2a-or-sh3e-up sh2a-or-sh3e + sh2a-or-sh3e.s -isa=sh2a-or-sh4 ERROR + sh2a-or-sh3e.s -isa=sh2a-or-sh4-up sh2a-or-sh4 + sh2a-or-sh3e.s -isa=sh2e sh2a-or-sh3e + sh2a-or-sh3e.s -isa=sh2e-up sh2a-or-sh3e + sh2a-or-sh3e.s -isa=sh3-dsp ERROR + sh2a-or-sh3e.s -isa=sh3-dsp-up ERROR + sh2a-or-sh3e.s -isa=sh3-nommu ERROR + sh2a-or-sh3e.s -isa=sh3-nommu-up sh2a-or-sh3e + sh2a-or-sh3e.s -isa=sh3 ERROR + sh2a-or-sh3e.s -isa=sh3-up sh2a-or-sh3e + sh2a-or-sh3e.s -isa=sh3e sh2a-or-sh3e + sh2a-or-sh3e.s -isa=sh3e-up sh2a-or-sh3e + sh2a-or-sh3e.s -isa=sh4-nofpu ERROR + sh2a-or-sh3e.s -isa=sh4-nofpu-up sh4 + sh2a-or-sh3e.s -isa=sh4-nommu-nofpu ERROR + sh2a-or-sh3e.s -isa=sh4-nommu-nofpu-up sh4 + sh2a-or-sh3e.s -isa=sh4 sh4 + sh2a-or-sh3e.s -isa=sh4-up sh4 + sh2a-or-sh3e.s -isa=sh4a-nofpu ERROR + sh2a-or-sh3e.s -isa=sh4a-nofpu-up sh4a + sh2a-or-sh3e.s -isa=sh4a sh4a + sh2a-or-sh3e.s -isa=sh4a-up sh4a + sh2a-or-sh3e.s -isa=sh4al-dsp ERROR + sh2a-or-sh3e.s -isa=sh4al-dsp-up ERROR + sh2a-or-sh4.s default-options sh2a-or-sh4 + sh2a-or-sh4.s -dsp ERROR + sh2a-or-sh4.s -isa=any sh2a-or-sh4 + sh2a-or-sh4.s -isa=dsp ERROR + sh2a-or-sh4.s -isa=fp sh2a-or-sh4 + sh2a-or-sh4.s -isa=sh-dsp ERROR + sh2a-or-sh4.s -isa=sh-dsp-up ERROR + sh2a-or-sh4.s -isa=sh ERROR + sh2a-or-sh4.s -isa=sh-up sh2a-or-sh4 + sh2a-or-sh4.s -isa=sh2 ERROR + sh2a-or-sh4.s -isa=sh2-up sh2a-or-sh4 + sh2a-or-sh4.s -isa=sh2a-nofpu-or-sh3-nommu ERROR + sh2a-or-sh4.s -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-or-sh4 + sh2a-or-sh4.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR + sh2a-or-sh4.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-or-sh4 + sh2a-or-sh4.s -isa=sh2a-or-sh3e ERROR + sh2a-or-sh4.s -isa=sh2a-or-sh3e-up sh2a-or-sh4 + sh2a-or-sh4.s -isa=sh2a-or-sh4 ERROR + sh2a-or-sh4.s -isa=sh2a-or-sh4-up sh2a-or-sh4 + sh2a-or-sh4.s -isa=sh2e ERROR + sh2a-or-sh4.s -isa=sh2e-up sh2a-or-sh4 + sh2a-or-sh4.s -isa=sh3-dsp ERROR + sh2a-or-sh4.s -isa=sh3-dsp-up ERROR + sh2a-or-sh4.s -isa=sh3-nommu ERROR + sh2a-or-sh4.s -isa=sh3-nommu-up sh2a-or-sh4 + sh2a-or-sh4.s -isa=sh3 ERROR + sh2a-or-sh4.s -isa=sh3-up sh2a-or-sh4 + sh2a-or-sh4.s -isa=sh3e ERROR + sh2a-or-sh4.s -isa=sh3e-up sh2a-or-sh4 + sh2a-or-sh4.s -isa=sh4-nofpu ERROR + sh2a-or-sh4.s -isa=sh4-nofpu-up sh4 + sh2a-or-sh4.s -isa=sh4-nommu-nofpu ERROR + sh2a-or-sh4.s -isa=sh4-nommu-nofpu-up sh4 + sh2a-or-sh4.s -isa=sh4 sh4 + sh2a-or-sh4.s -isa=sh4-up sh4 + sh2a-or-sh4.s -isa=sh4a-nofpu ERROR + sh2a-or-sh4.s -isa=sh4a-nofpu-up sh4a + sh2a-or-sh4.s -isa=sh4a sh4a + sh2a-or-sh4.s -isa=sh4a-up sh4a + sh2a-or-sh4.s -isa=sh4al-dsp ERROR + sh2a-or-sh4.s -isa=sh4al-dsp-up ERROR sh2e.s default-options sh2e sh2e.s -dsp ERROR sh2e.s -isa=any sh2e *************** sh2e.s -isa=sh *** 120,135 **** sh2e.s -isa=sh-up sh2e sh2e.s -isa=sh2 ERROR sh2e.s -isa=sh2-up sh2e sh2e.s -isa=sh2e sh2e sh2e.s -isa=sh2e-up sh2e sh2e.s -isa=sh3-dsp ERROR sh2e.s -isa=sh3-dsp-up ERROR sh2e.s -isa=sh3-nommu ERROR ! sh2e.s -isa=sh3-nommu-up sh3e sh2e.s -isa=sh3 ERROR ! sh2e.s -isa=sh3-up sh3e ! sh2e.s -isa=sh3e sh3e ! sh2e.s -isa=sh3e-up sh3e sh2e.s -isa=sh4-nofpu ERROR sh2e.s -isa=sh4-nofpu-up sh4 sh2e.s -isa=sh4-nommu-nofpu ERROR --- 308,331 ---- sh2e.s -isa=sh-up sh2e sh2e.s -isa=sh2 ERROR sh2e.s -isa=sh2-up sh2e + sh2e.s -isa=sh2a-nofpu-or-sh3-nommu ERROR + sh2e.s -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-or-sh3e + sh2e.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR + sh2e.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-or-sh4 + sh2e.s -isa=sh2a-or-sh3e ERROR + sh2e.s -isa=sh2a-or-sh3e-up sh2a-or-sh3e + sh2e.s -isa=sh2a-or-sh4 ERROR + sh2e.s -isa=sh2a-or-sh4-up sh2a-or-sh4 sh2e.s -isa=sh2e sh2e sh2e.s -isa=sh2e-up sh2e sh2e.s -isa=sh3-dsp ERROR sh2e.s -isa=sh3-dsp-up ERROR sh2e.s -isa=sh3-nommu ERROR ! sh2e.s -isa=sh3-nommu-up sh2a-or-sh3e sh2e.s -isa=sh3 ERROR ! sh2e.s -isa=sh3-up sh2a-or-sh3e ! sh2e.s -isa=sh3e sh2a-or-sh3e ! sh2e.s -isa=sh3e-up sh2a-or-sh3e sh2e.s -isa=sh4-nofpu ERROR sh2e.s -isa=sh4-nofpu-up sh4 sh2e.s -isa=sh4-nommu-nofpu ERROR *************** sh3-dsp.s -isa=sh *** 153,158 **** --- 349,362 ---- sh3-dsp.s -isa=sh-up sh3-dsp sh3-dsp.s -isa=sh2 ERROR sh3-dsp.s -isa=sh2-up sh3-dsp + sh3-dsp.s -isa=sh2a-nofpu-or-sh3-nommu ERROR + sh3-dsp.s -isa=sh2a-nofpu-or-sh3-nommu-up sh3-dsp + sh3-dsp.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR + sh3-dsp.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4al-dsp + sh3-dsp.s -isa=sh2a-or-sh3e ERROR + sh3-dsp.s -isa=sh2a-or-sh3e-up ERROR + sh3-dsp.s -isa=sh2a-or-sh4 ERROR + sh3-dsp.s -isa=sh2a-or-sh4-up ERROR sh3-dsp.s -isa=sh2e ERROR sh3-dsp.s -isa=sh2e-up ERROR sh3-dsp.s -isa=sh3-dsp sh3-dsp *************** sh3-dsp.s -isa=sh4a *** 175,201 **** sh3-dsp.s -isa=sh4a-up ERROR sh3-dsp.s -isa=sh4al-dsp sh4al-dsp sh3-dsp.s -isa=sh4al-dsp-up sh4al-dsp ! sh3-nommu.s default-options sh3-nommu ! sh3-nommu.s -dsp sh3-nommu ! sh3-nommu.s -isa=any sh3-nommu ! sh3-nommu.s -isa=dsp sh3-nommu ! sh3-nommu.s -isa=fp sh3-nommu sh3-nommu.s -isa=sh-dsp ERROR sh3-nommu.s -isa=sh-dsp-up sh3-dsp sh3-nommu.s -isa=sh ERROR ! sh3-nommu.s -isa=sh-up sh3-nommu sh3-nommu.s -isa=sh2 ERROR ! sh3-nommu.s -isa=sh2-up sh3-nommu ! sh3-nommu.s -isa=sh2e ERROR ! sh3-nommu.s -isa=sh2e-up sh3e sh3-nommu.s -isa=sh3-dsp sh3-dsp sh3-nommu.s -isa=sh3-dsp-up sh3-dsp ! sh3-nommu.s -isa=sh3-nommu sh3-nommu ! sh3-nommu.s -isa=sh3-nommu-up sh3-nommu ! sh3-nommu.s -isa=sh3 sh3 ! sh3-nommu.s -isa=sh3-up sh3 ! sh3-nommu.s -isa=sh3e sh3e ! sh3-nommu.s -isa=sh3e-up sh3e sh3-nommu.s -isa=sh4-nofpu sh4-nofpu sh3-nommu.s -isa=sh4-nofpu-up sh4-nofpu sh3-nommu.s -isa=sh4-nommu-nofpu sh4-nommu-nofpu --- 379,413 ---- sh3-dsp.s -isa=sh4a-up ERROR sh3-dsp.s -isa=sh4al-dsp sh4al-dsp sh3-dsp.s -isa=sh4al-dsp-up sh4al-dsp ! sh3-nommu.s default-options sh2a-nofpu-or-sh3-nommu ! sh3-nommu.s -dsp sh2a-nofpu-or-sh3-nommu ! sh3-nommu.s -isa=any sh2a-nofpu-or-sh3-nommu ! sh3-nommu.s -isa=dsp sh2a-nofpu-or-sh3-nommu ! sh3-nommu.s -isa=fp sh2a-nofpu-or-sh3-nommu sh3-nommu.s -isa=sh-dsp ERROR sh3-nommu.s -isa=sh-dsp-up sh3-dsp sh3-nommu.s -isa=sh ERROR ! sh3-nommu.s -isa=sh-up sh2a-nofpu-or-sh3-nommu sh3-nommu.s -isa=sh2 ERROR ! sh3-nommu.s -isa=sh2-up sh2a-nofpu-or-sh3-nommu ! sh3-nommu.s -isa=sh2a-nofpu-or-sh3-nommu sh2a-nofpu ! sh3-nommu.s -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-nofpu-or-sh3-nommu ! sh3-nommu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu sh2a-nofpu ! sh3-nommu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-nofpu-or-sh4-nommu-nofpu ! sh3-nommu.s -isa=sh2a-or-sh3e ERROR ! sh3-nommu.s -isa=sh2a-or-sh3e-up sh2a-or-sh3e ! sh3-nommu.s -isa=sh2a-or-sh4 ERROR ! sh3-nommu.s -isa=sh2a-or-sh4-up sh2a-or-sh4 ! sh3-nommu.s -isa=sh2e sh2a-or-sh3e ! sh3-nommu.s -isa=sh2e-up sh2a-or-sh3e sh3-nommu.s -isa=sh3-dsp sh3-dsp sh3-nommu.s -isa=sh3-dsp-up sh3-dsp ! sh3-nommu.s -isa=sh3-nommu sh2a-nofpu-or-sh3-nommu ! sh3-nommu.s -isa=sh3-nommu-up sh2a-nofpu-or-sh3-nommu ! sh3-nommu.s -isa=sh3 sh2a-nofpu-or-sh3-nommu ! sh3-nommu.s -isa=sh3-up sh2a-nofpu-or-sh3-nommu ! sh3-nommu.s -isa=sh3e sh2a-or-sh3e ! sh3-nommu.s -isa=sh3e-up sh2a-or-sh3e sh3-nommu.s -isa=sh4-nofpu sh4-nofpu sh3-nommu.s -isa=sh4-nofpu-up sh4-nofpu sh3-nommu.s -isa=sh4-nommu-nofpu sh4-nommu-nofpu *************** sh3-nommu.s -isa=sh4a *** 208,238 **** sh3-nommu.s -isa=sh4a-up sh4a sh3-nommu.s -isa=sh4al-dsp sh4al-dsp sh3-nommu.s -isa=sh4al-dsp-up sh4al-dsp ! sh3.s default-options sh3 ! sh3.s -dsp sh3 ! sh3.s -isa=any sh3 ! sh3.s -isa=dsp sh3 ! sh3.s -isa=fp sh3 sh3.s -isa=sh-dsp ERROR sh3.s -isa=sh-dsp-up sh3-dsp sh3.s -isa=sh ERROR ! sh3.s -isa=sh-up sh3 sh3.s -isa=sh2 ERROR ! sh3.s -isa=sh2-up sh3 ! sh3.s -isa=sh2e ERROR ! sh3.s -isa=sh2e-up sh3e sh3.s -isa=sh3-dsp sh3-dsp sh3.s -isa=sh3-dsp-up sh3-dsp ! sh3.s -isa=sh3-nommu ERROR ! sh3.s -isa=sh3-nommu-up sh3 ! sh3.s -isa=sh3 sh3 ! sh3.s -isa=sh3-up sh3 ! sh3.s -isa=sh3e sh3e ! sh3.s -isa=sh3e-up sh3e sh3.s -isa=sh4-nofpu sh4-nofpu sh3.s -isa=sh4-nofpu-up sh4-nofpu ! sh3.s -isa=sh4-nommu-nofpu ERROR ! sh3.s -isa=sh4-nommu-nofpu-up sh4-nofpu sh3.s -isa=sh4 sh4 sh3.s -isa=sh4-up sh4 sh3.s -isa=sh4a-nofpu sh4a-nofpu --- 420,458 ---- sh3-nommu.s -isa=sh4a-up sh4a sh3-nommu.s -isa=sh4al-dsp sh4al-dsp sh3-nommu.s -isa=sh4al-dsp-up sh4al-dsp ! sh3.s default-options sh2a-nofpu-or-sh3-nommu ! sh3.s -dsp sh2a-nofpu-or-sh3-nommu ! sh3.s -isa=any sh2a-nofpu-or-sh3-nommu ! sh3.s -isa=dsp sh2a-nofpu-or-sh3-nommu ! sh3.s -isa=fp sh2a-nofpu-or-sh3-nommu sh3.s -isa=sh-dsp ERROR sh3.s -isa=sh-dsp-up sh3-dsp sh3.s -isa=sh ERROR ! sh3.s -isa=sh-up sh2a-nofpu-or-sh3-nommu sh3.s -isa=sh2 ERROR ! sh3.s -isa=sh2-up sh2a-nofpu-or-sh3-nommu ! sh3.s -isa=sh2a-nofpu-or-sh3-nommu sh2a-nofpu ! sh3.s -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-nofpu-or-sh3-nommu ! sh3.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu sh2a-nofpu ! sh3.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-nofpu-or-sh4-nommu-nofpu ! sh3.s -isa=sh2a-or-sh3e ERROR ! sh3.s -isa=sh2a-or-sh3e-up sh2a-or-sh3e ! sh3.s -isa=sh2a-or-sh4 ERROR ! sh3.s -isa=sh2a-or-sh4-up sh2a-or-sh4 ! sh3.s -isa=sh2e sh2a-or-sh3e ! sh3.s -isa=sh2e-up sh2a-or-sh3e sh3.s -isa=sh3-dsp sh3-dsp sh3.s -isa=sh3-dsp-up sh3-dsp ! sh3.s -isa=sh3-nommu sh2a-nofpu-or-sh3-nommu ! sh3.s -isa=sh3-nommu-up sh2a-nofpu-or-sh3-nommu ! sh3.s -isa=sh3 sh2a-nofpu-or-sh3-nommu ! sh3.s -isa=sh3-up sh2a-nofpu-or-sh3-nommu ! sh3.s -isa=sh3e sh2a-or-sh3e ! sh3.s -isa=sh3e-up sh2a-or-sh3e sh3.s -isa=sh4-nofpu sh4-nofpu sh3.s -isa=sh4-nofpu-up sh4-nofpu ! sh3.s -isa=sh4-nommu-nofpu sh4-nommu-nofpu ! sh3.s -isa=sh4-nommu-nofpu-up sh4-nommu-nofpu sh3.s -isa=sh4 sh4 sh3.s -isa=sh4-up sh4 sh3.s -isa=sh4a-nofpu sh4a-nofpu *************** sh3.s -isa=sh4a *** 241,267 **** sh3.s -isa=sh4a-up sh4a sh3.s -isa=sh4al-dsp sh4al-dsp sh3.s -isa=sh4al-dsp-up sh4al-dsp ! sh3e.s default-options sh3e sh3e.s -dsp ERROR ! sh3e.s -isa=any sh3e sh3e.s -isa=dsp ERROR ! sh3e.s -isa=fp sh3e sh3e.s -isa=sh-dsp ERROR sh3e.s -isa=sh-dsp-up ERROR sh3e.s -isa=sh ERROR ! sh3e.s -isa=sh-up sh3e sh3e.s -isa=sh2 ERROR ! sh3e.s -isa=sh2-up sh3e ! sh3e.s -isa=sh2e ERROR ! sh3e.s -isa=sh2e-up sh3e sh3e.s -isa=sh3-dsp ERROR sh3e.s -isa=sh3-dsp-up ERROR sh3e.s -isa=sh3-nommu ERROR ! sh3e.s -isa=sh3-nommu-up sh3e sh3e.s -isa=sh3 ERROR ! sh3e.s -isa=sh3-up sh3e ! sh3e.s -isa=sh3e sh3e ! sh3e.s -isa=sh3e-up sh3e sh3e.s -isa=sh4-nofpu ERROR sh3e.s -isa=sh4-nofpu-up sh4 sh3e.s -isa=sh4-nommu-nofpu ERROR --- 461,495 ---- sh3.s -isa=sh4a-up sh4a sh3.s -isa=sh4al-dsp sh4al-dsp sh3.s -isa=sh4al-dsp-up sh4al-dsp ! sh3e.s default-options sh2a-or-sh3e sh3e.s -dsp ERROR ! sh3e.s -isa=any sh2a-or-sh3e sh3e.s -isa=dsp ERROR ! sh3e.s -isa=fp sh2a-or-sh3e sh3e.s -isa=sh-dsp ERROR sh3e.s -isa=sh-dsp-up ERROR sh3e.s -isa=sh ERROR ! sh3e.s -isa=sh-up sh2a-or-sh3e sh3e.s -isa=sh2 ERROR ! sh3e.s -isa=sh2-up sh2a-or-sh3e ! sh3e.s -isa=sh2a-nofpu-or-sh3-nommu ERROR ! sh3e.s -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-or-sh3e ! sh3e.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR ! sh3e.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-or-sh4 ! sh3e.s -isa=sh2a-or-sh3e ERROR ! sh3e.s -isa=sh2a-or-sh3e-up sh2a-or-sh3e ! sh3e.s -isa=sh2a-or-sh4 ERROR ! sh3e.s -isa=sh2a-or-sh4-up sh2a-or-sh4 ! sh3e.s -isa=sh2e sh2a-or-sh3e ! sh3e.s -isa=sh2e-up sh2a-or-sh3e sh3e.s -isa=sh3-dsp ERROR sh3e.s -isa=sh3-dsp-up ERROR sh3e.s -isa=sh3-nommu ERROR ! sh3e.s -isa=sh3-nommu-up sh2a-or-sh3e sh3e.s -isa=sh3 ERROR ! sh3e.s -isa=sh3-up sh2a-or-sh3e ! sh3e.s -isa=sh3e sh2a-or-sh3e ! sh3e.s -isa=sh3e-up sh2a-or-sh3e sh3e.s -isa=sh4-nofpu ERROR sh3e.s -isa=sh4-nofpu-up sh4 sh3e.s -isa=sh4-nommu-nofpu ERROR *************** sh3e.s -isa=sh4a *** 274,304 **** sh3e.s -isa=sh4a-up sh4a sh3e.s -isa=sh4al-dsp ERROR sh3e.s -isa=sh4al-dsp-up ERROR ! sh4-nofpu.s default-options sh4-nofpu ! sh4-nofpu.s -dsp sh4-nofpu ! sh4-nofpu.s -isa=any sh4-nofpu ! sh4-nofpu.s -isa=dsp sh4-nofpu ! sh4-nofpu.s -isa=fp sh4-nofpu sh4-nofpu.s -isa=sh-dsp ERROR sh4-nofpu.s -isa=sh-dsp-up sh4al-dsp sh4-nofpu.s -isa=sh ERROR ! sh4-nofpu.s -isa=sh-up sh4-nofpu sh4-nofpu.s -isa=sh2 ERROR ! sh4-nofpu.s -isa=sh2-up sh4-nofpu sh4-nofpu.s -isa=sh2e ERROR sh4-nofpu.s -isa=sh2e-up sh4 sh4-nofpu.s -isa=sh3-dsp ERROR sh4-nofpu.s -isa=sh3-dsp-up sh4al-dsp sh4-nofpu.s -isa=sh3-nommu ERROR ! sh4-nofpu.s -isa=sh3-nommu-up sh4-nofpu sh4-nofpu.s -isa=sh3 ERROR ! sh4-nofpu.s -isa=sh3-up sh4-nofpu sh4-nofpu.s -isa=sh3e ERROR sh4-nofpu.s -isa=sh3e-up sh4 sh4-nofpu.s -isa=sh4-nofpu sh4-nofpu sh4-nofpu.s -isa=sh4-nofpu-up sh4-nofpu ! sh4-nofpu.s -isa=sh4-nommu-nofpu ERROR ! sh4-nofpu.s -isa=sh4-nommu-nofpu-up sh4-nofpu sh4-nofpu.s -isa=sh4 sh4 sh4-nofpu.s -isa=sh4-up sh4 sh4-nofpu.s -isa=sh4a-nofpu sh4a-nofpu --- 502,540 ---- sh3e.s -isa=sh4a-up sh4a sh3e.s -isa=sh4al-dsp ERROR sh3e.s -isa=sh4al-dsp-up ERROR ! sh4-nofpu.s default-options sh4-nommu-nofpu ! sh4-nofpu.s -dsp sh4-nommu-nofpu ! sh4-nofpu.s -isa=any sh4-nommu-nofpu ! sh4-nofpu.s -isa=dsp sh4-nommu-nofpu ! sh4-nofpu.s -isa=fp sh4-nommu-nofpu sh4-nofpu.s -isa=sh-dsp ERROR sh4-nofpu.s -isa=sh-dsp-up sh4al-dsp sh4-nofpu.s -isa=sh ERROR ! sh4-nofpu.s -isa=sh-up sh4-nommu-nofpu sh4-nofpu.s -isa=sh2 ERROR ! sh4-nofpu.s -isa=sh2-up sh4-nommu-nofpu ! sh4-nofpu.s -isa=sh2a-nofpu-or-sh3-nommu ERROR ! sh4-nofpu.s -isa=sh2a-nofpu-or-sh3-nommu-up sh4-nommu-nofpu ! sh4-nofpu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu sh4-nommu-nofpu ! sh4-nofpu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4-nommu-nofpu ! sh4-nofpu.s -isa=sh2a-or-sh3e ERROR ! sh4-nofpu.s -isa=sh2a-or-sh3e-up sh4 ! sh4-nofpu.s -isa=sh2a-or-sh4 ERROR ! sh4-nofpu.s -isa=sh2a-or-sh4-up sh4 sh4-nofpu.s -isa=sh2e ERROR sh4-nofpu.s -isa=sh2e-up sh4 sh4-nofpu.s -isa=sh3-dsp ERROR sh4-nofpu.s -isa=sh3-dsp-up sh4al-dsp sh4-nofpu.s -isa=sh3-nommu ERROR ! sh4-nofpu.s -isa=sh3-nommu-up sh4-nommu-nofpu sh4-nofpu.s -isa=sh3 ERROR ! sh4-nofpu.s -isa=sh3-up sh4-nommu-nofpu sh4-nofpu.s -isa=sh3e ERROR sh4-nofpu.s -isa=sh3e-up sh4 sh4-nofpu.s -isa=sh4-nofpu sh4-nofpu sh4-nofpu.s -isa=sh4-nofpu-up sh4-nofpu ! sh4-nofpu.s -isa=sh4-nommu-nofpu sh4-nommu-nofpu ! sh4-nofpu.s -isa=sh4-nommu-nofpu-up sh4-nommu-nofpu sh4-nofpu.s -isa=sh4 sh4 sh4-nofpu.s -isa=sh4-up sh4 sh4-nofpu.s -isa=sh4a-nofpu sh4a-nofpu *************** sh4-nommu-nofpu.s -isa=sh *** 318,323 **** --- 554,567 ---- sh4-nommu-nofpu.s -isa=sh-up sh4-nommu-nofpu sh4-nommu-nofpu.s -isa=sh2 ERROR sh4-nommu-nofpu.s -isa=sh2-up sh4-nommu-nofpu + sh4-nommu-nofpu.s -isa=sh2a-nofpu-or-sh3-nommu ERROR + sh4-nommu-nofpu.s -isa=sh2a-nofpu-or-sh3-nommu-up sh4-nommu-nofpu + sh4-nommu-nofpu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu sh4-nommu-nofpu + sh4-nommu-nofpu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4-nommu-nofpu + sh4-nommu-nofpu.s -isa=sh2a-or-sh3e ERROR + sh4-nommu-nofpu.s -isa=sh2a-or-sh3e-up sh4 + sh4-nommu-nofpu.s -isa=sh2a-or-sh4 ERROR + sh4-nommu-nofpu.s -isa=sh2a-or-sh4-up sh4 sh4-nommu-nofpu.s -isa=sh2e ERROR sh4-nommu-nofpu.s -isa=sh2e-up sh4 sh4-nommu-nofpu.s -isa=sh3-dsp ERROR *************** sh4-nommu-nofpu.s -isa=sh3-dsp-up *** 325,331 **** sh4-nommu-nofpu.s -isa=sh3-nommu ERROR sh4-nommu-nofpu.s -isa=sh3-nommu-up sh4-nommu-nofpu sh4-nommu-nofpu.s -isa=sh3 ERROR ! sh4-nommu-nofpu.s -isa=sh3-up sh4-nofpu sh4-nommu-nofpu.s -isa=sh3e ERROR sh4-nommu-nofpu.s -isa=sh3e-up sh4 sh4-nommu-nofpu.s -isa=sh4-nofpu sh4-nofpu --- 569,575 ---- sh4-nommu-nofpu.s -isa=sh3-nommu ERROR sh4-nommu-nofpu.s -isa=sh3-nommu-up sh4-nommu-nofpu sh4-nommu-nofpu.s -isa=sh3 ERROR ! sh4-nommu-nofpu.s -isa=sh3-up sh4-nommu-nofpu sh4-nommu-nofpu.s -isa=sh3e ERROR sh4-nommu-nofpu.s -isa=sh3e-up sh4 sh4-nommu-nofpu.s -isa=sh4-nofpu sh4-nofpu *************** sh4.s -isa=sh *** 351,356 **** --- 595,608 ---- sh4.s -isa=sh-up sh4 sh4.s -isa=sh2 ERROR sh4.s -isa=sh2-up sh4 + sh4.s -isa=sh2a-nofpu-or-sh3-nommu ERROR + sh4.s -isa=sh2a-nofpu-or-sh3-nommu-up sh4 + sh4.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR + sh4.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4 + sh4.s -isa=sh2a-or-sh3e ERROR + sh4.s -isa=sh2a-or-sh3e-up sh4 + sh4.s -isa=sh2a-or-sh4 ERROR + sh4.s -isa=sh2a-or-sh4-up sh4 sh4.s -isa=sh2e ERROR sh4.s -isa=sh2e-up sh4 sh4.s -isa=sh3-dsp ERROR *************** sh4a-nofpu.s -isa=sh *** 384,389 **** --- 636,649 ---- sh4a-nofpu.s -isa=sh-up sh4a-nofpu sh4a-nofpu.s -isa=sh2 ERROR sh4a-nofpu.s -isa=sh2-up sh4a-nofpu + sh4a-nofpu.s -isa=sh2a-nofpu-or-sh3-nommu ERROR + sh4a-nofpu.s -isa=sh2a-nofpu-or-sh3-nommu-up sh4a-nofpu + sh4a-nofpu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR + sh4a-nofpu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4a-nofpu + sh4a-nofpu.s -isa=sh2a-or-sh3e ERROR + sh4a-nofpu.s -isa=sh2a-or-sh3e-up sh4a + sh4a-nofpu.s -isa=sh2a-or-sh4 ERROR + sh4a-nofpu.s -isa=sh2a-or-sh4-up sh4a sh4a-nofpu.s -isa=sh2e ERROR sh4a-nofpu.s -isa=sh2e-up sh4a sh4a-nofpu.s -isa=sh3-dsp ERROR *************** sh4a.s -isa=sh *** 417,422 **** --- 677,690 ---- sh4a.s -isa=sh-up sh4a sh4a.s -isa=sh2 ERROR sh4a.s -isa=sh2-up sh4a + sh4a.s -isa=sh2a-nofpu-or-sh3-nommu ERROR + sh4a.s -isa=sh2a-nofpu-or-sh3-nommu-up sh4a + sh4a.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR + sh4a.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4a + sh4a.s -isa=sh2a-or-sh3e ERROR + sh4a.s -isa=sh2a-or-sh3e-up sh4a + sh4a.s -isa=sh2a-or-sh4 ERROR + sh4a.s -isa=sh2a-or-sh4-up sh4a sh4a.s -isa=sh2e ERROR sh4a.s -isa=sh2e-up sh4a sh4a.s -isa=sh3-dsp ERROR *************** sh4al-dsp.s -isa=sh *** 450,455 **** --- 718,731 ---- sh4al-dsp.s -isa=sh-up sh4al-dsp sh4al-dsp.s -isa=sh2 ERROR sh4al-dsp.s -isa=sh2-up sh4al-dsp + sh4al-dsp.s -isa=sh2a-nofpu-or-sh3-nommu ERROR + sh4al-dsp.s -isa=sh2a-nofpu-or-sh3-nommu-up sh4al-dsp + sh4al-dsp.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR + sh4al-dsp.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4al-dsp + sh4al-dsp.s -isa=sh2a-or-sh3e ERROR + sh4al-dsp.s -isa=sh2a-or-sh3e-up ERROR + sh4al-dsp.s -isa=sh2a-or-sh4 ERROR + sh4al-dsp.s -isa=sh2a-or-sh4-up ERROR sh4al-dsp.s -isa=sh2e ERROR sh4al-dsp.s -isa=sh2e-up ERROR sh4al-dsp.s -isa=sh3-dsp ERROR Index: gas/testsuite/gas/sh/arch/sh4.s =================================================================== RCS file: /cvs/src/src/gas/testsuite/gas/sh/arch/sh4.s,v retrieving revision 1.1 diff -c -3 -p -r1.1 sh4.s *** gas/testsuite/gas/sh/arch/sh4.s 29 Jun 2004 16:35:05 -0000 1.1 --- gas/testsuite/gas/sh/arch/sh4.s 15 Dec 2004 16:36:27 -0000 *************** *** 1,3 **** .section .text sh4: ! fabs dr0 --- 1,4 ---- .section .text sh4: ! frchg ! Index: ld/testsuite/ld-sh/arch/arch_expected.txt =================================================================== RCS file: /cvs/src/src/ld/testsuite/ld-sh/arch/arch_expected.txt,v retrieving revision 1.1 diff -c -3 -p -r1.1 arch_expected.txt *** ld/testsuite/ld-sh/arch/arch_expected.txt 29 Jun 2004 16:35:05 -0000 1.1 --- ld/testsuite/ld-sh/arch/arch_expected.txt 15 Dec 2004 16:36:28 -0000 *************** *** 4,10 **** # It contains the expected results of the tests. # If the tests are failing because the expected results # have changed then run 'make check' and copy the new file ! # from <objdir>/ld/testsuite/arch_results.txt # to <srcdir>/ld/testsuite/ld-sh/arch/arch_expected.txt . # Make sure the new expected results are ALL correct. # --- 4,10 ---- # It contains the expected results of the tests. # If the tests are failing because the expected results # have changed then run 'make check' and copy the new file ! # from <objdir>/ld/arch_results.txt # to <srcdir>/ld/testsuite/ld-sh/arch/arch_expected.txt . # Make sure the new expected results are ALL correct. # *************** *** 13,18 **** --- 13,22 ---- sh-dsp.o sh-dsp.o sh-dsp sh-dsp.o sh.o sh-dsp sh-dsp.o sh2.o sh-dsp + sh-dsp.o sh2a-nofpu-or-sh3-nommu.o sh3-dsp + sh-dsp.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh4al-dsp + sh-dsp.o sh2a-or-sh3e.o ERROR + sh-dsp.o sh2a-or-sh4.o ERROR sh-dsp.o sh2e.o ERROR sh-dsp.o sh3-dsp.o sh3-dsp sh-dsp.o sh3-nommu.o sh3-dsp *************** sh-dsp.o sh-unknown.o *** 28,78 **** sh.o sh-dsp.o sh-dsp sh.o sh.o sh sh.o sh2.o sh2 sh.o sh2e.o sh2e sh.o sh3-dsp.o sh3-dsp ! sh.o sh3-nommu.o sh3-nommu ! sh.o sh3.o sh3 ! sh.o sh3e.o sh3e ! sh.o sh4-nofpu.o sh4-nofpu sh.o sh4-nommu-nofpu.o sh4-nommu-nofpu sh.o sh4.o sh4 sh.o sh4a-nofpu.o sh4a-nofpu sh.o sh4a.o sh4a sh.o sh4al-dsp.o sh4al-dsp ! sh.o sh-unknown.o sh3 sh2.o sh-dsp.o sh-dsp sh2.o sh.o sh2 sh2.o sh2.o sh2 sh2.o sh2e.o sh2e sh2.o sh3-dsp.o sh3-dsp ! sh2.o sh3-nommu.o sh3-nommu ! sh2.o sh3.o sh3 ! sh2.o sh3e.o sh3e ! sh2.o sh4-nofpu.o sh4-nofpu sh2.o sh4-nommu-nofpu.o sh4-nommu-nofpu sh2.o sh4.o sh4 sh2.o sh4a-nofpu.o sh4a-nofpu sh2.o sh4a.o sh4a sh2.o sh4al-dsp.o sh4al-dsp ! sh2.o sh-unknown.o sh3 sh2e.o sh-dsp.o ERROR sh2e.o sh.o sh2e sh2e.o sh2.o sh2e sh2e.o sh2e.o sh2e sh2e.o sh3-dsp.o ERROR ! sh2e.o sh3-nommu.o sh3e ! sh2e.o sh3.o sh3e ! sh2e.o sh3e.o sh3e sh2e.o sh4-nofpu.o sh4 sh2e.o sh4-nommu-nofpu.o sh4 sh2e.o sh4.o sh4 sh2e.o sh4a-nofpu.o sh4a sh2e.o sh4a.o sh4a sh2e.o sh4al-dsp.o ERROR ! sh2e.o sh-unknown.o sh3e sh3-dsp.o sh-dsp.o sh3-dsp sh3-dsp.o sh.o sh3-dsp sh3-dsp.o sh2.o sh3-dsp sh3-dsp.o sh2e.o ERROR sh3-dsp.o sh3-dsp.o sh3-dsp sh3-dsp.o sh3-nommu.o sh3-dsp --- 32,174 ---- sh.o sh-dsp.o sh-dsp sh.o sh.o sh sh.o sh2.o sh2 + sh.o sh2a-nofpu-or-sh3-nommu.o sh2a-nofpu-or-sh3-nommu + sh.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu + sh.o sh2a-or-sh3e.o sh2a-or-sh3e + sh.o sh2a-or-sh4.o sh2a-or-sh4 sh.o sh2e.o sh2e sh.o sh3-dsp.o sh3-dsp ! sh.o sh3-nommu.o sh2a-nofpu-or-sh3-nommu ! sh.o sh3.o sh2a-nofpu-or-sh3-nommu ! sh.o sh3e.o sh2a-or-sh3e ! sh.o sh4-nofpu.o sh4-nommu-nofpu sh.o sh4-nommu-nofpu.o sh4-nommu-nofpu sh.o sh4.o sh4 sh.o sh4a-nofpu.o sh4a-nofpu sh.o sh4a.o sh4a sh.o sh4al-dsp.o sh4al-dsp ! sh.o sh-unknown.o sh2a-nofpu-or-sh3-nommu sh2.o sh-dsp.o sh-dsp sh2.o sh.o sh2 sh2.o sh2.o sh2 + sh2.o sh2a-nofpu-or-sh3-nommu.o sh2a-nofpu-or-sh3-nommu + sh2.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu + sh2.o sh2a-or-sh3e.o sh2a-or-sh3e + sh2.o sh2a-or-sh4.o sh2a-or-sh4 sh2.o sh2e.o sh2e sh2.o sh3-dsp.o sh3-dsp ! sh2.o sh3-nommu.o sh2a-nofpu-or-sh3-nommu ! sh2.o sh3.o sh2a-nofpu-or-sh3-nommu ! sh2.o sh3e.o sh2a-or-sh3e ! sh2.o sh4-nofpu.o sh4-nommu-nofpu sh2.o sh4-nommu-nofpu.o sh4-nommu-nofpu sh2.o sh4.o sh4 sh2.o sh4a-nofpu.o sh4a-nofpu sh2.o sh4a.o sh4a sh2.o sh4al-dsp.o sh4al-dsp ! sh2.o sh-unknown.o sh2a-nofpu-or-sh3-nommu ! sh2a-nofpu-or-sh3-nommu.o sh-dsp.o sh3-dsp ! sh2a-nofpu-or-sh3-nommu.o sh.o sh2a-nofpu-or-sh3-nommu ! sh2a-nofpu-or-sh3-nommu.o sh2.o sh2a-nofpu-or-sh3-nommu ! sh2a-nofpu-or-sh3-nommu.o sh2a-nofpu-or-sh3-nommu.o sh2a-nofpu-or-sh3-nommu ! sh2a-nofpu-or-sh3-nommu.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu ! sh2a-nofpu-or-sh3-nommu.o sh2a-or-sh3e.o sh2a-or-sh3e ! sh2a-nofpu-or-sh3-nommu.o sh2a-or-sh4.o sh2a-or-sh4 ! sh2a-nofpu-or-sh3-nommu.o sh2e.o sh2a-or-sh3e ! sh2a-nofpu-or-sh3-nommu.o sh3-dsp.o sh3-dsp ! sh2a-nofpu-or-sh3-nommu.o sh3-nommu.o sh2a-nofpu-or-sh3-nommu ! sh2a-nofpu-or-sh3-nommu.o sh3.o sh2a-nofpu-or-sh3-nommu ! sh2a-nofpu-or-sh3-nommu.o sh3e.o sh2a-or-sh3e ! sh2a-nofpu-or-sh3-nommu.o sh4-nofpu.o sh4-nommu-nofpu ! sh2a-nofpu-or-sh3-nommu.o sh4-nommu-nofpu.o sh4-nommu-nofpu ! sh2a-nofpu-or-sh3-nommu.o sh4.o sh4 ! sh2a-nofpu-or-sh3-nommu.o sh4a-nofpu.o sh4a-nofpu ! sh2a-nofpu-or-sh3-nommu.o sh4a.o sh4a ! sh2a-nofpu-or-sh3-nommu.o sh4al-dsp.o sh4al-dsp ! sh2a-nofpu-or-sh3-nommu.o sh-unknown.o sh2a-nofpu-or-sh3-nommu ! sh2a-nofpu-or-sh4-nommu-nofpu.o sh-dsp.o sh4al-dsp ! sh2a-nofpu-or-sh4-nommu-nofpu.o sh.o sh2a-nofpu-or-sh4-nommu-nofpu ! sh2a-nofpu-or-sh4-nommu-nofpu.o sh2.o sh2a-nofpu-or-sh4-nommu-nofpu ! sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-nofpu-or-sh3-nommu.o sh2a-nofpu-or-sh4-nommu-nofpu ! sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu ! sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-or-sh3e.o sh2a-or-sh4 ! sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-or-sh4.o sh2a-or-sh4 ! sh2a-nofpu-or-sh4-nommu-nofpu.o sh2e.o sh2a-or-sh4 ! sh2a-nofpu-or-sh4-nommu-nofpu.o sh3-dsp.o sh4al-dsp ! sh2a-nofpu-or-sh4-nommu-nofpu.o sh3-nommu.o sh2a-nofpu-or-sh4-nommu-nofpu ! sh2a-nofpu-or-sh4-nommu-nofpu.o sh3.o sh2a-nofpu-or-sh4-nommu-nofpu ! sh2a-nofpu-or-sh4-nommu-nofpu.o sh3e.o sh2a-or-sh4 ! sh2a-nofpu-or-sh4-nommu-nofpu.o sh4-nofpu.o sh4-nommu-nofpu ! sh2a-nofpu-or-sh4-nommu-nofpu.o sh4-nommu-nofpu.o sh4-nommu-nofpu ! sh2a-nofpu-or-sh4-nommu-nofpu.o sh4.o sh4 ! sh2a-nofpu-or-sh4-nommu-nofpu.o sh4a-nofpu.o sh4a-nofpu ! sh2a-nofpu-or-sh4-nommu-nofpu.o sh4a.o sh4a ! sh2a-nofpu-or-sh4-nommu-nofpu.o sh4al-dsp.o sh4al-dsp ! sh2a-nofpu-or-sh4-nommu-nofpu.o sh-unknown.o sh2a-nofpu-or-sh4-nommu-nofpu ! sh2a-or-sh3e.o sh-dsp.o ERROR ! sh2a-or-sh3e.o sh.o sh2a-or-sh3e ! sh2a-or-sh3e.o sh2.o sh2a-or-sh3e ! sh2a-or-sh3e.o sh2a-nofpu-or-sh3-nommu.o sh2a-or-sh3e ! sh2a-or-sh3e.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-or-sh4 ! sh2a-or-sh3e.o sh2a-or-sh3e.o sh2a-or-sh3e ! sh2a-or-sh3e.o sh2a-or-sh4.o sh2a-or-sh4 ! sh2a-or-sh3e.o sh2e.o sh2a-or-sh3e ! sh2a-or-sh3e.o sh3-dsp.o ERROR ! sh2a-or-sh3e.o sh3-nommu.o sh2a-or-sh3e ! sh2a-or-sh3e.o sh3.o sh2a-or-sh3e ! sh2a-or-sh3e.o sh3e.o sh2a-or-sh3e ! sh2a-or-sh3e.o sh4-nofpu.o sh4 ! sh2a-or-sh3e.o sh4-nommu-nofpu.o sh4 ! sh2a-or-sh3e.o sh4.o sh4 ! sh2a-or-sh3e.o sh4a-nofpu.o sh4a ! sh2a-or-sh3e.o sh4a.o sh4a ! sh2a-or-sh3e.o sh4al-dsp.o ERROR ! sh2a-or-sh3e.o sh-unknown.o sh2a-or-sh3e ! sh2a-or-sh4.o sh-dsp.o ERROR ! sh2a-or-sh4.o sh.o sh2a-or-sh4 ! sh2a-or-sh4.o sh2.o sh2a-or-sh4 ! sh2a-or-sh4.o sh2a-nofpu-or-sh3-nommu.o sh2a-or-sh4 ! sh2a-or-sh4.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-or-sh4 ! sh2a-or-sh4.o sh2a-or-sh3e.o sh2a-or-sh4 ! sh2a-or-sh4.o sh2a-or-sh4.o sh2a-or-sh4 ! sh2a-or-sh4.o sh2e.o sh2a-or-sh4 ! sh2a-or-sh4.o sh3-dsp.o ERROR ! sh2a-or-sh4.o sh3-nommu.o sh2a-or-sh4 ! sh2a-or-sh4.o sh3.o sh2a-or-sh4 ! sh2a-or-sh4.o sh3e.o sh2a-or-sh4 ! sh2a-or-sh4.o sh4-nofpu.o sh4 ! sh2a-or-sh4.o sh4-nommu-nofpu.o sh4 ! sh2a-or-sh4.o sh4.o sh4 ! sh2a-or-sh4.o sh4a-nofpu.o sh4a ! sh2a-or-sh4.o sh4a.o sh4a ! sh2a-or-sh4.o sh4al-dsp.o ERROR ! sh2a-or-sh4.o sh-unknown.o sh2a-or-sh4 sh2e.o sh-dsp.o ERROR sh2e.o sh.o sh2e sh2e.o sh2.o sh2e + sh2e.o sh2a-nofpu-or-sh3-nommu.o sh2a-or-sh3e + sh2e.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-or-sh4 + sh2e.o sh2a-or-sh3e.o sh2a-or-sh3e + sh2e.o sh2a-or-sh4.o sh2a-or-sh4 sh2e.o sh2e.o sh2e sh2e.o sh3-dsp.o ERROR ! sh2e.o sh3-nommu.o sh2a-or-sh3e ! sh2e.o sh3.o sh2a-or-sh3e ! sh2e.o sh3e.o sh2a-or-sh3e sh2e.o sh4-nofpu.o sh4 sh2e.o sh4-nommu-nofpu.o sh4 sh2e.o sh4.o sh4 sh2e.o sh4a-nofpu.o sh4a sh2e.o sh4a.o sh4a sh2e.o sh4al-dsp.o ERROR ! sh2e.o sh-unknown.o sh2a-or-sh3e sh3-dsp.o sh-dsp.o sh3-dsp sh3-dsp.o sh.o sh3-dsp sh3-dsp.o sh2.o sh3-dsp + sh3-dsp.o sh2a-nofpu-or-sh3-nommu.o sh3-dsp + sh3-dsp.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh4al-dsp + sh3-dsp.o sh2a-or-sh3e.o ERROR + sh3-dsp.o sh2a-or-sh4.o ERROR sh3-dsp.o sh2e.o ERROR sh3-dsp.o sh3-dsp.o sh3-dsp sh3-dsp.o sh3-nommu.o sh3-dsp *************** sh3-dsp.o sh4a.o *** 86,168 **** sh3-dsp.o sh4al-dsp.o sh4al-dsp sh3-dsp.o sh-unknown.o sh3-dsp sh3-nommu.o sh-dsp.o sh3-dsp ! sh3-nommu.o sh.o sh3-nommu ! sh3-nommu.o sh2.o sh3-nommu ! sh3-nommu.o sh2e.o sh3e sh3-nommu.o sh3-dsp.o sh3-dsp ! sh3-nommu.o sh3-nommu.o sh3-nommu ! sh3-nommu.o sh3.o sh3 ! sh3-nommu.o sh3e.o sh3e ! sh3-nommu.o sh4-nofpu.o sh4-nofpu sh3-nommu.o sh4-nommu-nofpu.o sh4-nommu-nofpu sh3-nommu.o sh4.o sh4 sh3-nommu.o sh4a-nofpu.o sh4a-nofpu sh3-nommu.o sh4a.o sh4a sh3-nommu.o sh4al-dsp.o sh4al-dsp ! sh3-nommu.o sh-unknown.o sh3 sh3.o sh-dsp.o sh3-dsp ! sh3.o sh.o sh3 ! sh3.o sh2.o sh3 ! sh3.o sh2e.o sh3e sh3.o sh3-dsp.o sh3-dsp ! sh3.o sh3-nommu.o sh3 ! sh3.o sh3.o sh3 ! sh3.o sh3e.o sh3e ! sh3.o sh4-nofpu.o sh4-nofpu ! sh3.o sh4-nommu-nofpu.o sh4-nofpu sh3.o sh4.o sh4 sh3.o sh4a-nofpu.o sh4a-nofpu sh3.o sh4a.o sh4a sh3.o sh4al-dsp.o sh4al-dsp ! sh3.o sh-unknown.o sh3 sh3e.o sh-dsp.o ERROR ! sh3e.o sh.o sh3e ! sh3e.o sh2.o sh3e ! sh3e.o sh2e.o sh3e sh3e.o sh3-dsp.o ERROR ! sh3e.o sh3-nommu.o sh3e ! sh3e.o sh3.o sh3e ! sh3e.o sh3e.o sh3e sh3e.o sh4-nofpu.o sh4 sh3e.o sh4-nommu-nofpu.o sh4 sh3e.o sh4.o sh4 sh3e.o sh4a-nofpu.o sh4a sh3e.o sh4a.o sh4a sh3e.o sh4al-dsp.o ERROR ! sh3e.o sh-unknown.o sh3e sh4-nofpu.o sh-dsp.o sh4al-dsp ! sh4-nofpu.o sh.o sh4-nofpu ! sh4-nofpu.o sh2.o sh4-nofpu sh4-nofpu.o sh2e.o sh4 sh4-nofpu.o sh3-dsp.o sh4al-dsp ! sh4-nofpu.o sh3-nommu.o sh4-nofpu ! sh4-nofpu.o sh3.o sh4-nofpu sh4-nofpu.o sh3e.o sh4 ! sh4-nofpu.o sh4-nofpu.o sh4-nofpu ! sh4-nofpu.o sh4-nommu-nofpu.o sh4-nofpu sh4-nofpu.o sh4.o sh4 sh4-nofpu.o sh4a-nofpu.o sh4a-nofpu sh4-nofpu.o sh4a.o sh4a sh4-nofpu.o sh4al-dsp.o sh4al-dsp ! sh4-nofpu.o sh-unknown.o sh4-nofpu sh4-nommu-nofpu.o sh-dsp.o sh4al-dsp sh4-nommu-nofpu.o sh.o sh4-nommu-nofpu sh4-nommu-nofpu.o sh2.o sh4-nommu-nofpu sh4-nommu-nofpu.o sh2e.o sh4 sh4-nommu-nofpu.o sh3-dsp.o sh4al-dsp sh4-nommu-nofpu.o sh3-nommu.o sh4-nommu-nofpu ! sh4-nommu-nofpu.o sh3.o sh4-nofpu sh4-nommu-nofpu.o sh3e.o sh4 ! sh4-nommu-nofpu.o sh4-nofpu.o sh4-nofpu sh4-nommu-nofpu.o sh4-nommu-nofpu.o sh4-nommu-nofpu sh4-nommu-nofpu.o sh4.o sh4 sh4-nommu-nofpu.o sh4a-nofpu.o sh4a-nofpu sh4-nommu-nofpu.o sh4a.o sh4a sh4-nommu-nofpu.o sh4al-dsp.o sh4al-dsp ! sh4-nommu-nofpu.o sh-unknown.o sh4-nofpu sh4.o sh-dsp.o ERROR sh4.o sh.o sh4 sh4.o sh2.o sh4 sh4.o sh2e.o sh4 sh4.o sh3-dsp.o ERROR sh4.o sh3-nommu.o sh4 --- 182,288 ---- sh3-dsp.o sh4al-dsp.o sh4al-dsp sh3-dsp.o sh-unknown.o sh3-dsp sh3-nommu.o sh-dsp.o sh3-dsp ! sh3-nommu.o sh.o sh2a-nofpu-or-sh3-nommu ! sh3-nommu.o sh2.o sh2a-nofpu-or-sh3-nommu ! sh3-nommu.o sh2a-nofpu-or-sh3-nommu.o sh2a-nofpu-or-sh3-nommu ! sh3-nommu.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu ! sh3-nommu.o sh2a-or-sh3e.o sh2a-or-sh3e ! sh3-nommu.o sh2a-or-sh4.o sh2a-or-sh4 ! sh3-nommu.o sh2e.o sh2a-or-sh3e sh3-nommu.o sh3-dsp.o sh3-dsp ! sh3-nommu.o sh3-nommu.o sh2a-nofpu-or-sh3-nommu ! sh3-nommu.o sh3.o sh2a-nofpu-or-sh3-nommu ! sh3-nommu.o sh3e.o sh2a-or-sh3e ! sh3-nommu.o sh4-nofpu.o sh4-nommu-nofpu sh3-nommu.o sh4-nommu-nofpu.o sh4-nommu-nofpu sh3-nommu.o sh4.o sh4 sh3-nommu.o sh4a-nofpu.o sh4a-nofpu sh3-nommu.o sh4a.o sh4a sh3-nommu.o sh4al-dsp.o sh4al-dsp ! sh3-nommu.o sh-unknown.o sh2a-nofpu-or-sh3-nommu sh3.o sh-dsp.o sh3-dsp ! sh3.o sh.o sh2a-nofpu-or-sh3-nommu ! sh3.o sh2.o sh2a-nofpu-or-sh3-nommu ! sh3.o sh2a-nofpu-or-sh3-nommu.o sh2a-nofpu-or-sh3-nommu ! sh3.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu ! sh3.o sh2a-or-sh3e.o sh2a-or-sh3e ! sh3.o sh2a-or-sh4.o sh2a-or-sh4 ! sh3.o sh2e.o sh2a-or-sh3e sh3.o sh3-dsp.o sh3-dsp ! sh3.o sh3-nommu.o sh2a-nofpu-or-sh3-nommu ! sh3.o sh3.o sh2a-nofpu-or-sh3-nommu ! sh3.o sh3e.o sh2a-or-sh3e ! sh3.o sh4-nofpu.o sh4-nommu-nofpu ! sh3.o sh4-nommu-nofpu.o sh4-nommu-nofpu sh3.o sh4.o sh4 sh3.o sh4a-nofpu.o sh4a-nofpu sh3.o sh4a.o sh4a sh3.o sh4al-dsp.o sh4al-dsp ! sh3.o sh-unknown.o sh2a-nofpu-or-sh3-nommu sh3e.o sh-dsp.o ERROR ! sh3e.o sh.o sh2a-or-sh3e ! sh3e.o sh2.o sh2a-or-sh3e ! sh3e.o sh2a-nofpu-or-sh3-nommu.o sh2a-or-sh3e ! sh3e.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-or-sh4 ! sh3e.o sh2a-or-sh3e.o sh2a-or-sh3e ! sh3e.o sh2a-or-sh4.o sh2a-or-sh4 ! sh3e.o sh2e.o sh2a-or-sh3e sh3e.o sh3-dsp.o ERROR ! sh3e.o sh3-nommu.o sh2a-or-sh3e ! sh3e.o sh3.o sh2a-or-sh3e ! sh3e.o sh3e.o sh2a-or-sh3e sh3e.o sh4-nofpu.o sh4 sh3e.o sh4-nommu-nofpu.o sh4 sh3e.o sh4.o sh4 sh3e.o sh4a-nofpu.o sh4a sh3e.o sh4a.o sh4a sh3e.o sh4al-dsp.o ERROR ! sh3e.o sh-unknown.o sh2a-or-sh3e sh4-nofpu.o sh-dsp.o sh4al-dsp ! sh4-nofpu.o sh.o sh4-nommu-nofpu ! sh4-nofpu.o sh2.o sh4-nommu-nofpu ! sh4-nofpu.o sh2a-nofpu-or-sh3-nommu.o sh4-nommu-nofpu ! sh4-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh4-nommu-nofpu ! sh4-nofpu.o sh2a-or-sh3e.o sh4 ! sh4-nofpu.o sh2a-or-sh4.o sh4 sh4-nofpu.o sh2e.o sh4 sh4-nofpu.o sh3-dsp.o sh4al-dsp ! sh4-nofpu.o sh3-nommu.o sh4-nommu-nofpu ! sh4-nofpu.o sh3.o sh4-nommu-nofpu sh4-nofpu.o sh3e.o sh4 ! sh4-nofpu.o sh4-nofpu.o sh4-nommu-nofpu ! sh4-nofpu.o sh4-nommu-nofpu.o sh4-nommu-nofpu sh4-nofpu.o sh4.o sh4 sh4-nofpu.o sh4a-nofpu.o sh4a-nofpu sh4-nofpu.o sh4a.o sh4a sh4-nofpu.o sh4al-dsp.o sh4al-dsp ! sh4-nofpu.o sh-unknown.o sh4-nommu-nofpu sh4-nommu-nofpu.o sh-dsp.o sh4al-dsp sh4-nommu-nofpu.o sh.o sh4-nommu-nofpu sh4-nommu-nofpu.o sh2.o sh4-nommu-nofpu + sh4-nommu-nofpu.o sh2a-nofpu-or-sh3-nommu.o sh4-nommu-nofpu + sh4-nommu-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh4-nommu-nofpu + sh4-nommu-nofpu.o sh2a-or-sh3e.o sh4 + sh4-nommu-nofpu.o sh2a-or-sh4.o sh4 sh4-nommu-nofpu.o sh2e.o sh4 sh4-nommu-nofpu.o sh3-dsp.o sh4al-dsp sh4-nommu-nofpu.o sh3-nommu.o sh4-nommu-nofpu ! sh4-nommu-nofpu.o sh3.o sh4-nommu-nofpu sh4-nommu-nofpu.o sh3e.o sh4 ! sh4-nommu-nofpu.o sh4-nofpu.o sh4-nommu-nofpu sh4-nommu-nofpu.o sh4-nommu-nofpu.o sh4-nommu-nofpu sh4-nommu-nofpu.o sh4.o sh4 sh4-nommu-nofpu.o sh4a-nofpu.o sh4a-nofpu sh4-nommu-nofpu.o sh4a.o sh4a sh4-nommu-nofpu.o sh4al-dsp.o sh4al-dsp ! sh4-nommu-nofpu.o sh-unknown.o sh4-nommu-nofpu sh4.o sh-dsp.o ERROR sh4.o sh.o sh4 sh4.o sh2.o sh4 + sh4.o sh2a-nofpu-or-sh3-nommu.o sh4 + sh4.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh4 + sh4.o sh2a-or-sh3e.o sh4 + sh4.o sh2a-or-sh4.o sh4 sh4.o sh2e.o sh4 sh4.o sh3-dsp.o ERROR sh4.o sh3-nommu.o sh4 *************** sh4.o sh-unknown.o *** 178,183 **** --- 298,307 ---- sh4a-nofpu.o sh-dsp.o sh4al-dsp sh4a-nofpu.o sh.o sh4a-nofpu sh4a-nofpu.o sh2.o sh4a-nofpu + sh4a-nofpu.o sh2a-nofpu-or-sh3-nommu.o sh4a-nofpu + sh4a-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh4a-nofpu + sh4a-nofpu.o sh2a-or-sh3e.o sh4a + sh4a-nofpu.o sh2a-or-sh4.o sh4a sh4a-nofpu.o sh2e.o sh4a sh4a-nofpu.o sh3-dsp.o sh4al-dsp sh4a-nofpu.o sh3-nommu.o sh4a-nofpu *************** sh4a-nofpu.o sh-unknown.o *** 193,198 **** --- 317,326 ---- sh4a.o sh-dsp.o ERROR sh4a.o sh.o sh4a sh4a.o sh2.o sh4a + sh4a.o sh2a-nofpu-or-sh3-nommu.o sh4a + sh4a.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh4a + sh4a.o sh2a-or-sh3e.o sh4a + sh4a.o sh2a-or-sh4.o sh4a sh4a.o sh2e.o sh4a sh4a.o sh3-dsp.o ERROR sh4a.o sh3-nommu.o sh4a *************** sh4a.o sh-unknown.o *** 208,213 **** --- 336,345 ---- sh4al-dsp.o sh-dsp.o sh4al-dsp sh4al-dsp.o sh.o sh4al-dsp sh4al-dsp.o sh2.o sh4al-dsp + sh4al-dsp.o sh2a-nofpu-or-sh3-nommu.o sh4al-dsp + sh4al-dsp.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh4al-dsp + sh4al-dsp.o sh2a-or-sh3e.o ERROR + sh4al-dsp.o sh2a-or-sh4.o ERROR sh4al-dsp.o sh2e.o ERROR sh4al-dsp.o sh3-dsp.o sh4al-dsp sh4al-dsp.o sh3-nommu.o sh4al-dsp *************** sh4al-dsp.o sh4a.o *** 221,237 **** sh4al-dsp.o sh4al-dsp.o sh4al-dsp sh4al-dsp.o sh-unknown.o sh4al-dsp sh-unknown.o sh-dsp.o sh3-dsp ! sh-unknown.o sh.o sh3 ! sh-unknown.o sh2.o sh3 ! sh-unknown.o sh2e.o sh3e sh-unknown.o sh3-dsp.o sh3-dsp ! sh-unknown.o sh3-nommu.o sh3 ! sh-unknown.o sh3.o sh3 ! sh-unknown.o sh3e.o sh3e ! sh-unknown.o sh4-nofpu.o sh4-nofpu ! sh-unknown.o sh4-nommu-nofpu.o sh4-nofpu sh-unknown.o sh4.o sh4 sh-unknown.o sh4a-nofpu.o sh4a-nofpu sh-unknown.o sh4a.o sh4a sh-unknown.o sh4al-dsp.o sh4al-dsp ! sh-unknown.o sh-unknown.o sh3 --- 353,373 ---- sh4al-dsp.o sh4al-dsp.o sh4al-dsp sh4al-dsp.o sh-unknown.o sh4al-dsp sh-unknown.o sh-dsp.o sh3-dsp ! sh-unknown.o sh.o sh2a-nofpu-or-sh3-nommu ! sh-unknown.o sh2.o sh2a-nofpu-or-sh3-nommu ! sh-unknown.o sh2a-nofpu-or-sh3-nommu.o sh2a-nofpu-or-sh3-nommu ! sh-unknown.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu ! sh-unknown.o sh2a-or-sh3e.o sh2a-or-sh3e ! sh-unknown.o sh2a-or-sh4.o sh2a-or-sh4 ! sh-unknown.o sh2e.o sh2a-or-sh3e sh-unknown.o sh3-dsp.o sh3-dsp ! sh-unknown.o sh3-nommu.o sh2a-nofpu-or-sh3-nommu ! sh-unknown.o sh3.o sh2a-nofpu-or-sh3-nommu ! sh-unknown.o sh3e.o sh2a-or-sh3e ! sh-unknown.o sh4-nofpu.o sh4-nommu-nofpu ! sh-unknown.o sh4-nommu-nofpu.o sh4-nommu-nofpu sh-unknown.o sh4.o sh4 sh-unknown.o sh4a-nofpu.o sh4a-nofpu sh-unknown.o sh4a.o sh4a sh-unknown.o sh4al-dsp.o sh4al-dsp ! sh-unknown.o sh-unknown.o sh2a-nofpu-or-sh3-nommu Index: ld/testsuite/ld-sh/arch/sh4.s =================================================================== RCS file: /cvs/src/src/ld/testsuite/ld-sh/arch/sh4.s,v retrieving revision 1.1 diff -c -3 -p -r1.1 sh4.s *** ld/testsuite/ld-sh/arch/sh4.s 29 Jun 2004 16:35:05 -0000 1.1 --- ld/testsuite/ld-sh/arch/sh4.s 15 Dec 2004 16:36:28 -0000 *************** *** 1,3 **** .section .text sh4: ! fabs dr0 --- 1,4 ---- .section .text sh4: ! frchg ! ^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: Broken SH2a patches 2004-12-15 17:11 ` Nick Clifton @ 2004-12-16 13:24 ` Andrew STUBBS 2004-12-20 17:18 ` Nick Clifton 0 siblings, 1 reply; 26+ messages in thread From: Andrew STUBBS @ 2004-12-16 13:24 UTC (permalink / raw) To: 'Nick Clifton' Cc: 'Alexandre Oliva', binutils, 'Joern RENNECKE' Hi Nick, > Features of this patch include: > > * I did not try to update the ASCII art in sh-opc.h with the new > relationships. In my opinion it just makes the diagram too > cluttered to > be useful anymore. Hmmm. That may be true, but I don't like it. Here's my bash at it (note that the inheritance isn't quite as you had it - see below): SH1 | SH2 .------------'|`--------------------------------. / | \ SH-DSP SH3-nommu/SH2A-nofpu SH2E | | |`--------------------. | | | | \| | SH3-nommu SH4-nm-nf/SH2A-nofpu SH3E/SH2A | |\ | | | | | | `------. | SH2A-nofpu | | | | \| \ | | | SH3 SH4-nommu-nofpu `---------+---. | | /|\ | | \| | .-----------' | `--------+---------------------. | SH4/SH2A |/ | / \| | | | .-------' | | | |/ | | SH3-dsp SH4-nofpu SH3E /| | |`-------------------------------. | .-' | | | \|/ | | SH4A-nofpu SH4 SH2A | .------------' `-------------------------------. | |/ \| SH4AL-dsp SH4A Probably there ought to be a comment associated with the diagram explaining that SHx/SHy refers to the intersection between the two architecures. Alternatively the intersections could be made less confusing/dominant by replacing their names with letters and then adding a legend (perhaps also with details of shifts and prefetch differences). > * I have tried to use more meaningful names for the new > machine values. > > * I have added tests for the new machine values to the SH > specific > parts of the GAS and LD testsuites. > > What do you think ? These are all good things, and now there is a problem highlighted in the test results: One example: + sh2a-nofpu-or-sh3-nommu.s -isa=sh2e sh2a-or-sh3e When -isa=sh2e it shouldn't be able to output any other isa, but it clearly is. This is repeated many times. I think this is down to the fact that you haven't created any new base architectures, but instead ored them together: ! #define arch_sh2a_or_sh3e (arch_sh2a_base|arch_sh3_base) I haven't proven this though. In addition to this, the inheritance tree still isn't quite right. I'm beginning to think that if the head maintainer can't get this right then it must be too complicated. I can't think of a better way though. Whatever technique we use it needs to be able to select an architecture, based on the instructions in the file, that specifies what architecture the file will run on, without excluding any other similar, but different, architectures that it may also run on (hence the fake architectures). Any ideas? Specifically the problem is here #define arch_sh3e_up (arch_sh3e | arch_sh2a_or_sh4_up) and here #define arch_sh3_nommu_up (arch_sh3_nommu \ | arch_sh3_up | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up) Both these inheritances cause SH2A to allow SH3 instructions. E.g. 'ldc Rn, SSR', 'ldc Rn, Rn_BANK' etc. According to the document I have from the Renesas web site the SH2A does not have such instructions. Joern and I therefore think that the SH2A may descend from nothing but the SH2 and SH2e, and instead it conceptually introduces some of the instructions used by the SH3 and SH4. The diagram above shows this, but we have not checked this instruction-by-instruction. The code would then read: /* Central branches. */ #define arch_sh1_up (arch_sh1 \ | arch_sh2_up) #define arch_sh2_up (arch_sh2 \ | arch_sh2e_up \ | arch_sh2a_nofpu_or_sh3_nommu_up \ | arch_sh_dsp_up) #define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \ | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \ | arch_sh2a_or_sh3e_up \ | arch_sh3_nommu_up) #define arch_sh2a_nofpu_or_sh4_nommu_nofpu_up (arch_sh2a_nofpu_or_sh4_nommu_nofpu \ | arch_sh2a_nofpu_up \ | arch_sh4_nommu_nofpu_up) #define arch_sh2a_nofpu_up (arch_sh2a_nofpu \ | arch_sh2a_or_sh4_up) #define arch_sh3_nommu_up (arch_sh3_nommu \ | arch_sh3_up \ | arch_sh4_nommu_nofpu_up) #define arch_sh3_up (arch_sh3 \ | arch_sh3e_up \ | arch_sh3_dsp_up \ | arch_sh4_nofp_up) #define arch_sh4_nommu_nofpu_up (arch_sh4_nommu_nofpu \ | arch_sh4_nofp_up) #define arch_sh4_nofp_up (arch_sh4_nofpu \ | arch_sh4_up \ | arch_sh4a_nofp_up) #define arch_sh4a_nofp_up (arch_sh4a_nofpu \ | arch_sh4a_up \ | arch_sh4al_dsp_up) /* Right branches. */ #define arch_sh2e_up (arch_sh2e \ | arch_sh2a_or_sh3e_up) #define arch_sh2a_or_sh3e_up (arch_sh2a_or_sh3e \ | arch_sh2a_or_sh4_up \ | arch_sh3e_up) #define arch_sh2a_or_sh4_up (arch_sh2a_or_sh4 \ | arch_sh2a_up \ | arch_sh4_up) #define arch_sh2a_up (arch_sh2a) #define arch_sh3e_up (arch_sh3e \ | arch_sh4_up) #define arch_sh4_up (arch_sh4 \ | arch_sh4a_up) #define arch_sh4a_up (arch_sh4a) /* Left branch. */ #define arch_sh_dsp_up (arch_sh_dsp \ | arch_sh3_dsp_up) #define arch_sh3_dsp_up (arch_sh3_dsp \ | arch_sh4al_dsp_up) #define arch_sh4al_dsp_up (arch_sh4al_dsp) Please check this over yourself, but it looks right to me. I'm pretty sure it matches the diagram above, but I'm not certain that both match the SH2A architecture. There's plenty of room for screw ups here. We're thinking about ways to automate/simplify this stuff, but nothings going to happen this year I wouldn't think. -- Andrew Stubbs andrew.stubbs@st.com (aka. andrew.stubbs@superh.com) ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Broken SH2a patches 2004-12-16 13:24 ` Andrew STUBBS @ 2004-12-20 17:18 ` Nick Clifton 2005-01-05 13:27 ` Andrew STUBBS ` (3 more replies) 0 siblings, 4 replies; 26+ messages in thread From: Nick Clifton @ 2004-12-20 17:18 UTC (permalink / raw) To: Andrew STUBBS Cc: 'Alexandre Oliva', binutils, 'Joern RENNECKE' [-- Attachment #1: Type: text/plain, Size: 1658 bytes --] Hi Andrew, > Whatever technique we use it needs to be able to select an > architecture, based on the instructions in the file, that > specifies what architecture the file will run on, without > excluding any other similar, but different, architectures > that it may also run on (hence the fake architectures). Any > ideas? The simplest and most extensible scheme would be to drop the different machine values altogether. Just have one bfd_mach_sh number and one EF_SH_ number. Instead binary files would have a new .note section which contains an extensible bit mask of the architectures on which the instructions in that file can be run. When two or more files are combined this mask would be ANDed together to give the mask for the output binary and checked via XOR for incompatibilities. Each instruction would also need one of these bitmasks. When a new architecture is added every instruction's bitmask would have to be updated if it was supported by the new architecture. This would only have to be done once though and there are macros that could be defined to make it simpler. Anyway attached is a revised patch that includes your diagram of the dependencies (thanks) as well as some new base values and a fixed set of architecture definitions. (The problem you noticed with the -isa=sh2e selecting the sh2a-or-sh3e architecture was that the original definition of arch_sh2e defined it in terms of both sh2e_base and sh2a_base). I have also tweaked the #defines for the various base architecture values so it should be easier to add new ones in the future. What do you think of this version ? Cheers Nick [-- Attachment #2: sh.patch.3 --] [-- Type: text/x-troff-man, Size: 83572 bytes --] Index: opcodes/sh-opc.h =================================================================== RCS file: /cvs/src/src/opcodes/sh-opc.h,v retrieving revision 1.22 diff -c -3 -p -r1.22 sh-opc.h *** opcodes/sh-opc.h 29 Jul 2004 05:19:27 -0000 1.22 --- opcodes/sh-opc.h 20 Dec 2004 17:09:48 -0000 *************** typedef enum *** 198,244 **** } sh_dsp_reg_nums; ! #define arch_sh1_base 0x0001 ! #define arch_sh2_base 0x0002 ! #define arch_sh3_base 0x0004 ! #define arch_sh4_base 0x0008 ! #define arch_sh4a_base 0x0010 ! #define arch_sh2a_base 0x0020 ! ! /* This is an annotation on instruction types, but we abuse the arch ! field in instructions to denote it. */ ! #define arch_op32 0x00100000 /* This is a 32-bit opcode. */ ! ! #define arch_sh_no_mmu 0x04000000 ! #define arch_sh_has_mmu 0x08000000 ! #define arch_sh_no_co 0x10000000 /* neither FPU nor DSP co-processor */ ! #define arch_sh_sp_fpu 0x20000000 /* single precision FPU */ ! #define arch_sh_dp_fpu 0x40000000 /* double precision FPU */ ! #define arch_sh_has_dsp 0x80000000 ! ! ! #define arch_sh_base_mask 0x0000003f ! #define arch_opann_mask 0x00100000 ! #define arch_sh_mmu_mask 0x0c000000 ! #define arch_sh_co_mask 0xf0000000 ! ! ! #define arch_sh1 (arch_sh1_base|arch_sh_no_mmu|arch_sh_no_co) ! #define arch_sh2 (arch_sh2_base|arch_sh_no_mmu|arch_sh_no_co) ! #define arch_sh2a (arch_sh2a_base|arch_sh_no_mmu|arch_sh_dp_fpu) ! #define arch_sh2a_nofpu (arch_sh2a_base|arch_sh_no_mmu|arch_sh_no_co) ! #define arch_sh2e (arch_sh2_base|arch_sh2a_base|arch_sh_no_mmu|arch_sh_sp_fpu) ! #define arch_sh_dsp (arch_sh2_base|arch_sh_no_mmu|arch_sh_has_dsp) ! #define arch_sh3_nommu (arch_sh3_base|arch_sh_no_mmu|arch_sh_no_co) ! #define arch_sh3 (arch_sh3_base|arch_sh_has_mmu|arch_sh_no_co) ! #define arch_sh3e (arch_sh3_base|arch_sh_has_mmu|arch_sh_sp_fpu) ! #define arch_sh3_dsp (arch_sh3_base|arch_sh_has_mmu|arch_sh_has_dsp) ! #define arch_sh4 (arch_sh4_base|arch_sh_has_mmu|arch_sh_dp_fpu) ! #define arch_sh4a (arch_sh4a_base|arch_sh_has_mmu|arch_sh_dp_fpu) ! #define arch_sh4al_dsp (arch_sh4a_base|arch_sh_has_mmu|arch_sh_has_dsp) ! #define arch_sh4_nofpu (arch_sh4_base|arch_sh_has_mmu|arch_sh_no_co) ! #define arch_sh4a_nofpu (arch_sh4a_base|arch_sh_has_mmu|arch_sh_no_co) ! #define arch_sh4_nommu_nofpu (arch_sh4_base|arch_sh_no_mmu|arch_sh_no_co) #define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2)) #define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0) --- 198,255 ---- } sh_dsp_reg_nums; ! /* Return a mask with bits LO to HI (inclusive) set. */ ! #define MASK(LO,HI) ( LO < 1 ? ((1 << (HI + 1)) - 1) \ ! : HI > 30 ? (-1 << LO) \ ! : LO == HI ? (1 << LO) \ ! : (((1 << (HI + 1)) - 1) & (-1 << LO))) ! ! #define arch_sh1_base (1 << 0) ! #define arch_sh2_base (1 << 1) ! #define arch_sh2a_sh3_base (1 << 2) ! #define arch_sh3_base (1 << 3) ! #define arch_sh2a_sh4_base (1 << 4) ! #define arch_sh4_base (1 << 5) ! #define arch_sh4a_base (1 << 6) ! #define arch_sh2a_base (1 << 7) ! #define arch_sh_base_mask MASK (0, 7) ! ! /* This is an annotation on instruction types, but we ! abuse the arch field in instructions to denote it. */ ! #define arch_op32 (1 << 25) /* This is a 32-bit opcode. */ ! #define arch_opann_mask MASK (25, 25) ! ! #define arch_sh_no_mmu (1 << 26) ! #define arch_sh_has_mmu (1 << 27) ! #define arch_sh_mmu_mask MASK (26, 27) ! ! #define arch_sh_no_co (1 << 28) /* Neither FPU nor DSP co-processor. */ ! #define arch_sh_sp_fpu (1 << 29) /* Single precision FPU. */ ! #define arch_sh_dp_fpu (1 << 30) /* Double precision FPU. */ ! #define arch_sh_has_dsp (1 << 31) ! #define arch_sh_co_mask MASK (28, 31) ! ! ! #define arch_sh1 (arch_sh1_base |arch_sh_no_mmu |arch_sh_no_co) ! #define arch_sh2 (arch_sh2_base |arch_sh_no_mmu |arch_sh_no_co) ! #define arch_sh2a (arch_sh2a_base |arch_sh_no_mmu |arch_sh_dp_fpu) ! #define arch_sh2a_nofpu (arch_sh2a_base |arch_sh_no_mmu |arch_sh_no_co) ! #define arch_sh2e (arch_sh2_base |arch_sh_no_mmu |arch_sh_sp_fpu) ! #define arch_sh_dsp (arch_sh2_base |arch_sh_no_mmu |arch_sh_has_dsp) ! #define arch_sh3_nommu (arch_sh3_base |arch_sh_no_mmu |arch_sh_no_co) ! #define arch_sh3 (arch_sh3_base |arch_sh_has_mmu|arch_sh_no_co) ! #define arch_sh3e (arch_sh3_base |arch_sh_has_mmu|arch_sh_sp_fpu) ! #define arch_sh3_dsp (arch_sh3_base |arch_sh_has_mmu|arch_sh_has_dsp) ! #define arch_sh4 (arch_sh4_base |arch_sh_has_mmu|arch_sh_dp_fpu) ! #define arch_sh4a (arch_sh4a_base |arch_sh_has_mmu|arch_sh_dp_fpu) ! #define arch_sh4al_dsp (arch_sh4a_base |arch_sh_has_mmu|arch_sh_has_dsp) ! #define arch_sh4_nofpu (arch_sh4_base |arch_sh_has_mmu|arch_sh_no_co) ! #define arch_sh4a_nofpu (arch_sh4a_base |arch_sh_has_mmu|arch_sh_no_co) ! #define arch_sh4_nommu_nofpu (arch_sh4_base |arch_sh_no_mmu |arch_sh_no_co) ! #define arch_sh2a_nofpu_or_sh4_nommu_nofpu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co) ! #define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co) ! #define arch_sh2a_or_sh3e (arch_sh2a_sh4_base) ! #define arch_sh2a_or_sh4 (arch_sh2a_sh4_base |arch_sh_dp_fpu) #define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2)) #define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0) *************** bfd_boolean sh_merge_bfd_arch (bfd *ibfd *** 270,324 **** /* Below are the 'architecture sets'. They describe the following inheritance graph: ! SH1 | SH2 ! .------------'|`--------------------. ! / | \ ! SH-DSP SH3-nommu SH2E ! | |`--------. | ! | | \ | ! | SH3 SH4-nommu-nofpu | ! | | | | ! | .------------'|`----------+---------. | ! |/ / \| ! | | .-------' | ! | |/ | ! SH3-dsp SH4-nofpu SH3E ! | |`--------------------. | ! | | \| ! | SH4A-nofpu SH4 ! | .------------' `--------------------. | ! |/ \| ! SH4AL-dsp SH4A ! */ ! /* Central branches */ ! #define arch_sh1_up (arch_sh1 | arch_sh2_up) ! #define arch_sh2_up (arch_sh2 | arch_sh2e_up | arch_sh2a_nofpu_up | arch_sh3_nommu_up | arch_sh_dsp_up) ! #define arch_sh3_nommu_up (arch_sh3_nommu | arch_sh3_up | arch_sh4_nommu_nofpu_up) ! #define arch_sh3_up (arch_sh3 | arch_sh3e_up | arch_sh3_dsp_up | arch_sh4_nofp_up) ! #define arch_sh4_nommu_nofpu_up (arch_sh4_nommu_nofpu | arch_sh4_nofp_up) ! #define arch_sh4_nofp_up (arch_sh4_nofpu | arch_sh4_up | arch_sh4a_nofp_up) ! #define arch_sh4a_nofp_up (arch_sh4a_nofpu | arch_sh4a_up | arch_sh4al_dsp_up) ! ! /* Right branch */ ! #define arch_sh2e_up (arch_sh2e | arch_sh2a_up | arch_sh3e_up) ! #define arch_sh3e_up (arch_sh3e | arch_sh4_up) ! #define arch_sh4_up (arch_sh4 | arch_sh4a_up) ! #define arch_sh4a_up (arch_sh4a) ! ! /* Left branch */ ! #define arch_sh_dsp_up (arch_sh_dsp | arch_sh3_dsp_up) ! #define arch_sh3_dsp_up (arch_sh3_dsp | arch_sh4al_dsp_up) ! #define arch_sh4al_dsp_up (arch_sh4al_dsp) ! ! /* SH 2a branched off SH2e, adding a lot but not all of SH4 and SH4a. */ ! #define arch_sh2a_up (arch_sh2a) ! #define arch_sh2a_nofpu_up (arch_sh2a_nofpu | arch_sh2a_up) ! typedef struct { --- 281,368 ---- /* Below are the 'architecture sets'. They describe the following inheritance graph: ! SH1 | SH2 ! .------------'|`--------------------------------. ! / | \ ! SH-DSP SH3-nommu/SH2A-nofpu SH2E ! | | |`--------------------. | ! | | | \| ! | SH3-nommu SH4-nm-nf/SH2A-nofpu SH3E/SH2A ! | |\ | | | | ! | | `------. | SH2A-nofpu | | ! | | \| \ | | ! | SH3 SH4-nommu-nofpu `---------+---. | ! | /|\ | | \| ! | .-----------' | `--------+---------------------. | SH4/SH2A ! |/ | / \| | ! | | .-------' | | ! | |/ | | ! SH3-dsp SH4-nofpu SH3E /| ! | |`-------------------------------. | .-' | ! | | \|/ | ! | SH4A-nofpu SH4 SH2A ! | .------------' `-------------------------------. | ! |/ \| ! SH4AL-dsp SH4A */ ! /* Central branches. */ ! #define arch_sh1_up (arch_sh1 \ ! | arch_sh2_up) ! #define arch_sh2_up (arch_sh2 \ ! | arch_sh2e_up \ ! | arch_sh2a_nofpu_or_sh3_nommu_up \ ! | arch_sh_dsp_up) ! #define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \ ! | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \ ! | arch_sh2a_or_sh3e_up \ ! | arch_sh3_nommu_up) ! #define arch_sh2a_nofpu_or_sh4_nommu_nofpu_up (arch_sh2a_nofpu_or_sh4_nommu_nofpu \ ! | arch_sh2a_nofpu_up \ ! | arch_sh4_nommu_nofpu_up) ! #define arch_sh2a_nofpu_up (arch_sh2a_nofpu \ ! | arch_sh2a_or_sh4_up) ! #define arch_sh3_nommu_up (arch_sh3_nommu \ ! | arch_sh3_up \ ! | arch_sh4_nommu_nofpu_up) ! #define arch_sh3_up (arch_sh3 \ ! | arch_sh3e_up \ ! | arch_sh3_dsp_up \ ! | arch_sh4_nofp_up) ! #define arch_sh4_nommu_nofpu_up (arch_sh4_nommu_nofpu \ ! | arch_sh4_nofp_up) ! #define arch_sh4_nofp_up (arch_sh4_nofpu \ ! | arch_sh4_up \ ! | arch_sh4a_nofp_up) ! #define arch_sh4a_nofp_up (arch_sh4a_nofpu \ ! | arch_sh4a_up \ ! | arch_sh4al_dsp_up) ! ! /* Right branches. */ ! #define arch_sh2e_up (arch_sh2e \ ! | arch_sh2a_or_sh3e_up) ! #define arch_sh2a_or_sh3e_up (arch_sh2a_or_sh3e \ ! | arch_sh2a_or_sh4_up \ ! | arch_sh3e_up) ! #define arch_sh2a_or_sh4_up (arch_sh2a_or_sh4 \ ! | arch_sh2a_up \ ! | arch_sh4_up) ! #define arch_sh2a_up (arch_sh2a) ! #define arch_sh3e_up (arch_sh3e \ ! | arch_sh4_up) ! #define arch_sh4_up (arch_sh4 \ ! | arch_sh4a_up) ! #define arch_sh4a_up (arch_sh4a) ! ! /* Left branch. */ ! #define arch_sh_dsp_up (arch_sh_dsp \ ! | arch_sh3_dsp_up) ! #define arch_sh3_dsp_up (arch_sh3_dsp \ ! | arch_sh4al_dsp_up) ! #define arch_sh4al_dsp_up (arch_sh4al_dsp) typedef struct { *************** const sh_opcode_info sh_table[] = *** 634,640 **** /* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh1_up}, ! /* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh4_nommu_nofpu_up | arch_sh2a_nofpu_up}, /* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofp_up}, --- 678,684 ---- /* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh1_up}, ! /* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}, /* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofp_up}, *************** const sh_opcode_info sh_table[] = *** 664,672 **** /* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}, ! /* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh3_nommu_up | arch_sh2a_nofpu_up}, ! /* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh3_nommu_up | arch_sh2a_nofpu_up}, /* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh1_up}, --- 708,716 ---- /* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}, ! /* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}, ! /* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}, /* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh1_up}, *************** const sh_opcode_info sh_table[] = *** 985,1007 **** {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}, /* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}, ! /* 1111nnn001011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}, ! /* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}, ! /* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}, ! /* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh4_up | arch_sh2a_up}, ! /* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh4_up | arch_sh2a_up}, ! /* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}, ! /* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh4_up | arch_sh2a_up}, /* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up}, --- 1029,1051 ---- {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}, /* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}, ! /* 1111nnn001011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2a_or_sh4_up}, /* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}, ! /* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2a_or_sh4_up}, /* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}, ! /* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up}, /* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}, ! /* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_or_sh4_up}, ! /* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh2a_or_sh4_up}, ! /* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh2a_or_sh4_up}, /* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}, ! /* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2a_or_sh4_up}, /* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up}, *************** const sh_opcode_info sh_table[] = *** 1012,1053 **** /* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}, /* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}, ! /* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}, /* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}, ! /* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}, ! /* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}, ! /* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}, ! /* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}, ! /* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}, ! /* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}, ! /* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up | arch_sh2a_up}, ! ! /* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up | arch_sh2a_up}, ! ! /* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up | arch_sh2a_up}, ! ! /* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up | arch_sh2a_up}, ! ! /* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up | arch_sh2a_up}, ! ! /* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up | arch_sh2a_up}, ! /* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up | arch_sh2a_up}, /* 0011nnnnmmmm0001 0011dddddddddddd fmov.d <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.d",{DX_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY8}, arch_sh2a_up | arch_op32}, /* 0011nnnnmmmm0001 0111dddddddddddd fmov.d @(<DISP12>,<REG_M>),F_REG_N */ --- 1056,1092 ---- /* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}, /* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}, ! /* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2a_or_sh4_up}, /* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}, /* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}, ! /* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2a_or_sh4_up}, /* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}, ! /* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}, /* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}, ! /* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}, /* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}, ! /* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}, /* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}, ! /* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}, /* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}, ! /* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}, /* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}, ! /* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}, ! /* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}, ! /* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}, ! /* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}, ! /* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}, ! /* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}, ! /* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}, /* 0011nnnnmmmm0001 0011dddddddddddd fmov.d <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.d",{DX_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY8}, arch_sh2a_up | arch_op32}, /* 0011nnnnmmmm0001 0111dddddddddddd fmov.d @(<DISP12>,<REG_M>),F_REG_N */ *************** const sh_opcode_info sh_table[] = *** 1070,1079 **** {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}, /* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}, ! /* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}, ! /* 1111nnn001001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh4_up | arch_sh2a_up}, /* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}, --- 1109,1118 ---- {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}, /* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}, ! /* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2a_or_sh4_up}, /* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}, ! /* 1111nnn001001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2a_or_sh4_up}, /* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}, *************** const sh_opcode_info sh_table[] = *** 1081,1100 **** /* 1111nnn011111101 fsca FPUL,<D_REG_N> */{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_F,HEX_D}, arch_sh4_up}, ! /* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh4_up | arch_sh2a_up}, ! /* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh3e_up | arch_sh2a_up}, ! /* 1111nnn001101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}, /* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}, /* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}, ! /* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh4_up | arch_sh2a_up}, /* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}, ! /* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh4_up | arch_sh2a_up}, /* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}, --- 1120,1139 ---- /* 1111nnn011111101 fsca FPUL,<D_REG_N> */{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_F,HEX_D}, arch_sh4_up}, ! /* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh2a_or_sh4_up}, ! /* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}, ! /* 1111nnn001101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh4_up}, /* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}, /* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}, /* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}, ! /* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}, /* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}, ! /* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}, /* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}, Index: bfd/archures.c =================================================================== RCS file: /cvs/src/src/bfd/archures.c,v retrieving revision 1.100 diff -c -3 -p -r1.100 archures.c *** bfd/archures.c 9 Dec 2004 06:08:45 -0000 1.100 --- bfd/archures.c 20 Dec 2004 17:09:48 -0000 *************** DESCRIPTION *** 235,244 **** .#define bfd_mach_sh_dsp 0x2d .#define bfd_mach_sh2a 0x2a .#define bfd_mach_sh2a_nofpu 0x2b ! .#define bfd_mach_sh2a_fake1 0x2a1 ! .#define bfd_mach_sh2a_fake2 0x2a2 ! .#define bfd_mach_sh2a_fake3 0x2a3 ! .#define bfd_mach_sh2a_fake4 0x2a4 .#define bfd_mach_sh2e 0x2e .#define bfd_mach_sh3 0x30 .#define bfd_mach_sh3_nommu 0x31 --- 235,244 ---- .#define bfd_mach_sh_dsp 0x2d .#define bfd_mach_sh2a 0x2a .#define bfd_mach_sh2a_nofpu 0x2b ! .#define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1 ! .#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2 ! .#define bfd_mach_sh2a_or_sh4 0x2a3 ! .#define bfd_mach_sh2a_or_sh3e 0x2a4 .#define bfd_mach_sh2e 0x2e .#define bfd_mach_sh3 0x30 .#define bfd_mach_sh3_nommu 0x31 Index: bfd/cpu-sh.c =================================================================== RCS file: /cvs/src/src/bfd/cpu-sh.c,v retrieving revision 1.17 diff -c -3 -p -r1.17 cpu-sh.c *** bfd/cpu-sh.c 13 Aug 2004 03:15:56 -0000 1.17 --- bfd/cpu-sh.c 20 Dec 2004 17:09:49 -0000 *************** *** 24,46 **** #include "libbfd.h" #include "../opcodes/sh-opc.h" ! #define SH_NEXT &arch_info_struct[0] ! #define SH2_NEXT &arch_info_struct[1] ! #define SH2E_NEXT &arch_info_struct[2] ! #define SH_DSP_NEXT &arch_info_struct[3] ! #define SH3_NEXT &arch_info_struct[4] ! #define SH3_NOMMU_NEXT &arch_info_struct[5] ! #define SH3_DSP_NEXT &arch_info_struct[6] ! #define SH3E_NEXT &arch_info_struct[7] ! #define SH4_NEXT &arch_info_struct[8] ! #define SH4A_NEXT &arch_info_struct[9] ! #define SH4AL_DSP_NEXT &arch_info_struct[10] ! #define SH4_NOFPU_NEXT &arch_info_struct[11] ! #define SH4_NOMMU_NOFPU_NEXT &arch_info_struct[12] ! #define SH4A_NOFPU_NEXT &arch_info_struct[13] ! #define SH2A_NEXT &arch_info_struct[14] ! #define SH2A_NOFPU_NEXT &arch_info_struct[15] ! #define SH64_NEXT NULL static const bfd_arch_info_type arch_info_struct[] = { --- 24,50 ---- #include "libbfd.h" #include "../opcodes/sh-opc.h" ! #define SH_NEXT arch_info_struct + 0 ! #define SH2_NEXT arch_info_struct + 1 ! #define SH2E_NEXT arch_info_struct + 2 ! #define SH_DSP_NEXT arch_info_struct + 3 ! #define SH3_NEXT arch_info_struct + 4 ! #define SH3_NOMMU_NEXT arch_info_struct + 5 ! #define SH3_DSP_NEXT arch_info_struct + 6 ! #define SH3E_NEXT arch_info_struct + 7 ! #define SH4_NEXT arch_info_struct + 8 ! #define SH4A_NEXT arch_info_struct + 9 ! #define SH4AL_DSP_NEXT arch_info_struct + 10 ! #define SH4_NOFPU_NEXT arch_info_struct + 11 ! #define SH4_NOMMU_NOFPU_NEXT arch_info_struct + 12 ! #define SH4A_NOFPU_NEXT arch_info_struct + 13 ! #define SH2A_NEXT arch_info_struct + 14 ! #define SH2A_NOFPU_NEXT arch_info_struct + 15 ! #define SH2A_NOFPU_OR_SH4_NOMMU_NOFPU_NEXT arch_info_struct + 16 ! #define SH2A_NOFPU_OR_SH3_NOMMU_NEXT arch_info_struct + 17 ! #define SH2A_OR_SH4_NEXT arch_info_struct + 18 ! #define SH2A_OR_SH3E_NEXT arch_info_struct + 19 ! #define SH64_NEXT NULL static const bfd_arch_info_type arch_info_struct[] = { *************** static const bfd_arch_info_type arch_inf *** 255,260 **** --- 259,320 ---- SH2A_NOFPU_NEXT }, { + 32, /* 32 bits in a word. */ + 32, /* 32 bits in an address. */ + 8, /* 8 bits in a byte. */ + bfd_arch_sh, + bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, + "sh", /* Arch_name. */ + "sh2a-nofpu-or-sh4-nommu-nofpu", /* Printable name. */ + 1, + FALSE, /* Not the default. */ + bfd_default_compatible, + bfd_default_scan, + SH2A_NOFPU_OR_SH4_NOMMU_NOFPU_NEXT + }, + { + 32, /* 32 bits in a word. */ + 32, /* 32 bits in an address. */ + 8, /* 8 bits in a byte. */ + bfd_arch_sh, + bfd_mach_sh2a_nofpu_or_sh3_nommu, + "sh", /* Arch_name. */ + "sh2a-nofpu-or-sh3-nommu", /* Printable name. */ + 1, + FALSE, /* Not the default. */ + bfd_default_compatible, + bfd_default_scan, + SH2A_NOFPU_OR_SH3_NOMMU_NEXT + }, + { + 32, /* 32 bits in a word. */ + 32, /* 32 bits in an address. */ + 8, /* 8 bits in a byte. */ + bfd_arch_sh, + bfd_mach_sh2a_or_sh4, + "sh", /* Arch_name. */ + "sh2a-or-sh4", /* Printable name. */ + 1, + FALSE, /* Not the default. */ + bfd_default_compatible, + bfd_default_scan, + SH2A_OR_SH4_NEXT + }, + { + 32, /* 32 bits in a word. */ + 32, /* 32 bits in an address. */ + 8, /* 8 bits in a byte. */ + bfd_arch_sh, + bfd_mach_sh2a_or_sh3e, + "sh", /* Arch_name. */ + "sh2a-or-sh3e", /* Printable name. */ + 1, + FALSE, /* Not the default. */ + bfd_default_compatible, + bfd_default_scan, + SH2A_OR_SH3E_NEXT + }, + { 64, /* 64 bits in a word */ 64, /* 64 bits in an address */ 8, /* 8 bits in a byte */ *************** static struct { unsigned long bfd_mach, *** 301,306 **** --- 361,372 ---- { bfd_mach_sh_dsp, arch_sh_dsp, arch_sh_dsp_up }, { bfd_mach_sh2a, arch_sh2a, arch_sh2a_up }, { bfd_mach_sh2a_nofpu, arch_sh2a_nofpu, arch_sh2a_nofpu_up }, + + { bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, arch_sh2a_nofpu_or_sh4_nommu_nofpu, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up }, + { bfd_mach_sh2a_nofpu_or_sh3_nommu, arch_sh2a_nofpu_or_sh3_nommu, arch_sh2a_nofpu_or_sh3_nommu_up }, + { bfd_mach_sh2a_or_sh4, arch_sh2a_or_sh4, arch_sh2a_or_sh4_up }, + { bfd_mach_sh2a_or_sh3e, arch_sh2a_or_sh3e, arch_sh2a_or_sh3e_up }, + { bfd_mach_sh3, arch_sh3, arch_sh3_up }, { bfd_mach_sh3_nommu, arch_sh3_nommu, arch_sh3_nommu_up }, { bfd_mach_sh3_dsp, arch_sh3_dsp, arch_sh3_dsp_up }, Index: include/elf/sh.h =================================================================== RCS file: /cvs/src/src/include/elf/sh.h,v retrieving revision 1.19 diff -c -3 -p -r1.19 sh.h *** include/elf/sh.h 29 Jul 2004 05:17:37 -0000 1.19 --- include/elf/sh.h 20 Dec 2004 17:09:51 -0000 *************** *** 42,47 **** --- 42,52 ---- #define EF_SH2A_NOFPU 19 #define EF_SH3_NOMMU 20 + #define EF_SH2A_SH4_NOFPU 21 + #define EF_SH2A_SH3_NOFPU 22 + #define EF_SH2A_SH4 23 + #define EF_SH2A_SH3E 24 + /* This one can only mix in objects from other EF_SH5 objects. */ #define EF_SH5 10 *************** *** 68,74 **** /* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \ /* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \ /* EF_SH2A_NOFPU */ bfd_mach_sh2a_nofpu , \ ! /* EF_SH3_NOMMU */ bfd_mach_sh3_nommu /* Convert arch_sh* into EF_SH*. */ int sh_find_elf_flags (unsigned int arch_set); --- 73,83 ---- /* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \ /* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \ /* EF_SH2A_NOFPU */ bfd_mach_sh2a_nofpu , \ ! /* EF_SH3_NOMMU */ bfd_mach_sh3_nommu , \ ! /* EF_SH2A_SH4_NOFPU */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \ ! /* EF_SH2A_SH3_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \ ! /* EF_SH2A_SH4 */ bfd_mach_sh2a_or_sh4 , \ ! /* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e /* Convert arch_sh* into EF_SH*. */ int sh_find_elf_flags (unsigned int arch_set); Index: gas/testsuite/gas/sh/arch/arch_expected.txt =================================================================== RCS file: /cvs/src/src/gas/testsuite/gas/sh/arch/arch_expected.txt,v retrieving revision 1.1 diff -c -3 -p -r1.1 arch_expected.txt *** gas/testsuite/gas/sh/arch/arch_expected.txt 29 Jun 2004 16:35:05 -0000 1.1 --- gas/testsuite/gas/sh/arch/arch_expected.txt 20 Dec 2004 17:09:55 -0000 *************** sh-dsp.s -isa=sh *** 21,26 **** --- 21,34 ---- sh-dsp.s -isa=sh-up sh-dsp sh-dsp.s -isa=sh2 ERROR sh-dsp.s -isa=sh2-up sh-dsp + sh-dsp.s -isa=sh2a-nofpu-or-sh3-nommu ERROR + sh-dsp.s -isa=sh2a-nofpu-or-sh3-nommu-up sh3-dsp + sh-dsp.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR + sh-dsp.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4al-dsp + sh-dsp.s -isa=sh2a-or-sh3e ERROR + sh-dsp.s -isa=sh2a-or-sh3e-up ERROR + sh-dsp.s -isa=sh2a-or-sh4 ERROR + sh-dsp.s -isa=sh2a-or-sh4-up ERROR sh-dsp.s -isa=sh2e ERROR sh-dsp.s -isa=sh2e-up ERROR sh-dsp.s -isa=sh3-dsp sh3-dsp *************** sh.s -isa=sh *** 54,59 **** --- 62,75 ---- sh.s -isa=sh-up sh sh.s -isa=sh2 sh2 sh.s -isa=sh2-up sh2 + sh.s -isa=sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu + sh.s -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-nofpu-or-sh3-nommu + sh.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu sh2a-nofpu-or-sh4-nommu-nofpu + sh.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-nofpu-or-sh4-nommu-nofpu + sh.s -isa=sh2a-or-sh3e ERROR + sh.s -isa=sh2a-or-sh3e-up sh2a-or-sh3e + sh.s -isa=sh2a-or-sh4 ERROR + sh.s -isa=sh2a-or-sh4-up sh2a-or-sh4 sh.s -isa=sh2e sh2e sh.s -isa=sh2e-up sh2e sh.s -isa=sh3-dsp sh3-dsp *************** sh2.s -isa=sh *** 87,92 **** --- 103,116 ---- sh2.s -isa=sh-up sh2 sh2.s -isa=sh2 sh2 sh2.s -isa=sh2-up sh2 + sh2.s -isa=sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu + sh2.s -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-nofpu-or-sh3-nommu + sh2.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu sh2a-nofpu-or-sh4-nommu-nofpu + sh2.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-nofpu-or-sh4-nommu-nofpu + sh2.s -isa=sh2a-or-sh3e ERROR + sh2.s -isa=sh2a-or-sh3e-up sh2a-or-sh3e + sh2.s -isa=sh2a-or-sh4 ERROR + sh2.s -isa=sh2a-or-sh4-up sh2a-or-sh4 sh2.s -isa=sh2e sh2e sh2.s -isa=sh2e-up sh2e sh2.s -isa=sh3-dsp sh3-dsp *************** sh2.s -isa=sh4a *** 109,114 **** --- 133,302 ---- sh2.s -isa=sh4a-up sh4a sh2.s -isa=sh4al-dsp sh4al-dsp sh2.s -isa=sh4al-dsp-up sh4al-dsp + sh2a-nofpu-or-sh3-nommu.s default-options sh2a-nofpu-or-sh3-nommu + sh2a-nofpu-or-sh3-nommu.s -dsp sh2a-nofpu-or-sh3-nommu + sh2a-nofpu-or-sh3-nommu.s -isa=any sh2a-nofpu-or-sh3-nommu + sh2a-nofpu-or-sh3-nommu.s -isa=dsp sh2a-nofpu-or-sh3-nommu + sh2a-nofpu-or-sh3-nommu.s -isa=fp sh2a-nofpu-or-sh3-nommu + sh2a-nofpu-or-sh3-nommu.s -isa=sh-dsp ERROR + sh2a-nofpu-or-sh3-nommu.s -isa=sh-dsp-up sh3-dsp + sh2a-nofpu-or-sh3-nommu.s -isa=sh ERROR + sh2a-nofpu-or-sh3-nommu.s -isa=sh-up sh2a-nofpu-or-sh3-nommu + sh2a-nofpu-or-sh3-nommu.s -isa=sh2 ERROR + sh2a-nofpu-or-sh3-nommu.s -isa=sh2-up sh2a-nofpu-or-sh3-nommu + sh2a-nofpu-or-sh3-nommu.s -isa=sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu + sh2a-nofpu-or-sh3-nommu.s -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-nofpu-or-sh3-nommu + sh2a-nofpu-or-sh3-nommu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu sh2a-nofpu-or-sh4-nommu-nofpu + sh2a-nofpu-or-sh3-nommu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-nofpu-or-sh4-nommu-nofpu + sh2a-nofpu-or-sh3-nommu.s -isa=sh2a-or-sh3e ERROR + sh2a-nofpu-or-sh3-nommu.s -isa=sh2a-or-sh3e-up sh2a-or-sh3e + sh2a-nofpu-or-sh3-nommu.s -isa=sh2a-or-sh4 ERROR + sh2a-nofpu-or-sh3-nommu.s -isa=sh2a-or-sh4-up sh2a-or-sh4 + sh2a-nofpu-or-sh3-nommu.s -isa=sh2e ERROR + sh2a-nofpu-or-sh3-nommu.s -isa=sh2e-up sh2a-or-sh3e + sh2a-nofpu-or-sh3-nommu.s -isa=sh3-dsp sh3-dsp + sh2a-nofpu-or-sh3-nommu.s -isa=sh3-dsp-up sh3-dsp + sh2a-nofpu-or-sh3-nommu.s -isa=sh3-nommu sh3-nommu + sh2a-nofpu-or-sh3-nommu.s -isa=sh3-nommu-up sh3-nommu + sh2a-nofpu-or-sh3-nommu.s -isa=sh3 sh3 + sh2a-nofpu-or-sh3-nommu.s -isa=sh3-up sh3 + sh2a-nofpu-or-sh3-nommu.s -isa=sh3e sh3e + sh2a-nofpu-or-sh3-nommu.s -isa=sh3e-up sh3e + sh2a-nofpu-or-sh3-nommu.s -isa=sh4-nofpu sh4-nofpu + sh2a-nofpu-or-sh3-nommu.s -isa=sh4-nofpu-up sh4-nofpu + sh2a-nofpu-or-sh3-nommu.s -isa=sh4-nommu-nofpu sh4-nommu-nofpu + sh2a-nofpu-or-sh3-nommu.s -isa=sh4-nommu-nofpu-up sh4-nommu-nofpu + sh2a-nofpu-or-sh3-nommu.s -isa=sh4 sh4 + sh2a-nofpu-or-sh3-nommu.s -isa=sh4-up sh4 + sh2a-nofpu-or-sh3-nommu.s -isa=sh4a-nofpu sh4a-nofpu + sh2a-nofpu-or-sh3-nommu.s -isa=sh4a-nofpu-up sh4a-nofpu + sh2a-nofpu-or-sh3-nommu.s -isa=sh4a sh4a + sh2a-nofpu-or-sh3-nommu.s -isa=sh4a-up sh4a + sh2a-nofpu-or-sh3-nommu.s -isa=sh4al-dsp sh4al-dsp + sh2a-nofpu-or-sh3-nommu.s -isa=sh4al-dsp-up sh4al-dsp + sh2a-nofpu-or-sh4-nommu-nofpu.s default-options sh2a-nofpu-or-sh4-nommu-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -dsp sh2a-nofpu-or-sh4-nommu-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=any sh2a-nofpu-or-sh4-nommu-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=dsp sh2a-nofpu-or-sh4-nommu-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=fp sh2a-nofpu-or-sh4-nommu-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh-dsp ERROR + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh-dsp-up sh4al-dsp + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh ERROR + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh-up sh2a-nofpu-or-sh4-nommu-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2 ERROR + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2-up sh2a-nofpu-or-sh4-nommu-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-nofpu-or-sh4-nommu-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu sh2a-nofpu-or-sh4-nommu-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-nofpu-or-sh4-nommu-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a-or-sh3e ERROR + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a-or-sh3e-up sh2a-or-sh4 + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a-or-sh4 ERROR + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a-or-sh4-up sh2a-or-sh4 + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2e ERROR + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2e-up sh2a-or-sh4 + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh3-dsp ERROR + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh3-dsp-up sh4al-dsp + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh3-nommu ERROR + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh3-nommu-up sh4-nommu-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh3 ERROR + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh3-up sh4-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh3e ERROR + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh3e-up sh4 + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4-nofpu sh4-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4-nofpu-up sh4-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4-nommu-nofpu sh4-nommu-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4-nommu-nofpu-up sh4-nommu-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4 sh4 + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4-up sh4 + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4a-nofpu sh4a-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4a-nofpu-up sh4a-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4a sh4a + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4a-up sh4a + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4al-dsp sh4al-dsp + sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4al-dsp-up sh4al-dsp + sh2a-or-sh3e.s default-options sh2a-or-sh3e + sh2a-or-sh3e.s -dsp ERROR + sh2a-or-sh3e.s -isa=any sh2a-or-sh3e + sh2a-or-sh3e.s -isa=dsp ERROR + sh2a-or-sh3e.s -isa=fp sh2a-or-sh3e + sh2a-or-sh3e.s -isa=sh-dsp ERROR + sh2a-or-sh3e.s -isa=sh-dsp-up ERROR + sh2a-or-sh3e.s -isa=sh ERROR + sh2a-or-sh3e.s -isa=sh-up sh2a-or-sh3e + sh2a-or-sh3e.s -isa=sh2 ERROR + sh2a-or-sh3e.s -isa=sh2-up sh2a-or-sh3e + sh2a-or-sh3e.s -isa=sh2a-nofpu-or-sh3-nommu ERROR + sh2a-or-sh3e.s -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-or-sh3e + sh2a-or-sh3e.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR + sh2a-or-sh3e.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-or-sh4 + sh2a-or-sh3e.s -isa=sh2a-or-sh3e ERROR + sh2a-or-sh3e.s -isa=sh2a-or-sh3e-up sh2a-or-sh3e + sh2a-or-sh3e.s -isa=sh2a-or-sh4 ERROR + sh2a-or-sh3e.s -isa=sh2a-or-sh4-up sh2a-or-sh4 + sh2a-or-sh3e.s -isa=sh2e ERROR + sh2a-or-sh3e.s -isa=sh2e-up sh2a-or-sh3e + sh2a-or-sh3e.s -isa=sh3-dsp ERROR + sh2a-or-sh3e.s -isa=sh3-dsp-up ERROR + sh2a-or-sh3e.s -isa=sh3-nommu ERROR + sh2a-or-sh3e.s -isa=sh3-nommu-up sh3e + sh2a-or-sh3e.s -isa=sh3 ERROR + sh2a-or-sh3e.s -isa=sh3-up sh3e + sh2a-or-sh3e.s -isa=sh3e sh3e + sh2a-or-sh3e.s -isa=sh3e-up sh3e + sh2a-or-sh3e.s -isa=sh4-nofpu ERROR + sh2a-or-sh3e.s -isa=sh4-nofpu-up sh4 + sh2a-or-sh3e.s -isa=sh4-nommu-nofpu ERROR + sh2a-or-sh3e.s -isa=sh4-nommu-nofpu-up sh4 + sh2a-or-sh3e.s -isa=sh4 sh4 + sh2a-or-sh3e.s -isa=sh4-up sh4 + sh2a-or-sh3e.s -isa=sh4a-nofpu ERROR + sh2a-or-sh3e.s -isa=sh4a-nofpu-up sh4a + sh2a-or-sh3e.s -isa=sh4a sh4a + sh2a-or-sh3e.s -isa=sh4a-up sh4a + sh2a-or-sh3e.s -isa=sh4al-dsp ERROR + sh2a-or-sh3e.s -isa=sh4al-dsp-up ERROR + sh2a-or-sh4.s default-options sh2a-or-sh4 + sh2a-or-sh4.s -dsp ERROR + sh2a-or-sh4.s -isa=any sh2a-or-sh4 + sh2a-or-sh4.s -isa=dsp ERROR + sh2a-or-sh4.s -isa=fp sh2a-or-sh4 + sh2a-or-sh4.s -isa=sh-dsp ERROR + sh2a-or-sh4.s -isa=sh-dsp-up ERROR + sh2a-or-sh4.s -isa=sh ERROR + sh2a-or-sh4.s -isa=sh-up sh2a-or-sh4 + sh2a-or-sh4.s -isa=sh2 ERROR + sh2a-or-sh4.s -isa=sh2-up sh2a-or-sh4 + sh2a-or-sh4.s -isa=sh2a-nofpu-or-sh3-nommu ERROR + sh2a-or-sh4.s -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-or-sh4 + sh2a-or-sh4.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR + sh2a-or-sh4.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-or-sh4 + sh2a-or-sh4.s -isa=sh2a-or-sh3e ERROR + sh2a-or-sh4.s -isa=sh2a-or-sh3e-up sh2a-or-sh4 + sh2a-or-sh4.s -isa=sh2a-or-sh4 ERROR + sh2a-or-sh4.s -isa=sh2a-or-sh4-up sh2a-or-sh4 + sh2a-or-sh4.s -isa=sh2e ERROR + sh2a-or-sh4.s -isa=sh2e-up sh2a-or-sh4 + sh2a-or-sh4.s -isa=sh3-dsp ERROR + sh2a-or-sh4.s -isa=sh3-dsp-up ERROR + sh2a-or-sh4.s -isa=sh3-nommu ERROR + sh2a-or-sh4.s -isa=sh3-nommu-up sh4 + sh2a-or-sh4.s -isa=sh3 ERROR + sh2a-or-sh4.s -isa=sh3-up sh4 + sh2a-or-sh4.s -isa=sh3e ERROR + sh2a-or-sh4.s -isa=sh3e-up sh4 + sh2a-or-sh4.s -isa=sh4-nofpu ERROR + sh2a-or-sh4.s -isa=sh4-nofpu-up sh4 + sh2a-or-sh4.s -isa=sh4-nommu-nofpu ERROR + sh2a-or-sh4.s -isa=sh4-nommu-nofpu-up sh4 + sh2a-or-sh4.s -isa=sh4 sh4 + sh2a-or-sh4.s -isa=sh4-up sh4 + sh2a-or-sh4.s -isa=sh4a-nofpu ERROR + sh2a-or-sh4.s -isa=sh4a-nofpu-up sh4a + sh2a-or-sh4.s -isa=sh4a sh4a + sh2a-or-sh4.s -isa=sh4a-up sh4a + sh2a-or-sh4.s -isa=sh4al-dsp ERROR + sh2a-or-sh4.s -isa=sh4al-dsp-up ERROR sh2e.s default-options sh2e sh2e.s -dsp ERROR sh2e.s -isa=any sh2e *************** sh2e.s -isa=sh *** 120,125 **** --- 308,321 ---- sh2e.s -isa=sh-up sh2e sh2e.s -isa=sh2 ERROR sh2e.s -isa=sh2-up sh2e + sh2e.s -isa=sh2a-nofpu-or-sh3-nommu ERROR + sh2e.s -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-or-sh3e + sh2e.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR + sh2e.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-or-sh4 + sh2e.s -isa=sh2a-or-sh3e ERROR + sh2e.s -isa=sh2a-or-sh3e-up sh2a-or-sh3e + sh2e.s -isa=sh2a-or-sh4 ERROR + sh2e.s -isa=sh2a-or-sh4-up sh2a-or-sh4 sh2e.s -isa=sh2e sh2e sh2e.s -isa=sh2e-up sh2e sh2e.s -isa=sh3-dsp ERROR *************** sh3-dsp.s -isa=sh *** 153,158 **** --- 349,362 ---- sh3-dsp.s -isa=sh-up sh3-dsp sh3-dsp.s -isa=sh2 ERROR sh3-dsp.s -isa=sh2-up sh3-dsp + sh3-dsp.s -isa=sh2a-nofpu-or-sh3-nommu ERROR + sh3-dsp.s -isa=sh2a-nofpu-or-sh3-nommu-up sh3-dsp + sh3-dsp.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR + sh3-dsp.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4al-dsp + sh3-dsp.s -isa=sh2a-or-sh3e ERROR + sh3-dsp.s -isa=sh2a-or-sh3e-up ERROR + sh3-dsp.s -isa=sh2a-or-sh4 ERROR + sh3-dsp.s -isa=sh2a-or-sh4-up ERROR sh3-dsp.s -isa=sh2e ERROR sh3-dsp.s -isa=sh2e-up ERROR sh3-dsp.s -isa=sh3-dsp sh3-dsp *************** sh3-nommu.s -isa=sh *** 186,191 **** --- 390,403 ---- sh3-nommu.s -isa=sh-up sh3-nommu sh3-nommu.s -isa=sh2 ERROR sh3-nommu.s -isa=sh2-up sh3-nommu + sh3-nommu.s -isa=sh2a-nofpu-or-sh3-nommu ERROR + sh3-nommu.s -isa=sh2a-nofpu-or-sh3-nommu-up sh3-nommu + sh3-nommu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR + sh3-nommu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4-nommu-nofpu + sh3-nommu.s -isa=sh2a-or-sh3e ERROR + sh3-nommu.s -isa=sh2a-or-sh3e-up sh3e + sh3-nommu.s -isa=sh2a-or-sh4 ERROR + sh3-nommu.s -isa=sh2a-or-sh4-up sh4 sh3-nommu.s -isa=sh2e ERROR sh3-nommu.s -isa=sh2e-up sh3e sh3-nommu.s -isa=sh3-dsp sh3-dsp *************** sh3.s -isa=sh *** 219,224 **** --- 431,444 ---- sh3.s -isa=sh-up sh3 sh3.s -isa=sh2 ERROR sh3.s -isa=sh2-up sh3 + sh3.s -isa=sh2a-nofpu-or-sh3-nommu ERROR + sh3.s -isa=sh2a-nofpu-or-sh3-nommu-up sh3 + sh3.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR + sh3.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4-nofpu + sh3.s -isa=sh2a-or-sh3e ERROR + sh3.s -isa=sh2a-or-sh3e-up sh3e + sh3.s -isa=sh2a-or-sh4 ERROR + sh3.s -isa=sh2a-or-sh4-up sh4 sh3.s -isa=sh2e ERROR sh3.s -isa=sh2e-up sh3e sh3.s -isa=sh3-dsp sh3-dsp *************** sh3.s -isa=sh4a *** 241,259 **** sh3.s -isa=sh4a-up sh4a sh3.s -isa=sh4al-dsp sh4al-dsp sh3.s -isa=sh4al-dsp-up sh4al-dsp ! sh3e.s default-options sh3e sh3e.s -dsp ERROR ! sh3e.s -isa=any sh3e sh3e.s -isa=dsp ERROR ! sh3e.s -isa=fp sh3e sh3e.s -isa=sh-dsp ERROR sh3e.s -isa=sh-dsp-up ERROR sh3e.s -isa=sh ERROR ! sh3e.s -isa=sh-up sh3e sh3e.s -isa=sh2 ERROR ! sh3e.s -isa=sh2-up sh3e sh3e.s -isa=sh2e ERROR ! sh3e.s -isa=sh2e-up sh3e sh3e.s -isa=sh3-dsp ERROR sh3e.s -isa=sh3-dsp-up ERROR sh3e.s -isa=sh3-nommu ERROR --- 461,487 ---- sh3.s -isa=sh4a-up sh4a sh3.s -isa=sh4al-dsp sh4al-dsp sh3.s -isa=sh4al-dsp-up sh4al-dsp ! sh3e.s default-options sh2a-or-sh3e sh3e.s -dsp ERROR ! sh3e.s -isa=any sh2a-or-sh3e sh3e.s -isa=dsp ERROR ! sh3e.s -isa=fp sh2a-or-sh3e sh3e.s -isa=sh-dsp ERROR sh3e.s -isa=sh-dsp-up ERROR sh3e.s -isa=sh ERROR ! sh3e.s -isa=sh-up sh2a-or-sh3e sh3e.s -isa=sh2 ERROR ! sh3e.s -isa=sh2-up sh2a-or-sh3e ! sh3e.s -isa=sh2a-nofpu-or-sh3-nommu ERROR ! sh3e.s -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-or-sh3e ! sh3e.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR ! sh3e.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-or-sh4 ! sh3e.s -isa=sh2a-or-sh3e ERROR ! sh3e.s -isa=sh2a-or-sh3e-up sh2a-or-sh3e ! sh3e.s -isa=sh2a-or-sh4 ERROR ! sh3e.s -isa=sh2a-or-sh4-up sh2a-or-sh4 sh3e.s -isa=sh2e ERROR ! sh3e.s -isa=sh2e-up sh2a-or-sh3e sh3e.s -isa=sh3-dsp ERROR sh3e.s -isa=sh3-dsp-up ERROR sh3e.s -isa=sh3-nommu ERROR *************** sh4-nofpu.s -isa=sh *** 285,290 **** --- 513,526 ---- sh4-nofpu.s -isa=sh-up sh4-nofpu sh4-nofpu.s -isa=sh2 ERROR sh4-nofpu.s -isa=sh2-up sh4-nofpu + sh4-nofpu.s -isa=sh2a-nofpu-or-sh3-nommu ERROR + sh4-nofpu.s -isa=sh2a-nofpu-or-sh3-nommu-up sh4-nofpu + sh4-nofpu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR + sh4-nofpu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4-nofpu + sh4-nofpu.s -isa=sh2a-or-sh3e ERROR + sh4-nofpu.s -isa=sh2a-or-sh3e-up sh4 + sh4-nofpu.s -isa=sh2a-or-sh4 ERROR + sh4-nofpu.s -isa=sh2a-or-sh4-up sh4 sh4-nofpu.s -isa=sh2e ERROR sh4-nofpu.s -isa=sh2e-up sh4 sh4-nofpu.s -isa=sh3-dsp ERROR *************** sh4-nommu-nofpu.s -isa=sh *** 318,323 **** --- 554,567 ---- sh4-nommu-nofpu.s -isa=sh-up sh4-nommu-nofpu sh4-nommu-nofpu.s -isa=sh2 ERROR sh4-nommu-nofpu.s -isa=sh2-up sh4-nommu-nofpu + sh4-nommu-nofpu.s -isa=sh2a-nofpu-or-sh3-nommu ERROR + sh4-nommu-nofpu.s -isa=sh2a-nofpu-or-sh3-nommu-up sh4-nommu-nofpu + sh4-nommu-nofpu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR + sh4-nommu-nofpu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4-nommu-nofpu + sh4-nommu-nofpu.s -isa=sh2a-or-sh3e ERROR + sh4-nommu-nofpu.s -isa=sh2a-or-sh3e-up sh4 + sh4-nommu-nofpu.s -isa=sh2a-or-sh4 ERROR + sh4-nommu-nofpu.s -isa=sh2a-or-sh4-up sh4 sh4-nommu-nofpu.s -isa=sh2e ERROR sh4-nommu-nofpu.s -isa=sh2e-up sh4 sh4-nommu-nofpu.s -isa=sh3-dsp ERROR *************** sh4.s -isa=sh *** 351,356 **** --- 595,608 ---- sh4.s -isa=sh-up sh4 sh4.s -isa=sh2 ERROR sh4.s -isa=sh2-up sh4 + sh4.s -isa=sh2a-nofpu-or-sh3-nommu ERROR + sh4.s -isa=sh2a-nofpu-or-sh3-nommu-up sh4 + sh4.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR + sh4.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4 + sh4.s -isa=sh2a-or-sh3e ERROR + sh4.s -isa=sh2a-or-sh3e-up sh4 + sh4.s -isa=sh2a-or-sh4 ERROR + sh4.s -isa=sh2a-or-sh4-up sh4 sh4.s -isa=sh2e ERROR sh4.s -isa=sh2e-up sh4 sh4.s -isa=sh3-dsp ERROR *************** sh4a-nofpu.s -isa=sh *** 384,389 **** --- 636,649 ---- sh4a-nofpu.s -isa=sh-up sh4a-nofpu sh4a-nofpu.s -isa=sh2 ERROR sh4a-nofpu.s -isa=sh2-up sh4a-nofpu + sh4a-nofpu.s -isa=sh2a-nofpu-or-sh3-nommu ERROR + sh4a-nofpu.s -isa=sh2a-nofpu-or-sh3-nommu-up sh4a-nofpu + sh4a-nofpu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR + sh4a-nofpu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4a-nofpu + sh4a-nofpu.s -isa=sh2a-or-sh3e ERROR + sh4a-nofpu.s -isa=sh2a-or-sh3e-up sh4a + sh4a-nofpu.s -isa=sh2a-or-sh4 ERROR + sh4a-nofpu.s -isa=sh2a-or-sh4-up sh4a sh4a-nofpu.s -isa=sh2e ERROR sh4a-nofpu.s -isa=sh2e-up sh4a sh4a-nofpu.s -isa=sh3-dsp ERROR *************** sh4a.s -isa=sh *** 417,422 **** --- 677,690 ---- sh4a.s -isa=sh-up sh4a sh4a.s -isa=sh2 ERROR sh4a.s -isa=sh2-up sh4a + sh4a.s -isa=sh2a-nofpu-or-sh3-nommu ERROR + sh4a.s -isa=sh2a-nofpu-or-sh3-nommu-up sh4a + sh4a.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR + sh4a.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4a + sh4a.s -isa=sh2a-or-sh3e ERROR + sh4a.s -isa=sh2a-or-sh3e-up sh4a + sh4a.s -isa=sh2a-or-sh4 ERROR + sh4a.s -isa=sh2a-or-sh4-up sh4a sh4a.s -isa=sh2e ERROR sh4a.s -isa=sh2e-up sh4a sh4a.s -isa=sh3-dsp ERROR *************** sh4al-dsp.s -isa=sh *** 450,455 **** --- 718,731 ---- sh4al-dsp.s -isa=sh-up sh4al-dsp sh4al-dsp.s -isa=sh2 ERROR sh4al-dsp.s -isa=sh2-up sh4al-dsp + sh4al-dsp.s -isa=sh2a-nofpu-or-sh3-nommu ERROR + sh4al-dsp.s -isa=sh2a-nofpu-or-sh3-nommu-up sh4al-dsp + sh4al-dsp.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR + sh4al-dsp.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4al-dsp + sh4al-dsp.s -isa=sh2a-or-sh3e ERROR + sh4al-dsp.s -isa=sh2a-or-sh3e-up ERROR + sh4al-dsp.s -isa=sh2a-or-sh4 ERROR + sh4al-dsp.s -isa=sh2a-or-sh4-up ERROR sh4al-dsp.s -isa=sh2e ERROR sh4al-dsp.s -isa=sh2e-up ERROR sh4al-dsp.s -isa=sh3-dsp ERROR Index: gas/testsuite/gas/sh/arch/sh4.s =================================================================== RCS file: /cvs/src/src/gas/testsuite/gas/sh/arch/sh4.s,v retrieving revision 1.1 diff -c -3 -p -r1.1 sh4.s *** gas/testsuite/gas/sh/arch/sh4.s 29 Jun 2004 16:35:05 -0000 1.1 --- gas/testsuite/gas/sh/arch/sh4.s 20 Dec 2004 17:09:55 -0000 *************** *** 1,3 **** .section .text sh4: ! fabs dr0 --- 1,4 ---- .section .text sh4: ! frchg ! Index: ld/testsuite/ld-sh/arch/arch_expected.txt =================================================================== RCS file: /cvs/src/src/ld/testsuite/ld-sh/arch/arch_expected.txt,v retrieving revision 1.1 diff -c -3 -p -r1.1 arch_expected.txt *** ld/testsuite/ld-sh/arch/arch_expected.txt 29 Jun 2004 16:35:05 -0000 1.1 --- ld/testsuite/ld-sh/arch/arch_expected.txt 20 Dec 2004 17:09:56 -0000 *************** *** 4,10 **** # It contains the expected results of the tests. # If the tests are failing because the expected results # have changed then run 'make check' and copy the new file ! # from <objdir>/ld/testsuite/arch_results.txt # to <srcdir>/ld/testsuite/ld-sh/arch/arch_expected.txt . # Make sure the new expected results are ALL correct. # --- 4,10 ---- # It contains the expected results of the tests. # If the tests are failing because the expected results # have changed then run 'make check' and copy the new file ! # from <objdir>/ld/arch_results.txt # to <srcdir>/ld/testsuite/ld-sh/arch/arch_expected.txt . # Make sure the new expected results are ALL correct. # *************** *** 13,18 **** --- 13,22 ---- sh-dsp.o sh-dsp.o sh-dsp sh-dsp.o sh.o sh-dsp sh-dsp.o sh2.o sh-dsp + sh-dsp.o sh2a-nofpu-or-sh3-nommu.o sh3-dsp + sh-dsp.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh4al-dsp + sh-dsp.o sh2a-or-sh3e.o ERROR + sh-dsp.o sh2a-or-sh4.o ERROR sh-dsp.o sh2e.o ERROR sh-dsp.o sh3-dsp.o sh3-dsp sh-dsp.o sh3-nommu.o sh3-dsp *************** sh-dsp.o sh-unknown.o *** 28,38 **** sh.o sh-dsp.o sh-dsp sh.o sh.o sh sh.o sh2.o sh2 sh.o sh2e.o sh2e sh.o sh3-dsp.o sh3-dsp sh.o sh3-nommu.o sh3-nommu sh.o sh3.o sh3 ! sh.o sh3e.o sh3e sh.o sh4-nofpu.o sh4-nofpu sh.o sh4-nommu-nofpu.o sh4-nommu-nofpu sh.o sh4.o sh4 --- 32,46 ---- sh.o sh-dsp.o sh-dsp sh.o sh.o sh sh.o sh2.o sh2 + sh.o sh2a-nofpu-or-sh3-nommu.o sh2a-nofpu-or-sh3-nommu + sh.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu + sh.o sh2a-or-sh3e.o sh2a-or-sh3e + sh.o sh2a-or-sh4.o sh2a-or-sh4 sh.o sh2e.o sh2e sh.o sh3-dsp.o sh3-dsp sh.o sh3-nommu.o sh3-nommu sh.o sh3.o sh3 ! sh.o sh3e.o sh2a-or-sh3e sh.o sh4-nofpu.o sh4-nofpu sh.o sh4-nommu-nofpu.o sh4-nommu-nofpu sh.o sh4.o sh4 *************** sh.o sh-unknown.o *** 43,53 **** sh2.o sh-dsp.o sh-dsp sh2.o sh.o sh2 sh2.o sh2.o sh2 sh2.o sh2e.o sh2e sh2.o sh3-dsp.o sh3-dsp sh2.o sh3-nommu.o sh3-nommu sh2.o sh3.o sh3 ! sh2.o sh3e.o sh3e sh2.o sh4-nofpu.o sh4-nofpu sh2.o sh4-nommu-nofpu.o sh4-nommu-nofpu sh2.o sh4.o sh4 --- 51,65 ---- sh2.o sh-dsp.o sh-dsp sh2.o sh.o sh2 sh2.o sh2.o sh2 + sh2.o sh2a-nofpu-or-sh3-nommu.o sh2a-nofpu-or-sh3-nommu + sh2.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu + sh2.o sh2a-or-sh3e.o sh2a-or-sh3e + sh2.o sh2a-or-sh4.o sh2a-or-sh4 sh2.o sh2e.o sh2e sh2.o sh3-dsp.o sh3-dsp sh2.o sh3-nommu.o sh3-nommu sh2.o sh3.o sh3 ! sh2.o sh3e.o sh2a-or-sh3e sh2.o sh4-nofpu.o sh4-nofpu sh2.o sh4-nommu-nofpu.o sh4-nommu-nofpu sh2.o sh4.o sh4 *************** sh2.o sh4a-nofpu.o *** 55,68 **** sh2.o sh4a.o sh4a sh2.o sh4al-dsp.o sh4al-dsp sh2.o sh-unknown.o sh3 sh2e.o sh-dsp.o ERROR sh2e.o sh.o sh2e sh2e.o sh2.o sh2e sh2e.o sh2e.o sh2e sh2e.o sh3-dsp.o ERROR sh2e.o sh3-nommu.o sh3e sh2e.o sh3.o sh3e ! sh2e.o sh3e.o sh3e sh2e.o sh4-nofpu.o sh4 sh2e.o sh4-nommu-nofpu.o sh4 sh2e.o sh4.o sh4 --- 67,160 ---- sh2.o sh4a.o sh4a sh2.o sh4al-dsp.o sh4al-dsp sh2.o sh-unknown.o sh3 + sh2a-nofpu-or-sh3-nommu.o sh-dsp.o sh3-dsp + sh2a-nofpu-or-sh3-nommu.o sh.o sh2a-nofpu-or-sh3-nommu + sh2a-nofpu-or-sh3-nommu.o sh2.o sh2a-nofpu-or-sh3-nommu + sh2a-nofpu-or-sh3-nommu.o sh2a-nofpu-or-sh3-nommu.o sh2a-nofpu-or-sh3-nommu + sh2a-nofpu-or-sh3-nommu.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu + sh2a-nofpu-or-sh3-nommu.o sh2a-or-sh3e.o sh2a-or-sh3e + sh2a-nofpu-or-sh3-nommu.o sh2a-or-sh4.o sh2a-or-sh4 + sh2a-nofpu-or-sh3-nommu.o sh2e.o sh2a-or-sh3e + sh2a-nofpu-or-sh3-nommu.o sh3-dsp.o sh3-dsp + sh2a-nofpu-or-sh3-nommu.o sh3-nommu.o sh3-nommu + sh2a-nofpu-or-sh3-nommu.o sh3.o sh3 + sh2a-nofpu-or-sh3-nommu.o sh3e.o sh2a-or-sh3e + sh2a-nofpu-or-sh3-nommu.o sh4-nofpu.o sh4-nofpu + sh2a-nofpu-or-sh3-nommu.o sh4-nommu-nofpu.o sh4-nommu-nofpu + sh2a-nofpu-or-sh3-nommu.o sh4.o sh4 + sh2a-nofpu-or-sh3-nommu.o sh4a-nofpu.o sh4a-nofpu + sh2a-nofpu-or-sh3-nommu.o sh4a.o sh4a + sh2a-nofpu-or-sh3-nommu.o sh4al-dsp.o sh4al-dsp + sh2a-nofpu-or-sh3-nommu.o sh-unknown.o sh3 + sh2a-nofpu-or-sh4-nommu-nofpu.o sh-dsp.o sh4al-dsp + sh2a-nofpu-or-sh4-nommu-nofpu.o sh.o sh2a-nofpu-or-sh4-nommu-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.o sh2.o sh2a-nofpu-or-sh4-nommu-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-nofpu-or-sh3-nommu.o sh2a-nofpu-or-sh4-nommu-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-or-sh3e.o sh2a-or-sh4 + sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-or-sh4.o sh2a-or-sh4 + sh2a-nofpu-or-sh4-nommu-nofpu.o sh2e.o sh2a-or-sh4 + sh2a-nofpu-or-sh4-nommu-nofpu.o sh3-dsp.o sh4al-dsp + sh2a-nofpu-or-sh4-nommu-nofpu.o sh3-nommu.o sh4-nommu-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.o sh3.o sh4-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.o sh3e.o sh2a-or-sh4 + sh2a-nofpu-or-sh4-nommu-nofpu.o sh4-nofpu.o sh4-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.o sh4-nommu-nofpu.o sh4-nommu-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.o sh4.o sh4 + sh2a-nofpu-or-sh4-nommu-nofpu.o sh4a-nofpu.o sh4a-nofpu + sh2a-nofpu-or-sh4-nommu-nofpu.o sh4a.o sh4a + sh2a-nofpu-or-sh4-nommu-nofpu.o sh4al-dsp.o sh4al-dsp + sh2a-nofpu-or-sh4-nommu-nofpu.o sh-unknown.o sh4-nofpu + sh2a-or-sh3e.o sh-dsp.o ERROR + sh2a-or-sh3e.o sh.o sh2a-or-sh3e + sh2a-or-sh3e.o sh2.o sh2a-or-sh3e + sh2a-or-sh3e.o sh2a-nofpu-or-sh3-nommu.o sh2a-or-sh3e + sh2a-or-sh3e.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-or-sh4 + sh2a-or-sh3e.o sh2a-or-sh3e.o sh2a-or-sh3e + sh2a-or-sh3e.o sh2a-or-sh4.o sh2a-or-sh4 + sh2a-or-sh3e.o sh2e.o sh2a-or-sh3e + sh2a-or-sh3e.o sh3-dsp.o ERROR + sh2a-or-sh3e.o sh3-nommu.o sh3e + sh2a-or-sh3e.o sh3.o sh3e + sh2a-or-sh3e.o sh3e.o sh2a-or-sh3e + sh2a-or-sh3e.o sh4-nofpu.o sh4 + sh2a-or-sh3e.o sh4-nommu-nofpu.o sh4 + sh2a-or-sh3e.o sh4.o sh4 + sh2a-or-sh3e.o sh4a-nofpu.o sh4a + sh2a-or-sh3e.o sh4a.o sh4a + sh2a-or-sh3e.o sh4al-dsp.o ERROR + sh2a-or-sh3e.o sh-unknown.o sh3e + sh2a-or-sh4.o sh-dsp.o ERROR + sh2a-or-sh4.o sh.o sh2a-or-sh4 + sh2a-or-sh4.o sh2.o sh2a-or-sh4 + sh2a-or-sh4.o sh2a-nofpu-or-sh3-nommu.o sh2a-or-sh4 + sh2a-or-sh4.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-or-sh4 + sh2a-or-sh4.o sh2a-or-sh3e.o sh2a-or-sh4 + sh2a-or-sh4.o sh2a-or-sh4.o sh2a-or-sh4 + sh2a-or-sh4.o sh2e.o sh2a-or-sh4 + sh2a-or-sh4.o sh3-dsp.o ERROR + sh2a-or-sh4.o sh3-nommu.o sh4 + sh2a-or-sh4.o sh3.o sh4 + sh2a-or-sh4.o sh3e.o sh2a-or-sh4 + sh2a-or-sh4.o sh4-nofpu.o sh4 + sh2a-or-sh4.o sh4-nommu-nofpu.o sh4 + sh2a-or-sh4.o sh4.o sh4 + sh2a-or-sh4.o sh4a-nofpu.o sh4a + sh2a-or-sh4.o sh4a.o sh4a + sh2a-or-sh4.o sh4al-dsp.o ERROR + sh2a-or-sh4.o sh-unknown.o sh4 sh2e.o sh-dsp.o ERROR sh2e.o sh.o sh2e sh2e.o sh2.o sh2e + sh2e.o sh2a-nofpu-or-sh3-nommu.o sh2a-or-sh3e + sh2e.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-or-sh4 + sh2e.o sh2a-or-sh3e.o sh2a-or-sh3e + sh2e.o sh2a-or-sh4.o sh2a-or-sh4 sh2e.o sh2e.o sh2e sh2e.o sh3-dsp.o ERROR sh2e.o sh3-nommu.o sh3e sh2e.o sh3.o sh3e ! sh2e.o sh3e.o sh2a-or-sh3e sh2e.o sh4-nofpu.o sh4 sh2e.o sh4-nommu-nofpu.o sh4 sh2e.o sh4.o sh4 *************** sh2e.o sh-unknown.o *** 73,78 **** --- 165,174 ---- sh3-dsp.o sh-dsp.o sh3-dsp sh3-dsp.o sh.o sh3-dsp sh3-dsp.o sh2.o sh3-dsp + sh3-dsp.o sh2a-nofpu-or-sh3-nommu.o sh3-dsp + sh3-dsp.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh4al-dsp + sh3-dsp.o sh2a-or-sh3e.o ERROR + sh3-dsp.o sh2a-or-sh4.o ERROR sh3-dsp.o sh2e.o ERROR sh3-dsp.o sh3-dsp.o sh3-dsp sh3-dsp.o sh3-nommu.o sh3-dsp *************** sh3-dsp.o sh-unknown.o *** 88,93 **** --- 184,193 ---- sh3-nommu.o sh-dsp.o sh3-dsp sh3-nommu.o sh.o sh3-nommu sh3-nommu.o sh2.o sh3-nommu + sh3-nommu.o sh2a-nofpu-or-sh3-nommu.o sh3-nommu + sh3-nommu.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh4-nommu-nofpu + sh3-nommu.o sh2a-or-sh3e.o sh3e + sh3-nommu.o sh2a-or-sh4.o sh4 sh3-nommu.o sh2e.o sh3e sh3-nommu.o sh3-dsp.o sh3-dsp sh3-nommu.o sh3-nommu.o sh3-nommu *************** sh3-nommu.o sh-unknown.o *** 103,108 **** --- 203,212 ---- sh3.o sh-dsp.o sh3-dsp sh3.o sh.o sh3 sh3.o sh2.o sh3 + sh3.o sh2a-nofpu-or-sh3-nommu.o sh3 + sh3.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh4-nofpu + sh3.o sh2a-or-sh3e.o sh3e + sh3.o sh2a-or-sh4.o sh4 sh3.o sh2e.o sh3e sh3.o sh3-dsp.o sh3-dsp sh3.o sh3-nommu.o sh3 *************** sh3.o sh4a.o *** 116,128 **** sh3.o sh4al-dsp.o sh4al-dsp sh3.o sh-unknown.o sh3 sh3e.o sh-dsp.o ERROR ! sh3e.o sh.o sh3e ! sh3e.o sh2.o sh3e ! sh3e.o sh2e.o sh3e sh3e.o sh3-dsp.o ERROR sh3e.o sh3-nommu.o sh3e sh3e.o sh3.o sh3e ! sh3e.o sh3e.o sh3e sh3e.o sh4-nofpu.o sh4 sh3e.o sh4-nommu-nofpu.o sh4 sh3e.o sh4.o sh4 --- 220,236 ---- sh3.o sh4al-dsp.o sh4al-dsp sh3.o sh-unknown.o sh3 sh3e.o sh-dsp.o ERROR ! sh3e.o sh.o sh2a-or-sh3e ! sh3e.o sh2.o sh2a-or-sh3e ! sh3e.o sh2a-nofpu-or-sh3-nommu.o sh2a-or-sh3e ! sh3e.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-or-sh4 ! sh3e.o sh2a-or-sh3e.o sh2a-or-sh3e ! sh3e.o sh2a-or-sh4.o sh2a-or-sh4 ! sh3e.o sh2e.o sh2a-or-sh3e sh3e.o sh3-dsp.o ERROR sh3e.o sh3-nommu.o sh3e sh3e.o sh3.o sh3e ! sh3e.o sh3e.o sh2a-or-sh3e sh3e.o sh4-nofpu.o sh4 sh3e.o sh4-nommu-nofpu.o sh4 sh3e.o sh4.o sh4 *************** sh3e.o sh-unknown.o *** 133,138 **** --- 241,250 ---- sh4-nofpu.o sh-dsp.o sh4al-dsp sh4-nofpu.o sh.o sh4-nofpu sh4-nofpu.o sh2.o sh4-nofpu + sh4-nofpu.o sh2a-nofpu-or-sh3-nommu.o sh4-nofpu + sh4-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh4-nofpu + sh4-nofpu.o sh2a-or-sh3e.o sh4 + sh4-nofpu.o sh2a-or-sh4.o sh4 sh4-nofpu.o sh2e.o sh4 sh4-nofpu.o sh3-dsp.o sh4al-dsp sh4-nofpu.o sh3-nommu.o sh4-nofpu *************** sh4-nofpu.o sh-unknown.o *** 148,153 **** --- 260,269 ---- sh4-nommu-nofpu.o sh-dsp.o sh4al-dsp sh4-nommu-nofpu.o sh.o sh4-nommu-nofpu sh4-nommu-nofpu.o sh2.o sh4-nommu-nofpu + sh4-nommu-nofpu.o sh2a-nofpu-or-sh3-nommu.o sh4-nommu-nofpu + sh4-nommu-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh4-nommu-nofpu + sh4-nommu-nofpu.o sh2a-or-sh3e.o sh4 + sh4-nommu-nofpu.o sh2a-or-sh4.o sh4 sh4-nommu-nofpu.o sh2e.o sh4 sh4-nommu-nofpu.o sh3-dsp.o sh4al-dsp sh4-nommu-nofpu.o sh3-nommu.o sh4-nommu-nofpu *************** sh4-nommu-nofpu.o sh-unknown.o *** 163,168 **** --- 279,288 ---- sh4.o sh-dsp.o ERROR sh4.o sh.o sh4 sh4.o sh2.o sh4 + sh4.o sh2a-nofpu-or-sh3-nommu.o sh4 + sh4.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh4 + sh4.o sh2a-or-sh3e.o sh4 + sh4.o sh2a-or-sh4.o sh4 sh4.o sh2e.o sh4 sh4.o sh3-dsp.o ERROR sh4.o sh3-nommu.o sh4 *************** sh4.o sh-unknown.o *** 178,183 **** --- 298,307 ---- sh4a-nofpu.o sh-dsp.o sh4al-dsp sh4a-nofpu.o sh.o sh4a-nofpu sh4a-nofpu.o sh2.o sh4a-nofpu + sh4a-nofpu.o sh2a-nofpu-or-sh3-nommu.o sh4a-nofpu + sh4a-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh4a-nofpu + sh4a-nofpu.o sh2a-or-sh3e.o sh4a + sh4a-nofpu.o sh2a-or-sh4.o sh4a sh4a-nofpu.o sh2e.o sh4a sh4a-nofpu.o sh3-dsp.o sh4al-dsp sh4a-nofpu.o sh3-nommu.o sh4a-nofpu *************** sh4a-nofpu.o sh-unknown.o *** 193,198 **** --- 317,326 ---- sh4a.o sh-dsp.o ERROR sh4a.o sh.o sh4a sh4a.o sh2.o sh4a + sh4a.o sh2a-nofpu-or-sh3-nommu.o sh4a + sh4a.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh4a + sh4a.o sh2a-or-sh3e.o sh4a + sh4a.o sh2a-or-sh4.o sh4a sh4a.o sh2e.o sh4a sh4a.o sh3-dsp.o ERROR sh4a.o sh3-nommu.o sh4a *************** sh4a.o sh-unknown.o *** 208,213 **** --- 336,345 ---- sh4al-dsp.o sh-dsp.o sh4al-dsp sh4al-dsp.o sh.o sh4al-dsp sh4al-dsp.o sh2.o sh4al-dsp + sh4al-dsp.o sh2a-nofpu-or-sh3-nommu.o sh4al-dsp + sh4al-dsp.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh4al-dsp + sh4al-dsp.o sh2a-or-sh3e.o ERROR + sh4al-dsp.o sh2a-or-sh4.o ERROR sh4al-dsp.o sh2e.o ERROR sh4al-dsp.o sh3-dsp.o sh4al-dsp sh4al-dsp.o sh3-nommu.o sh4al-dsp *************** sh4al-dsp.o sh-unknown.o *** 223,228 **** --- 355,364 ---- sh-unknown.o sh-dsp.o sh3-dsp sh-unknown.o sh.o sh3 sh-unknown.o sh2.o sh3 + sh-unknown.o sh2a-nofpu-or-sh3-nommu.o sh3 + sh-unknown.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh4-nofpu + sh-unknown.o sh2a-or-sh3e.o sh3e + sh-unknown.o sh2a-or-sh4.o sh4 sh-unknown.o sh2e.o sh3e sh-unknown.o sh3-dsp.o sh3-dsp sh-unknown.o sh3-nommu.o sh3 Index: ld/testsuite/ld-sh/arch/sh4.s =================================================================== RCS file: /cvs/src/src/ld/testsuite/ld-sh/arch/sh4.s,v retrieving revision 1.1 diff -c -3 -p -r1.1 sh4.s *** ld/testsuite/ld-sh/arch/sh4.s 29 Jun 2004 16:35:05 -0000 1.1 --- ld/testsuite/ld-sh/arch/sh4.s 20 Dec 2004 17:09:56 -0000 *************** *** 1,3 **** .section .text sh4: ! fabs dr0 --- 1,4 ---- .section .text sh4: ! frchg ! *** /dev/null 2004-06-24 19:04:38.000000000 +0100 --- gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2004-12-15 15:43:37.000000000 +0000 *************** *** 0 **** --- 1,3 ---- + .section .text + sh2a_nofpu_or_sh3_nommu: + shad r3, r4 *** /dev/null 2004-06-24 19:04:38.000000000 +0100 --- gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2004-12-15 15:45:26.000000000 +0000 *************** *** 0 **** --- 1,3 ---- + .section .text + sh2a_nofpu_or_sh4_nommu_nofpu: + pref @r3 *** /dev/null 2004-06-24 19:04:38.000000000 +0100 --- gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2004-12-15 15:46:02.000000000 +0000 *************** *** 0 **** --- 1,3 ---- + .section .text + sh2a_or_sh3e: + fsqrt fr3 *** /dev/null 2004-06-24 19:04:38.000000000 +0100 --- gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2004-12-15 15:46:26.000000000 +0000 *************** *** 0 **** --- 1,3 ---- + .section .text + sh2a_or_sh4: + fcnvsd fpul, dr4 *** /dev/null 2004-06-24 19:04:38.000000000 +0100 --- ld/testsuite/ld-sh/arch/sh2a-nofpu-or-sh3-nommu.s 2004-12-15 15:49:55.000000000 +0000 *************** *** 0 **** --- 1,3 ---- + .section .text + sh2a_nofpu_or_sh3_nommu: + shad r3, r4 *** /dev/null 2004-06-24 19:04:38.000000000 +0100 --- ld/testsuite/ld-sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2004-12-15 15:49:55.000000000 +0000 *************** *** 0 **** --- 1,3 ---- + .section .text + sh2a_nofpu_or_sh4_nommu_nofpu: + pref @r3 *** /dev/null 2004-06-24 19:04:38.000000000 +0100 --- ld/testsuite/ld-sh/arch/sh2a-or-sh3e.s 2004-12-15 15:49:55.000000000 +0000 *************** *** 0 **** --- 1,3 ---- + .section .text + sh2a_or_sh3e: + fsqrt fr3 *** /dev/null 2004-06-24 19:04:38.000000000 +0100 --- ld/testsuite/ld-sh/arch/sh2a-or-sh4.s 2004-12-15 15:49:55.000000000 +0000 *************** *** 0 **** --- 1,3 ---- + .section .text + sh2a_or_sh4: + fcnvsd fpul, dr4 ^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: Broken SH2a patches 2004-12-20 17:18 ` Nick Clifton @ 2005-01-05 13:27 ` Andrew STUBBS 2005-01-06 11:28 ` Andrew STUBBS ` (2 subsequent siblings) 3 siblings, 0 replies; 26+ messages in thread From: Andrew STUBBS @ 2005-01-05 13:27 UTC (permalink / raw) To: 'Nick Clifton' Cc: 'Alexandre Oliva', binutils, 'Joern RENNECKE' The patch is good but I spotted a mistake in the test results: + sh.s -isa=sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu There are similar mistakes for most of the results for this -isa option. I have traced this to here: ! #define arch_sh2a_nofpu_or_sh4_nommu_nofpu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co) ! #define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co) Note that both architectures have the same flags. I'm in the process or testing it further. -- ------------------------------------------------------------------------ | Andrew Stubbs, | E-mail: Andrew.Stubbs@st.com | | STMicroelectronics (R&D) Ltd., | or Andrew.Stubbs@superh.com | | 1000 Aztec West, | | | Almondsbury, | Tel: +44 (0)1454 462611 | | Bristol, BS32 4SQ, U.K. | Fax: +44 (0)1454 462305 | ------------------------------------------------------------------------ > -----Original Message----- > From: Nick Clifton [mailto:nickc@redhat.com] > Sent: 20 December 2004 17:24 > To: Andrew STUBBS > Cc: 'Alexandre Oliva'; binutils@sources.redhat.com; 'Joern RENNECKE' > Subject: Re: Broken SH2a patches > > > Hi Andrew, > > > Whatever technique we use it needs to be able to select an > > architecture, based on the instructions in the file, that > > specifies what architecture the file will run on, without > > excluding any other similar, but different, architectures > > that it may also run on (hence the fake architectures). Any > > ideas? > > The simplest and most extensible scheme would be to drop the > different machine values altogether. Just have one > bfd_mach_sh number > and one EF_SH_ number. Instead binary files would have a new .note > section which contains an extensible bit mask of the architectures on > which the instructions in that file can be run. When two or > more files > are combined this mask would be ANDed together to give the > mask for the > output binary and checked via XOR for incompatibilities. > > Each instruction would also need one of these bitmasks. > When a new > architecture is added every instruction's bitmask would have to be > updated if it was supported by the new architecture. This would only > have to be done once though and there are macros that could > be defined > to make it simpler. > > Anyway attached is a revised patch that includes your diagram of the > dependencies (thanks) as well as some new base values and a > fixed set of > architecture definitions. (The problem you noticed with the > -isa=sh2e > selecting the sh2a-or-sh3e architecture was that the original > definition > of arch_sh2e defined it in terms of both sh2e_base and sh2a_base). > > I have also tweaked the #defines for the various base architecture > values so it should be easier to add new ones in the future. > > What do you think of this version ? > > Cheers > Nick > > > ^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: Broken SH2a patches 2004-12-20 17:18 ` Nick Clifton 2005-01-05 13:27 ` Andrew STUBBS @ 2005-01-06 11:28 ` Andrew STUBBS 2005-01-12 16:23 ` Nick Clifton 2005-01-07 12:55 ` Andrew STUBBS 2005-01-11 18:01 ` Andrew STUBBS 3 siblings, 1 reply; 26+ messages in thread From: Andrew STUBBS @ 2005-01-06 11:28 UTC (permalink / raw) To: 'Nick Clifton' Cc: 'Alexandre Oliva', binutils, 'Joern RENNECKE' There appears to be another mistake in the inheritance. The SH4 descends from the SH2A-nofpu which can't be right. Here is a corrected tree: SH1 | SH2 .------------'|`--------------------------------. / | \ SH-DSP SH3-nommu/SH2A-nofpu SH2E | | |`--------------------. | | | | \| | SH3-nommu SH4-nm-nf/SH2A-nofpu SH3E/SH2A | |\ | | | | | | `------. | SH2A-nofpu | SH4/SH2A | | \| \ | | | | SH3 SH4-nommu-nofpu `---------+--. | | | /|\ | | \| | | .-----------' | `--------+---------------------. | SH2A | |/ | / \| | | | .-------' | | | |/ | | SH3-dsp SH4-nofpu SH3E | | |`-------------------------------. | .-----' | | \|/ | SH4A-nofpu SH4 | .------------' `-------------------------------. | |/ \| SH4AL-dsp SH4A */ /* Central branches. */ #define arch_sh1_up (arch_sh1 \ | arch_sh2_up) #define arch_sh2_up (arch_sh2 \ | arch_sh2e_up \ | arch_sh2a_nofpu_or_sh3_nommu_up \ | arch_sh_dsp_up) #define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \ | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \ | arch_sh2a_or_sh3e_up \ | arch_sh3_nommu_up) #define arch_sh2a_nofpu_or_sh4_nommu_nofpu_up (arch_sh2a_nofpu_or_sh4_nommu_nofpu \ | arch_sh2a_nofpu_up \ | arch_sh4_nommu_nofpu_up) #define arch_sh2a_nofpu_up (arch_sh2a_nofpu \ | arch_sh2a_up) #define arch_sh3_nommu_up (arch_sh3_nommu \ | arch_sh3_up \ | arch_sh4_nommu_nofpu_up) #define arch_sh3_up (arch_sh3 \ | arch_sh3e_up \ | arch_sh3_dsp_up \ | arch_sh4_nofp_up) #define arch_sh4_nommu_nofpu_up (arch_sh4_nommu_nofpu \ | arch_sh4_nofp_up) #define arch_sh4_nofp_up (arch_sh4_nofpu \ | arch_sh4_up \ | arch_sh4a_nofp_up) #define arch_sh4a_nofp_up (arch_sh4a_nofpu \ | arch_sh4a_up \ | arch_sh4al_dsp_up) /* Right branches. */ #define arch_sh2e_up (arch_sh2e \ | arch_sh2a_or_sh3e_up) #define arch_sh2a_or_sh3e_up (arch_sh2a_or_sh3e \ | arch_sh2a_or_sh4_up \ | arch_sh3e_up) #define arch_sh2a_or_sh4_up (arch_sh2a_or_sh4 \ | arch_sh2a_up \ | arch_sh4_up) #define arch_sh2a_up (arch_sh2a) #define arch_sh3e_up (arch_sh3e \ | arch_sh4_up) #define arch_sh4_up (arch_sh4 \ | arch_sh4a_up) #define arch_sh4a_up (arch_sh4a) /* Left branch. */ #define arch_sh_dsp_up (arch_sh_dsp \ | arch_sh3_dsp_up) #define arch_sh3_dsp_up (arch_sh3_dsp \ | arch_sh4al_dsp_up) #define arch_sh4al_dsp_up (arch_sh4al_dsp) -- Andrew Stubbs andrew.stubbs@st.com andrew.stubbs@superh.com ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Broken SH2a patches 2005-01-06 11:28 ` Andrew STUBBS @ 2005-01-12 16:23 ` Nick Clifton 0 siblings, 0 replies; 26+ messages in thread From: Nick Clifton @ 2005-01-12 16:23 UTC (permalink / raw) To: Andrew STUBBS Cc: 'Alexandre Oliva', binutils, 'Joern RENNECKE' [-- Attachment #1: Type: text/plain, Size: 945 bytes --] Hi Andrew, > There appears to be another mistake in the inheritance. The SH4 descends > from the SH2A-nofpu which can't be right. > > Here is a corrected tree: Thanks - I have put that into the latest patch (attached) along with a fix for the other problem you spotted (arch_sh2a_nofpu_or_sh4_nommu_nofpu being the same as arch_sh2a_nofpu_or_sh3_nommu). Otherwise this patch is the same as the previous one with a suitably amended arch_expected.txt for the GAS tests. > Do you think it worth bothering with any new scheme? Personally yes - but only if: a) Someone is willing to put the effort into developing it. I do not think that it will be a trivial programming exercise and I am not volunteering, at least not right now. b) There are more SH variants to come. A bit of crystal ball gazing is required for this one, but presumably it is quite likely that the SH line will continue to be developed. Cheers Nick [-- Attachment #2: sh.patch.4.bz2 --] [-- Type: application/x-bzip2, Size: 8259 bytes --] ^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: Broken SH2a patches 2004-12-20 17:18 ` Nick Clifton 2005-01-05 13:27 ` Andrew STUBBS 2005-01-06 11:28 ` Andrew STUBBS @ 2005-01-07 12:55 ` Andrew STUBBS 2005-01-10 13:31 ` Joern RENNECKE 2005-01-11 18:01 ` Andrew STUBBS 3 siblings, 1 reply; 26+ messages in thread From: Andrew STUBBS @ 2005-01-07 12:55 UTC (permalink / raw) To: 'Nick Clifton' Cc: 'Alexandre Oliva', binutils, 'Joern RENNECKE' Hi Nick, I have been thinking about what you suggested. > > Whatever technique we use it needs to be able to select an > > architecture, based on the instructions in the file, that > > specifies what architecture the file will run on, without > > excluding any other similar, but different, architectures > > that it may also run on (hence the fake architectures). Any > > ideas? > > The simplest and most extensible scheme would be to drop the > different machine values altogether. Just have one > bfd_mach_sh number > and one EF_SH_ number. Presumably we would still need backwards compatibility with the old EF_SH_ numbers. We don't need to generate them, but we do need to read them. > Instead binary files would have a new .note > section which contains an extensible bit mask of the architectures on > which the instructions in that file can be run. When two or > more files > are combined this mask would be ANDed together to give the > mask for the > output binary and checked via XOR for incompatibilities. So basically you are suggesting we list all the architectures the file can run on. This is something that I had concidered, but had no idea how to achieve. Ideally, if there was an extra section involved, we would also store information about the ABI used in the file, as mixing these is more serious than mixing architectures. I suppose it would work equally well for any file format that supports non-loadable sections, not just ELF. This scheme will work within one version of binutils, but what happens when an upgrade occurs? Old files may cause confusion because they do not list something they could run on. Of course, this already can happen so maybe it wouldn't be a problem. An alternative approach would be to list all the architectures it cannot run on. This would have the effect that old programs would be concidered to run on new architectures, even if they are unsuitable. Perhaps something more intellegent could be done if both sets were known. In any case, the four 'fake' architectures have not yet been included in an official release so, if we want to implement an alternative, we have until 2.16 is released to remove them. Otherwise their EF_SH_ numbers will have to be supported forever (if perhaps invisibly). We would also have to consider the -isa option. Currently it allows individual architectures, which need not change, but also a -up for each, which might no longer make sense. Also, the -isa option is significant because it allows the assembler to use architecture specific relaxation optimisations (which it could not do if it were not certain of the architcture). Do you think it worth bothering with any new scheme? -- Andrew Stubbs andrew.stubbs@st.com andrew.stubbs@superh.com ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Broken SH2a patches 2005-01-07 12:55 ` Andrew STUBBS @ 2005-01-10 13:31 ` Joern RENNECKE 0 siblings, 0 replies; 26+ messages in thread From: Joern RENNECKE @ 2005-01-10 13:31 UTC (permalink / raw) To: Andrew STUBBS; +Cc: 'Nick Clifton', 'Alexandre Oliva', binutils Andrew STUBBS wrote: > Ideally, if there was an extra section involved, we would also >store information about the ABI used in the file, as mixing these is more >serious than mixing architectures. > While mixing compatible architectures is fine, mixing processors from the sh2e branch with ones from the sh-dsp branch of the family is an absoilute no-no. Unless someone comes up with a mode-switched processor that can run both instruction sets ;-) . On the other hand, mixing code with different ABIs in one executable can make perfect sense, if you have some single-fp heavy code and some double-fp heavy code. You just to make sure that you use proper symbol wrapping for __fpscr_values and use appropriate glue for calling between different ABIs. In fact, we could make gcc do the interlinking automatically with machine specific attributes, if that seems worthwhile. > An alternative approach would be to list all the architectures it > cannot run > on. This would have the effect that old programs would be concidered > to run > >on new architectures, even if they are unsuitable. Perhaps something more >intellegent could be done if both sets were known. > Something that will allow a bit more upward compatibility is to list all architectures the code can run on that are not a proper superset of any other listed one. This would be equivalent in terms of described sets and future upward compatibility to the current scheme (the fake nodes stand for intersections of instruction sets of actual processors, just as the architecture lists do). >We would also have to consider the -isa option. Currently it allows >individual architectures, which need not change, but also a -up for each, >which might no longer make sense. Also, the -isa option is significant >because it allows the assembler to use architecture specific relaxation >optimisations (which it could not do if it were not certain of the >architcture). > More exactly, the assembler encodes this information in the object file so that the linker can then do these relaxations. The linker both needs to know about what instructions are available - e.g. braf is only available from SH2 upwards - as well as about what relaxations make sense at all - e.g. the instruction reordering done for SH2 memory access scheduling hurts SH4, and the algorith can also confuse integer and floating point registers. ^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: Broken SH2a patches 2004-12-20 17:18 ` Nick Clifton ` (2 preceding siblings ...) 2005-01-07 12:55 ` Andrew STUBBS @ 2005-01-11 18:01 ` Andrew STUBBS 3 siblings, 0 replies; 26+ messages in thread From: Andrew STUBBS @ 2005-01-11 18:01 UTC (permalink / raw) To: 'Nick Clifton' Cc: 'Alexandre Oliva', binutils, 'Joern RENNECKE' Hi Nick, I have found another problem with your patch. Your patch has: #define arch_sh2a_or_sh3e (arch_sh2a_sh4_base) #define arch_sh2a_or_sh4 (arch_sh2a_sh4_base |arch_sh_dp_fpu) Which should be: #define arch_sh2a_or_sh3e (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu) #define arch_sh2a_or_sh4 (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu) Otherwise the -isa=sh2a-or-sh3e and -isa=sh2a-or-sh4 options cause the assembler to reject all instructions, which isn't helpful. I am developing a new script for the testsuite which will hopefully point all these issues out in future, should anybody make any broken changes. It hasn't found any issues with your patch other than the ones I have already pointed out (although I have had to modifiy sh-opc.h a little to make it work, so maybe I am not testing the same thing). Interestingly, one thing my script has exposed is that mul.l is defined twice! Once for sh2 and once for sh1, which is obviously wrong. -- Andrew Stubbs andrew.stubbs@st.com andrew.stubbs@superh.com ^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: Broken SH2a patches @ 2004-12-02 12:19 Andrew STUBBS 0 siblings, 0 replies; 26+ messages in thread From: Andrew STUBBS @ 2004-12-02 12:19 UTC (permalink / raw) To: 'Nick Clifton', 'Alexandre Oliva' Cc: binutils, Joern RENNECKE Any furthur progress with this problem? As I said before, I would like to see it fixed before 2.16 comes along. Thanks -- Andrew Stubbs andrew.stubbs@st.com andrew.stubbs@superh.com ^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2005-01-12 16:23 UTC | newest] Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2004-10-13 17:00 Broken SH2a patches Andrew STUBBS 2004-10-28 20:33 ` Alexandre Oliva 2004-10-29 10:39 ` Nick Clifton 2004-10-29 12:11 ` Andrew STUBBS 2004-10-29 12:28 ` [OT] " Dave Korn 2004-10-29 12:59 ` Andrew STUBBS 2004-10-29 13:03 ` Dave Korn 2004-10-29 13:21 ` Andrew STUBBS 2004-10-29 13:59 ` Ian Lance Taylor 2004-10-29 14:35 ` Andrew STUBBS 2004-10-29 14:58 ` Ian Lance Taylor 2004-10-29 15:44 ` Andrew STUBBS 2004-11-08 9:04 ` Nick Clifton 2004-11-08 15:12 ` Andrew STUBBS 2004-11-08 16:27 ` Joern RENNECKE 2004-11-08 16:36 ` Joern RENNECKE 2004-12-15 17:11 ` Nick Clifton 2004-12-16 13:24 ` Andrew STUBBS 2004-12-20 17:18 ` Nick Clifton 2005-01-05 13:27 ` Andrew STUBBS 2005-01-06 11:28 ` Andrew STUBBS 2005-01-12 16:23 ` Nick Clifton 2005-01-07 12:55 ` Andrew STUBBS 2005-01-10 13:31 ` Joern RENNECKE 2005-01-11 18:01 ` Andrew STUBBS 2004-12-02 12:19 Andrew STUBBS
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