RE: [PATH] AMD MWAITX enablement

["Pawar, Amit" <Amit.Pawar@amd.com>]

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Third operand has been added to MWAITX instruction. It has been tested for correctness and found no regression. Please let me know the process to apply to trunk or can you apply to trunk from my side.

Amit Pawar

-----Original Message-----
From: Jan Beulich [mailto:JBeulich@suse.com] 
Sent: Tuesday, June 02, 2015 1:52 PM
To: Pawar, Amit
Cc: binutils@sourceware.org
Subject: Re: [PATH] AMD MWAITX enablement

>>> On 02.06.15 at 08:55, <Amit.Pawar@amd.com> wrote:
>--- a/opcodes/i386-opc.tbl
>+++ b/opcodes/i386-opc.tbl
>@@ -5938,3 +5938,16 @@ clzero, 0, 0xf01fc, None, 3, CpuCLZERO, 
>No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|
> 
> // CLZERO instructions end
> 
>+// MONITORX/MWAITX instructions
>+monitorx, 0, 0xf01, 0xfa, 2, CpuMWAITX, 
>+No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } // Need to ensure only "monitorx %eax/%ax,%ecx,%edx" is accepted.
>+monitorx, 3, 0xf01, 0xfa, 2, CpuMWAITX|CpuNo64, 
>+No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOp0, { Reg16|Reg32, Reg32, Reg32 } // Need to ensure only "monitorx %rax/%eax,%rcx,%rdx" is accepted.
>+monitorx, 3, 0xf01, 0xfa, 2, CpuMWAITX|Cpu64,   No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOp0|NoRex64, { Reg32|Reg64, Reg64, Reg64 }
>+
>+mwaitx, 0, 0xf01, 0xfb, 2, CpuMWAITX, 
>+No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } // Need to ensure only "mwaitx %eax,%ecx" is accepted.
>+mwaitx, 2, 0xf01, 0xfb, 2, CpuMWAITX|CpuNo64, 
>+No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|NoAVX, { Reg32, Reg32 } // Need to ensure only "mwaitx %rax,%rcx" is accepted.
>+mwaitx, 2, 0xf01, 0xfb, 2, CpuMWAITX|Cpu64, 
>+No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|NoRex64|NoAVX, 
>+{ Reg64, Reg64 } // MONITORX/MWAITX instructions end

Looking at the earlier submitted Linux side patch at least one of the instructions also uses %ebx - why is that not being expressed by the instruction forms taking explicit operands?

Jan


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