From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 550023853811 for ; Tue, 1 Feb 2022 13:53:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 550023853811 From: Tsukasa OI To: Tsukasa OI Cc: binutils@sourceware.org Subject: [PATCH 3/4] RISC-V: Add assembler testcases for Zqinx regs Date: Tue, 1 Feb 2022 22:53:37 +0900 Message-Id: <04d155d94eca64a6117a9f741d7533c80f9faa9e.1643723585.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-13.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TO_EQ_FM_DIRECT_MX, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 01 Feb 2022 13:54:05 -0000 This commit adds several assembler tests for Zqinx register pairs / quad-register groups. gas/ChangeLog: * testsuite/gas/riscv/zqinx-64-regpair.s: Test RV64_Zqinx register pairs. * testsuite/gas/riscv/zqinx-64-regpair.d: Likewise. * testsuite/gas/riscv/zqinx-64-regpair-fail.s: Test RV64_Zqinx register pairs (failure cases). * testsuite/gas/riscv/zqinx-64-regpair-fail.d: Likewise. * testsuite/gas/riscv/zqinx-64-regpair-fail.l: Likewise. * testsuite/gas/riscv/zqinx-32-regpair.s: Test RV32_Zqinx register pairs and quad-register groups. * testsuite/gas/riscv/zqinx-32-regpair.d: Likewise. * testsuite/gas/riscv/zqinx-32-regpair-fail.s: Test RV32_Zqinx register pairs and quad-register groups (failure cases). * testsuite/gas/riscv/zqinx-32-regpair-fail.d: Likewise. * testsuite/gas/riscv/zqinx-32-regpair-fail.l: Likewise. --- .../gas/riscv/zqinx-32-regpair-fail.d | 3 + .../gas/riscv/zqinx-32-regpair-fail.l | 212 +++++++++++++++++ .../gas/riscv/zqinx-32-regpair-fail.s | 218 ++++++++++++++++++ gas/testsuite/gas/riscv/zqinx-32-regpair.d | 66 ++++++ gas/testsuite/gas/riscv/zqinx-32-regpair.s | 64 +++++ .../gas/riscv/zqinx-64-regpair-fail.d | 3 + .../gas/riscv/zqinx-64-regpair-fail.l | 133 +++++++++++ .../gas/riscv/zqinx-64-regpair-fail.s | 138 +++++++++++ gas/testsuite/gas/riscv/zqinx-64-regpair.d | 87 +++++++ gas/testsuite/gas/riscv/zqinx-64-regpair.s | 84 +++++++ 10 files changed, 1008 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.s diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d new file mode 100644 index 00000000000..957401f4683 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32ima_zqinx +#source: zqinx-32-regpair-fail.s +#error_output: zqinx-32-regpair-fail.l diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l new file mode 100644 index 00000000000..ad8aa69ffd7 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l @@ -0,0 +1,212 @@ +.*Assembler messages: +.*Error: illegal operands `fadd\.q x5,x8,x12' +.*Error: illegal operands `fadd\.q x5,x8,x12,rtz' +.*Error: illegal operands `fadd\.q x6,x8,x12' +.*Error: illegal operands `fadd\.q x6,x8,x12,rtz' +.*Error: illegal operands `fadd\.q x4,x5,x12' +.*Error: illegal operands `fadd\.q x4,x5,x12,rtz' +.*Error: illegal operands `fadd\.q x4,x6,x12' +.*Error: illegal operands `fadd\.q x4,x6,x12,rtz' +.*Error: illegal operands `fadd\.q x4,x8,x5' +.*Error: illegal operands `fadd\.q x4,x8,x5,rtz' +.*Error: illegal operands `fadd\.q x4,x8,x6' +.*Error: illegal operands `fadd\.q x4,x8,x6,rtz' +.*Error: illegal operands `fsub\.q x5,x8,x12' +.*Error: illegal operands `fsub\.q x5,x8,x12,rtz' +.*Error: illegal operands `fsub\.q x6,x8,x12' +.*Error: illegal operands `fsub\.q x6,x8,x12,rtz' +.*Error: illegal operands `fsub\.q x4,x5,x12' +.*Error: illegal operands `fsub\.q x4,x5,x12,rtz' +.*Error: illegal operands `fsub\.q x4,x6,x12' +.*Error: illegal operands `fsub\.q x4,x6,x12,rtz' +.*Error: illegal operands `fsub\.q x4,x8,x5' +.*Error: illegal operands `fsub\.q x4,x8,x5,rtz' +.*Error: illegal operands `fsub\.q x4,x8,x6' +.*Error: illegal operands `fsub\.q x4,x8,x6,rtz' +.*Error: illegal operands `fmul\.q x5,x8,x12' +.*Error: illegal operands `fmul\.q x5,x8,x12,rtz' +.*Error: illegal operands `fmul\.q x6,x8,x12' +.*Error: illegal operands `fmul\.q x6,x8,x12,rtz' +.*Error: illegal operands `fmul\.q x4,x5,x12' +.*Error: illegal operands `fmul\.q x4,x5,x12,rtz' +.*Error: illegal operands `fmul\.q x4,x6,x12' +.*Error: illegal operands `fmul\.q x4,x6,x12,rtz' +.*Error: illegal operands `fmul\.q x4,x8,x5' +.*Error: illegal operands `fmul\.q x4,x8,x5,rtz' +.*Error: illegal operands `fmul\.q x4,x8,x6' +.*Error: illegal operands `fmul\.q x4,x8,x6,rtz' +.*Error: illegal operands `fdiv\.q x5,x8,x12' +.*Error: illegal operands `fdiv\.q x5,x8,x12,rtz' +.*Error: illegal operands `fdiv\.q x6,x8,x12' +.*Error: illegal operands `fdiv\.q x6,x8,x12,rtz' +.*Error: illegal operands `fdiv\.q x4,x5,x12' +.*Error: illegal operands `fdiv\.q x4,x5,x12,rtz' +.*Error: illegal operands `fdiv\.q x4,x6,x12' +.*Error: illegal operands `fdiv\.q x4,x6,x12,rtz' +.*Error: illegal operands `fdiv\.q x4,x8,x5' +.*Error: illegal operands `fdiv\.q x4,x8,x5,rtz' +.*Error: illegal operands `fdiv\.q x4,x8,x6' +.*Error: illegal operands `fdiv\.q x4,x8,x6,rtz' +.*Error: illegal operands `fsqrt\.q x5,x8' +.*Error: illegal operands `fsqrt\.q x5,x8,rtz' +.*Error: illegal operands `fsqrt\.q x6,x8' +.*Error: illegal operands `fsqrt\.q x6,x8,rtz' +.*Error: illegal operands `fsqrt\.q x4,x5' +.*Error: illegal operands `fsqrt\.q x4,x5,rtz' +.*Error: illegal operands `fsqrt\.q x4,x6' +.*Error: illegal operands `fsqrt\.q x4,x6,rtz' +.*Error: illegal operands `fmin\.q x5,x8,x12' +.*Error: illegal operands `fmin\.q x6,x8,x12' +.*Error: illegal operands `fmin\.q x4,x5,x12' +.*Error: illegal operands `fmin\.q x4,x6,x12' +.*Error: illegal operands `fmin\.q x4,x8,x5' +.*Error: illegal operands `fmin\.q x4,x8,x6' +.*Error: illegal operands `fmax\.q x5,x8,x12' +.*Error: illegal operands `fmax\.q x6,x8,x12' +.*Error: illegal operands `fmax\.q x4,x5,x12' +.*Error: illegal operands `fmax\.q x4,x6,x12' +.*Error: illegal operands `fmax\.q x4,x8,x5' +.*Error: illegal operands `fmax\.q x4,x8,x6' +.*Error: illegal operands `fmadd\.q x5,x8,x12,x16' +.*Error: illegal operands `fmadd\.q x5,x8,x12,x16,rtz' +.*Error: illegal operands `fmadd\.q x6,x8,x12,x16' +.*Error: illegal operands `fmadd\.q x6,x8,x12,x16,rtz' +.*Error: illegal operands `fmadd\.q x4,x5,x12,x16' +.*Error: illegal operands `fmadd\.q x4,x5,x12,x16,rtz' +.*Error: illegal operands `fmadd\.q x4,x6,x12,x16' +.*Error: illegal operands `fmadd\.q x4,x6,x12,x16,rtz' +.*Error: illegal operands `fmadd\.q x4,x8,x5,x16' +.*Error: illegal operands `fmadd\.q x4,x8,x5,x16,rtz' +.*Error: illegal operands `fmadd\.q x4,x8,x6,x16' +.*Error: illegal operands `fmadd\.q x4,x8,x6,x16,rtz' +.*Error: illegal operands `fmadd\.q x4,x8,x12,x5' +.*Error: illegal operands `fmadd\.q x4,x8,x12,x5,rtz' +.*Error: illegal operands `fmadd\.q x4,x8,x12,x6' +.*Error: illegal operands `fmadd\.q x4,x8,x12,x6,rtz' +.*Error: illegal operands `fnmadd\.q x5,x8,x12,x16' +.*Error: illegal operands `fnmadd\.q x5,x8,x12,x16,rtz' +.*Error: illegal operands `fnmadd\.q x6,x8,x12,x16' +.*Error: illegal operands `fnmadd\.q x6,x8,x12,x16,rtz' +.*Error: illegal operands `fnmadd\.q x4,x5,x12,x16' +.*Error: illegal operands `fnmadd\.q x4,x5,x12,x16,rtz' +.*Error: illegal operands `fnmadd\.q x4,x6,x12,x16' +.*Error: illegal operands `fnmadd\.q x4,x6,x12,x16,rtz' +.*Error: illegal operands `fnmadd\.q x4,x8,x5,x16' +.*Error: illegal operands `fnmadd\.q x4,x8,x5,x16,rtz' +.*Error: illegal operands `fnmadd\.q x4,x8,x6,x16' +.*Error: illegal operands `fnmadd\.q x4,x8,x6,x16,rtz' +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x5' +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x5,rtz' +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x6' +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x6,rtz' +.*Error: illegal operands `fmsub\.q x5,x8,x12,x16' +.*Error: illegal operands `fmsub\.q x5,x8,x12,x16,rtz' +.*Error: illegal operands `fmsub\.q x6,x8,x12,x16' +.*Error: illegal operands `fmsub\.q x6,x8,x12,x16,rtz' +.*Error: illegal operands `fmsub\.q x4,x5,x12,x16' +.*Error: illegal operands `fmsub\.q x4,x5,x12,x16,rtz' +.*Error: illegal operands `fmsub\.q x4,x6,x12,x16' +.*Error: illegal operands `fmsub\.q x4,x6,x12,x16,rtz' +.*Error: illegal operands `fmsub\.q x4,x8,x5,x16' +.*Error: illegal operands `fmsub\.q x4,x8,x5,x16,rtz' +.*Error: illegal operands `fmsub\.q x4,x8,x6,x16' +.*Error: illegal operands `fmsub\.q x4,x8,x6,x16,rtz' +.*Error: illegal operands `fmsub\.q x4,x8,x12,x5' +.*Error: illegal operands `fmsub\.q x4,x8,x12,x5,rtz' +.*Error: illegal operands `fmsub\.q x4,x8,x12,x6' +.*Error: illegal operands `fmsub\.q x4,x8,x12,x6,rtz' +.*Error: illegal operands `fnmsub\.q x5,x8,x12,x16' +.*Error: illegal operands `fnmsub\.q x5,x8,x12,x16,rtz' +.*Error: illegal operands `fnmsub\.q x6,x8,x12,x16' +.*Error: illegal operands `fnmsub\.q x6,x8,x12,x16,rtz' +.*Error: illegal operands `fnmsub\.q x4,x5,x12,x16' +.*Error: illegal operands `fnmsub\.q x4,x5,x12,x16,rtz' +.*Error: illegal operands `fnmsub\.q x4,x6,x12,x16' +.*Error: illegal operands `fnmsub\.q x4,x6,x12,x16,rtz' +.*Error: illegal operands `fnmsub\.q x4,x8,x5,x16' +.*Error: illegal operands `fnmsub\.q x4,x8,x5,x16,rtz' +.*Error: illegal operands `fnmsub\.q x4,x8,x6,x16' +.*Error: illegal operands `fnmsub\.q x4,x8,x6,x16,rtz' +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x5' +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x5,rtz' +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x6' +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x6,rtz' +.*Error: illegal operands `fsgnj\.q x5,x8,x12' +.*Error: illegal operands `fsgnj\.q x6,x8,x12' +.*Error: illegal operands `fsgnj\.q x4,x5,x12' +.*Error: illegal operands `fsgnj\.q x4,x6,x12' +.*Error: illegal operands `fsgnj\.q x4,x8,x5' +.*Error: illegal operands `fsgnj\.q x4,x8,x6' +.*Error: illegal operands `fsgnjn\.q x5,x8,x12' +.*Error: illegal operands `fsgnjn\.q x6,x8,x12' +.*Error: illegal operands `fsgnjn\.q x4,x5,x12' +.*Error: illegal operands `fsgnjn\.q x4,x6,x12' +.*Error: illegal operands `fsgnjn\.q x4,x8,x5' +.*Error: illegal operands `fsgnjn\.q x4,x8,x6' +.*Error: illegal operands `fsgnjx\.q x5,x8,x12' +.*Error: illegal operands `fsgnjx\.q x6,x8,x12' +.*Error: illegal operands `fsgnjx\.q x4,x5,x12' +.*Error: illegal operands `fsgnjx\.q x4,x6,x12' +.*Error: illegal operands `fsgnjx\.q x4,x8,x5' +.*Error: illegal operands `fsgnjx\.q x4,x8,x6' +.*Error: illegal operands `fmv\.q x5,x8' +.*Error: illegal operands `fmv\.q x6,x8' +.*Error: illegal operands `fmv\.q x4,x5' +.*Error: illegal operands `fmv\.q x4,x6' +.*Error: illegal operands `fneg\.q x5,x8' +.*Error: illegal operands `fneg\.q x6,x8' +.*Error: illegal operands `fneg\.q x4,x5' +.*Error: illegal operands `fneg\.q x4,x6' +.*Error: illegal operands `fabs\.q x5,x8' +.*Error: illegal operands `fabs\.q x6,x8' +.*Error: illegal operands `fabs\.q x4,x5' +.*Error: illegal operands `fabs\.q x4,x6' +.*Error: illegal operands `feq\.q x4,x5,x12' +.*Error: illegal operands `feq\.q x4,x6,x12' +.*Error: illegal operands `feq\.q x4,x8,x5' +.*Error: illegal operands `feq\.q x4,x8,x6' +.*Error: illegal operands `flt\.q x4,x5,x12' +.*Error: illegal operands `flt\.q x4,x6,x12' +.*Error: illegal operands `flt\.q x4,x8,x5' +.*Error: illegal operands `flt\.q x4,x8,x6' +.*Error: illegal operands `fle\.q x4,x5,x12' +.*Error: illegal operands `fle\.q x4,x6,x12' +.*Error: illegal operands `fle\.q x4,x8,x5' +.*Error: illegal operands `fle\.q x4,x8,x6' +.*Error: illegal operands `fgt\.q x4,x5,x12' +.*Error: illegal operands `fgt\.q x4,x6,x12' +.*Error: illegal operands `fgt\.q x4,x8,x5' +.*Error: illegal operands `fgt\.q x4,x8,x6' +.*Error: illegal operands `fge\.q x4,x5,x12' +.*Error: illegal operands `fge\.q x4,x6,x12' +.*Error: illegal operands `fge\.q x4,x8,x5' +.*Error: illegal operands `fge\.q x4,x8,x6' +.*Error: illegal operands `fclass\.q x4,x5' +.*Error: illegal operands `fclass\.q x4,x6' +.*Error: illegal operands `fcvt\.w\.q x4,x5' +.*Error: illegal operands `fcvt\.w\.q x4,x5,rtz' +.*Error: illegal operands `fcvt\.w\.q x4,x6' +.*Error: illegal operands `fcvt\.w\.q x4,x6,rtz' +.*Error: illegal operands `fcvt\.wu\.q x4,x5' +.*Error: illegal operands `fcvt\.wu\.q x4,x5,rtz' +.*Error: illegal operands `fcvt\.wu\.q x4,x6' +.*Error: illegal operands `fcvt\.wu\.q x4,x6,rtz' +.*Error: illegal operands `fcvt\.q\.w x5,x4' +.*Error: illegal operands `fcvt\.q\.w x6,x4' +.*Error: illegal operands `fcvt\.q\.wu x5,x4' +.*Error: illegal operands `fcvt\.q\.wu x6,x4' +.*Error: illegal operands `fcvt\.s\.q x4,x5' +.*Error: illegal operands `fcvt\.s\.q x4,x5,rtz' +.*Error: illegal operands `fcvt\.s\.q x4,x6' +.*Error: illegal operands `fcvt\.s\.q x4,x6,rtz' +.*Error: illegal operands `fcvt\.d\.q x4,x5' +.*Error: illegal operands `fcvt\.d\.q x4,x5,rtz' +.*Error: illegal operands `fcvt\.d\.q x4,x6' +.*Error: illegal operands `fcvt\.d\.q x4,x6,rtz' +.*Error: illegal operands `fcvt\.d\.q x5,x8' +.*Error: illegal operands `fcvt\.d\.q x5,x8,rtz' +.*Error: illegal operands `fcvt\.q\.s x5,x4' +.*Error: illegal operands `fcvt\.q\.s x6,x4' +.*Error: illegal operands `fcvt\.q\.d x5,x4' +.*Error: illegal operands `fcvt\.q\.d x6,x4' +.*Error: illegal operands `fcvt\.q\.d x8,x5' diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s new file mode 100644 index 00000000000..f1437239202 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s @@ -0,0 +1,218 @@ +target: + fadd.q x5, x8, x12 + fadd.q x5, x8, x12, rtz + fadd.q x6, x8, x12 + fadd.q x6, x8, x12, rtz + fadd.q x4, x5, x12 + fadd.q x4, x5, x12, rtz + fadd.q x4, x6, x12 + fadd.q x4, x6, x12, rtz + fadd.q x4, x8, x5 + fadd.q x4, x8, x5, rtz + fadd.q x4, x8, x6 + fadd.q x4, x8, x6, rtz + fsub.q x5, x8, x12 + fsub.q x5, x8, x12, rtz + fsub.q x6, x8, x12 + fsub.q x6, x8, x12, rtz + fsub.q x4, x5, x12 + fsub.q x4, x5, x12, rtz + fsub.q x4, x6, x12 + fsub.q x4, x6, x12, rtz + fsub.q x4, x8, x5 + fsub.q x4, x8, x5, rtz + fsub.q x4, x8, x6 + fsub.q x4, x8, x6, rtz + fmul.q x5, x8, x12 + fmul.q x5, x8, x12, rtz + fmul.q x6, x8, x12 + fmul.q x6, x8, x12, rtz + fmul.q x4, x5, x12 + fmul.q x4, x5, x12, rtz + fmul.q x4, x6, x12 + fmul.q x4, x6, x12, rtz + fmul.q x4, x8, x5 + fmul.q x4, x8, x5, rtz + fmul.q x4, x8, x6 + fmul.q x4, x8, x6, rtz + fdiv.q x5, x8, x12 + fdiv.q x5, x8, x12, rtz + fdiv.q x6, x8, x12 + fdiv.q x6, x8, x12, rtz + fdiv.q x4, x5, x12 + fdiv.q x4, x5, x12, rtz + fdiv.q x4, x6, x12 + fdiv.q x4, x6, x12, rtz + fdiv.q x4, x8, x5 + fdiv.q x4, x8, x5, rtz + fdiv.q x4, x8, x6 + fdiv.q x4, x8, x6, rtz + fsqrt.q x5, x8 + fsqrt.q x5, x8, rtz + fsqrt.q x6, x8 + fsqrt.q x6, x8, rtz + fsqrt.q x4, x5 + fsqrt.q x4, x5, rtz + fsqrt.q x4, x6 + fsqrt.q x4, x6, rtz + fmin.q x5, x8, x12 + fmin.q x6, x8, x12 + fmin.q x4, x5, x12 + fmin.q x4, x6, x12 + fmin.q x4, x8, x5 + fmin.q x4, x8, x6 + fmax.q x5, x8, x12 + fmax.q x6, x8, x12 + fmax.q x4, x5, x12 + fmax.q x4, x6, x12 + fmax.q x4, x8, x5 + fmax.q x4, x8, x6 + fmadd.q x5, x8, x12, x16 + fmadd.q x5, x8, x12, x16, rtz + fmadd.q x6, x8, x12, x16 + fmadd.q x6, x8, x12, x16, rtz + fmadd.q x4, x5, x12, x16 + fmadd.q x4, x5, x12, x16, rtz + fmadd.q x4, x6, x12, x16 + fmadd.q x4, x6, x12, x16, rtz + fmadd.q x4, x8, x5, x16 + fmadd.q x4, x8, x5, x16, rtz + fmadd.q x4, x8, x6, x16 + fmadd.q x4, x8, x6, x16, rtz + fmadd.q x4, x8, x12, x5 + fmadd.q x4, x8, x12, x5, rtz + fmadd.q x4, x8, x12, x6 + fmadd.q x4, x8, x12, x6, rtz + fnmadd.q x5, x8, x12, x16 + fnmadd.q x5, x8, x12, x16, rtz + fnmadd.q x6, x8, x12, x16 + fnmadd.q x6, x8, x12, x16, rtz + fnmadd.q x4, x5, x12, x16 + fnmadd.q x4, x5, x12, x16, rtz + fnmadd.q x4, x6, x12, x16 + fnmadd.q x4, x6, x12, x16, rtz + fnmadd.q x4, x8, x5, x16 + fnmadd.q x4, x8, x5, x16, rtz + fnmadd.q x4, x8, x6, x16 + fnmadd.q x4, x8, x6, x16, rtz + fnmadd.q x4, x8, x12, x5 + fnmadd.q x4, x8, x12, x5, rtz + fnmadd.q x4, x8, x12, x6 + fnmadd.q x4, x8, x12, x6, rtz + fmsub.q x5, x8, x12, x16 + fmsub.q x5, x8, x12, x16, rtz + fmsub.q x6, x8, x12, x16 + fmsub.q x6, x8, x12, x16, rtz + fmsub.q x4, x5, x12, x16 + fmsub.q x4, x5, x12, x16, rtz + fmsub.q x4, x6, x12, x16 + fmsub.q x4, x6, x12, x16, rtz + fmsub.q x4, x8, x5, x16 + fmsub.q x4, x8, x5, x16, rtz + fmsub.q x4, x8, x6, x16 + fmsub.q x4, x8, x6, x16, rtz + fmsub.q x4, x8, x12, x5 + fmsub.q x4, x8, x12, x5, rtz + fmsub.q x4, x8, x12, x6 + fmsub.q x4, x8, x12, x6, rtz + fnmsub.q x5, x8, x12, x16 + fnmsub.q x5, x8, x12, x16, rtz + fnmsub.q x6, x8, x12, x16 + fnmsub.q x6, x8, x12, x16, rtz + fnmsub.q x4, x5, x12, x16 + fnmsub.q x4, x5, x12, x16, rtz + fnmsub.q x4, x6, x12, x16 + fnmsub.q x4, x6, x12, x16, rtz + fnmsub.q x4, x8, x5, x16 + fnmsub.q x4, x8, x5, x16, rtz + fnmsub.q x4, x8, x6, x16 + fnmsub.q x4, x8, x6, x16, rtz + fnmsub.q x4, x8, x12, x5 + fnmsub.q x4, x8, x12, x5, rtz + fnmsub.q x4, x8, x12, x6 + fnmsub.q x4, x8, x12, x6, rtz + fsgnj.q x5, x8, x12 + fsgnj.q x6, x8, x12 + fsgnj.q x4, x5, x12 + fsgnj.q x4, x6, x12 + fsgnj.q x4, x8, x5 + fsgnj.q x4, x8, x6 + fsgnjn.q x5, x8, x12 + fsgnjn.q x6, x8, x12 + fsgnjn.q x4, x5, x12 + fsgnjn.q x4, x6, x12 + fsgnjn.q x4, x8, x5 + fsgnjn.q x4, x8, x6 + fsgnjx.q x5, x8, x12 + fsgnjx.q x6, x8, x12 + fsgnjx.q x4, x5, x12 + fsgnjx.q x4, x6, x12 + fsgnjx.q x4, x8, x5 + fsgnjx.q x4, x8, x6 + fmv.q x5, x8 + fmv.q x6, x8 + fmv.q x4, x5 + fmv.q x4, x6 + fneg.q x5, x8 + fneg.q x6, x8 + fneg.q x4, x5 + fneg.q x4, x6 + fabs.q x5, x8 + fabs.q x6, x8 + fabs.q x4, x5 + fabs.q x4, x6 + # Compare instructions: destination is a GPR + feq.q x4, x5, x12 + feq.q x4, x6, x12 + feq.q x4, x8, x5 + feq.q x4, x8, x6 + flt.q x4, x5, x12 + flt.q x4, x6, x12 + flt.q x4, x8, x5 + flt.q x4, x8, x6 + fle.q x4, x5, x12 + fle.q x4, x6, x12 + fle.q x4, x8, x5 + fle.q x4, x8, x6 + fgt.q x4, x5, x12 + fgt.q x4, x6, x12 + fgt.q x4, x8, x5 + fgt.q x4, x8, x6 + fge.q x4, x5, x12 + fge.q x4, x6, x12 + fge.q x4, x8, x5 + fge.q x4, x8, x6 + # fclass instruction: destination is a GPR + fclass.q x4, x5 + fclass.q x4, x6 + # fcvt instructions (float-int or int-float; + # integer operand register can be any) + fcvt.w.q x4, x5 + fcvt.w.q x4, x5, rtz + fcvt.w.q x4, x6 + fcvt.w.q x4, x6, rtz + fcvt.wu.q x4, x5 + fcvt.wu.q x4, x5, rtz + fcvt.wu.q x4, x6 + fcvt.wu.q x4, x6, rtz + fcvt.q.w x5, x4 + fcvt.q.w x6, x4 + fcvt.q.wu x5, x4 + fcvt.q.wu x6, x4 + # fcvt instructions (float-float; FP32 operand can be any, + # FP64 operand can be (x%4)==2) + fcvt.s.q x4, x5 + fcvt.s.q x4, x5, rtz + fcvt.s.q x4, x6 + fcvt.s.q x4, x6, rtz + fcvt.d.q x4, x5 + fcvt.d.q x4, x5, rtz + fcvt.d.q x4, x6 + fcvt.d.q x4, x6, rtz + fcvt.d.q x5, x8 + fcvt.d.q x5, x8, rtz + fcvt.q.s x5, x4 + fcvt.q.s x6, x4 + fcvt.q.d x5, x4 + fcvt.q.d x6, x4 + fcvt.q.d x8, x5 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair.d b/gas/testsuite/gas/riscv/zqinx-32-regpair.d new file mode 100644 index 00000000000..fcfdab597b1 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair.d @@ -0,0 +1,66 @@ +#as: -march=rv32ima_zqinx +#source: zqinx-32-regpair.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+06c47253[ ]+fadd.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+0ec47253[ ]+fsub.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+16c47253[ ]+fmul.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+1ec47253[ ]+fdiv.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+5e047253[ ]+fsqrt.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+2ec40253[ ]+fmin.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+2ec41253[ ]+fmax.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+86c47243[ ]+fmadd.q[ ]+tp,s0,a2,a6 +[ ]+[0-9a-f]+:[ ]+86c4724f[ ]+fnmadd.q[ ]+tp,s0,a2,a6 +[ ]+[0-9a-f]+:[ ]+86c47247[ ]+fmsub.q[ ]+tp,s0,a2,a6 +[ ]+[0-9a-f]+:[ ]+86c4724b[ ]+fnmsub.q[ ]+tp,s0,a2,a6 +[ ]+[0-9a-f]+:[ ]+26c40253[ ]+fsgnj.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+26c41253[ ]+fsgnjn.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+26c42253[ ]+fsgnjx.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+26840253[ ]+fmv.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+26841253[ ]+fneg.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+26842253[ ]+fabs.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+a6c42253[ ]+feq.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c422d3[ ]+feq.q[ ]+t0,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c42353[ ]+feq.q[ ]+t1,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c41253[ ]+flt.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c412d3[ ]+flt.q[ ]+t0,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c41353[ ]+flt.q[ ]+t1,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c40253[ ]+fle.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c402d3[ ]+fle.q[ ]+t0,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c40353[ ]+fle.q[ ]+t1,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6861253[ ]+flt.q[ ]+tp,a2,s0 +[ ]+[0-9a-f]+:[ ]+a68612d3[ ]+flt.q[ ]+t0,a2,s0 +[ ]+[0-9a-f]+:[ ]+a6861353[ ]+flt.q[ ]+t1,a2,s0 +[ ]+[0-9a-f]+:[ ]+a6860253[ ]+fle.q[ ]+tp,a2,s0 +[ ]+[0-9a-f]+:[ ]+a68602d3[ ]+fle.q[ ]+t0,a2,s0 +[ ]+[0-9a-f]+:[ ]+a6860353[ ]+fle.q[ ]+t1,a2,s0 +[ ]+[0-9a-f]+:[ ]+e6041253[ ]+fclass.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+e60412d3[ ]+fclass.q[ ]+t0,s0 +[ ]+[0-9a-f]+:[ ]+e6041353[ ]+fclass.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+c6047253[ ]+fcvt.w.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+c60472d3[ ]+fcvt.w.q[ ]+t0,s0 +[ ]+[0-9a-f]+:[ ]+c6047353[ ]+fcvt.w.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+c6147253[ ]+fcvt.wu.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+c61472d3[ ]+fcvt.wu.q[ ]+t0,s0 +[ ]+[0-9a-f]+:[ ]+c6147353[ ]+fcvt.wu.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+d6020453[ ]+fcvt.q.w[ ]+s0,tp +[ ]+[0-9a-f]+:[ ]+d6028453[ ]+fcvt.q.w[ ]+s0,t0 +[ ]+[0-9a-f]+:[ ]+d6030453[ ]+fcvt.q.w[ ]+s0,t1 +[ ]+[0-9a-f]+:[ ]+d6120453[ ]+fcvt.q.wu[ ]+s0,tp +[ ]+[0-9a-f]+:[ ]+d6128453[ ]+fcvt.q.wu[ ]+s0,t0 +[ ]+[0-9a-f]+:[ ]+d6130453[ ]+fcvt.q.wu[ ]+s0,t1 +[ ]+[0-9a-f]+:[ ]+40347253[ ]+fcvt.s.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+403472d3[ ]+fcvt.s.q[ ]+t0,s0 +[ ]+[0-9a-f]+:[ ]+40347353[ ]+fcvt.s.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+42347253[ ]+fcvt.d.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+42347353[ ]+fcvt.d.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+46020453[ ]+fcvt.q.s[ ]+s0,tp +[ ]+[0-9a-f]+:[ ]+46028453[ ]+fcvt.q.s[ ]+s0,t0 +[ ]+[0-9a-f]+:[ ]+46030453[ ]+fcvt.q.s[ ]+s0,t1 +[ ]+[0-9a-f]+:[ ]+46120453[ ]+fcvt.q.d[ ]+s0,tp +[ ]+[0-9a-f]+:[ ]+46130453[ ]+fcvt.q.d[ ]+s0,t1 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair.s b/gas/testsuite/gas/riscv/zqinx-32-regpair.s new file mode 100644 index 00000000000..2f340767376 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair.s @@ -0,0 +1,64 @@ +target: + fadd.q x4, x8, x12 + fsub.q x4, x8, x12 + fmul.q x4, x8, x12 + fdiv.q x4, x8, x12 + fsqrt.q x4, x8 + fmin.q x4, x8, x12 + fmax.q x4, x8, x12 + fmadd.q x4, x8, x12, x16 + fnmadd.q x4, x8, x12, x16 + fmsub.q x4, x8, x12, x16 + fnmsub.q x4, x8, x12, x16 + fsgnj.q x4, x8, x12 + fsgnjn.q x4, x8, x12 + fsgnjx.q x4, x8, x12 + fmv.q x4, x8 + fneg.q x4, x8 + fabs.q x4, x8 + # Compare instructions: destination is a GPR + feq.q x4, x8, x12 + feq.q x5, x8, x12 + feq.q x6, x8, x12 + flt.q x4, x8, x12 + flt.q x5, x8, x12 + flt.q x6, x8, x12 + fle.q x4, x8, x12 + fle.q x5, x8, x12 + fle.q x6, x8, x12 + fgt.q x4, x8, x12 + fgt.q x5, x8, x12 + fgt.q x6, x8, x12 + fge.q x4, x8, x12 + fge.q x5, x8, x12 + fge.q x6, x8, x12 + # fclass instruction: destination is a GPR + fclass.q x4, x8 + fclass.q x5, x8 + fclass.q x6, x8 + # fcvt instructions (float-int or int-float; + # integer operand register can be any) + fcvt.w.q x4, x8 + fcvt.w.q x5, x8 + fcvt.w.q x6, x8 + fcvt.wu.q x4, x8 + fcvt.wu.q x5, x8 + fcvt.wu.q x6, x8 + fcvt.q.w x8, x4 + fcvt.q.w x8, x5 + fcvt.q.w x8, x6 + fcvt.q.wu x8, x4 + fcvt.q.wu x8, x5 + fcvt.q.wu x8, x6 + # fcvt instructions (float-float; FP32 operand can be any, + # FP64 operand can be (x%4)==2) + fcvt.s.q x4, x8 + fcvt.s.q x5, x8 + fcvt.s.q x6, x8 + fcvt.d.q x4, x8 + fcvt.d.q x6, x8 + fcvt.q.s x8, x4 + fcvt.q.s x8, x5 + fcvt.q.s x8, x6 + fcvt.q.d x8, x4 + fcvt.q.d x8, x6 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d new file mode 100644 index 00000000000..bac4e356675 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv64ima_zqinx +#source: zqinx-64-regpair-fail.s +#error_output: zqinx-64-regpair-fail.l diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l new file mode 100644 index 00000000000..414b10e48cc --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l @@ -0,0 +1,133 @@ +.*Assembler messages: +.*Error: illegal operands `fadd\.q a1,a2,a4' +.*Error: illegal operands `fadd\.q a1,a2,a4,rtz' +.*Error: illegal operands `fadd\.q a0,a1,a4' +.*Error: illegal operands `fadd\.q a0,a1,a4,rtz' +.*Error: illegal operands `fadd\.q a0,a2,a1' +.*Error: illegal operands `fadd\.q a0,a2,a1,rtz' +.*Error: illegal operands `fsub\.q a1,a2,a4' +.*Error: illegal operands `fsub\.q a1,a2,a4,rtz' +.*Error: illegal operands `fsub\.q a0,a1,a4' +.*Error: illegal operands `fsub\.q a0,a1,a4,rtz' +.*Error: illegal operands `fsub\.q a0,a2,a1' +.*Error: illegal operands `fsub\.q a0,a2,a1,rtz' +.*Error: illegal operands `fmul\.q a1,a2,a4' +.*Error: illegal operands `fmul\.q a1,a2,a4,rtz' +.*Error: illegal operands `fmul\.q a0,a1,a4' +.*Error: illegal operands `fmul\.q a0,a1,a4,rtz' +.*Error: illegal operands `fmul\.q a0,a2,a1' +.*Error: illegal operands `fmul\.q a0,a2,a1,rtz' +.*Error: illegal operands `fdiv\.q a1,a2,a4' +.*Error: illegal operands `fdiv\.q a1,a2,a4,rtz' +.*Error: illegal operands `fdiv\.q a0,a1,a4' +.*Error: illegal operands `fdiv\.q a0,a1,a4,rtz' +.*Error: illegal operands `fdiv\.q a0,a2,a1' +.*Error: illegal operands `fdiv\.q a0,a2,a1,rtz' +.*Error: illegal operands `fsqrt\.q a1,a2' +.*Error: illegal operands `fsqrt\.q a1,a2,rtz' +.*Error: illegal operands `fsqrt\.q a0,a1' +.*Error: illegal operands `fsqrt\.q a0,a1,rtz' +.*Error: illegal operands `fmin\.q a1,a2,a4' +.*Error: illegal operands `fmin\.q a0,a1,a4' +.*Error: illegal operands `fmin\.q a0,a2,a1' +.*Error: illegal operands `fmax\.q a1,a2,a4' +.*Error: illegal operands `fmax\.q a0,a1,a4' +.*Error: illegal operands `fmax\.q a0,a2,a1' +.*Error: illegal operands `fmadd\.q a1,a2,a4,a6' +.*Error: illegal operands `fmadd\.q a1,a2,a4,a6,rtz' +.*Error: illegal operands `fmadd\.q a0,a1,a4,a6' +.*Error: illegal operands `fmadd\.q a0,a1,a4,a6,rtz' +.*Error: illegal operands `fmadd\.q a0,a2,a1,a6' +.*Error: illegal operands `fmadd\.q a0,a2,a1,a6,rtz' +.*Error: illegal operands `fmadd\.q a0,a2,a4,a1' +.*Error: illegal operands `fmadd\.q a0,a2,a4,a1,rtz' +.*Error: illegal operands `fnmadd\.q a1,a2,a4,a6' +.*Error: illegal operands `fnmadd\.q a1,a2,a4,a6,rtz' +.*Error: illegal operands `fnmadd\.q a0,a1,a4,a6' +.*Error: illegal operands `fnmadd\.q a0,a1,a4,a6,rtz' +.*Error: illegal operands `fnmadd\.q a0,a2,a1,a6' +.*Error: illegal operands `fnmadd\.q a0,a2,a1,a6,rtz' +.*Error: illegal operands `fnmadd\.q a0,a2,a4,a1' +.*Error: illegal operands `fnmadd\.q a0,a2,a4,a1,rtz' +.*Error: illegal operands `fmsub\.q a1,a2,a4,a6' +.*Error: illegal operands `fmsub\.q a1,a2,a4,a6,rtz' +.*Error: illegal operands `fmsub\.q a0,a1,a4,a6' +.*Error: illegal operands `fmsub\.q a0,a1,a4,a6,rtz' +.*Error: illegal operands `fmsub\.q a0,a2,a1,a6' +.*Error: illegal operands `fmsub\.q a0,a2,a1,a6,rtz' +.*Error: illegal operands `fmsub\.q a0,a2,a4,a1' +.*Error: illegal operands `fmsub\.q a0,a2,a4,a1,rtz' +.*Error: illegal operands `fnmsub\.q a1,a2,a4,a6' +.*Error: illegal operands `fnmsub\.q a1,a2,a4,a6,rtz' +.*Error: illegal operands `fnmsub\.q a0,a1,a4,a6' +.*Error: illegal operands `fnmsub\.q a0,a1,a4,a6,rtz' +.*Error: illegal operands `fnmsub\.q a0,a2,a1,a6' +.*Error: illegal operands `fnmsub\.q a0,a2,a1,a6,rtz' +.*Error: illegal operands `fnmsub\.q a0,a2,a4,a1' +.*Error: illegal operands `fnmsub\.q a0,a2,a4,a1,rtz' +.*Error: illegal operands `fsgnj\.q a1,a2,a4' +.*Error: illegal operands `fsgnj\.q a0,a1,a4' +.*Error: illegal operands `fsgnj\.q a0,a2,a1' +.*Error: illegal operands `fsgnjn\.q a1,a2,a4' +.*Error: illegal operands `fsgnjn\.q a0,a1,a4' +.*Error: illegal operands `fsgnjn\.q a0,a2,a1' +.*Error: illegal operands `fsgnjx\.q a1,a2,a4' +.*Error: illegal operands `fsgnjx\.q a0,a1,a4' +.*Error: illegal operands `fsgnjx\.q a0,a2,a1' +.*Error: illegal operands `fmv\.q a1,a2' +.*Error: illegal operands `fmv\.q a0,a1' +.*Error: illegal operands `fneg\.q a1,a2' +.*Error: illegal operands `fneg\.q a0,a1' +.*Error: illegal operands `fabs\.q a1,a2' +.*Error: illegal operands `fabs\.q a0,a1' +.*Error: illegal operands `feq\.q a0,a1,a4' +.*Error: illegal operands `feq\.q a0,a2,a1' +.*Error: illegal operands `flt\.q a0,a1,a4' +.*Error: illegal operands `flt\.q a0,a2,a1' +.*Error: illegal operands `fle\.q a0,a1,a4' +.*Error: illegal operands `fle\.q a0,a2,a1' +.*Error: illegal operands `fgt\.q a0,a1,a4' +.*Error: illegal operands `fgt\.q a0,a2,a1' +.*Error: illegal operands `fge\.q a0,a1,a4' +.*Error: illegal operands `fge\.q a0,a2,a1' +.*Error: illegal operands `fclass\.q a0,a1' +.*Error: illegal operands `fcvt\.w\.q a0,a1' +.*Error: illegal operands `fcvt\.w\.q a0,a1,rtz' +.*Error: illegal operands `fcvt\.w\.q a3,a1' +.*Error: illegal operands `fcvt\.w\.q a3,a1,rtz' +.*Error: illegal operands `fcvt\.wu\.q a0,a1' +.*Error: illegal operands `fcvt\.wu\.q a0,a1,rtz' +.*Error: illegal operands `fcvt\.wu\.q a3,a1' +.*Error: illegal operands `fcvt\.wu\.q a3,a1,rtz' +.*Error: illegal operands `fcvt\.l\.q a0,a1' +.*Error: illegal operands `fcvt\.l\.q a0,a1,rtz' +.*Error: illegal operands `fcvt\.l\.q a3,a1' +.*Error: illegal operands `fcvt\.l\.q a3,a1,rtz' +.*Error: illegal operands `fcvt\.lu\.q a0,a1' +.*Error: illegal operands `fcvt\.lu\.q a0,a1,rtz' +.*Error: illegal operands `fcvt\.lu\.q a3,a1' +.*Error: illegal operands `fcvt\.lu\.q a3,a1,rtz' +.*Error: illegal operands `fcvt\.q\.w a1,a2' +.*Error: illegal operands `fcvt\.q\.w a1,a3' +.*Error: illegal operands `fcvt\.q\.wu a1,a2' +.*Error: illegal operands `fcvt\.q\.wu a1,a3' +.*Error: illegal operands `fcvt\.q\.l a1,a2' +.*Error: illegal operands `fcvt\.q\.l a1,a2,rtz' +.*Error: illegal operands `fcvt\.q\.l a1,a3' +.*Error: illegal operands `fcvt\.q\.l a1,a3,rtz' +.*Error: illegal operands `fcvt\.q\.lu a1,a2' +.*Error: illegal operands `fcvt\.q\.lu a1,a2,rtz' +.*Error: illegal operands `fcvt\.q\.lu a1,a3' +.*Error: illegal operands `fcvt\.q\.lu a1,a3,rtz' +.*Error: illegal operands `fcvt\.s\.q a0,a1' +.*Error: illegal operands `fcvt\.s\.q a0,a1,rtz' +.*Error: illegal operands `fcvt\.s\.q a3,a1' +.*Error: illegal operands `fcvt\.s\.q a3,a1,rtz' +.*Error: illegal operands `fcvt\.d\.q a0,a1' +.*Error: illegal operands `fcvt\.d\.q a0,a1,rtz' +.*Error: illegal operands `fcvt\.d\.q a3,a1' +.*Error: illegal operands `fcvt\.d\.q a3,a1,rtz' +.*Error: illegal operands `fcvt\.q\.s a1,a2' +.*Error: illegal operands `fcvt\.q\.s a1,a3' +.*Error: illegal operands `fcvt\.q\.d a1,a2' +.*Error: illegal operands `fcvt\.q\.d a1,a3' diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s new file mode 100644 index 00000000000..f01c4f98b9f --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s @@ -0,0 +1,138 @@ +target: + fadd.q a1, a2, a4 + fadd.q a1, a2, a4, rtz + fadd.q a0, a1, a4 + fadd.q a0, a1, a4, rtz + fadd.q a0, a2, a1 + fadd.q a0, a2, a1, rtz + fsub.q a1, a2, a4 + fsub.q a1, a2, a4, rtz + fsub.q a0, a1, a4 + fsub.q a0, a1, a4, rtz + fsub.q a0, a2, a1 + fsub.q a0, a2, a1, rtz + fmul.q a1, a2, a4 + fmul.q a1, a2, a4, rtz + fmul.q a0, a1, a4 + fmul.q a0, a1, a4, rtz + fmul.q a0, a2, a1 + fmul.q a0, a2, a1, rtz + fdiv.q a1, a2, a4 + fdiv.q a1, a2, a4, rtz + fdiv.q a0, a1, a4 + fdiv.q a0, a1, a4, rtz + fdiv.q a0, a2, a1 + fdiv.q a0, a2, a1, rtz + fsqrt.q a1, a2 + fsqrt.q a1, a2, rtz + fsqrt.q a0, a1 + fsqrt.q a0, a1, rtz + fmin.q a1, a2, a4 + fmin.q a0, a1, a4 + fmin.q a0, a2, a1 + fmax.q a1, a2, a4 + fmax.q a0, a1, a4 + fmax.q a0, a2, a1 + fmadd.q a1, a2, a4, a6 + fmadd.q a1, a2, a4, a6, rtz + fmadd.q a0, a1, a4, a6 + fmadd.q a0, a1, a4, a6, rtz + fmadd.q a0, a2, a1, a6 + fmadd.q a0, a2, a1, a6, rtz + fmadd.q a0, a2, a4, a1 + fmadd.q a0, a2, a4, a1, rtz + fnmadd.q a1, a2, a4, a6 + fnmadd.q a1, a2, a4, a6, rtz + fnmadd.q a0, a1, a4, a6 + fnmadd.q a0, a1, a4, a6, rtz + fnmadd.q a0, a2, a1, a6 + fnmadd.q a0, a2, a1, a6, rtz + fnmadd.q a0, a2, a4, a1 + fnmadd.q a0, a2, a4, a1, rtz + fmsub.q a1, a2, a4, a6 + fmsub.q a1, a2, a4, a6, rtz + fmsub.q a0, a1, a4, a6 + fmsub.q a0, a1, a4, a6, rtz + fmsub.q a0, a2, a1, a6 + fmsub.q a0, a2, a1, a6, rtz + fmsub.q a0, a2, a4, a1 + fmsub.q a0, a2, a4, a1, rtz + fnmsub.q a1, a2, a4, a6 + fnmsub.q a1, a2, a4, a6, rtz + fnmsub.q a0, a1, a4, a6 + fnmsub.q a0, a1, a4, a6, rtz + fnmsub.q a0, a2, a1, a6 + fnmsub.q a0, a2, a1, a6, rtz + fnmsub.q a0, a2, a4, a1 + fnmsub.q a0, a2, a4, a1, rtz + fsgnj.q a1, a2, a4 + fsgnj.q a0, a1, a4 + fsgnj.q a0, a2, a1 + fsgnjn.q a1, a2, a4 + fsgnjn.q a0, a1, a4 + fsgnjn.q a0, a2, a1 + fsgnjx.q a1, a2, a4 + fsgnjx.q a0, a1, a4 + fsgnjx.q a0, a2, a1 + fmv.q a1, a2 + fmv.q a0, a1 + fneg.q a1, a2 + fneg.q a0, a1 + fabs.q a1, a2 + fabs.q a0, a1 + # Compare instructions: destination is a GPR + feq.q a0, a1, a4 + feq.q a0, a2, a1 + flt.q a0, a1, a4 + flt.q a0, a2, a1 + fle.q a0, a1, a4 + fle.q a0, a2, a1 + fgt.q a0, a1, a4 + fgt.q a0, a2, a1 + fge.q a0, a1, a4 + fge.q a0, a2, a1 + # fclass instruction: destination is a GPR + fclass.q a0, a1 + # fcvt instructions (float-int or int-float; + # integer operand register can be odd) + fcvt.w.q a0, a1 + fcvt.w.q a0, a1, rtz + fcvt.w.q a3, a1 + fcvt.w.q a3, a1, rtz + fcvt.wu.q a0, a1 + fcvt.wu.q a0, a1, rtz + fcvt.wu.q a3, a1 + fcvt.wu.q a3, a1, rtz + fcvt.l.q a0, a1 + fcvt.l.q a0, a1, rtz + fcvt.l.q a3, a1 + fcvt.l.q a3, a1, rtz + fcvt.lu.q a0, a1 + fcvt.lu.q a0, a1, rtz + fcvt.lu.q a3, a1 + fcvt.lu.q a3, a1, rtz + fcvt.q.w a1, a2 + fcvt.q.w a1, a3 + fcvt.q.wu a1, a2 + fcvt.q.wu a1, a3 + fcvt.q.l a1, a2 + fcvt.q.l a1, a2, rtz + fcvt.q.l a1, a3 + fcvt.q.l a1, a3, rtz + fcvt.q.lu a1, a2 + fcvt.q.lu a1, a2, rtz + fcvt.q.lu a1, a3 + fcvt.q.lu a1, a3, rtz + # fcvt instructions (float-float; FP32/FP64 operand can be odd) + fcvt.s.q a0, a1 + fcvt.s.q a0, a1, rtz + fcvt.s.q a3, a1 + fcvt.s.q a3, a1, rtz + fcvt.d.q a0, a1 + fcvt.d.q a0, a1, rtz + fcvt.d.q a3, a1 + fcvt.d.q a3, a1, rtz + fcvt.q.s a1, a2 + fcvt.q.s a1, a3 + fcvt.q.d a1, a2 + fcvt.q.d a1, a3 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair.d b/gas/testsuite/gas/riscv/zqinx-64-regpair.d new file mode 100644 index 00000000000..62eefdf69f6 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair.d @@ -0,0 +1,87 @@ +#as: -march=rv64ima_zqinx +#source: zqinx-64-regpair.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+06e67553[ ]+fadd.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+06e61553[ ]+fadd.q[ ]+a0,a2,a4,rtz +[ ]+[0-9a-f]+:[ ]+0ee67553[ ]+fsub.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+0ee61553[ ]+fsub.q[ ]+a0,a2,a4,rtz +[ ]+[0-9a-f]+:[ ]+16e67553[ ]+fmul.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+16e61553[ ]+fmul.q[ ]+a0,a2,a4,rtz +[ ]+[0-9a-f]+:[ ]+1ee67553[ ]+fdiv.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+1ee61553[ ]+fdiv.q[ ]+a0,a2,a4,rtz +[ ]+[0-9a-f]+:[ ]+5e067553[ ]+fsqrt.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+5e061553[ ]+fsqrt.q[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+2ee60553[ ]+fmin.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+2ee61553[ ]+fmax.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+86e67543[ ]+fmadd.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e61543[ ]+fmadd.q[ ]+a0,a2,a4,a6,rtz +[ ]+[0-9a-f]+:[ ]+86e6754f[ ]+fnmadd.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e6154f[ ]+fnmadd.q[ ]+a0,a2,a4,a6,rtz +[ ]+[0-9a-f]+:[ ]+86e67547[ ]+fmsub.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e61547[ ]+fmsub.q[ ]+a0,a2,a4,a6,rtz +[ ]+[0-9a-f]+:[ ]+86e6754b[ ]+fnmsub.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e6154b[ ]+fnmsub.q[ ]+a0,a2,a4,a6,rtz +[ ]+[0-9a-f]+:[ ]+26e60553[ ]+fsgnj.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26e61553[ ]+fsgnjn.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26e62553[ ]+fsgnjx.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26c60553[ ]+fmv.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+26c61553[ ]+fneg.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+26c62553[ ]+fabs.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+a6e62553[ ]+feq.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e625d3[ ]+feq.q[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e61553[ ]+flt.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e615d3[ ]+flt.q[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e60553[ ]+fle.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e605d3[ ]+fle.q[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6c71553[ ]+flt.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a6c715d3[ ]+flt.q[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+a6c70553[ ]+fle.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a6c705d3[ ]+fle.q[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+e6061553[ ]+fclass.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+e60615d3[ ]+fclass.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c6067553[ ]+fcvt.w.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6061553[ ]+fcvt.w.q[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+c60675d3[ ]+fcvt.w.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c60615d3[ ]+fcvt.w.q[ ]+a1,a2,rtz +[ ]+[0-9a-f]+:[ ]+c6167553[ ]+fcvt.wu.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6161553[ ]+fcvt.wu.q[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+c61675d3[ ]+fcvt.wu.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c61615d3[ ]+fcvt.wu.q[ ]+a1,a2,rtz +[ ]+[0-9a-f]+:[ ]+c6267553[ ]+fcvt.l.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6261553[ ]+fcvt.l.q[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+c62675d3[ ]+fcvt.l.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c62615d3[ ]+fcvt.l.q[ ]+a1,a2,rtz +[ ]+[0-9a-f]+:[ ]+c6367553[ ]+fcvt.lu.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6361553[ ]+fcvt.lu.q[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+c63675d3[ ]+fcvt.lu.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c63615d3[ ]+fcvt.lu.q[ ]+a1,a2,rtz +[ ]+[0-9a-f]+:[ ]+d6060553[ ]+fcvt.q.w[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6058553[ ]+fcvt.q.w[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d6160553[ ]+fcvt.q.wu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6158553[ ]+fcvt.q.wu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d6267553[ ]+fcvt.q.l[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6261553[ ]+fcvt.q.l[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+d625f553[ ]+fcvt.q.l[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d6259553[ ]+fcvt.q.l[ ]+a0,a1,rtz +[ ]+[0-9a-f]+:[ ]+d6367553[ ]+fcvt.q.lu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6361553[ ]+fcvt.q.lu[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+d635f553[ ]+fcvt.q.lu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d6359553[ ]+fcvt.q.lu[ ]+a0,a1,rtz +[ ]+[0-9a-f]+:[ ]+40367553[ ]+fcvt.s.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+40361553[ ]+fcvt.s.q[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+403675d3[ ]+fcvt.s.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+403615d3[ ]+fcvt.s.q[ ]+a1,a2,rtz +[ ]+[0-9a-f]+:[ ]+42367553[ ]+fcvt.d.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+42361553[ ]+fcvt.d.q[ ]+a0,a2,rtz +[ ]+[0-9a-f]+:[ ]+423675d3[ ]+fcvt.d.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+423615d3[ ]+fcvt.d.q[ ]+a1,a2,rtz +[ ]+[0-9a-f]+:[ ]+46060553[ ]+fcvt.q.s[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+46058553[ ]+fcvt.q.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+46160553[ ]+fcvt.q.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+46158553[ ]+fcvt.q.d[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair.s b/gas/testsuite/gas/riscv/zqinx-64-regpair.s new file mode 100644 index 00000000000..0c80749fd66 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair.s @@ -0,0 +1,84 @@ +target: + fadd.q a0, a2, a4 + fadd.q a0, a2, a4, rtz + fsub.q a0, a2, a4 + fsub.q a0, a2, a4, rtz + fmul.q a0, a2, a4 + fmul.q a0, a2, a4, rtz + fdiv.q a0, a2, a4 + fdiv.q a0, a2, a4, rtz + fsqrt.q a0, a2 + fsqrt.q a0, a2, rtz + fmin.q a0, a2, a4 + fmax.q a0, a2, a4 + fmadd.q a0, a2, a4, a6 + fmadd.q a0, a2, a4, a6, rtz + fnmadd.q a0, a2, a4, a6 + fnmadd.q a0, a2, a4, a6, rtz + fmsub.q a0, a2, a4, a6 + fmsub.q a0, a2, a4, a6, rtz + fnmsub.q a0, a2, a4, a6 + fnmsub.q a0, a2, a4, a6, rtz + fsgnj.q a0, a2, a4 + fsgnjn.q a0, a2, a4 + fsgnjx.q a0, a2, a4 + fmv.q a0, a2 + fneg.q a0, a2 + fabs.q a0, a2 + # Compare instructions: destination is a GPR + feq.q a0, a2, a4 + feq.q a1, a2, a4 + flt.q a0, a2, a4 + flt.q a1, a2, a4 + fle.q a0, a2, a4 + fle.q a1, a2, a4 + fgt.q a0, a2, a4 + fgt.q a1, a2, a4 + fge.q a0, a2, a4 + fge.q a1, a2, a4 + # fclass instruction: destination is a GPR + fclass.q a0, a2 + fclass.q a1, a2 + # fcvt instructions (float-int or int-float; + # integer operand register can be odd) + fcvt.w.q a0, a2 + fcvt.w.q a0, a2, rtz + fcvt.w.q a1, a2 + fcvt.w.q a1, a2, rtz + fcvt.wu.q a0, a2 + fcvt.wu.q a0, a2, rtz + fcvt.wu.q a1, a2 + fcvt.wu.q a1, a2, rtz + fcvt.l.q a0, a2 + fcvt.l.q a0, a2, rtz + fcvt.l.q a1, a2 + fcvt.l.q a1, a2, rtz + fcvt.lu.q a0, a2 + fcvt.lu.q a0, a2, rtz + fcvt.lu.q a1, a2 + fcvt.lu.q a1, a2, rtz + fcvt.q.w a0, a2 + fcvt.q.w a0, a1 + fcvt.q.wu a0, a2 + fcvt.q.wu a0, a1 + fcvt.q.l a0, a2 + fcvt.q.l a0, a2, rtz + fcvt.q.l a0, a1 + fcvt.q.l a0, a1, rtz + fcvt.q.lu a0, a2 + fcvt.q.lu a0, a2, rtz + fcvt.q.lu a0, a1 + fcvt.q.lu a0, a1, rtz + # fcvt instructions (float-float; FP32/FP64 operand can be odd) + fcvt.s.q a0, a2 + fcvt.s.q a0, a2, rtz + fcvt.s.q a1, a2 + fcvt.s.q a1, a2, rtz + fcvt.d.q a0, a2 + fcvt.d.q a0, a2, rtz + fcvt.d.q a1, a2 + fcvt.d.q a1, a2, rtz + fcvt.q.s a0, a2 + fcvt.q.s a0, a1 + fcvt.q.d a0, a2 + fcvt.q.d a0, a1 -- 2.32.0