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From: Saurabh Jha <saurabh.jha@arm.com>
To: binutils@sourceware.org, Richard Earnshaw <richard.earnshaw@arm.com>
Subject: Re: [PATCH v4 1/2] gas, aarch64: Add AdvSIMD lut extension
Date: Wed, 22 May 2024 11:26:47 +0100	[thread overview]
Message-ID: <04d93b7f-e78f-47fe-a9d3-a53b3503167a@arm.com> (raw)
In-Reply-To: <ec760df2-2c9f-42dc-bc98-097bbe42ef2f@arm.com>

On 5/21/2024 1:54 PM, Saurabh Jha wrote:
> Introduces instructions for the Advanced SIMD lut extension for AArch64. 
> They are documented in the following links:
> * luti2: 
> https://developer.arm.com/documentation/ddi0602/2024-03/SIMD-FP-Instructions/LUTI2--Lookup-table-read-with-2-bit-indices-?lang=en
> * luti4: 
> https://developer.arm.com/documentation/ddi0602/2024-03/SIMD-FP-Instructions/LUTI4--Lookup-table-read-with-4-bit-indices-?lang=en
> 
> These instructions needed definition of some new operands. We will first
> discuss operands for the third operand of the instructions and then
> discuss a vector register list operand needed for the second operand.
> 
> The third operands are vectors with bit indices and without type
> qualifiers. They are called Em_INDEX1_14, Em_INDEX2_13, and Em_INDEX3_12
> and they have 1 bit, 2 bit, and 3 bit indices respectively. For these
> new operands, we defined new parsing case branch and a new instruction
> class. We also modified the existing reglane inserters and extractors
> to handle the new operands. The lsb and width of these operands are
> the same as many existing operands but the convention is to give
> different names to fields that serve different purpose so we
> introduced new fields in aarch64-opc.c and aarch64-opc.h for these
> operands.
> 
> For the second operand of these instructions, we introduced a new
> operand called LVn_LUT. This represents a vector register list with
> stride 1. We defined new inserter and extractor for this new operand and
> it is encoded in FLD_Rn. We are enforcing the number of registers in the
> reglist using opcode flag rather than operand flag as this is what other
> SIMD vector register list operands are doing. The disassembly also uses
> opcode flag to print the correct number of registers.
> ---
> Hi,
> 
> Regression tested for aarch64-none-elf and found no regressions.
> 
> Ok for binutils-master? I don't have commit access so can someone please 
> commit on my behalf?
> 
> Regards,
> Saurabh

A new version of this patch is here 
https://sourceware.org/pipermail/binutils/2024-May/134230.html. The 
generated files are in this patch 
https://sourceware.org/pipermail/binutils/2024-May/134231.html

      reply	other threads:[~2024-05-22 10:27 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-21 12:54 Saurabh Jha
2024-05-22 10:26 ` Saurabh Jha [this message]

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