From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2054.outbound.protection.outlook.com [40.107.20.54]) by sourceware.org (Postfix) with ESMTPS id 3CD74385B53D for ; Fri, 3 Feb 2023 07:32:18 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3CD74385B53D Authentication-Results: sourceware.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=suse.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=dMSW8DsdMCIlyqjM1eBRlUUOafYVvExZLaTNdekXD+WW2uYeoG/PHKRkPXBt+u4fG1VQKkWhNH+WMZjdi2Ws7t/yPmXK7EZX/FKXf5am8Cpj15Z20mbyc6q7+2RYitMHJeF+ul3pSJRwVJjkp2PxXGHVp4wxskEmOnDER8eL6v+/CZDoBdcZblVh1WeUNP6fv7fVX03lIGv0IUgYT+juvTpmcm5BJfWsjyvZTsrWYDsNSDfCOPkbT1Moldwi0bO644cMHIxWaxtK4e8OaUE1kbzl0euURTUXdYte95bxSiJO8MDOzz1tn5o3VCTJvPNQINyP1euUAa8eJOp0Iv6q6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=966F406icbPpuC0LV2xCjfRnBzzfP8fTd+3eGt90uWg=; b=Vpg9SGewZ8C+1y/Vu+hQbmZmajUHY+hi3zAa4kcbzFkvcjRNZnap/jpPX7G0P2+l9JQzz7Xk52zDw5SJ6U6LCUJTiuAitSW9gJzFCYzlMa82N8eTRw0SwcBfKhgPNwwbKfYQFk/LI5KJmOASQXKKTeKdjVKc9Jo4CwnLl1wsWNcDpWsRK8ZLHdwUFSOD2/p5hnK5WsPNF498ZrENyQ+0ev3Y9RptJQi+FwjJF3H6/BvuY2RKOfL4xiuyiyBAcKX//az7jPaAE4fCEOoL4XirQoGni5qqvYX2quaRUPCKN+GcaKy6Tlt29g8bqjxNJkBRW0otsWfzTIohfgjR6zhJPw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=suse.com; dmarc=pass action=none header.from=suse.com; dkim=pass header.d=suse.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=966F406icbPpuC0LV2xCjfRnBzzfP8fTd+3eGt90uWg=; b=mSsDDq0Q4w72+TFYErcgjNRg7iFgM93ItyPhFuPt93gwJDLZyZ8V5AUBEq/oEfJ69nWkqtnLIvygVExc74qUYQMOYsnMQ/Fam7PjuY2kcXkJpCasBb0FOfvVEZ3RwidzAg2WJWYGUKS4dEbo0BptoQu5dx1hMWIwuhtoTdMmQQYujGwUokaJf5IIl9k+7C2VNjFEAolGWvGSsMOiAzp+2mBjUm0XqartGodFXga7d9pPjRGpgyMJjBeA/lidQENy+21Qgkz2PC05CAR6LzYwoOBQvwD3NSvtKGM/TJncRrwTJf3wVQiQSl7NDV571pG1u1/3MefHNfWz737aNaP8Tw== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=suse.com; Received: from VE1PR04MB6560.eurprd04.prod.outlook.com (2603:10a6:803:122::25) by AS4PR04MB9715.eurprd04.prod.outlook.com (2603:10a6:20b:4f9::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6064.25; Fri, 3 Feb 2023 07:32:15 +0000 Received: from VE1PR04MB6560.eurprd04.prod.outlook.com ([fe80::e138:4fc3:705c:d178]) by VE1PR04MB6560.eurprd04.prod.outlook.com ([fe80::e138:4fc3:705c:d178%6]) with mapi id 15.20.6064.024; Fri, 3 Feb 2023 07:32:15 +0000 Message-ID: <06804163-be78-6130-b082-71661e50e876@suse.com> Date: Fri, 3 Feb 2023 08:32:13 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: [PATCH 1/3] x86: improve special casing of certain insns Content-Language: en-US To: Binutils Cc: "H.J. Lu" References: <1387362a-7920-de18-18e5-9fe42f923f0b@suse.com> From: Jan Beulich In-Reply-To: <1387362a-7920-de18-18e5-9fe42f923f0b@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-ClientProxiedBy: FR3P281CA0100.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:a1::18) To VE1PR04MB6560.eurprd04.prod.outlook.com (2603:10a6:803:122::25) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: VE1PR04MB6560:EE_|AS4PR04MB9715:EE_ X-MS-Office365-Filtering-Correlation-Id: a2229746-f532-4502-84d8-08db05b8c569 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: xQuup6kSoiofLE7h1Jo63LyMwW01YYBM6RRFDE3vHYin1zxZ7DLX4/QC7tIchKVOYrrzZh0bagjnQ3ev81htHS1X2yKkcHWtl2ykWJkpdlNjpVy/2Sna8Pq7SP3tv1SQBDCgKX3pv3GZrbJxnW/w6+2iErHonauVEKcycTyTMIA8ykIKLDoKVeNb4++dXiCNeXUGXMuLXJadvK4cVUhr+napBJgFZeE8eMMRNqFCa85qUy0dZJKIqfJ2VvcHMiZGY3IakaVL3vUDHFFwtT/EQYG7At2mCnfFkUFJ5F4UxDDdWiwN+PZJofg60y8vkBJIlEKXCAXFmUwmrDtjxG5NkgvWEUhQ8qkRwX72vUtcauUML/GANxohEfwRVBmPccleyfdO4TCHg10IrEKEUDJKfby6HodVDZwrPcdCO8KdE550iguwbZnShYC+8S4FReGfgcMZt+l3hea9LC9XKPzsNtO5XRF7ZvmuE0+Y3xXhGnBm1m2vKti2yLdObb0NQ4L5uBRuNgMmrIIU1cZiYWLrtU+nPaCL2LWl4YMqU+lk2f5jUSoYW/HGcPWykDc8TKE7MCm9oyP1R4V8Nckqe40535pPYHooQN5rxakl61D2pKNcsoHOzazyAwJJNHUxFQwJiX/r3yjv7De4XRl2b1DP234jbZ9RCX6JSpy878iB9xC61YiQgSXfY3g1bI5PMJvH8x/mOzsjBWi3djuffShdB15wWcb2eW0UrGjjqv1jn4w= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:VE1PR04MB6560.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230025)(346002)(376002)(39860400002)(136003)(396003)(366004)(451199018)(478600001)(6486002)(83380400001)(31696002)(86362001)(38100700002)(36756003)(2616005)(6512007)(26005)(186003)(6506007)(31686004)(5660300002)(66556008)(316002)(4326008)(66946007)(8936002)(41300700001)(6916009)(66476007)(8676002)(2906002)(45980500001)(43740500002);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?czNtMW95M3B1d0IyKzJkSTF2VE9FM1dmUjJWSDR5dUJMbmM0Z0puc25BTDlD?= =?utf-8?B?SHVWRmlaY2ExL2w4Y2Q5VjRxampOTWpaaWt2aU9FZmNrenlGUDJSUXgxZnBH?= =?utf-8?B?a2Z4ZFV5WUd6dHovdkl1dzd5Yk96d1Q3ZVBzZGducEdGYWNYbHJlcm5ZdmMw?= =?utf-8?B?V0I4WkNiSzZwZ0UvMFRvM2xUb1ArNjYzbnFlelBkU21MdHNuOGhsVWpYQlJM?= =?utf-8?B?eWlUN2lPcE5JQzhnVW1pZTJKeWthckhjZG9ZNk9xVjBUMUZpdnk4S0xUVXZi?= =?utf-8?B?bDVCVUk0UnFLbjVrUERNalp1M3lvQW1ScHphamV6QWZzakd0SWlaNjlYSFh5?= =?utf-8?B?bG4zQlFQTVdobkdLN0dnY2NmU2tCSm5GTm5Td0x0SlVOd0hVaVVPS0gxSlhu?= =?utf-8?B?YUFuTit4Tk1GbXBpUGxON3RyNGdlb0FsV1o3ZmJBY2JSNHE2ZkJPd0lHZklH?= =?utf-8?B?TEJ1WTJib2JSZ2xKeWp0RzZ4bmE4ZnhYVFFJaHhIKy9MbWd5RkxLblFicjRK?= =?utf-8?B?OFkxc2QvWm9FTk9LenpJamZiN2dPdHNuU2twQjA5NkV2ZjlHNi8xU21ZUDJl?= =?utf-8?B?NDlTYityR2I0VEVYdEhjYXA3Q3lUNVNkc2l3Q1pPSE8yclJybU9vQlU0bzhH?= =?utf-8?B?R1c0Qkg2RzZ1WGRoOVhtVk9ESVp1alV5YllROTRycmZQeUQ3Y3V5YTBTV3Yy?= =?utf-8?B?bzIyUHhmbktVZ0JHNlNRaEZkeklDdFpsOGJFR1A1TU15bnlIbFpJMmxEdUhO?= =?utf-8?B?Uk9jVzhnWG9ndnJEb1I2d3NURWlRZlZJUEtQMTB1ZjRXLzVIMFEzdjVxbGE2?= =?utf-8?B?Y0ZnMG91MEhZOWhyYVZja2pmS2V6aGtNd0I5cDVzeEl0SzgwUi81dXdSZC9u?= =?utf-8?B?SjRaUnhEYkU0VDFVRG4xT1RqekN2TlJDdFA2d3lOTXFXd0p0UTJaeDhDSnp3?= =?utf-8?B?Q2t1U3AvSTd6Z3hjaE53azV6dFF1MHNHV2pnVjVwMERoZTFseDNQVXdrQ1pT?= =?utf-8?B?UWlneXg4NDZ1emhkenRoRmNCdW85b01TTm5sbEVHc0RTZ1N3bmVJanpBUEta?= =?utf-8?B?ZDdHa1hmd2toYmxhNldheVNTdXM1RnVWb0xETEZtVyt4NnQ1K2cvSVpQY2c5?= =?utf-8?B?YnI1NGRpb3ZnZWdlYXNlV0dZQWdyV0RIQnFldmJzZkpack5GRFFINFkvKzNU?= =?utf-8?B?WGJYWmpsWTU0MkRGTXBOVDhiOG52cUFsWUVMU0JSYS9BSGFDUVJSWWFCZjhV?= =?utf-8?B?SHFMLy9GRHRwS2xMYkVVQUUxYjgvN2FIQnhHaloxb284MlZPaEplV1FNTHlK?= =?utf-8?B?cEJUV25VYXJZQzVRc2NwS1FWeUttTCtsZVFDOFkreUVxSzhMa2VqU3pmRFpm?= =?utf-8?B?b2dIOU1jVitGdUFJVUczRVFTeHEwalh6dnl2bk9yUHZaZFVpZzVYK1NnRFNx?= =?utf-8?B?MWZwRmcxYm1ReHNWdFRqRVBGaG10Z2tGUGNEU1ZualJHUTVCNzJsVERjYlI3?= =?utf-8?B?d3VFVVB4cVY0RVE5TzdaK3BkM0tJM0lIOHVmenNtQkNNTmUrZmJHMXNoR0F1?= =?utf-8?B?Z2ZvMHJ3REpManRnV2VZUFloK3Y3c2tHY1JtRTkxREFGV1hucmdTdkRSQjNW?= =?utf-8?B?UDJpWUVBcHBOSlNMa2dLbEVLM3QwdzZtbENDWVV2bjR4bE1Kd2hwUEtBUk5J?= =?utf-8?B?VXpFUnR2UUJnREJ1UkV6TTVnVHd3VGJPdWJjdzh4RE5aSFR4OW9tb0Y5RThT?= =?utf-8?B?RklkbjNGOVRwNjRadkw5VzhhMCtLU2pXRlRZN01ucEtNWmx6WlVqZXdhbXdX?= =?utf-8?B?d0FvaE5Mcktra0lsVWdQb2dZVmdWUEU5WDcrM3NFUGhJOEg5ellrbVBIN3py?= =?utf-8?B?MEx3Y1p0RElsT3VtMG9HbjFOWTBMblNsUFdadGFxU2JsSmF6dlljYzM3cEZa?= =?utf-8?B?V2xlMWQyR3NLMlpkOW8yR0JraU9CWE13MktEVmgxSHdQcVBsaHBJUFN1VmxZ?= =?utf-8?B?UjFqS085a1grKy9GMCtjaDF0ZjdYam0rV1BiYkt3U1RvOENGek1aRkd2cWVj?= =?utf-8?B?UjhnQnZmdWVTellBSlY0ZXczOWRXckZqTHdPQTRUaUZlWHRzMFNmTU9IeGcz?= =?utf-8?Q?IDBMFkpCdimSo/HWu7RTZZXZ0?= X-OriginatorOrg: suse.com X-MS-Exchange-CrossTenant-Network-Message-Id: a2229746-f532-4502-84d8-08db05b8c569 X-MS-Exchange-CrossTenant-AuthSource: VE1PR04MB6560.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2023 07:32:15.1423 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: hftR/OFwbK7A8v1nIS3LFYkRQi4C9CcGn/c/7jGhQwYt85zHCLYw1B1/A+t9UwWuAPONTqWe0HW0Ef2UAG/iYw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS4PR04MB9715 X-Spam-Status: No, score=-3028.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Now that we have identifiers for the mnemonic strings we can avoid opcode based comparisons, for (in many cases) being more expensive and (in a few cases) being a little fragile and not self-documenting. Note that the MOV optimization can be engaged by the earlier LEA one, and hence LEA also needs checking for there. --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -3487,8 +3487,7 @@ want_disp32 (const insn_template *t) { return flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX] - || (t->base_opcode == 0x8d - && t->opcode_modifier.opcodespace == SPACE_BASE + || (t->mnem_off == MN_lea && (!i.types[1].bitfield.qword || t->opcode_modifier.size == SIZE32)); } @@ -4096,8 +4095,7 @@ optimize_encoding (void) { unsigned int j; - if (i.tm.opcode_modifier.opcodespace == SPACE_BASE - && i.tm.base_opcode == 0x8d) + if (i.tm.mnem_off == MN_lea) { /* Optimize: -O: lea symbol, %rN -> mov $symbol, %rN @@ -4245,15 +4243,12 @@ optimize_encoding (void) } if (optimize_for_space - && i.tm.opcode_modifier.opcodespace == SPACE_BASE + && i.tm.mnem_off == MN_test && i.reg_operands == 1 && i.imm_operands == 1 && !i.types[1].bitfield.byte && i.op[0].imms->X_op == O_constant - && fits_in_imm7 (i.op[0].imms->X_add_number) - && (i.tm.base_opcode == 0xa8 - || (i.tm.base_opcode == 0xf6 - && i.tm.extension_opcode == 0x0))) + && fits_in_imm7 (i.op[0].imms->X_add_number)) { /* Optimize: -Os: test $imm7, %r64/%r32/%r16 -> test $imm7, %r8 @@ -4286,12 +4281,11 @@ optimize_encoding (void) && i.tm.extension_opcode == None && fits_in_unsigned_long (i.op[0].imms->X_add_number)) || (fits_in_imm31 (i.op[0].imms->X_add_number) - && ((i.tm.base_opcode == 0x24 - || i.tm.base_opcode == 0xa8) + && (i.tm.base_opcode == 0x24 || (i.tm.base_opcode == 0x80 && i.tm.extension_opcode == 0x4) - || ((i.tm.base_opcode == 0xf6 - || (i.tm.base_opcode | 1) == 0xc7) + || i.tm.mnem_off == MN_test + || ((i.tm.base_opcode | 1) == 0xc7 && i.tm.extension_opcode == 0x0))) || (fits_in_imm7 (i.op[0].imms->X_add_number) && i.tm.base_opcode == 0x83 @@ -4299,11 +4293,9 @@ optimize_encoding (void) || (i.types[0].bitfield.qword && ((i.reg_operands == 2 && i.op[0].regs == i.op[1].regs - && (i.tm.base_opcode == 0x30 - || i.tm.base_opcode == 0x28)) - || (i.reg_operands == 1 - && i.operands == 1 - && i.tm.base_opcode == 0x30))))) + && (i.tm.mnem_off == MN_xor + || i.tm.mnem_off == MN_sub)) + || i.tm.mnem_off == MN_clr)))) { /* Optimize: -O: andq $imm31, %r64 -> andl $imm31, %r32 @@ -4328,7 +4320,7 @@ optimize_encoding (void) } i.types[1].bitfield.dword = 1; i.types[1].bitfield.qword = 0; - if (i.tm.base_opcode == 0xb8 || (i.tm.base_opcode | 1) == 0xc7) + if (i.tm.mnem_off == MN_mov || i.tm.mnem_off == MN_lea) { /* Handle movq $imm31, %r64 -> movl $imm31, %r32 @@ -4351,11 +4343,9 @@ optimize_encoding (void) } else if (optimize > 1 && !optimize_for_space - && i.tm.opcode_modifier.opcodespace == SPACE_BASE && i.reg_operands == 2 && i.op[0].regs == i.op[1].regs - && ((i.tm.base_opcode & ~(Opcode_D | 1)) == 0x8 - || (i.tm.base_opcode & ~(Opcode_D | 1)) == 0x20) + && (i.tm.mnem_off == MN_and || i.tm.mnem_off == MN_or) && (flag_code != CODE_64BIT || !i.types[0].bitfield.dword)) { /* Optimize: -O2: @@ -4580,12 +4570,7 @@ load_insn_p (void) if (any_vex_p) { - /* vldmxcsr. */ - if (i.tm.base_opcode == 0xae - && i.tm.opcode_modifier.vex - && i.tm.opcode_modifier.opcodespace == SPACE_0F - && i.tm.opcode_modifier.opcodeprefix == PREFIX_NONE - && i.tm.extension_opcode == 2) + if (i.tm.mnem_off == MN_vldmxcsr) return 1; } else if (i.tm.opcode_modifier.opcodespace == SPACE_BASE) @@ -4699,9 +4684,7 @@ load_insn_p (void) || (base_opcode | 2) == 0x87)) return 1; - /* xadd. */ - if (i.tm.opcode_modifier.opcodespace == SPACE_0F - && base_opcode == 0xc1) + if (i.tm.mnem_off == MN_xadd) return 1; /* Check for load instruction. */ @@ -5361,12 +5344,8 @@ md_assemble (char *line) i.rex &= REX_OPCODE; } - /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 - instructions may define INT_OPCODE as well, so avoid this corner - case for those instructions that use MODRM. */ - if (i.tm.opcode_modifier.opcodespace == SPACE_BASE - && i.tm.base_opcode == INT_OPCODE - && !i.tm.opcode_modifier.modrm + /* Handle conversion of 'int $3' --> special int3 insn. */ + if (i.tm.mnem_off == MN_int && i.op[0].imms->X_add_number == 3) { i.tm.base_opcode = INT3_OPCODE; @@ -5476,10 +5455,7 @@ static INLINE bool q_suffix_allowed(cons || (t->opcode_modifier.opcodespace == SPACE_BASE && t->base_opcode == 0xdf && (t->extension_opcode & 1)) /* fild / fistp / fisttp */ - || (t->opcode_modifier.opcodespace == SPACE_0F - && t->base_opcode == 0xc7 - && t->opcode_modifier.opcodeprefix == PREFIX_NONE - && t->extension_opcode == 1) /* cmpxchg8b */; + || t->mnem_off == MN_cmpxchg8b; } static const char * @@ -7201,7 +7177,7 @@ check_string (void) static int process_suffix (void) { - bool is_crc32 = false, is_movx = false; + bool is_movx = false; /* If matched instruction specifies an explicit instruction mnemonic suffix, use it. */ @@ -7224,11 +7200,6 @@ process_suffix (void) && i.tm.base_opcode == 0x63 && i.tm.cpu_flags.bitfield.cpu64); - /* CRC32 */ - is_crc32 = (i.tm.base_opcode == 0xf0 - && i.tm.opcode_modifier.opcodespace == SPACE_0F38 - && i.tm.opcode_modifier.opcodeprefix == PREFIX_0XF2); - /* movsx/movzx want only their source operand considered here, for the ambiguity checking below. The suffix will be replaced afterwards to represent the destination (register). */ @@ -7236,7 +7207,7 @@ process_suffix (void) --i.operands; /* crc32 needs REX.W set regardless of suffix / source operand size. */ - if (is_crc32 && i.tm.operand_types[1].bitfield.qword) + if (i.tm.mnem_off == MN_crc32 && i.tm.operand_types[1].bitfield.qword) i.rex |= REX_W; /* If there's no instruction mnemonic suffix we try to invent one @@ -7247,7 +7218,7 @@ process_suffix (void) Destination register type is more significant than source register type. crc32 in SSE4.2 prefers source register type. */ - unsigned int op = is_crc32 ? 1 : i.operands; + unsigned int op = i.tm.mnem_off == MN_crc32 ? 1 : i.operands; while (op--) if (i.tm.operand_types[op].bitfield.instance == InstanceNone @@ -7571,8 +7542,7 @@ process_suffix (void) /* InOutPortReg */ || i.tm.operand_types[0].bitfield.instance == RegD || i.tm.operand_types[1].bitfield.instance == RegD - /* CRC32 */ - || is_crc32)))) + || i.tm.mnem_off == MN_crc32)))) i.tm.base_opcode |= 1; break; } @@ -7691,10 +7661,7 @@ check_byte_reg (void) continue; /* crc32 only wants its source operand checked here. */ - if (i.tm.base_opcode == 0xf0 - && i.tm.opcode_modifier.opcodespace == SPACE_0F38 - && i.tm.opcode_modifier.opcodeprefix == PREFIX_0XF2 - && op != 0) + if (i.tm.mnem_off == MN_crc32 && op != 0) continue; /* Any other register is bad. */ @@ -8160,9 +8127,7 @@ process_operands (void) } if ((i.seg[0] || i.prefix[SEG_PREFIX]) - && i.tm.base_opcode == 0x8d /* lea */ - && i.tm.opcode_modifier.opcodespace == SPACE_BASE - && !is_any_vex_encoding(&i.tm)) + && i.tm.mnem_off == MN_lea) { if (!quiet_warnings) as_warn (_("segment override on `%s' is ineffectual"), insn_name (&i.tm)); @@ -9089,7 +9054,7 @@ output_jump (void) break; case 2: - if (i.tm.base_opcode == 0xc7f8) + if (i.tm.mnem_off == MN_xbegin) fixP->fx_signed = 1; break; @@ -9601,10 +9566,8 @@ output_insn (void) x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87; if ((i.xstate & xstate_mmx) - || (i.tm.opcode_modifier.opcodespace == SPACE_0F - && !is_any_vex_encoding (&i.tm) - && (i.tm.base_opcode == 0x77 /* emms */ - || i.tm.base_opcode == 0x0e /* femms */))) + || i.tm.mnem_off == MN_emms + || i.tm.mnem_off == MN_femms) x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX; if (i.index_reg) @@ -9648,10 +9611,7 @@ output_insn (void) if (x86_feature_2_used || i.tm.cpu_flags.bitfield.cpucmov || i.tm.cpu_flags.bitfield.cpusyscall - || (i.tm.opcode_modifier.opcodespace == SPACE_0F - && i.tm.base_opcode == 0xc7 - && i.tm.opcode_modifier.opcodeprefix == PREFIX_NONE - && i.tm.extension_opcode == 1) /* cmpxchg8b */) + || i.tm.mnem_off == MN_cmpxchg8b) x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_BASELINE; if (i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpussse3 @@ -11503,12 +11463,9 @@ i386_index_check (const char *operand_st goto bad_address; /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */ - if ((t->opcode_modifier.opcodeprefix == PREFIX_0XF3 - && t->opcode_modifier.opcodespace == SPACE_0F - && t->base_opcode == 0x1b) - || (t->opcode_modifier.opcodeprefix == PREFIX_NONE - && t->opcode_modifier.opcodespace == SPACE_0F - && (t->base_opcode & ~1) == 0x1a) + if (t->mnem_off == MN_bndmk + || t->mnem_off == MN_bndldx + || t->mnem_off == MN_bndstx || t->opcode_modifier.sib == SIBMEM) { /* They cannot use RIP-relative addressing. */ @@ -11519,9 +11476,7 @@ i386_index_check (const char *operand_st } /* bndldx and bndstx ignore their scale factor. */ - if (t->opcode_modifier.opcodeprefix == PREFIX_NONE - && t->opcode_modifier.opcodespace == SPACE_0F - && (t->base_opcode & ~1) == 0x1a + if ((t->mnem_off == MN_bndldx || t->mnem_off == MN_bndstx) && i.log2_scale_factor) as_warn (_("register scaling is being ignored here")); }