From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 140F63858D39 for ; Mon, 14 Aug 2023 05:10:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 140F63858D39 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 87BAD300089; Mon, 14 Aug 2023 05:10:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1691989833; bh=e2nd1Llz7J0Z7EG3Yzeud9iSEte6+mA5xOBWli8OrJQ=; h=Message-ID:Date:Mime-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type:Content-Transfer-Encoding; b=to+Jn41wISvbtnIdfReieJJ/TBL251xY4FNj7F0MtkMsty+vAc6bNfZCTICeXT93N iesF57E1LcSLGAsiifXkzm6Qpqm3nGhyDu/bkbT7ub82oTF0UwrdgijdrVrcXHvFA5 78AZYNe5jcahDaaLnMEI9W91GcDbceLUg2HY0pKU= Message-ID: <08771591-9c4a-4b30-a143-5cb6f4ecc7bb@irq.a4lg.com> Date: Mon, 14 Aug 2023 14:10:33 +0900 Mime-Version: 1.0 Subject: Re: [PATCH] RISC-V: Make "fli.h" available to 'Zvfh' + 'Zfa' Content-Language: en-US To: Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , Kito Cheng , Nick Clifton Cc: binutils@sourceware.org References: <846929799c325fad57040e1c7560a0ed4d801065.1691857665.git.research_trasio@irq.a4lg.com> From: Tsukasa OI In-Reply-To: <846929799c325fad57040e1c7560a0ed4d801065.1691857665.git.research_trasio@irq.a4lg.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,GIT_PATCH_0,KAM_MANYTO,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: A little more background of this patch set. When I wrote the initial 'Zfa' proposal (which is improved by Christoph Müllner and upstreamed into master), I already noticed this reference to the 'Zvfh' extension but ignored it. Because I assumed that 'Zvfh' approval will take some time (turned out that it was wrong) and I didn't think both 'Zvfh' and 'Zfa' are approved in a similar timeline. When I had a chance to notice before GNU Binutils 2.41 is released (when both extensions are nearing their approval and ratification), I had no spare time due to my poor health condition at the time. I finally noticed after GNU Binutils 2.41 is released and started to learn how to extend GCC (when I'm writing a GCC optimization utilizing the 'Zfa' extension's FLI instructions). So, not only to the master branch, I request approval for binutils-2_41-branch (to Nick). Regards, Tsukasa On 2023/08/13 1:28, Tsukasa OI wrote: > From: Tsukasa OI > > The documentation of the 'Zfa' extension states that "fli.h" is available > "if the Zfh or Zvfh extension is implemented" (both the latest and the > oldest editions are checked). > > This fact was not reflected in Binutils ('Zvfh' implies 'Zfhmin', not full > 'Zfh' extension and "fli.h" required 'Zfh' and 'Zfa' extensions). > This commit makes "fli.h" also available when both 'Zfa' and 'Zvfh' > extensions are implemented. > > bfd/ChangeLog: > > * elfxx-riscv.c (riscv_multi_subset_supports): Add new > instruction class handling. > (riscv_multi_subset_supports_ext): Likewise. > > gas/ChangeLog: > > * testsuite/gas/riscv/zfa-zvfh.s: New test. > * testsuite/gas/riscv/zfa-zvfh.d: Ditto. > > include/ChangeLog: > > * opcode/riscv.h (enum riscv_insn_class): Add new instruction > class. > > opcodes/ChangeLog: > > * riscv-opc.c (riscv_opcodes): Change instruction class of "fli.h" > from INSN_CLASS_ZFH_AND_ZFA to new INSN_CLASS_ZFH_OR_ZVFH_AND_ZFA. > --- > bfd/elfxx-riscv.c | 15 +++++++++++++++ > gas/testsuite/gas/riscv/zfa-zvfh.d | 16 ++++++++++++++++ > gas/testsuite/gas/riscv/zfa-zvfh.s | 10 ++++++++++ > include/opcode/riscv.h | 1 + > opcodes/riscv-opc.c | 2 +- > 5 files changed, 43 insertions(+), 1 deletion(-) > create mode 100644 gas/testsuite/gas/riscv/zfa-zvfh.d > create mode 100644 gas/testsuite/gas/riscv/zfa-zvfh.s > > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c > index 9cc0c7b1c109..b78b79dc3c4b 100644 > --- a/bfd/elfxx-riscv.c > +++ b/bfd/elfxx-riscv.c > @@ -2456,6 +2456,10 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, > case INSN_CLASS_ZFH_AND_ZFA: > return riscv_subset_supports (rps, "zfh") > && riscv_subset_supports (rps, "zfa"); > + case INSN_CLASS_ZFH_OR_ZVFH_AND_ZFA: > + return (riscv_subset_supports (rps, "zfh") > + || riscv_subset_supports (rps, "zvfh")) > + && riscv_subset_supports (rps, "zfa"); > case INSN_CLASS_ZBA: > return riscv_subset_supports (rps, "zba"); > case INSN_CLASS_ZBB: > @@ -2684,6 +2688,17 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, > return "zfh"; > else > return "zfa"; > + case INSN_CLASS_ZFH_OR_ZVFH_AND_ZFA: > + if (!riscv_subset_supports (rps, "zfa")) > + { > + if (!riscv_subset_supports (rps, "zfh") > + && !riscv_subset_supports (rps, "zvfh")) > + return _("zfh' and `zfa', or `zvfh' and `zfa"); > + else > + return "zfa"; > + } > + else > + return _("zfh' or `zvfh"); > case INSN_CLASS_ZBA: > return "zba"; > case INSN_CLASS_ZBB: > diff --git a/gas/testsuite/gas/riscv/zfa-zvfh.d b/gas/testsuite/gas/riscv/zfa-zvfh.d > new file mode 100644 > index 000000000000..8fbe06c40c0a > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zfa-zvfh.d > @@ -0,0 +1,16 @@ > +#as: -march=rv32iq_zfa_zvfh > +#objdump: -d > + > +.*:[ ]+file format .* > + > +Disassembly of section .text: > + > +0+000 : > +[ ]+[0-9a-f]+:[ ]+f41c00d3[ ]+fli\.h[ ]+ft1,0x1p\+3 > +[ ]+[0-9a-f]+:[ ]+f41c80d3[ ]+fli\.h[ ]+ft1,0x1p\+4 > +[ ]+[0-9a-f]+:[ ]+f41d00d3[ ]+fli\.h[ ]+ft1,0x1p\+7 > +[ ]+[0-9a-f]+:[ ]+f41d80d3[ ]+fli\.h[ ]+ft1,0x1p\+8 > +[ ]+[0-9a-f]+:[ ]+f41e00d3[ ]+fli\.h[ ]+ft1,0x1p\+15 > +[ ]+[0-9a-f]+:[ ]+f41e80d3[ ]+fli\.h[ ]+ft1,0x1p\+16 > +[ ]+[0-9a-f]+:[ ]+f41f00d3[ ]+fli\.h[ ]+ft1,inf > +[ ]+[0-9a-f]+:[ ]+f41f80d3[ ]+fli\.h[ ]+ft1,nan > diff --git a/gas/testsuite/gas/riscv/zfa-zvfh.s b/gas/testsuite/gas/riscv/zfa-zvfh.s > new file mode 100644 > index 000000000000..61c26e66f26f > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zfa-zvfh.s > @@ -0,0 +1,10 @@ > +target: > + # fli.h is available on (('Zfh' || 'Zvfh') && 'Zfa') > + fli.h ft1, 8.0 > + fli.h ft1, 0x1p4 > + fli.h ft1, 128.0 > + fli.h ft1, 0x1p8 > + fli.h ft1, 32768.0 > + fli.h ft1, 0x1p16 > + fli.h ft1, inf > + fli.h ft1, nan > diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h > index 808f36573030..3f2f7abd788f 100644 > --- a/include/opcode/riscv.h > +++ b/include/opcode/riscv.h > @@ -407,6 +407,7 @@ enum riscv_insn_class > INSN_CLASS_D_AND_ZFA, > INSN_CLASS_Q_AND_ZFA, > INSN_CLASS_ZFH_AND_ZFA, > + INSN_CLASS_ZFH_OR_ZVFH_AND_ZFA, > INSN_CLASS_ZBA, > INSN_CLASS_ZBB, > INSN_CLASS_ZBC, > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > index f9e5ded3a6e3..72d31456874e 100644 > --- a/opcodes/riscv-opc.c > +++ b/opcodes/riscv-opc.c > @@ -978,7 +978,7 @@ const struct riscv_opcode riscv_opcodes[] = > {"fli.s", 0, INSN_CLASS_ZFA, "D,Wfv", MATCH_FLI_S, MASK_FLI_S, match_opcode, 0 }, > {"fli.d", 0, INSN_CLASS_D_AND_ZFA, "D,Wfv", MATCH_FLI_D, MASK_FLI_D, match_opcode, 0 }, > {"fli.q", 0, INSN_CLASS_Q_AND_ZFA, "D,Wfv", MATCH_FLI_Q, MASK_FLI_Q, match_opcode, 0 }, > -{"fli.h", 0, INSN_CLASS_ZFH_AND_ZFA, "D,Wfv", MATCH_FLI_H, MASK_FLI_H, match_opcode, 0 }, > +{"fli.h", 0, INSN_CLASS_ZFH_OR_ZVFH_AND_ZFA, "D,Wfv", MATCH_FLI_H, MASK_FLI_H, match_opcode, 0 }, > {"fminm.s", 0, INSN_CLASS_ZFA, "D,S,T", MATCH_FMINM_S, MASK_FMINM_S, match_opcode, 0 }, > {"fmaxm.s", 0, INSN_CLASS_ZFA, "D,S,T", MATCH_FMAXM_S, MASK_FMAXM_S, match_opcode, 0 }, > {"fminm.d", 0, INSN_CLASS_D_AND_ZFA, "D,S,T", MATCH_FMINM_D, MASK_FMINM_D, match_opcode, 0 }, > > base-commit: 8c8224dc1637a3e695c17e4c1026247196813c48