diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index af7723f8ba5577156544166a392a3a94b26bcdb5..7ee168120e14abb025483e2e8c4bfd2384d85d34 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -20419,12 +20419,11 @@ do_vrint_1 (enum neon_cvt_mode mode) if (et.type == NT_invtype) return; - set_pred_insn_type (OUTSIDE_PRED_INSN); - NEON_ENCODE (FLOAT, inst); - - if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL) + if (check_simd_pred_availability (1, NEON_CHECK_CC | NEON_CHECK_ARCH8)) return; + NEON_ENCODE (FLOAT, inst); + inst.instruction |= LOW4 (inst.operands[0].reg) << 12; inst.instruction |= HI1 (inst.operands[0].reg) << 22; inst.instruction |= LOW4 (inst.operands[1].reg); @@ -23559,12 +23558,12 @@ static const struct asm_opcode insns[] = nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel), nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel), nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr), - nCE(vrintz, _vrintr, 2, (RNSDQ, oRNSDQ), vrintz), - nCE(vrintx, _vrintr, 2, (RNSDQ, oRNSDQ), vrintx), - nUF(vrinta, _vrinta, 2, (RNSDQ, oRNSDQ), vrinta), - nUF(vrintn, _vrinta, 2, (RNSDQ, oRNSDQ), vrintn), - nUF(vrintp, _vrinta, 2, (RNSDQ, oRNSDQ), vrintp), - nUF(vrintm, _vrinta, 2, (RNSDQ, oRNSDQ), vrintm), + mnCE(vrintz, _vrintr, 2, (RNSDQMQ, oRNSDQMQ), vrintz), + mnCE(vrintx, _vrintr, 2, (RNSDQMQ, oRNSDQMQ), vrintx), + mnUF(vrinta, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrinta), + mnUF(vrintn, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrintn), + mnUF(vrintp, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrintp), + mnUF(vrintm, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrintm), /* Crypto v1 extensions. */ #undef ARM_VARIANT diff --git a/gas/testsuite/gas/arm/mve-vrint-bad.d b/gas/testsuite/gas/arm/mve-vrint-bad.d new file mode 100644 index 0000000000000000000000000000000000000000..081a00880eb27107f9435ee0a41d2cae7e3f5953 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vrint-bad.d @@ -0,0 +1,5 @@ +#name: bad MVE VRINT instructions +#as: -march=armv8.1-m.main+mve.fp +#error_output: mve-vrint-bad.l + +.*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/mve-vrint-bad.l b/gas/testsuite/gas/arm/mve-vrint-bad.l new file mode 100644 index 0000000000000000000000000000000000000000..1d68a82badabae2a56559f476b356fdec9713c48 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vrint-bad.l @@ -0,0 +1,80 @@ +[^:]*: Assembler messages: +[^:]*:13: Error: bad type in SIMD instruction -- `vrintn.i16 q0,q1' +[^:]*:13: Error: bad type in SIMD instruction -- `vrintn.f64 q0,q1' +[^:]*:13: Error: bad type in SIMD instruction -- `vrintx.i16 q0,q1' +[^:]*:13: Error: bad type in SIMD instruction -- `vrintx.f64 q0,q1' +[^:]*:13: Error: bad type in SIMD instruction -- `vrinta.i16 q0,q1' +[^:]*:13: Error: bad type in SIMD instruction -- `vrinta.f64 q0,q1' +[^:]*:13: Error: bad type in SIMD instruction -- `vrintz.i16 q0,q1' +[^:]*:13: Error: bad type in SIMD instruction -- `vrintz.f64 q0,q1' +[^:]*:13: Error: bad type in SIMD instruction -- `vrintm.i16 q0,q1' +[^:]*:13: Error: bad type in SIMD instruction -- `vrintm.f64 q0,q1' +[^:]*:13: Error: bad type in SIMD instruction -- `vrintp.i16 q0,q1' +[^:]*:13: Error: bad type in SIMD instruction -- `vrintp.f64 q0,q1' +[^:]*:14: Error: invalid rounding mode -- `vrintr.f16 q0,q1' +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Error: syntax error -- `vrintneq.f16 q0,q1' +[^:]*:25: Error: syntax error -- `vrintneq.f16 q0,q1' +[^:]*:25: Error: syntax error -- `vrintneq.f16 q0,q1' +[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vrintnt.f16 q0,q1' +[^:]*:25: Error: instruction missing MVE vector predication code -- `vrintn.f16 q0,q1' +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Error: syntax error -- `vrintxeq.f16 q0,q1' +[^:]*:25: Error: syntax error -- `vrintxeq.f16 q0,q1' +[^:]*:25: Error: syntax error -- `vrintxeq.f16 q0,q1' +[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vrintxt.f16 q0,q1' +[^:]*:25: Error: instruction missing MVE vector predication code -- `vrintx.f16 q0,q1' +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Error: syntax error -- `vrintaeq.f16 q0,q1' +[^:]*:25: Error: syntax error -- `vrintaeq.f16 q0,q1' +[^:]*:25: Error: syntax error -- `vrintaeq.f16 q0,q1' +[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vrintat.f16 q0,q1' +[^:]*:25: Error: instruction missing MVE vector predication code -- `vrinta.f16 q0,q1' +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Error: syntax error -- `vrintzeq.f16 q0,q1' +[^:]*:25: Error: syntax error -- `vrintzeq.f16 q0,q1' +[^:]*:25: Error: syntax error -- `vrintzeq.f16 q0,q1' +[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vrintzt.f16 q0,q1' +[^:]*:25: Error: instruction missing MVE vector predication code -- `vrintz.f16 q0,q1' +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Error: syntax error -- `vrintmeq.f16 q0,q1' +[^:]*:25: Error: syntax error -- `vrintmeq.f16 q0,q1' +[^:]*:25: Error: syntax error -- `vrintmeq.f16 q0,q1' +[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vrintmt.f16 q0,q1' +[^:]*:25: Error: instruction missing MVE vector predication code -- `vrintm.f16 q0,q1' +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Error: syntax error -- `vrintpeq.f16 q0,q1' +[^:]*:25: Error: syntax error -- `vrintpeq.f16 q0,q1' +[^:]*:25: Error: syntax error -- `vrintpeq.f16 q0,q1' +[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vrintpt.f16 q0,q1' +[^:]*:25: Error: instruction missing MVE vector predication code -- `vrintp.f16 q0,q1' diff --git a/gas/testsuite/gas/arm/mve-vrint-bad.s b/gas/testsuite/gas/arm/mve-vrint-bad.s new file mode 100644 index 0000000000000000000000000000000000000000..7e9a531a2b1f3374bd3dfe41370d4ea43f5b2038 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vrint-bad.s @@ -0,0 +1,25 @@ +.macro cond, mode +.irp cond, eq, ne, gt, ge, lt, le +it \cond +vrint\mode\().f16 q0, q1 +.endr +.endm + +.syntax unified +.thumb +.irp mode, n, x, a, z, m, p +vrint\mode\().i16 q0, q1 +vrint\mode\().f64 q0, q1 +.endr +vrintr.f16 q0, q1 +.irp mode, n, x, a, z, m, p +cond \mode +it eq +vrint\mode\()eq.f16 q0, q1 +vrint\mode\()eq.f16 q0, q1 +vpst +vrint\mode\()eq.f16 q0, q1 +vrint\mode\()t.f16 q0, q1 +vpst +vrint\mode\().f16 q0, q1 +.endr