From: Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com>
To: Andrew Burgess <andrew.burgess@embecosm.com>,
"binutils@sourceware.org" <binutils@sourceware.org>
Cc: "Cupertino.Miranda@synopsys.com" <Cupertino.Miranda@synopsys.com>,
"noamca@mellanox.com" <noamca@mellanox.com>
Subject: RE: [PATCH 1/3] opcodes/arc: Compute insn lengths in disassembler
Date: Tue, 12 Apr 2016 09:27:00 -0000 [thread overview]
Message-ID: <098ECE41A0A6114BB2A07F1EC238DE896617DE83@DE02WEMBXB.internal.synopsys.com> (raw)
In-Reply-To: <1460027127-1121-2-git-send-email-andrew.burgess@embecosm.com>
Hi Andrew,
> The table is self-checking while being built, it only contains the
> instructions for the current architecture being disassembled, and if
> different instructions with the same major opcode have different
> lengths, this will cause an error while the table is being filled.
I still have some questions regarding your newly proposed way of decoding the instructions. What bothers me is the fact you relay on the existing encodings, but what is happening when we have extension instructions. For ARCompact the extension instructions may start from major 0x05 and end somewhere at 0x0B, For ARCv2 the extension instructions start from 0x05 and ends at 0x07. The official docs are stipulating those ones are 32-bit. Though, I've seen custom instructions defined as short instructions(16-bit). How your proposed patch is addressing the extension instructions (let us not take into account the short ones)?
As far as I can see, we can actually say that all major larger than 0x0B for ARCompact are 16-bit, and all major larger than 0x07 for ARCv2 are 16-bit. Though some sanity testing needs to be done.
Name conventions:
MAJOR Notes
0x04 ARC 32-bit basecase instructions;
0x05 - 0x06 ARC 32-bit extension instructions;
0x07 User 32-bit extension instructions;
0x08 ARCompact: User 32-bit extension instructions; ARCv2: 16-bit instructions
0x09 ARCompact: Market-specific extension instructions; ARCv2: 16-bit instructions
0x0A ARCompact: Market-specific extension instructions; ARCv2: 16-bit instructions
0x0B ARCompact: Market-specific extension instructions; ARCv2: 16-bit instructions
Thanks,
Claudiu
next prev parent reply other threads:[~2016-04-12 9:27 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-12 11:00 [PATCHv2 0/3] ARC: Add another group of nps instructions Andrew Burgess
2016-04-07 11:05 ` [PATCH " Andrew Burgess
2016-04-07 11:05 ` [PATCH 1/3] opcodes/arc: Compute insn lengths in disassembler Andrew Burgess
2016-04-07 11:27 ` Claudiu Zissulescu
2016-04-12 9:27 ` Claudiu Zissulescu [this message]
2016-04-07 11:05 ` [PATCH 2/3] bfd/arc: Rename enum entries to avoid conflicts Andrew Burgess
2016-04-07 11:20 ` Claudiu Zissulescu
2016-04-07 11:05 ` [PATCH 3/3] arc/nps400 : New cmem instructions and associated relocation Andrew Burgess
2016-04-11 12:55 ` Cupertino Miranda
2016-04-12 11:00 ` [PATCHv2 2/3] bfd/arc: Rename enum entries to avoid conflicts Andrew Burgess
2016-04-13 13:34 ` Nick Clifton
2016-04-12 11:00 ` [PATCHv2 1/3] opcodes/arc: Move instruction length logic to new function Andrew Burgess
2016-04-12 12:27 ` Claudiu Zissulescu
2016-04-13 13:32 ` Nick Clifton
2016-04-13 14:41 ` Andrew Burgess
2016-04-13 15:30 ` Nick Clifton
2016-04-14 12:40 ` Andrew Burgess
2016-04-14 14:45 ` Nick Clifton
2016-04-12 11:00 ` [PATCHv2 3/3] arc/nps400 : New cmem instructions and associated relocation Andrew Burgess
2016-04-13 13:37 ` Nick Clifton
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