From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 102252 invoked by alias); 9 Mar 2015 14:28:17 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 102236 invoked by uid 89); 9 Mar 2015 14:28:16 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.6 required=5.0 tests=AWL,BAYES_00,SPF_PASS,T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: mailapp01.imgtec.com Received: from mailapp01.imgtec.com (HELO mailapp01.imgtec.com) (195.59.15.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 09 Mar 2015 14:27:59 +0000 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id 3BEBBBD63BA07; Mon, 9 Mar 2015 14:27:54 +0000 (GMT) Received: from LEMAIL01.le.imgtec.org (192.168.152.62) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Mon, 9 Mar 2015 14:27:56 +0000 Received: from LEMAIL01.le.imgtec.org ([fe80::5ae:ee16:f4b9:cda9]) by LEMAIL01.le.imgtec.org ([fe80::5ae:ee16:f4b9:cda9%17]) with mapi id 14.03.0210.002; Mon, 9 Mar 2015 14:27:56 +0000 From: Andrew Bennett To: "binutils@sourceware.org" CC: "rdsandiford@googlemail.com" Subject: [PATCH] MIPS: Fix constraint issues with the R6 beqc and bnec instructions Date: Mon, 09 Mar 2015 14:28:00 -0000 Message-ID: <0DA23CC379F5F945ACB41CF394B9827720F81BA1@LEMAIL01.le.imgtec.org> Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-IsSubscribed: yes X-SW-Source: 2015-03/txt/msg00068.txt.bz2 Hi, The encoding for the MIPS R6 beqc and bnec instructions firstly requires=20 that the register number in the rs field is less than the rt field; and secondly the rs and rt fields do not contain the zero register. However, the current mips operands for these instructions do not follow these constr= aints.=20=20 The -u operand allows the zero register; and the -y operand allows the rs and rt registers to be the same. The following patch and ChangeLog upda= tes=20 these constraints so that they are correct. Ok to commit? Many thanks, Andrew opcodes/ * mips-opc.c (decode_mips_operand): Fix constraint issues with -u and -y operands. diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 0472b5b..07b3d04 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -48,11 +48,11 @@ decode_mips_operand (const char *p) case 'd': SPECIAL (0, 0, REPEAT_DEST_REG); case 's': SPECIAL (5, 21, NON_ZERO_REG); case 't': SPECIAL (5, 16, NON_ZERO_REG); - case 'u': PREV_CHECK (5, 16, TRUE, FALSE, FALSE, TRUE); + case 'u': PREV_CHECK (5, 16, TRUE, FALSE, FALSE, FALSE); case 'v': PREV_CHECK (5, 16, TRUE, TRUE, FALSE, FALSE); case 'w': PREV_CHECK (5, 16, FALSE, TRUE, TRUE, TRUE); case 'x': PREV_CHECK (5, 21, TRUE, FALSE, FALSE, TRUE); - case 'y': PREV_CHECK (5, 21, FALSE, TRUE, TRUE, FALSE); + case 'y': PREV_CHECK (5, 21, FALSE, TRUE, FALSE, FALSE); case 'A': PCREL (19, 0, TRUE, 2, 2, FALSE, FALSE); case 'B': PCREL (18, 0, TRUE, 3, 3, FALSE, FALSE); }