* [PATCH 2/5] Remove some custom sections from RISC-V's default linker scripts
2017-01-02 2:26 [PATCH] Various RISC-V Fixes Palmer Dabbelt
` (2 preceding siblings ...)
2017-01-02 2:26 ` [PATCH 1/5] Add support for the RISC-V Q extension Palmer Dabbelt
@ 2017-01-02 2:26 ` Palmer Dabbelt
2017-01-04 10:27 ` Nick Clifton
2017-01-02 2:26 ` [PATCH 4/5] RISC-V/GAS: Improve handling of invalid relocs Palmer Dabbelt
4 siblings, 1 reply; 16+ messages in thread
From: Palmer Dabbelt @ 2017-01-02 2:26 UTC (permalink / raw)
To: binutils; +Cc: Andrew Waterman, amorda, Palmer Dabbelt
This was added so compressed loads could have smaller offsets for
accessing the data section, but the result was that writable sections
ended up in INITIAL_READONLY_SECTIONS. This is a bad idea. The fix is
to just remove this micro-optimization.
Thanks to Alan Morda for finding the problem!
ld/ChangeLog
2016-12-29 Palmer Dabbelt <palmer@dabbelt.com>
Kito Cheng <kito.cheng@gmail.com>
* emulparams/elf32lriscv-defs.sh (INITIAL_READONLY_SECTIONS):
Removed.
(SDATA_START_SYMBOLS): Likewise.
---
ld/emulparams/elf32lriscv-defs.sh | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/ld/emulparams/elf32lriscv-defs.sh b/ld/emulparams/elf32lriscv-defs.sh
index 0e4b723..0eba0d1 100644
--- a/ld/emulparams/elf32lriscv-defs.sh
+++ b/ld/emulparams/elf32lriscv-defs.sh
@@ -26,17 +26,5 @@ COMMONPAGESIZE="CONSTANT (COMMONPAGESIZE)"
SDATA_START_SYMBOLS="_gp = . + 0x800;
*(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*)"
-# Place the data section before text section. This enables more compact
-# global variable access for RVC code via linker relaxation.
-INITIAL_READONLY_SECTIONS="
- .data : { *(.data) *(.data.*) *(.gnu.linkonce.d.*) }
- .rodata : { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r.*) }
- .srodata : { ${SDATA_START_SYMBOLS} }
- .sdata : { *(.sdata .sdata.* .gnu.linkonce.s.*) }
- .sbss : { *(.dynsbss) *(.sbss .sbss.* .gnu.linkonce.sb.*) }
- .bss : { *(.dynbss) *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) }
- . = ALIGN(${SEGMENT_SIZE}) + (. & (${MAXPAGESIZE} - 1));"
INITIAL_READONLY_SECTIONS=".interp : { *(.interp) } ${CREATE_PIE-${INITIAL_READONLY_SECTIONS}}"
INITIAL_READONLY_SECTIONS="${RELOCATING+${CREATE_SHLIB-${INITIAL_READONLY_SECTIONS}}}"
-
-SDATA_START_SYMBOLS="${CREATE_PIE+${SDATA_START_SYMBOLS}}"
--
2.10.2
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 5/5] RISC-V/GAS: Support more relocs against constant addresses
2017-01-02 2:26 [PATCH] Various RISC-V Fixes Palmer Dabbelt
@ 2017-01-02 2:26 ` Palmer Dabbelt
2017-01-04 10:36 ` Nick Clifton
2017-01-02 2:26 ` [PATCH 3/5] RISC-V/GAS: Correct branch relaxation for weak symbols Palmer Dabbelt
` (3 subsequent siblings)
4 siblings, 1 reply; 16+ messages in thread
From: Palmer Dabbelt @ 2017-01-02 2:26 UTC (permalink / raw)
To: binutils; +Cc: Andrew Waterman, amorda
From: Andrew Waterman <andrew@sifive.com>
Previously, some pseudoinstructions like "call" only accepted
symbolic addresses and rejected constant addresses with an
esoteric internal error. This patch enables them by deferring
application of constant relocations to md_apply_fix, rather than
eagerly applying them during instruction assembly.
gas/ChangeLog
2016-12-21 Andrew Waterman <andrew@sifive.com>
* config/tc-riscv.c (append_insn): Don't eagerly apply relocations
against constants.
(md_apply_fix): Mark relocations against constants as "done."
---
gas/config/tc-riscv.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 03c84e8..139fae7 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -688,9 +688,6 @@ append_insn (struct riscv_cl_insn *ip, expressionS *address_expr,
address_expr->X_add_number);
return;
}
- else if (address_expr->X_op == O_constant)
- ip->insn_opcode |= riscv_apply_const_reloc (reloc_type,
- address_expr->X_add_number);
else
{
howto = bfd_reloc_type_lookup (stdoutput, reloc_type);
@@ -1861,6 +1858,8 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
case BFD_RELOC_RISCV_LO12_S:
bfd_putl32 (riscv_apply_const_reloc (fixP->fx_r_type, *valP)
| bfd_getl32 (buf), buf);
+ if (fixP->fx_addsy == NULL)
+ fixP->fx_done = TRUE;
relaxable = TRUE;
break;
--
2.10.2
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 3/5] RISC-V/GAS: Correct branch relaxation for weak symbols
2017-01-02 2:26 [PATCH] Various RISC-V Fixes Palmer Dabbelt
2017-01-02 2:26 ` [PATCH 5/5] RISC-V/GAS: Support more relocs against constant addresses Palmer Dabbelt
@ 2017-01-02 2:26 ` Palmer Dabbelt
2017-01-04 10:28 ` Nick Clifton
2017-01-02 2:26 ` [PATCH 1/5] Add support for the RISC-V Q extension Palmer Dabbelt
` (2 subsequent siblings)
4 siblings, 1 reply; 16+ messages in thread
From: Palmer Dabbelt @ 2017-01-02 2:26 UTC (permalink / raw)
To: binutils; +Cc: Andrew Waterman, amorda
From: Andrew Waterman <andrew@sifive.com>
Do not shorten branches to weak symbols, since they can be preempted at
link time.
gas/ChangeLog
2016-12-21 Andrew Waterman <andrew@sifive.com>
* config/tc-riscv.c (relaxed_branch_length): Use the long
sequence when the target is a weak symbol.
---
gas/config/tc-riscv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 38dcd04..03db275 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -360,6 +360,7 @@ relaxed_branch_length (fragS *fragp, asection *sec, int update)
if (fragp->fr_symbol != NULL
&& S_IS_DEFINED (fragp->fr_symbol)
+ && !S_IS_WEAK (fragp->fr_symbol)
&& sec == S_GET_SEGMENT (fragp->fr_symbol))
{
offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
--
2.10.2
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/5] Add support for the RISC-V Q extension
2017-01-02 2:26 [PATCH] Various RISC-V Fixes Palmer Dabbelt
2017-01-02 2:26 ` [PATCH 5/5] RISC-V/GAS: Support more relocs against constant addresses Palmer Dabbelt
2017-01-02 2:26 ` [PATCH 3/5] RISC-V/GAS: Correct branch relaxation for weak symbols Palmer Dabbelt
@ 2017-01-02 2:26 ` Palmer Dabbelt
2017-01-03 17:46 ` Nick Clifton
2017-01-02 2:26 ` [PATCH 2/5] Remove some custom sections from RISC-V's default linker scripts Palmer Dabbelt
2017-01-02 2:26 ` [PATCH 4/5] RISC-V/GAS: Improve handling of invalid relocs Palmer Dabbelt
4 siblings, 1 reply; 16+ messages in thread
From: Palmer Dabbelt @ 2017-01-02 2:26 UTC (permalink / raw)
To: binutils; +Cc: Andrew Waterman, amorda, Kito Cheng
From: Kito Cheng <kito.cheng@gmail.com>
The RISC-V ISA manual defines a Q instruction set extension that enables
hardware support for quad precision IEEE floating point. This patch
enables support for the Q extension: it declares the Q instruction
encoding macros, adds support for the various Q instructions to the
encoding table, whitelists "q" as an ISA extension, and sets
FLOAT_ABI_QUAD when the Q extension is enabled.
gas/ChangeLog
2016-12-21 Kito Cheng <kito.cheng@gmail.com>
* config/tc-riscv.c (riscv_set_arch): Whitelist the "q" ISA
extension.
(riscv_after_parse_args): Set FLOAT_ABI_QUAD when the Q ISA is
enabled and no other ABI is specified.
include/ChangeLog
2016-12-21 Kito Cheng <kito.cheng@gmail.com>
* opcode/riscv-opc.h: Add support for the "q" ISA extension.
opcodes/ChangeLog
2016-12-21 Kito Cheng <kito.cheng@gmail.com>
* riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
extension.
* riscv-opcodes/all-opcodes: Likewise.
---
gas/config/tc-riscv.c | 14 ++++++-
include/opcode/riscv-opc.h | 102 +++++++++++++++++++++++++++++++++++++++++++++
include/opcode/riscv.h | 2 +
opcodes/riscv-opc.c | 60 ++++++++++++++++++++++++++
4 files changed, 176 insertions(+), 2 deletions(-)
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 8c732f0..38dcd04 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -197,6 +197,12 @@ riscv_set_arch (const char *s)
all_subsets++;
p++;
}
+ else if (*p == 'q')
+ {
+ const char subset[] = {*p, 0};
+ riscv_add_subset (subset);
+ p++;
+ }
else
as_fatal ("-march=%s: unsupported ISA subset `%c'", s, *p);
}
@@ -1817,8 +1823,12 @@ riscv_after_parse_args (void)
float_abi = FLOAT_ABI_SOFT;
for (subset = riscv_subsets; subset != NULL; subset = subset->next)
- if (strcasecmp (subset->name, "D") == 0)
- float_abi = FLOAT_ABI_DOUBLE;
+ {
+ if (strcasecmp (subset->name, "D") == 0)
+ float_abi = FLOAT_ABI_DOUBLE;
+ if (strcasecmp (subset->name, "Q") == 0)
+ float_abi = FLOAT_ABI_QUAD;
+ }
}
/* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index d10c7f8..09d680b 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -285,6 +285,34 @@
#define MASK_FCVT_D_S 0xfff0007f
#define MATCH_FSQRT_D 0x5a000053
#define MASK_FSQRT_D 0xfff0007f
+#define MATCH_FADD_Q 0x6000053
+#define MASK_FADD_Q 0xfe00007f
+#define MATCH_FSUB_Q 0xe000053
+#define MASK_FSUB_Q 0xfe00007f
+#define MATCH_FMUL_Q 0x16000053
+#define MASK_FMUL_Q 0xfe00007f
+#define MATCH_FDIV_Q 0x1e000053
+#define MASK_FDIV_Q 0xfe00007f
+#define MATCH_FSGNJ_Q 0x26000053
+#define MASK_FSGNJ_Q 0xfe00707f
+#define MATCH_FSGNJN_Q 0x26001053
+#define MASK_FSGNJN_Q 0xfe00707f
+#define MATCH_FSGNJX_Q 0x26002053
+#define MASK_FSGNJX_Q 0xfe00707f
+#define MATCH_FMIN_Q 0x2e000053
+#define MASK_FMIN_Q 0xfe00707f
+#define MATCH_FMAX_Q 0x2e001053
+#define MASK_FMAX_Q 0xfe00707f
+#define MATCH_FCVT_S_Q 0x40300053
+#define MASK_FCVT_S_Q 0xfff0007f
+#define MATCH_FCVT_Q_S 0x46000053
+#define MASK_FCVT_Q_S 0xfff0007f
+#define MATCH_FCVT_D_Q 0x42300053
+#define MASK_FCVT_D_Q 0xfff0007f
+#define MATCH_FCVT_Q_D 0x46100053
+#define MASK_FCVT_Q_D 0xfff0007f
+#define MATCH_FSQRT_Q 0x5e000053
+#define MASK_FSQRT_Q 0xfff0007f
#define MATCH_FLE_S 0xa0000053
#define MASK_FLE_S 0xfe00707f
#define MATCH_FLT_S 0xa0001053
@@ -297,6 +325,12 @@
#define MASK_FLT_D 0xfe00707f
#define MATCH_FEQ_D 0xa2002053
#define MASK_FEQ_D 0xfe00707f
+#define MATCH_FLE_Q 0xa6000053
+#define MASK_FLE_Q 0xfe00707f
+#define MATCH_FLT_Q 0xa6001053
+#define MASK_FLT_Q 0xfe00707f
+#define MATCH_FEQ_Q 0xa6002053
+#define MASK_FEQ_Q 0xfe00707f
#define MATCH_FCVT_W_S 0xc0000053
#define MASK_FCVT_W_S 0xfff0007f
#define MATCH_FCVT_WU_S 0xc0100053
@@ -321,6 +355,18 @@
#define MASK_FMV_X_D 0xfff0707f
#define MATCH_FCLASS_D 0xe2001053
#define MASK_FCLASS_D 0xfff0707f
+#define MATCH_FCVT_W_Q 0xc6000053
+#define MASK_FCVT_W_Q 0xfff0007f
+#define MATCH_FCVT_WU_Q 0xc6100053
+#define MASK_FCVT_WU_Q 0xfff0007f
+#define MATCH_FCVT_L_Q 0xc6200053
+#define MASK_FCVT_L_Q 0xfff0007f
+#define MATCH_FCVT_LU_Q 0xc6300053
+#define MASK_FCVT_LU_Q 0xfff0007f
+#define MATCH_FMV_X_Q 0xe6000053
+#define MASK_FMV_X_Q 0xfff0707f
+#define MATCH_FCLASS_Q 0xe6001053
+#define MASK_FCLASS_Q 0xfff0707f
#define MATCH_FCVT_S_W 0xd0000053
#define MASK_FCVT_S_W 0xfff0007f
#define MATCH_FCVT_S_WU 0xd0100053
@@ -341,14 +387,28 @@
#define MASK_FCVT_D_LU 0xfff0007f
#define MATCH_FMV_D_X 0xf2000053
#define MASK_FMV_D_X 0xfff0707f
+#define MATCH_FCVT_Q_W 0xd6000053
+#define MASK_FCVT_Q_W 0xfff0007f
+#define MATCH_FCVT_Q_WU 0xd6100053
+#define MASK_FCVT_Q_WU 0xfff0007f
+#define MATCH_FCVT_Q_L 0xd6200053
+#define MASK_FCVT_Q_L 0xfff0007f
+#define MATCH_FCVT_Q_LU 0xd6300053
+#define MASK_FCVT_Q_LU 0xfff0007f
+#define MATCH_FMV_Q_X 0xf6000053
+#define MASK_FMV_Q_X 0xfff0707f
#define MATCH_FLW 0x2007
#define MASK_FLW 0x707f
#define MATCH_FLD 0x3007
#define MASK_FLD 0x707f
+#define MATCH_FLQ 0x4007
+#define MASK_FLQ 0x707f
#define MATCH_FSW 0x2027
#define MASK_FSW 0x707f
#define MATCH_FSD 0x3027
#define MASK_FSD 0x707f
+#define MATCH_FSQ 0x4027
+#define MASK_FSQ 0x707f
#define MATCH_FMADD_S 0x43
#define MASK_FMADD_S 0x600007f
#define MATCH_FMSUB_S 0x47
@@ -365,6 +425,14 @@
#define MASK_FNMSUB_D 0x600007f
#define MATCH_FNMADD_D 0x200004f
#define MASK_FNMADD_D 0x600007f
+#define MATCH_FMADD_Q 0x6000043
+#define MASK_FMADD_Q 0x600007f
+#define MATCH_FMSUB_Q 0x6000047
+#define MASK_FMSUB_Q 0x600007f
+#define MATCH_FNMSUB_Q 0x600004b
+#define MASK_FNMSUB_Q 0x600007f
+#define MATCH_FNMADD_Q 0x600004f
+#define MASK_FNMADD_Q 0x600007f
#define MATCH_C_ADDI4SPN 0x0
#define MASK_C_ADDI4SPN 0xe003
#define MATCH_C_FLD 0x2000
@@ -844,12 +912,29 @@ DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
+DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q)
+DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q)
+DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q)
+DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q)
+DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q)
+DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q)
+DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q)
+DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q)
+DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q)
+DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q)
+DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S)
+DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q)
+DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D)
+DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q)
DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
+DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q)
+DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q)
+DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q)
DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
@@ -862,6 +947,12 @@ DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
+DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q)
+DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q)
+DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q)
+DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q)
+DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q)
+DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q)
DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
@@ -872,10 +963,17 @@ DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
+DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W)
+DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU)
+DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L)
+DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU)
+DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X)
DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
+DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ)
DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
+DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ)
DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
@@ -884,6 +982,10 @@ DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
+DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q)
+DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q)
+DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q)
+DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q)
DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 8845c06..115d946 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -323,8 +323,10 @@ enum
M_SD,
M_FLW,
M_FLD,
+ M_FLQ,
M_FSW,
M_FSD,
+ M_FSQ,
M_CALL,
M_J,
M_LI,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 464078d..c1b42ed 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -547,6 +547,66 @@ const struct riscv_opcode riscv_opcodes[] =
{"fcvt.d.lu", "64D", "D,s", MATCH_FCVT_D_LU | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, 0 },
{"fcvt.d.lu", "64D", "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 },
+/* Quad-precision floating-point instruction subset */
+{"flq", "Q", "D,o(s)", MATCH_FLQ, MASK_FLQ, match_opcode, 0 },
+{"flq", "Q", "D,A,s", 0, (int) M_FLQ, match_never, INSN_MACRO },
+{"fsq", "Q", "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, 0 },
+{"fsq", "Q", "T,A,s", 0, (int) M_FSQ, match_never, INSN_MACRO },
+{"fmv.q", "Q", "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS },
+{"fneg.q", "Q", "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS },
+{"fabs.q", "Q", "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS },
+{"fsgnj.q", "Q", "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 },
+{"fsgnjn.q", "Q", "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 },
+{"fsgnjx.q", "Q", "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 },
+{"fadd.q", "Q", "D,S,T", MATCH_FADD_Q | MASK_RM, MASK_FADD_Q | MASK_RM, match_opcode, 0 },
+{"fadd.q", "Q", "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 },
+{"fsub.q", "Q", "D,S,T", MATCH_FSUB_Q | MASK_RM, MASK_FSUB_Q | MASK_RM, match_opcode, 0 },
+{"fsub.q", "Q", "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 },
+{"fmul.q", "Q", "D,S,T", MATCH_FMUL_Q | MASK_RM, MASK_FMUL_Q | MASK_RM, match_opcode, 0 },
+{"fmul.q", "Q", "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 },
+{"fdiv.q", "Q", "D,S,T", MATCH_FDIV_Q | MASK_RM, MASK_FDIV_Q | MASK_RM, match_opcode, 0 },
+{"fdiv.q", "Q", "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 },
+{"fsqrt.q", "Q", "D,S", MATCH_FSQRT_Q | MASK_RM, MASK_FSQRT_Q | MASK_RM, match_opcode, 0 },
+{"fsqrt.q", "Q", "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 },
+{"fmin.q", "Q", "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 },
+{"fmax.q", "Q", "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 },
+{"fmadd.q", "Q", "D,S,T,R", MATCH_FMADD_Q | MASK_RM, MASK_FMADD_Q | MASK_RM, match_opcode, 0 },
+{"fmadd.q", "Q", "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 },
+{"fnmadd.q", "Q", "D,S,T,R", MATCH_FNMADD_Q | MASK_RM, MASK_FNMADD_Q | MASK_RM, match_opcode, 0 },
+{"fnmadd.q", "Q", "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 },
+{"fmsub.q", "Q", "D,S,T,R", MATCH_FMSUB_Q | MASK_RM, MASK_FMSUB_Q | MASK_RM, match_opcode, 0 },
+{"fmsub.q", "Q", "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 },
+{"fnmsub.q", "Q", "D,S,T,R", MATCH_FNMSUB_Q | MASK_RM, MASK_FNMSUB_Q | MASK_RM, match_opcode, 0 },
+{"fnmsub.q", "Q", "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 },
+{"fcvt.w.q", "Q", "d,S", MATCH_FCVT_W_Q | MASK_RM, MASK_FCVT_W_Q | MASK_RM, match_opcode, 0 },
+{"fcvt.w.q", "Q", "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 },
+{"fcvt.wu.q", "Q", "d,S", MATCH_FCVT_WU_Q | MASK_RM, MASK_FCVT_WU_Q | MASK_RM, match_opcode, 0 },
+{"fcvt.wu.q", "Q", "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 },
+{"fcvt.q.w", "Q", "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W | MASK_RM, match_opcode, 0 },
+{"fcvt.q.wu", "Q", "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU | MASK_RM, match_opcode, 0 },
+{"fcvt.q.s", "Q", "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S | MASK_RM, match_opcode, 0 },
+{"fcvt.q.d", "Q", "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D | MASK_RM, match_opcode, 0 },
+{"fcvt.s.q", "Q", "D,S", MATCH_FCVT_S_Q | MASK_RM, MASK_FCVT_S_Q | MASK_RM, match_opcode, 0 },
+{"fcvt.s.q", "Q", "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 },
+{"fcvt.d.q", "Q", "D,S", MATCH_FCVT_D_Q | MASK_RM, MASK_FCVT_D_Q | MASK_RM, match_opcode, 0 },
+{"fcvt.d.q", "Q", "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 },
+{"fclass.q", "Q", "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 },
+{"feq.q", "Q", "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 },
+{"flt.q", "Q", "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
+{"fle.q", "Q", "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
+{"fgt.q", "Q", "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
+{"fge.q", "Q", "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
+{"fmv.x.q", "64Q", "d,S", MATCH_FMV_X_Q, MASK_FMV_X_Q, match_opcode, 0 },
+{"fmv.q.x", "64Q", "D,s", MATCH_FMV_Q_X, MASK_FMV_Q_X, match_opcode, 0 },
+{"fcvt.l.q", "64Q", "d,S", MATCH_FCVT_L_Q | MASK_RM, MASK_FCVT_L_Q | MASK_RM, match_opcode, 0 },
+{"fcvt.l.q", "64Q", "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 },
+{"fcvt.lu.q", "64Q", "d,S", MATCH_FCVT_LU_Q | MASK_RM, MASK_FCVT_LU_Q | MASK_RM, match_opcode, 0 },
+{"fcvt.lu.q", "64Q", "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 },
+{"fcvt.q.l", "64Q", "D,s", MATCH_FCVT_Q_L | MASK_RM, MASK_FCVT_Q_L | MASK_RM, match_opcode, 0 },
+{"fcvt.q.l", "64Q", "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 },
+{"fcvt.q.lu", "64Q", "D,s", MATCH_FCVT_Q_LU | MASK_RM, MASK_FCVT_Q_L | MASK_RM, match_opcode, 0 },
+{"fcvt.q.lu", "64Q", "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 },
+
/* Compressed instructions. */
{"c.ebreak", "C", "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, 0 },
{"c.jr", "C", "d", MATCH_C_JR, MASK_C_JR, match_rd_nonzero, 0 },
--
2.10.2
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH] Various RISC-V Fixes
@ 2017-01-02 2:26 Palmer Dabbelt
2017-01-02 2:26 ` [PATCH 5/5] RISC-V/GAS: Support more relocs against constant addresses Palmer Dabbelt
` (4 more replies)
0 siblings, 5 replies; 16+ messages in thread
From: Palmer Dabbelt @ 2017-01-02 2:26 UTC (permalink / raw)
To: binutils; +Cc: Andrew Waterman, amorda
This is actually a set of unrelated fixes to various parts of the RISC-V port,
each of which is described in their respective patch message. I'm submitting a
cover letter here because I think all of these should end up on both master and
the 2.28 branch and I'm not sure what the process is for doing that.
I've checked this patch set builds against both 61baf72 (master from this
morning) and 49af4dd (binutils-2_28 from this morning) and everything looks
good to me. Is there anything else I should do if I want things on a release
branch?
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 4/5] RISC-V/GAS: Improve handling of invalid relocs
2017-01-02 2:26 [PATCH] Various RISC-V Fixes Palmer Dabbelt
` (3 preceding siblings ...)
2017-01-02 2:26 ` [PATCH 2/5] Remove some custom sections from RISC-V's default linker scripts Palmer Dabbelt
@ 2017-01-02 2:26 ` Palmer Dabbelt
2017-01-04 10:33 ` Nick Clifton
4 siblings, 1 reply; 16+ messages in thread
From: Palmer Dabbelt @ 2017-01-02 2:26 UTC (permalink / raw)
To: binutils; +Cc: Andrew Waterman, amorda
From: Andrew Waterman <andrew@sifive.com>
TLS relocs against constants previously segfaulted, and illegal
symbol subtractions were silently ignored.
The previous behavior was to segfault.
gas/ChangeLog
2016-12-21 Andrew Waterman <andrew@sifive.com>
* config/tc-riscv.c (md_apply_fix): Report TLS relocations against
constants. Report disallowed symbol subtractions.
---
gas/config/tc-riscv.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 03db275..03c84e8 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1889,7 +1889,11 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
case BFD_RELOC_RISCV_TLS_GD_HI20:
case BFD_RELOC_RISCV_TLS_DTPREL32:
case BFD_RELOC_RISCV_TLS_DTPREL64:
- S_SET_THREAD_LOCAL (fixP->fx_addsy);
+ if (fixP->fx_addsy != NULL)
+ S_SET_THREAD_LOCAL (fixP->fx_addsy);
+ else
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("TLS relocation against a constant"));
break;
case BFD_RELOC_64:
@@ -2045,6 +2049,10 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
as_fatal (_("internal error: bad relocation #%d"), fixP->fx_r_type);
}
+ if (fixP->fx_subsy != NULL)
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("unsupported symbol subtraction"));
+
/* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
if (relaxable && fixP->fx_tcbit && fixP->fx_addsy != NULL)
{
--
2.10.2
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/5] Add support for the RISC-V Q extension
2017-01-02 2:26 ` [PATCH 1/5] Add support for the RISC-V Q extension Palmer Dabbelt
@ 2017-01-03 17:46 ` Nick Clifton
2017-01-03 18:55 ` Palmer Dabbelt
0 siblings, 1 reply; 16+ messages in thread
From: Nick Clifton @ 2017-01-03 17:46 UTC (permalink / raw)
To: Palmer Dabbelt, binutils, Kito Cheng, Tristan Gingold
Cc: Andrew Waterman, amorda
Hi Palmer, Hi Kito,
> gas/ChangeLog
>
> 2016-12-21 Kito Cheng <kito.cheng@gmail.com>
>
> * config/tc-riscv.c (riscv_set_arch): Whitelist the "q" ISA
> extension.
> (riscv_after_parse_args): Set FLOAT_ABI_QUAD when the Q ISA is
> enabled and no other ABI is specified.
>
> include/ChangeLog
>
> 2016-12-21 Kito Cheng <kito.cheng@gmail.com>
>
> * opcode/riscv-opc.h: Add support for the "q" ISA extension.
>
> opcodes/ChangeLog
>
> 2016-12-21 Kito Cheng <kito.cheng@gmail.com>
>
> * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
> extension.
> * riscv-opcodes/all-opcodes: Likewise.
Approved and applied to the mainline sources.
Unfortunately now that the 2.28 branch has been created you need approval
from the branch maintainer (Tristan Gringold, CC'ed) before the patch can
be checked in there.
Cheers
Nick
PS. Sorry for the delay in reviewing these patches. I know that you wanted
to get them in to the mainline sources before the 2.28 branch happened. You
just picked an unfortunate time of year when I was on holiday...
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/5] Add support for the RISC-V Q extension
2017-01-03 17:46 ` Nick Clifton
@ 2017-01-03 18:55 ` Palmer Dabbelt
2017-01-04 14:36 ` Nick Clifton
0 siblings, 1 reply; 16+ messages in thread
From: Palmer Dabbelt @ 2017-01-03 18:55 UTC (permalink / raw)
To: nickc; +Cc: binutils, kito.cheng, gingold, Andrew Waterman, amorda
On Tue, 03 Jan 2017 09:45:59 PST (-0800), nickc@redhat.com wrote:
> Hi Palmer, Hi Kito,
>
>> gas/ChangeLog
>>
>> 2016-12-21 Kito Cheng <kito.cheng@gmail.com>
>>
>> * config/tc-riscv.c (riscv_set_arch): Whitelist the "q" ISA
>> extension.
>> (riscv_after_parse_args): Set FLOAT_ABI_QUAD when the Q ISA is
>> enabled and no other ABI is specified.
>>
>> include/ChangeLog
>>
>> 2016-12-21 Kito Cheng <kito.cheng@gmail.com>
>>
>> * opcode/riscv-opc.h: Add support for the "q" ISA extension.
>>
>> opcodes/ChangeLog
>>
>> 2016-12-21 Kito Cheng <kito.cheng@gmail.com>
>>
>> * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
>> extension.
>> * riscv-opcodes/all-opcodes: Likewise.
>
> Approved and applied to the mainline sources.
Thanks! This was part of a patch set, does your statement apply to all 5
patches or just the first one?
> Unfortunately now that the 2.28 branch has been created you need approval
> from the branch maintainer (Tristan Gringold, CC'ed) before the patch can
> be checked in there.
OK, I'll do that in the future.
> Cheers
> Nick
>
> PS. Sorry for the delay in reviewing these patches. I know that you wanted
> to get them in to the mainline sources before the 2.28 branch happened. You
> just picked an unfortunate time of year when I was on holiday...
It's fine, these changes are all pretty self-contained so I don't mind
maintaining both branches (it was essentially zero work for these).
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/5] Remove some custom sections from RISC-V's default linker scripts
2017-01-02 2:26 ` [PATCH 2/5] Remove some custom sections from RISC-V's default linker scripts Palmer Dabbelt
@ 2017-01-04 10:27 ` Nick Clifton
0 siblings, 0 replies; 16+ messages in thread
From: Nick Clifton @ 2017-01-04 10:27 UTC (permalink / raw)
To: Palmer Dabbelt, binutils; +Cc: Andrew Waterman, amorda
Hi Peter,
> ld/ChangeLog
>
> 2016-12-29 Palmer Dabbelt <palmer@dabbelt.com>
> Kito Cheng <kito.cheng@gmail.com>
>
> * emulparams/elf32lriscv-defs.sh (INITIAL_READONLY_SECTIONS):
> Removed.
> (SDATA_START_SYMBOLS): Likewise.
Approved (for mainline) - please apply.
Cheers
Nick
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 3/5] RISC-V/GAS: Correct branch relaxation for weak symbols
2017-01-02 2:26 ` [PATCH 3/5] RISC-V/GAS: Correct branch relaxation for weak symbols Palmer Dabbelt
@ 2017-01-04 10:28 ` Nick Clifton
2017-01-06 19:15 ` Palmer Dabbelt
0 siblings, 1 reply; 16+ messages in thread
From: Nick Clifton @ 2017-01-04 10:28 UTC (permalink / raw)
To: Palmer Dabbelt, binutils; +Cc: Andrew Waterman, amorda
Hi Peter, Hi Andrew,
> gas/ChangeLog
>
> 2016-12-21 Andrew Waterman <andrew@sifive.com>
>
> * config/tc-riscv.c (relaxed_branch_length): Use the long
> sequence when the target is a weak symbol.
Approved (for mainline) - please apply.
Cheers
Nick
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 4/5] RISC-V/GAS: Improve handling of invalid relocs
2017-01-02 2:26 ` [PATCH 4/5] RISC-V/GAS: Improve handling of invalid relocs Palmer Dabbelt
@ 2017-01-04 10:33 ` Nick Clifton
0 siblings, 0 replies; 16+ messages in thread
From: Nick Clifton @ 2017-01-04 10:33 UTC (permalink / raw)
To: Palmer Dabbelt, binutils, Andrew Waterman; +Cc: amorda
Hi Palmer, Hi Andrew,
> 2016-12-21 Andrew Waterman <andrew@sifive.com>
>
> * config/tc-riscv.c (md_apply_fix): Report TLS relocations against
> constants. Report disallowed symbol subtractions.
Approved (for mainline) - please apply.
Cheers
Nick
> + as_bad_where (fixP->fx_file, fixP->fx_line,
> + _("TLS relocation against a constant"));
FYI - I think that it might be possible to trigger this error message when
something other than a constant is involved, eg an expression that is too
complex, or a register name is used instead of a symbol name. In such cases
the error message might be considered a little confusing. This is not a
big issue now, but more of a heads-up in case you get complaints from users.
Cheers
Nick
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 5/5] RISC-V/GAS: Support more relocs against constant addresses
2017-01-02 2:26 ` [PATCH 5/5] RISC-V/GAS: Support more relocs against constant addresses Palmer Dabbelt
@ 2017-01-04 10:36 ` Nick Clifton
0 siblings, 0 replies; 16+ messages in thread
From: Nick Clifton @ 2017-01-04 10:36 UTC (permalink / raw)
To: Palmer Dabbelt, binutils, Andrew Waterman; +Cc: amorda
Hi Palmer, Hi Andrew,
> 2016-12-21 Andrew Waterman <andrew@sifive.com>
>
> * config/tc-riscv.c (append_insn): Don't eagerly apply relocations
> against constants.
> (md_apply_fix): Mark relocations against constants as "done."
Approved (for mainline) - please apply.
Cheers
Nick
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/5] Add support for the RISC-V Q extension
2017-01-03 18:55 ` Palmer Dabbelt
@ 2017-01-04 14:36 ` Nick Clifton
0 siblings, 0 replies; 16+ messages in thread
From: Nick Clifton @ 2017-01-04 14:36 UTC (permalink / raw)
To: Palmer Dabbelt; +Cc: binutils, kito.cheng, gingold, Andrew Waterman, amorda
Hi Palmer,
>> Approved and applied to the mainline sources.
>
> Thanks! This was part of a patch set, does your statement apply to all 5
> patches or just the first one?
This approval just applies to this patch (ie patch 1 of 5).
Cheers
Nick
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 3/5] RISC-V/GAS: Correct branch relaxation for weak symbols
2017-01-04 10:28 ` Nick Clifton
@ 2017-01-06 19:15 ` Palmer Dabbelt
2017-01-09 9:25 ` Nick Clifton
0 siblings, 1 reply; 16+ messages in thread
From: Palmer Dabbelt @ 2017-01-06 19:15 UTC (permalink / raw)
To: nickc; +Cc: binutils, Andrew Waterman
On Wed, 04 Jan 2017 02:28:19 PST (-0800), nickc@redhat.com wrote:
> Hi Peter, Hi Andrew,
>
>> gas/ChangeLog
>>
>> 2016-12-21 Andrew Waterman <andrew@sifive.com>
>>
>> * config/tc-riscv.c (relaxed_branch_length): Use the long
>> sequence when the target is a weak symbol.
>
> Approved (for mainline) - please apply.
Sorry for the confusion, am I supposed to apply this patch? I don't see it on the binutils git master.
As far as I know I don't have write access to the binutils repository. Should
I fill out the form on sourceware.org to request access?
Thanks!
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 3/5] RISC-V/GAS: Correct branch relaxation for weak symbols
2017-01-06 19:15 ` Palmer Dabbelt
@ 2017-01-09 9:25 ` Nick Clifton
2017-01-09 14:22 ` Palmer Dabbelt
0 siblings, 1 reply; 16+ messages in thread
From: Nick Clifton @ 2017-01-09 9:25 UTC (permalink / raw)
To: Palmer Dabbelt; +Cc: binutils, Andrew Waterman
Hi Palmer,
>> Approved (for mainline) - please apply.
>
> Sorry for the confusion, am I supposed to apply this patch? I don't see it on the binutils git master.
That was my intention, yes. To avoid delays however I have gone ahead and checked the patch in.
> As far as I know I don't have write access to the binutils repository. Should
> I fill out the form on sourceware.org to request access?
I think that that would be a good idea. Please use this form:
https://sourceware.org/cgi-bin/pdw/ps_form.cgi
You can use my email address as the approver.
Cheers
Nick
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 3/5] RISC-V/GAS: Correct branch relaxation for weak symbols
2017-01-09 9:25 ` Nick Clifton
@ 2017-01-09 14:22 ` Palmer Dabbelt
0 siblings, 0 replies; 16+ messages in thread
From: Palmer Dabbelt @ 2017-01-09 14:22 UTC (permalink / raw)
To: nickc; +Cc: binutils, Andrew Waterman
On Mon, 09 Jan 2017 01:24:58 PST (-0800), nickc@redhat.com wrote:
> Hi Palmer,
>
>>> Approved (for mainline) - please apply.
>>
>> Sorry for the confusion, am I supposed to apply this patch? I don't see it on the binutils git master.
>
> That was my intention, yes. To avoid delays however I have gone ahead and checked the patch in.
Thanks!
>> As far as I know I don't have write access to the binutils repository. Should
>> I fill out the form on sourceware.org to request access?
>
> I think that that would be a good idea. Please use this form:
>
> https://sourceware.org/cgi-bin/pdw/ps_form.cgi
>
> You can use my email address as the approver.
I just submitted the form.
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2017-01-09 14:22 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-01-02 2:26 [PATCH] Various RISC-V Fixes Palmer Dabbelt
2017-01-02 2:26 ` [PATCH 5/5] RISC-V/GAS: Support more relocs against constant addresses Palmer Dabbelt
2017-01-04 10:36 ` Nick Clifton
2017-01-02 2:26 ` [PATCH 3/5] RISC-V/GAS: Correct branch relaxation for weak symbols Palmer Dabbelt
2017-01-04 10:28 ` Nick Clifton
2017-01-06 19:15 ` Palmer Dabbelt
2017-01-09 9:25 ` Nick Clifton
2017-01-09 14:22 ` Palmer Dabbelt
2017-01-02 2:26 ` [PATCH 1/5] Add support for the RISC-V Q extension Palmer Dabbelt
2017-01-03 17:46 ` Nick Clifton
2017-01-03 18:55 ` Palmer Dabbelt
2017-01-04 14:36 ` Nick Clifton
2017-01-02 2:26 ` [PATCH 2/5] Remove some custom sections from RISC-V's default linker scripts Palmer Dabbelt
2017-01-04 10:27 ` Nick Clifton
2017-01-02 2:26 ` [PATCH 4/5] RISC-V/GAS: Improve handling of invalid relocs Palmer Dabbelt
2017-01-04 10:33 ` Nick Clifton
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