From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 97F4E3858D3C for ; Wed, 5 Oct 2022 17:48:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 97F4E3858D3C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=foss.arm.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=foss.arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2E3E5106F; Wed, 5 Oct 2022 10:48:41 -0700 (PDT) Received: from [10.57.36.39] (unknown [10.57.36.39]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 75AE53F67D; Wed, 5 Oct 2022 10:48:33 -0700 (PDT) Message-ID: <0b9ce1b7-baf1-baf0-a465-cfd5a7fc6ed1@foss.arm.com> Date: Wed, 5 Oct 2022 18:48:32 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: Ping: [PATCH] Arm64: support CLEARBHB alias Content-Language: en-GB To: Jan Beulich , Richard Earnshaw , Marcus Shawcroft Cc: Binutils References: <03b04b63-3781-1fdd-8885-832647b2543b@suse.com> From: Richard Earnshaw In-Reply-To: <03b04b63-3781-1fdd-8885-832647b2543b@suse.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-3491.2 required=5.0 tests=BAYES_00,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,NICE_REPLY_A,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 28/09/2022 13:00, Jan Beulich via Binutils wrote: > On 12.09.2022 10:40, Jan Beulich via Binutils wrote: >> While the Arm v8 ARM (rev I-a) still doesn't mention this alias, it is >> (typically via a macro) already in use in kernels and alike. > > May I ask for feedback here? Without hearing back, I guess I'll simply > put this in some time next week. > > Jan Sorry for the delay. The details on this instruction were only made public earlier today. (https://developer.arm.com/documentation/ddi0602/2022-09/Base-Instructions/CLRBHB--Clear-Branch-History-?lang=en) OK. R. > >> --- >> Diffs of generated files omitted. >> >> --- a/gas/testsuite/gas/aarch64/system.d >> +++ b/gas/testsuite/gas/aarch64/system.d >> @@ -12,6 +12,7 @@ Disassembly of section \.text: >> .*: d503207f wfi >> .*: d503209f sev >> .*: d50320bf sevl >> +.*: d50322df clearbhb >> .*: d503201f nop >> .*: d503203f yield >> .*: d503205f wfe >> @@ -34,7 +35,7 @@ Disassembly of section \.text: >> .*: d503227f hint #0x13 >> .*: d503229f (hint #0x14|csdb) >> .*: d50322bf hint #0x15 >> -.*: d50322df hint #0x16 >> +.*: d50322df (hint #0x16|clearbhb) >> .*: d50322ff hint #0x17 >> .*: d503231f (hint #0x18|paciaz) >> .*: d503233f (hint #0x19|paciasp) >> --- a/gas/testsuite/gas/aarch64/system.s >> +++ b/gas/testsuite/gas/aarch64/system.s >> @@ -11,6 +11,7 @@ >> wfi >> sev >> sevl >> + clearbhb >> >> .macro all_hints from=0, to=127 >> hint \from >> --- a/opcodes/aarch64-tbl.h >> +++ b/opcodes/aarch64-tbl.h >> @@ -4034,6 +4034,7 @@ const struct aarch64_opcode aarch64_opco >> CORE_INSN ("esb", 0xd503221f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), >> CORE_INSN ("psb", 0xd503223f, 0xffffffff, ic_system, 0, OP1 (BARRIER_PSB), {}, F_ALIAS), >> CORE_INSN ("tsb", 0xd503225f, 0xffffffff, ic_system, 0, OP1 (BARRIER_PSB), {}, F_ALIAS), >> + CORE_INSN ("clearbhb", 0xd50322df, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), >> CORE_INSN ("clrex", 0xd503305f, 0xfffff0ff, ic_system, 0, OP1 (UIMM4), {}, F_OPD0_OPT | F_DEFAULT (0xF)), >> CORE_INSN ("dsb", 0xd503309f, 0xfffff0ff, ic_system, 0, OP1 (BARRIER), {}, F_HAS_ALIAS), >> V8_7_INSN ("dsb", 0xd503323f, 0xfffff3ff, ic_system, OP1 (BARRIER_DSB_NXS), {}, F_HAS_ALIAS), >