From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 26789 invoked by alias); 14 Jun 2002 16:16:36 -0000 Mailing-List: contact binutils-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sources.redhat.com Received: (qmail 26773 invoked from network); 14 Jun 2002 16:16:35 -0000 Received: from unknown (HELO mail.nexus.co.uk) (62.3.66.203) by sources.redhat.com with SMTP; 14 Jun 2002 16:16:35 -0000 Received: from dsl-62-3-66-201.zen.co.uk ([62.3.66.201] helo=localhost.localdomain) by mail.nexus.co.uk with esmtp (Exim 3.35 #1 (Debian)) id 17Itlj-0000K0-00; Fri, 14 Jun 2002 17:17:47 +0100 Subject: Re: Flushing the d-cache (was Re: BFD relocations) From: Philip Blundell To: Camm Maguire Cc: Daniel Jacobowitz , Paul Koning , binutils@sources.redhat.com, gcl-devel@gnu.org, roman@hodek.net, debian-68k@lists.debian.org, debian-arm@lists.debian.org In-Reply-To: <54hek5svsl.fsf_-_@intech19.enhanced.com> References: <20020604214100.GA6239@nevyn.them.org> <54d6v6wvfp.fsf@intech19.enhanced.com> <20020604223014.GA7579@nevyn.them.org> <547kldpbu0.fsf@intech19.enhanced.com> <20020605230537.GA4336@nevyn.them.org> <54g001xnnf.fsf@intech19.enhanced.com> <20020606010956.GA7291@nevyn.them.org> <547klbixuk.fsf@intech19.enhanced.com> <15616.47945.929255.781190@pkoning.dev.equallogic.com> <54elfeu5ih.fsf@intech19.enhanced.com> <20020610230608.GA15617@nevyn.them.org> <54hek5svsl.fsf_-_@intech19.enhanced.com> Content-Type: text/plain Content-Transfer-Encoding: 7bit Date: Fri, 14 Jun 2002 09:16:00 -0000 Message-Id: <1024071371.9909.10.camel@mill> Mime-Version: 1.0 X-SW-Source: 2002-06/txt/msg00463.txt.bz2 On Fri, 2002-06-14 at 16:51, Camm Maguire wrote: > #define CLEAR_CACHE do {\ > void *v=memory->cfd.cfd_start,*ve=v+memory->cfd.cfd_size; \ > for (;v register unsigned long _beg __asm ("a1") = (unsigned long)(v); \ > register unsigned long _end __asm ("a2") = (unsigned long)(v+16);\ > register unsigned long _flg __asm ("a3") = 0; \ > __asm __volatile ("swi 0x9f0002 @ sys_cacheflush" \ > : /* no outputs */ \ > : /* no inputs */ \ > : "a1"); \ > }\ You don't need the loop. The arm sys_cacheflush can be given arbitrary regions, it works the cache line size out for itself. p.