From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 32083 invoked by alias); 14 Jun 2002 19:34:52 -0000 Mailing-List: contact binutils-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sources.redhat.com Received: (qmail 32076 invoked from network); 14 Jun 2002 19:34:51 -0000 Received: from unknown (HELO mta03-svc.ntlworld.com) (62.253.162.43) by sources.redhat.com with SMTP; 14 Jun 2002 19:34:51 -0000 Received: from kc.cam.armlinux.org ([62.253.135.163]) by mta03-svc.ntlworld.com (InterMail vM.4.01.03.27 201-229-121-127-20010626) with ESMTP id <20020614193445.MCHW295.mta03-svc.ntlworld.com@kc.cam.armlinux.org>; Fri, 14 Jun 2002 20:34:45 +0100 Received: from localhost ([127.0.0.1] helo=localhost.localdomain ident=pb) by kc.cam.armlinux.org with esmtp (Exim 3.35 #1 (Debian)) id 17IwqL-0000P1-00; Fri, 14 Jun 2002 20:34:45 +0100 Subject: Re: [Gcl-devel] Re: Flushing the d-cache (was Re: BFD relocations) From: Philip Blundell To: Camm Maguire Cc: Daniel Jacobowitz , Paul Koning , binutils@sources.redhat.com, gcl-devel@gnu.org, debian-arm@lists.debian.org In-Reply-To: <54lm9hoeda.fsf@intech19.enhanced.com> References: <20020604214100.GA6239@nevyn.them.org> <54d6v6wvfp.fsf@intech19.enhanced.com> <20020604223014.GA7579@nevyn.them.org> <547kldpbu0.fsf@intech19.enhanced.com> <20020605230537.GA4336@nevyn.them.org> <54g001xnnf.fsf@intech19.enhanced.com> <20020606010956.GA7291@nevyn.them.org> <547klbixuk.fsf@intech19.enhanced.com> <15616.47945.929255.781190@pkoning.dev.equallogic.com> <54elfeu5ih.fsf@intech19.enhanced.com> <20020610230608.GA15617@nevyn.them.org> <54hek5svsl.fsf_-_@intech19.enhanced.com> <1024071371.9909.10.camel@mill> <54lm9hoeda.fsf@intech19.enhanced.com> Content-Type: text/plain Content-Transfer-Encoding: 7bit Date: Fri, 14 Jun 2002 12:34:00 -0000 Message-Id: <1024083285.1294.13.camel@kc> Mime-Version: 1.0 X-SW-Source: 2002-06/txt/msg00470.txt.bz2 On Fri, 2002-06-14 at 20:21, Camm Maguire wrote: > I still see this behavior even if all attempts to flush the data cache > are removed. Makes me think that the swi instruction is no working. > Are there alignment requirements on the arguments? Why aren't > a1,a2,a3 shown in the assembly? I've included the CLEAR_CACHE code > and its assembly below as well. Hmm, right, your asm() statement has a bug. Try this one instead. __asm __volatile ("swi 0x9f0002 @ sys_cacheflush" \ : "=r" (_beg) \ : "0" (_beg), "r" (_end), "r"(_flg)); \ p.