* [PATCH] MIPS gas: Cleanup address insn conditionals
@ 2003-06-15 20:22 Thiemo Seufer
[not found] ` <mailpost.1055708605.24715@news-sj1-1>
2003-06-16 7:00 ` Eric Christopher
0 siblings, 2 replies; 13+ messages in thread
From: Thiemo Seufer @ 2003-06-15 20:22 UTC (permalink / raw)
To: binutils
Hello All,
this is some cleanup of the addressing instruction conditionals in MIPS gas.
Thiemo
2003-06-15 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
/gas/ChangeLog
* config/tc-mips.c (ADDRESS_ADD_INSN,ADDRESS_ADDI_INSN,
ADDRESS_LOAD_INSN,ADDRESS_STORE_INSN): New macros.
(macro_build_ldst_constoffset,load_address,macro,s_cpsetup,
s_cprestore,s_cpadd): Use them.
diff -BurpNX /bigdisk/src/gcc-exclude source-orig/gas/config/tc-mips.c source/gas/config/tc-mips.c
--- source-orig/gas/config/tc-mips.c Thu Jun 12 15:21:50 2003
+++ source/gas/config/tc-mips.c Sun Jun 15 17:40:33 2003
@@ -300,6 +300,18 @@ static int mips_32bitmode = 0;
#define HAVE_64BIT_ADDRESS_CONSTANTS (HAVE_64BIT_ADDRESSES \
|| HAVE_64BIT_GPRS)
+#define ADDRESS_ADD_INSN \
+ (HAVE_32BIT_ADDRESSES ? HAVE_NEWABI ? "add" : "addu" : "daddu")
+
+#define ADDRESS_ADDI_INSN \
+ (HAVE_32BIT_ADDRESSES ? HAVE_NEWABI ? "addi" : "addiu" : "daddiu")
+
+#define ADDRESS_LOAD_INSN \
+ (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
+
+#define ADDRESS_STORE_INSN \
+ (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
+
/* Return true if the given CPU supports the MIPS16 ASE. */
#define CPU_HAS_MIPS16(cpu) \
(strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
@@ -3381,9 +3393,7 @@ macro_build_ldst_constoffset (place, cou
macro_build_lui (place, counter, ep, AT);
if (place != NULL)
place += 4;
- macro_build (place, counter, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? HAVE_NEWABI
- ? "add" : "addu" : "daddu",
+ macro_build (place, counter, (expressionS *) NULL, ADDRESS_ADD_INSN,
"d,v,t", AT, AT, breg);
if (place != NULL)
place += 4;
@@ -3870,10 +3880,9 @@ load_address (counter, reg, ep, used_at)
&& ! nopic_need_relax (ep->X_add_symbol, 1))
{
frag_grow (20);
- macro_build ((char *) NULL, counter, ep,
- HAVE_32BIT_ADDRESSES ? HAVE_NEWABI
- ? "addi" : "addiu" : "daddiu", "t,r,j",
- reg, mips_gp_register, (int) BFD_RELOC_GPREL16);
+ macro_build ((char *) NULL, counter, ep, ADDRESS_ADDI_INSN,
+ "t,r,j", reg, mips_gp_register,
+ (int) BFD_RELOC_GPREL16);
p = frag_var (rs_machine_dependent, 8, 0,
RELAX_ENCODE (4, 8, 0, 4, 0,
mips_opts.warn_about_macros),
@@ -3882,9 +3891,7 @@ load_address (counter, reg, ep, used_at)
macro_build_lui (p, counter, ep, reg);
if (p != NULL)
p += 4;
- macro_build (p, counter, ep,
- HAVE_32BIT_ADDRESSES ? HAVE_NEWABI
- ? "addi" : "addiu" : "daddiu",
+ macro_build (p, counter, ep, ADDRESS_ADDI_INSN,
"t,r,j", reg, reg, (int) BFD_RELOC_LO16);
}
}
@@ -3913,14 +3920,13 @@ load_address (counter, reg, ep, used_at)
frag_now->tc_frag_data.tc_fr_offset =
ex.X_add_number = ep->X_add_number;
ep->X_add_number = 0;
- macro_build ((char *) NULL, counter, ep,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg,
- (int) BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
+ macro_build ((char *) NULL, counter, ep, ADDRESS_LOAD_INSN,
+ "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_DISP,
+ mips_gp_register);
if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
ex.X_op = O_constant;
- macro_build ((char *) NULL, counter, &ex,
- HAVE_32BIT_ADDRESSES ? "addi" : "daddiu",
+ macro_build ((char *) NULL, counter, &ex, ADDRESS_ADDI_INSN,
"t,r,j", reg, reg, (int) BFD_RELOC_LO16);
p = frag_var (rs_machine_dependent, 8, 0,
RELAX_ENCODE (8, 4, 0, 0, 0,
@@ -3929,8 +3935,7 @@ load_address (counter, reg, ep, used_at)
ep->X_add_number = ex.X_add_number;
}
- macro_build (p, counter, ep,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg,
+ macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
(int) BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
if (! p)
@@ -3946,15 +3951,14 @@ load_address (counter, reg, ep, used_at)
ex.X_add_number = ep->X_add_number;
ep->X_add_number = 0;
frag_grow (20);
- macro_build ((char *) NULL, counter, ep,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)",
- reg, (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
+ macro_build ((char *) NULL, counter, ep, ADDRESS_LOAD_INSN,
+ "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16,
+ mips_gp_register);
macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", "");
p = frag_var (rs_machine_dependent, 4, 0,
RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros),
ep->X_add_symbol, (offsetT) 0, (char *) NULL);
- macro_build (p, counter, ep,
- HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
+ macro_build (p, counter, ep, ADDRESS_ADDI_INSN,
"t,r,j", reg, reg, (int) BFD_RELOC_LO16);
if (ex.X_add_number != 0)
@@ -3962,8 +3966,7 @@ load_address (counter, reg, ep, used_at)
if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
ex.X_op = O_constant;
- macro_build ((char *) NULL, counter, &ex,
- HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
+ macro_build ((char *) NULL, counter, &ex, ADDRESS_ADDI_INSN,
"t,r,j", reg, reg, (int) BFD_RELOC_LO16);
}
}
@@ -3999,18 +4002,15 @@ load_address (counter, reg, ep, used_at)
macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
(int) BFD_RELOC_MIPS_GOT_HI16);
macro_build ((char *) NULL, counter, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? "add" : "daddu", "d,v,t", reg,
- reg, mips_gp_register);
- macro_build ((char *) NULL, counter, ep,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld",
+ ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
+ macro_build ((char *) NULL, counter, ep, ADDRESS_LOAD_INSN,
"t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg);
if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
else if (ex.X_add_number)
{
ex.X_op = O_constant;
- macro_build ((char *) NULL, counter, &ex,
- HAVE_32BIT_ADDRESSES ? "addi" : "daddiu",
+ macro_build ((char *) NULL, counter, &ex, ADDRESS_ADDI_INSN,
"t,r,j", reg, reg, (int) BFD_RELOC_LO16);
}
@@ -4019,11 +4019,9 @@ load_address (counter, reg, ep, used_at)
RELAX_ENCODE (ex.X_add_number ? 16 : 12, 8, 0, 4, 0,
mips_opts.warn_about_macros),
ep->X_add_symbol, 0, (char *) NULL);
- macro_build (p, counter, ep,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg,
+ macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
(int) BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
- macro_build (p + 4, counter, ep,
- HAVE_32BIT_ADDRESSES ? "addi" : "daddiu", "t,r,j",
+ macro_build (p + 4, counter, ep, ADDRESS_ADDI_INSN, "t,r,j",
reg, reg, (int) BFD_RELOC_MIPS_GOT_OFST);
}
else
@@ -4038,10 +4036,8 @@ load_address (counter, reg, ep, used_at)
macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
(int) BFD_RELOC_MIPS_GOT_HI16);
macro_build ((char *) NULL, counter, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? "addu" : "daddu", "d,v,t", reg,
- reg, mips_gp_register);
- macro_build ((char *) NULL, counter, ep,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld",
+ ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
+ macro_build ((char *) NULL, counter, ep, ADDRESS_LOAD_INSN,
"t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg);
p = frag_var (rs_machine_dependent, 12 + off, 0,
RELAX_ENCODE (12, 12 + off, off, 8 + off, 0,
@@ -4056,14 +4052,12 @@ load_address (counter, reg, ep, used_at)
macro_build (p, counter, (expressionS *) NULL, "nop", "");
p += 4;
}
- macro_build (p, counter, ep,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg,
+ macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
(int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
p += 4;
macro_build (p, counter, (expressionS *) NULL, "nop", "");
p += 4;
- macro_build (p, counter, ep,
- HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
+ macro_build (p, counter, ep, ADDRESS_ADDI_INSN,
"t,r,j", reg, reg, (int) BFD_RELOC_LO16);
if (ex.X_add_number != 0)
@@ -4071,8 +4065,7 @@ load_address (counter, reg, ep, used_at)
if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
ex.X_op = O_constant;
- macro_build ((char *) NULL, counter, &ex,
- HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
+ macro_build ((char *) NULL, counter, &ex, ADDRESS_ADDI_INSN,
"t,r,j", reg, reg, (int) BFD_RELOC_LO16);
}
}
@@ -4082,8 +4075,7 @@ load_address (counter, reg, ep, used_at)
/* We always do
addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
*/
- macro_build ((char *) NULL, counter, ep,
- HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
+ macro_build ((char *) NULL, counter, ep, ADDRESS_ADDI_INSN,
"t,r,j", reg, mips_gp_register, (int) BFD_RELOC_GPREL16);
}
else
@@ -5000,9 +4992,8 @@ macro (ip)
{
frag_grow (20);
macro_build ((char *) NULL, &icnt, &offset_expr,
- HAVE_NEWABI ? "addi" : "addiu",
- "t,r,j", tempreg, mips_gp_register,
- (int) BFD_RELOC_GPREL16);
+ ADDRESS_ADDI_INSN, "t,r,j", tempreg,
+ mips_gp_register, (int) BFD_RELOC_GPREL16);
p = frag_var (rs_machine_dependent, 8, 0,
RELAX_ENCODE (4, 8, 0, 4, 0,
mips_opts.warn_about_macros),
@@ -5011,8 +5002,7 @@ macro (ip)
macro_build_lui (p, &icnt, &offset_expr, tempreg);
if (p != NULL)
p += 4;
- macro_build (p, &icnt, &offset_expr,
- HAVE_NEWABI ? "addi" : "addiu",
+ macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
}
}
@@ -5055,8 +5045,7 @@ macro (ip)
frag_grow (32);
if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
- macro_build ((char *) NULL, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld",
+ macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
"t,o(b)", tempreg, lw_reloc_type, mips_gp_register);
if (expr1.X_add_number == 0)
{
@@ -5085,8 +5074,7 @@ macro (ip)
macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
p += 4;
}
- macro_build (p, &icnt, &expr1,
- HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
+ macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN,
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
/* FIXME: If breg == 0, and the next instruction uses
$tempreg, then if this variant case is used an extra
@@ -5097,8 +5085,7 @@ macro (ip)
{
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
"nop", "");
- macro_build ((char *) NULL, &icnt, &expr1,
- HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
+ macro_build ((char *) NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
frag_var (rs_machine_dependent, 0, 0,
RELAX_ENCODE (0, 0, -12, -4, 0, 0),
@@ -5122,8 +5109,7 @@ macro (ip)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
"nop", "");
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
- "d,v,t", treg, AT, breg);
+ ADDRESS_ADD_INSN, "d,v,t", treg, AT, breg);
breg = 0;
tempreg = treg;
off1 = -8;
@@ -5136,12 +5122,10 @@ macro (ip)
macro_build_lui (NULL, &icnt, &expr1, AT);
mips_optimize = hold_mips_optimize;
- macro_build ((char *) NULL, &icnt, &expr1,
- HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
+ macro_build ((char *) NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
"t,r,j", AT, AT, (int) BFD_RELOC_LO16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
- "d,v,t", tempreg, tempreg, AT);
+ ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, AT);
frag_var (rs_machine_dependent, 0, 0,
RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0),
offset_expr.X_add_symbol, 0, NULL);
@@ -5187,16 +5171,14 @@ macro (ip)
offset_expr.X_add_number = 0;
macro_build ((char *) NULL, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld",
- "t,o(b)", tempreg, lw_reloc_type,
- mips_gp_register);
+ ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
+ lw_reloc_type, mips_gp_register);
if (expr1.X_add_number >= -0x8000
&& expr1.X_add_number < 0x8000)
{
macro_build ((char *) NULL, &icnt, &expr1,
- HAVE_32BIT_ADDRESSES ? "addi" : "daddiu",
- "t,r,j", tempreg, tempreg,
+ ADDRESS_ADDI_INSN, "t,r,j", tempreg, tempreg,
(int) BFD_RELOC_LO16);
p = frag_var (rs_machine_dependent, 4, 0,
RELAX_ENCODE (8, 4, 0, 0, 0, 0),
@@ -5219,19 +5201,17 @@ macro (ip)
{
assert (tempreg == AT);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? "add" : "daddu",
- "d,v,t", treg, AT, breg);
+ ADDRESS_ADD_INSN, "d,v,t", treg, AT, breg);
dreg = treg;
adj = 4;
}
macro_build_lui ((char *) NULL, &icnt, &expr1, AT);
macro_build ((char *) NULL, &icnt, &expr1,
- HAVE_32BIT_ADDRESSES ? "addi" : "daddiu",
- "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
+ ADDRESS_ADDI_INSN, "t,r,j", AT, AT,
+ (int) BFD_RELOC_LO16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? "add" : "daddu",
- "d,v,t", dreg, dreg, AT);
+ ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
p = frag_var (rs_machine_dependent, 4 + adj, 0,
RELAX_ENCODE (16 + adj, 4 + adj,
@@ -5245,15 +5225,14 @@ macro (ip)
offset_expr.X_add_number = expr1.X_add_number;
- macro_build (p, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld",
+ macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
"t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_DISP,
mips_gp_register);
if (adj)
{
macro_build (p + 4, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? "add" : "daddu",
- "d,v,t", treg, tempreg, breg);
+ ADDRESS_ADD_INSN, "d,v,t",
+ treg, tempreg, breg);
breg = 0;
tempreg = treg;
}
@@ -5261,9 +5240,8 @@ macro (ip)
else
{
macro_build ((char *) NULL, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld",
- "t,o(b)", tempreg, lw_reloc_type,
- mips_gp_register);
+ ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
+ lw_reloc_type, mips_gp_register);
if (lw_reloc_type != BFD_RELOC_MIPS_GOT_DISP)
p = frag_var (rs_machine_dependent, 0, 0,
RELAX_ENCODE (0, 0, -4, 0, 0, 0),
@@ -5342,10 +5320,9 @@ macro (ip)
macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
tempreg, lui_reloc_type);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
- "d,v,t", tempreg, tempreg, mips_gp_register);
- macro_build ((char *) NULL, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld",
+ ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
+ mips_gp_register);
+ macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
"t,o(b)", tempreg, lw_reloc_type, tempreg);
if (expr1.X_add_number == 0)
{
@@ -5376,8 +5353,7 @@ macro (ip)
{
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
"nop", "");
- macro_build ((char *) NULL, &icnt, &expr1,
- HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
+ macro_build ((char *) NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
@@ -5409,8 +5385,7 @@ macro (ip)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
"nop", "");
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
- "d,v,t", treg, AT, breg);
+ ADDRESS_ADD_INSN, "d,v,t", treg, AT, breg);
dreg = treg;
adj = 8;
}
@@ -5422,12 +5397,10 @@ macro (ip)
macro_build_lui (NULL, &icnt, &expr1, AT);
mips_optimize = hold_mips_optimize;
- macro_build ((char *) NULL, &icnt, &expr1,
- HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
+ macro_build ((char *) NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
"t,r,j", AT, AT, (int) BFD_RELOC_LO16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
- "d,v,t", dreg, dreg, AT);
+ ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0,
RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel,
@@ -5448,19 +5421,15 @@ macro (ip)
p += 4;
}
- macro_build (p, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld",
- "t,o(b)", tempreg,
- local_reloc_type,
- mips_gp_register);
+ macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
+ tempreg, local_reloc_type, mips_gp_register);
p += 4;
if (expr1.X_add_number >= -0x8000
&& expr1.X_add_number < 0x8000)
{
macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
p += 4;
- macro_build (p, &icnt, &expr1,
- HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
+ macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN,
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
/* FIXME: If add_number is 0, and there was no base
register, the external symbol case ended with a load,
@@ -5478,8 +5447,7 @@ macro (ip)
macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
p += 4;
macro_build (p, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
- "d,v,t", treg, AT, breg);
+ ADDRESS_ADD_INSN, "d,v,t", treg, AT, breg);
p += 4;
tempreg = treg;
/* We set breg to 0 because we have arranged to add
@@ -5489,12 +5457,10 @@ macro (ip)
macro_build_lui (p, &icnt, &expr1, AT);
p += 4;
- macro_build (p, &icnt, &expr1,
- HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
+ macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN,
"t,r,j", AT, AT, (int) BFD_RELOC_LO16);
p += 4;
- macro_build (p, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
+ macro_build (p, &icnt, (expressionS *) NULL, ADDRESS_ADD_INSN,
"d,v,t", tempreg, tempreg, AT);
p += 4;
}
@@ -5551,10 +5517,9 @@ macro (ip)
macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
tempreg, lui_reloc_type);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? "add" : "daddu",
- "d,v,t", tempreg, tempreg, mips_gp_register);
- macro_build ((char *) NULL, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld",
+ ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
+ mips_gp_register);
+ macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
"t,o(b)", tempreg, lw_reloc_type, tempreg);
if (expr1.X_add_number == 0)
@@ -5567,8 +5532,7 @@ macro (ip)
else if (expr1.X_add_number >= -0x8000
&& expr1.X_add_number < 0x8000)
{
- macro_build ((char *) NULL, &icnt, &expr1,
- HAVE_32BIT_ADDRESSES ? "addi" : "daddiu",
+ macro_build ((char *) NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
"t,r,j", tempreg, tempreg,
(int) BFD_RELOC_LO16);
p = frag_var (rs_machine_dependent, 8, 0,
@@ -5593,8 +5557,7 @@ macro (ip)
{
assert (tempreg == AT);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? "add" : "daddu",
- "d,v,t", treg, AT, breg);
+ ADDRESS_ADD_INSN, "d,v,t", treg, AT, breg);
dreg = treg;
adj = 4;
}
@@ -5602,12 +5565,10 @@ macro (ip)
/* Set mips_optimize around the lui instruction to avoid
inserting an unnecessary nop after the lw. */
macro_build_lui ((char *) NULL, &icnt, &expr1, AT);
- macro_build ((char *) NULL, &icnt, &expr1,
- HAVE_32BIT_ADDRESSES ? "addi" : "daddiu",
+ macro_build ((char *) NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
"t,r,j", AT, AT, (int) BFD_RELOC_LO16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? "add" : "daddu",
- "d,v,t", dreg, dreg, AT);
+ ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
p = frag_var (rs_machine_dependent, 8 + adj, 0,
RELAX_ENCODE (24 + adj, 8 + adj,
@@ -5623,18 +5584,15 @@ macro (ip)
as_bad (_("PIC code offset overflow (max 32 signed bits)"));
offset_expr.X_add_number = expr1.X_add_number;
- macro_build (p, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)",
- tempreg,
- (int) BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
- macro_build (p + 4, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "addi" : "daddiu", "t,r,j",
+ macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
+ tempreg, (int) BFD_RELOC_MIPS_GOT_PAGE,
+ mips_gp_register);
+ macro_build (p + 4, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
tempreg, tempreg, (int) BFD_RELOC_MIPS_GOT_OFST);
if (adj)
{
macro_build (p + 8, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? "add" : "daddu",
- "d,v,t", treg, tempreg, breg);
+ ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
breg = 0;
tempreg = treg;
}
@@ -5644,9 +5602,9 @@ macro (ip)
/* We use
addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
*/
- macro_build ((char *) NULL, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
- tempreg, mips_gp_register, (int) BFD_RELOC_GPREL16);
+ macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
+ "t,r,j", tempreg, mips_gp_register,
+ (int) BFD_RELOC_GPREL16);
}
else
abort ();
@@ -5659,7 +5617,7 @@ macro (ip)
s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" :
HAVE_NEWABI ? "add" : "addu";
else
- s = HAVE_64BIT_ADDRESSES ? "daddu" : HAVE_NEWABI ? "add" : "addu";
+ s = ADDRESS_ADD_INSN;
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s,
"d,v,t", treg, tempreg, breg);
@@ -5718,8 +5676,9 @@ macro (ip)
}
expr1.X_add_number = mips_cprestore_offset;
macro_build_ldst_constoffset ((char *) NULL, &icnt, &expr1,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld",
- mips_gp_register, mips_frame_reg);
+ ADDRESS_LOAD_INSN,
+ mips_gp_register,
+ mips_frame_reg);
}
}
}
@@ -5769,8 +5728,7 @@ macro (ip)
{
frag_grow (4);
macro_build ((char *) NULL, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld",
- "t,o(b)", PIC_CALL_REG,
+ ADDRESS_LOAD_INSN, "t,o(b)", PIC_CALL_REG,
(int) BFD_RELOC_MIPS_CALL16,
mips_gp_register);
frag_var (rs_machine_dependent, 0, 0,
@@ -5784,22 +5742,19 @@ macro (ip)
"t,u", PIC_CALL_REG,
(int) BFD_RELOC_MIPS_CALL_HI16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? "add" : "daddu",
- "d,v,t", PIC_CALL_REG, PIC_CALL_REG,
- mips_gp_register);
+ ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
+ PIC_CALL_REG, mips_gp_register);
macro_build ((char *) NULL, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld",
- "t,o(b)", PIC_CALL_REG,
+ ADDRESS_LOAD_INSN, "t,o(b)", PIC_CALL_REG,
(int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
p = frag_var (rs_machine_dependent, 8, 0,
RELAX_ENCODE (12, 8, 0, 4, 0, 0),
offset_expr.X_add_symbol, 0, NULL);
- macro_build (p, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)",
- PIC_CALL_REG, (int) BFD_RELOC_MIPS_GOT_PAGE,
+ macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
+ "t,o(b)", PIC_CALL_REG,
+ (int) BFD_RELOC_MIPS_GOT_PAGE,
mips_gp_register);
- macro_build (p + 4, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "addi" : "daddiu",
+ macro_build (p + 4, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
"t,r,j", PIC_CALL_REG, PIC_CALL_REG,
(int) BFD_RELOC_MIPS_GOT_OFST);
}
@@ -5812,8 +5767,7 @@ macro (ip)
if (! mips_big_got)
{
macro_build ((char *) NULL, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld",
- "t,o(b)", PIC_CALL_REG,
+ ADDRESS_LOAD_INSN, "t,o(b)", PIC_CALL_REG,
(int) BFD_RELOC_MIPS_CALL16, mips_gp_register);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
"nop", "");
@@ -5833,12 +5787,10 @@ macro (ip)
"t,u", PIC_CALL_REG,
(int) BFD_RELOC_MIPS_CALL_HI16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
- "d,v,t", PIC_CALL_REG, PIC_CALL_REG,
- mips_gp_register);
+ ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
+ PIC_CALL_REG, mips_gp_register);
macro_build ((char *) NULL, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld",
- "t,o(b)", PIC_CALL_REG,
+ ADDRESS_LOAD_INSN, "t,o(b)", PIC_CALL_REG,
(int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
"nop", "");
@@ -5851,16 +5803,14 @@ macro (ip)
macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
p += 4;
}
- macro_build (p, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld",
+ macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
"t,o(b)", PIC_CALL_REG,
(int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
p += 4;
macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
p += 4;
}
- macro_build (p, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
+ macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
"t,r,j", PIC_CALL_REG, PIC_CALL_REG,
(int) BFD_RELOC_LO16);
macro_build_jalr (icnt, &offset_expr);
@@ -5886,8 +5836,9 @@ macro (ip)
"nop", "");
expr1.X_add_number = mips_cprestore_offset;
macro_build_ldst_constoffset ((char *) NULL, &icnt, &expr1,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld",
- mips_gp_register, mips_frame_reg);
+ ADDRESS_LOAD_INSN,
+ mips_gp_register,
+ mips_frame_reg);
}
}
}
@@ -6298,9 +6249,8 @@ macro (ip)
{
frag_grow (28);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? HAVE_NEWABI
- ? "add" : "addu" : "daddu",
- "d,v,t", tempreg, breg, mips_gp_register);
+ ADDRESS_ADD_INSN, "d,v,t", tempreg, breg,
+ mips_gp_register);
macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
treg, (int) BFD_RELOC_GPREL16, tempreg);
p = frag_var (rs_machine_dependent, 12, 0,
@@ -6310,9 +6260,7 @@ macro (ip)
macro_build_lui (p, &icnt, &offset_expr, tempreg);
if (p != NULL)
p += 4;
- macro_build (p, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? HAVE_NEWABI
- ? "add" : "addu" : "daddu",
+ macro_build (p, &icnt, (expressionS *) NULL, ADDRESS_ADD_INSN,
"d,v,t", tempreg, tempreg, breg);
if (p != NULL)
p += 4;
@@ -6349,13 +6297,12 @@ macro (ip)
if (HAVE_NEWABI)
{
macro_build ((char *) NULL, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld",
- "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_PAGE,
- mips_gp_register);
+ ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
+ BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? "add" : "daddu",
- "d,v,t", tempreg, tempreg, breg);
+ ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
+ breg);
macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, treg,
(int) BFD_RELOC_MIPS_GOT_OFST, tempreg);
@@ -6370,20 +6317,18 @@ macro (ip)
|| expr1.X_add_number >= 0x8000)
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
frag_grow (20);
- macro_build ((char *) NULL, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", tempreg,
- (int) lw_reloc_type, mips_gp_register);
+ macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
+ "t,o(b)", tempreg, (int) lw_reloc_type,
+ mips_gp_register);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
p = frag_var (rs_machine_dependent, 4, 0,
RELAX_ENCODE (0, 4, -8, 0, 0, 0),
offset_expr.X_add_symbol, 0, NULL);
- macro_build (p, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
+ macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
- "d,v,t", tempreg, tempreg, breg);
+ ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, breg);
macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
(int) BFD_RELOC_LO16, tempreg);
}
@@ -6422,10 +6367,9 @@ macro (ip)
macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
tempreg, (int) BFD_RELOC_MIPS_GOT_HI16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
- "d,v,t", tempreg, tempreg, mips_gp_register);
- macro_build ((char *) NULL, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld",
+ ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
+ mips_gp_register);
+ macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
"t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16,
tempreg);
p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
@@ -6436,20 +6380,17 @@ macro (ip)
macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
p += 4;
}
- macro_build (p, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld",
+ macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
"t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16,
mips_gp_register);
p += 4;
macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
p += 4;
- macro_build (p, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
+ macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
- "d,v,t", tempreg, tempreg, breg);
+ ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, breg);
macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
(int) BFD_RELOC_LO16, tempreg);
}
@@ -6477,16 +6418,14 @@ macro (ip)
macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
tempreg, (int) BFD_RELOC_MIPS_GOT_HI16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? "add" : "daddu",
- "d,v,t", tempreg, tempreg, mips_gp_register);
- macro_build ((char *) NULL, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld",
+ ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
+ mips_gp_register);
+ macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
"t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16,
tempreg);
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? "add" : "daddu",
- "d,v,t", tempreg, tempreg, breg);
+ ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, breg);
macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
(int) BFD_RELOC_LO16, tempreg);
@@ -6495,15 +6434,12 @@ macro (ip)
RELAX_ENCODE (16 + bregsz, 8 + bregsz,
0, 4 + bregsz, 0, 0),
offset_expr.X_add_symbol, 0, NULL);
- macro_build (p, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld",
- "t,o(b)", tempreg,
- (int) BFD_RELOC_MIPS_GOT_PAGE,
+ macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
+ tempreg, (int) BFD_RELOC_MIPS_GOT_PAGE,
mips_gp_register);
if (breg != 0)
macro_build (p + 4, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? "add" : "daddu",
- "d,v,t", tempreg, tempreg, breg);
+ ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, breg);
macro_build (p + 4 + bregsz, &icnt, &offset_expr, s, fmt, treg,
(int) BFD_RELOC_MIPS_GOT_OFST, tempreg);
}
@@ -6525,8 +6461,8 @@ macro (ip)
else
{
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
- "d,v,t", tempreg, breg, mips_gp_register);
+ ADDRESS_ADD_INSN, "d,v,t", tempreg, breg,
+ mips_gp_register);
macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
treg, (int) BFD_RELOC_GPREL16, tempreg);
}
@@ -6616,8 +6552,7 @@ macro (ip)
}
else if (mips_pic == SVR4_PIC)
{
- macro_build ((char *) NULL, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld",
+ macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
"t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
mips_gp_register);
}
@@ -6625,9 +6560,9 @@ macro (ip)
{
/* For embedded PIC we pick up the entire address off $gp in
a single instruction. */
- macro_build ((char *) NULL, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", AT,
- mips_gp_register, (int) BFD_RELOC_GPREL16);
+ macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
+ "t,r,j", AT, mips_gp_register,
+ (int) BFD_RELOC_GPREL16);
offset_expr.X_op = O_constant;
offset_expr.X_add_number = 0;
}
@@ -6713,9 +6648,8 @@ macro (ip)
assert (strcmp (s, RDATA_SECTION_NAME) == 0);
if (mips_pic == SVR4_PIC)
macro_build ((char *) NULL, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld",
- "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
- mips_gp_register);
+ ADDRESS_LOAD_INSN, "t,o(b)", AT,
+ (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
else
{
/* FIXME: This won't work for a 64 bit address. */
@@ -6898,9 +6832,8 @@ macro (ip)
{
frag_grow (36);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? HAVE_NEWABI
- ? "add" : "addu" : "daddu",
- "d,v,t", AT, breg, mips_gp_register);
+ ADDRESS_ADD_INSN, "d,v,t", AT, breg,
+ mips_gp_register);
tempreg = AT;
off = 4;
used_at = 1;
@@ -6953,9 +6886,7 @@ macro (ip)
p += 4;
if (breg != 0)
{
- macro_build (p, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? HAVE_NEWABI
- ? "add" : "addu" : "daddu",
+ macro_build (p, &icnt, (expressionS *) NULL, ADDRESS_ADD_INSN,
"d,v,t", AT, breg, AT);
if (p != NULL)
p += 4;
@@ -7001,15 +6932,13 @@ macro (ip)
else
off = 4;
frag_grow (24 + off);
- macro_build ((char *) NULL, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", AT,
- (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
+ macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
+ "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
+ mips_gp_register);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? HAVE_NEWABI
- ? "add" : "addu" : "daddu",
- "d,v,t", AT, breg, AT);
+ ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
/* Itbl support may require additional care here. */
macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
coproc ? treg + 1 : treg,
@@ -7068,18 +6997,13 @@ macro (ip)
macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
AT, (int) BFD_RELOC_MIPS_GOT_HI16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? HAVE_NEWABI
- ? "add" : "addu" : "daddu",
- "d,v,t", AT, AT, mips_gp_register);
- macro_build ((char *) NULL, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld",
+ ADDRESS_ADD_INSN, "d,v,t", AT, AT, mips_gp_register);
+ macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
"t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? HAVE_NEWABI
- ? "add" : "addu" : "daddu",
- "d,v,t", AT, breg, AT);
+ ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
/* Itbl support may require additional care here. */
macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
coproc ? treg + 1 : treg,
@@ -7106,8 +7030,7 @@ macro (ip)
macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
p += 4;
}
- macro_build (p, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "lw" : "ld",
+ macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
"t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
mips_gp_register);
p += 4;
@@ -7115,9 +7038,7 @@ macro (ip)
p += 4;
if (breg != 0)
{
- macro_build (p, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? HAVE_NEWABI
- ? "add" : "addu" : "daddu",
+ macro_build (p, &icnt, (expressionS *) NULL, ADDRESS_ADD_INSN,
"d,v,t", AT, breg, AT);
p += 4;
}
@@ -7156,8 +7077,8 @@ macro (ip)
else
{
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
- "d,v,t", AT, breg, mips_gp_register);
+ ADDRESS_ADD_INSN, "d,v,t", AT, breg,
+ mips_gp_register);
tempreg = AT;
used_at = 1;
}
@@ -7683,8 +7604,7 @@ macro2 (ip)
imm_expr.X_add_number = -imm_expr.X_add_number;
macro_build ((char *) NULL, &icnt, &imm_expr,
HAVE_32BIT_GPRS ? "addiu" : "daddiu",
- "t,r,j", dreg, sreg,
- (int) BFD_RELOC_LO16);
+ "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
used_at = 0;
}
else
@@ -8042,9 +7962,7 @@ macro2 (ip)
load_address (&icnt, AT, &offset_expr, &used_at);
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? HAVE_NEWABI
- ? "add" : "addu" : "daddu",
- "d,v,t", AT, AT, breg);
+ ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
if (! target_big_endian)
expr1.X_add_number = off;
else
@@ -8065,9 +7983,7 @@ macro2 (ip)
load_address (&icnt, AT, &offset_expr, &used_at);
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? HAVE_NEWABI
- ? "add" : "addu" : "daddu",
- "d,v,t", AT, AT, breg);
+ ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
if (target_big_endian)
expr1.X_add_number = 0;
macro_build ((char *) NULL, &icnt, &expr1,
@@ -8140,9 +8056,7 @@ macro2 (ip)
load_address (&icnt, AT, &offset_expr, &used_at);
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? HAVE_NEWABI
- ? "add" : "addu" : "daddu",
- "d,v,t", AT, AT, breg);
+ ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
if (! target_big_endian)
expr1.X_add_number = off;
else
@@ -8162,9 +8076,7 @@ macro2 (ip)
load_address (&icnt, AT, &offset_expr, &used_at);
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? HAVE_NEWABI
- ? "add" : "addu" : "daddu",
- "d,v,t", AT, AT, breg);
+ ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
if (! target_big_endian)
expr1.X_add_number = 0;
macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
@@ -12722,9 +12634,8 @@ s_cpsetup (ignore)
fix_new (frag_now, f - frag_now->fr_literal,
4, NULL, 0, 0, BFD_RELOC_LO16);
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- HAVE_64BIT_ADDRESSES ? "daddu" : "add", "d,v,t",
- mips_gp_register, mips_gp_register, reg1);
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, ADDRESS_ADD_INSN,
+ "d,v,t", mips_gp_register, mips_gp_register, reg1);
demand_empty_rest_of_line ();
}
@@ -12772,8 +12683,7 @@ s_cprestore (ignore)
ex.X_op_symbol = NULL;
ex.X_add_number = mips_cprestore_offset;
- macro_build_ldst_constoffset ((char *) NULL, &icnt, &ex,
- HAVE_32BIT_ADDRESSES ? "sw" : "sd",
+ macro_build_ldst_constoffset ((char *) NULL, &icnt, &ex, ADDRESS_STORE_INSN,
mips_gp_register, mips_frame_reg);
demand_empty_rest_of_line ();
@@ -12941,8 +12851,7 @@ s_cpadd (ignore)
/* Add $gp to the register named as an argument. */
reg = tc_get_register (0);
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? HAVE_NEWABI ? "add" : "addu" : "daddu",
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, ADDRESS_ADD_INSN,
"d,v,t", reg, reg, mips_gp_register);
demand_empty_rest_of_line ();
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] MIPS gas: Cleanup address insn conditionals
[not found] ` <mailpost.1055708605.24715@news-sj1-1>
@ 2003-06-16 4:52 ` cgd
0 siblings, 0 replies; 13+ messages in thread
From: cgd @ 2003-06-16 4:52 UTC (permalink / raw)
To: ica2_ts; +Cc: binutils
At Sun, 15 Jun 2003 20:23:25 +0000 (UTC), "Thiemo Seufer" wrote:
> +#define ADDRESS_ADD_INSN \
> + (HAVE_32BIT_ADDRESSES ? HAVE_NEWABI ? "add" : "addu" : "daddu")
> +
> +#define ADDRESS_ADDI_INSN \
> + (HAVE_32BIT_ADDRESSES ? HAVE_NEWABI ? "addi" : "addiu" : "daddiu")
Could you please add more parens to these?
If somebody has to go look at the C operator precedence rules to tell
what is meant, something is wrong. (yes, *I*'d have to go look at the
rules to figure out what the above means, unless i derive it from my
understanding the ABIs in question.)
I know, it's the way the code was before, but that doesn't mean it was
good...
cgd
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] MIPS gas: Cleanup address insn conditionals
2003-06-15 20:22 [PATCH] MIPS gas: Cleanup address insn conditionals Thiemo Seufer
[not found] ` <mailpost.1055708605.24715@news-sj1-1>
@ 2003-06-16 7:00 ` Eric Christopher
2003-06-16 12:11 ` Thiemo Seufer
1 sibling, 1 reply; 13+ messages in thread
From: Eric Christopher @ 2003-06-16 7:00 UTC (permalink / raw)
To: Thiemo Seufer; +Cc: binutils
>
> +#define ADDRESS_ADD_INSN \
> + (HAVE_32BIT_ADDRESSES ? HAVE_NEWABI ? "add" : "addu" : "daddu")
> +
> +#define ADDRESS_ADDI_INSN \
> + (HAVE_32BIT_ADDRESSES ? HAVE_NEWABI ? "addi" : "addiu" : "daddiu")
> +
Hey, can you add some parens here and maybe some comments explaining the
abis? :)
-eric
--
Eric Christopher <echristo@redhat.com>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] MIPS gas: Cleanup address insn conditionals
2003-06-16 7:00 ` Eric Christopher
@ 2003-06-16 12:11 ` Thiemo Seufer
2003-06-16 13:15 ` Maciej W. Rozycki
0 siblings, 1 reply; 13+ messages in thread
From: Thiemo Seufer @ 2003-06-16 12:11 UTC (permalink / raw)
To: Eric Christopher; +Cc: binutils
Eric Christopher wrote:
>
> >
> > +#define ADDRESS_ADD_INSN \
> > + (HAVE_32BIT_ADDRESSES ? HAVE_NEWABI ? "add" : "addu" : "daddu")
> > +
> > +#define ADDRESS_ADDI_INSN \
> > + (HAVE_32BIT_ADDRESSES ? HAVE_NEWABI ? "addi" : "addiu" : "daddiu")
> > +
>
> Hey, can you add some parens here and maybe some comments explaining the
> abis? :)
I changed it to:
/* Addresses are loaded in different ways, depending on the address
size in use and the ABI. N32_ABI uses additions with overflow
checking, this allows to catch code generation errors which would
distort the proper sign extension of the 64-bit wide registers. */
#define ADDRESS_ADD_INSN \
(HAVE_32BIT_ADDRESSES ? (HAVE_NEWABI ? "add" : "addu") : "daddu")
#define ADDRESS_ADDI_INSN \
(HAVE_32BIT_ADDRESSES ? (HAVE_NEWABI ? "addi" : "addiu") : "daddiu")
#define ADDRESS_LOAD_INSN \
(HAVE_32BIT_ADDRESSES ? "lw" : "ld")
#define ADDRESS_STORE_INSN \
(HAVE_32BIT_ADDRESSES ? "sw" : "sd")
Thiemo
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] MIPS gas: Cleanup address insn conditionals
2003-06-16 12:11 ` Thiemo Seufer
@ 2003-06-16 13:15 ` Maciej W. Rozycki
2003-06-16 14:02 ` Thiemo Seufer
0 siblings, 1 reply; 13+ messages in thread
From: Maciej W. Rozycki @ 2003-06-16 13:15 UTC (permalink / raw)
To: Thiemo Seufer; +Cc: Eric Christopher, binutils
On Mon, 16 Jun 2003, Thiemo Seufer wrote:
> I changed it to:
>
> /* Addresses are loaded in different ways, depending on the address
> size in use and the ABI. N32_ABI uses additions with overflow
> checking, this allows to catch code generation errors which would
> distort the proper sign extension of the 64-bit wide registers. */
> #define ADDRESS_ADD_INSN \
> (HAVE_32BIT_ADDRESSES ? (HAVE_NEWABI ? "add" : "addu") : "daddu")
>
> #define ADDRESS_ADDI_INSN \
> (HAVE_32BIT_ADDRESSES ? (HAVE_NEWABI ? "addi" : "addiu") : "daddiu")
Hmm, this effectively disables addresses in the ranges of 0x7fff8000 -
0x7fffffff and 0xffff8000 - 0xffffffff for certain operations for the n32
ABI. The latter is probably out of the scope of the ABI, but the former
certainly is not. Does any of the ABI documents contain any specific
comment on a special treatment of the range? Why do you think such an
overflow check should be done -- what advantages are there? Certainly
"addu" and "addiu" cannot result in improper sign-extension of low 32-bit
halfs of registers.
--
+ Maciej W. Rozycki, Technical University of Gdansk, Poland +
+--------------------------------------------------------------+
+ e-mail: macro@ds2.pg.gda.pl, PGP key available +
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] MIPS gas: Cleanup address insn conditionals
2003-06-16 13:15 ` Maciej W. Rozycki
@ 2003-06-16 14:02 ` Thiemo Seufer
2003-06-16 14:30 ` Maciej W. Rozycki
0 siblings, 1 reply; 13+ messages in thread
From: Thiemo Seufer @ 2003-06-16 14:02 UTC (permalink / raw)
To: Maciej W. Rozycki; +Cc: Eric Christopher, binutils
Maciej W. Rozycki wrote:
> On Mon, 16 Jun 2003, Thiemo Seufer wrote:
>
> > I changed it to:
> >
> > /* Addresses are loaded in different ways, depending on the address
> > size in use and the ABI. N32_ABI uses additions with overflow
> > checking, this allows to catch code generation errors which would
> > distort the proper sign extension of the 64-bit wide registers. */
> > #define ADDRESS_ADD_INSN \
> > (HAVE_32BIT_ADDRESSES ? (HAVE_NEWABI ? "add" : "addu") : "daddu")
> >
> > #define ADDRESS_ADDI_INSN \
> > (HAVE_32BIT_ADDRESSES ? (HAVE_NEWABI ? "addi" : "addiu") : "daddiu")
>
> Hmm, this effectively disables addresses in the ranges of 0x7fff8000 -
> 0x7fffffff and 0xffff8000 - 0xffffffff for certain operations for the n32
> ABI. The latter is probably out of the scope of the ABI, but the former
> certainly is not.
Well, IRIX works this way, and the n32 ABI documentation mandates the
use of add/addi.
> Does any of the ABI documents contain any specific
> comment on a special treatment of the range? Why do you think such an
> overflow check should be done -- what advantages are there? Certainly
> "addu" and "addiu" cannot result in improper sign-extension of low 32-bit
> halfs of registers.
Right, the idea of catching improper sign-extension was only valid
for n64 (where it isn't done). I'll fix the comment.
Thiemo
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] MIPS gas: Cleanup address insn conditionals
2003-06-16 14:02 ` Thiemo Seufer
@ 2003-06-16 14:30 ` Maciej W. Rozycki
2003-06-20 4:14 ` Thiemo Seufer
0 siblings, 1 reply; 13+ messages in thread
From: Maciej W. Rozycki @ 2003-06-16 14:30 UTC (permalink / raw)
To: Thiemo Seufer; +Cc: Eric Christopher, binutils
On Mon, 16 Jun 2003, Thiemo Seufer wrote:
> > Hmm, this effectively disables addresses in the ranges of 0x7fff8000 -
> > 0x7fffffff and 0xffff8000 - 0xffffffff for certain operations for the n32
> > ABI. The latter is probably out of the scope of the ABI, but the former
> > certainly is not.
>
> Well, IRIX works this way, and the n32 ABI documentation mandates the
> use of add/addi.
The only n32 reference I have is "MIPSPro N32 ABI Handbook" and it indeed
uses trapping instructions, namely "add" and "sub", but only for address
arithmetics and not loading. Which seems to make more sense; actually
regardless of the ABI used. But only a little, as such a trap would only
be of any use for a kernel; for userland an address error exception would
be triggered if the resulting address was ever used. And that's the job
of a compiler, not gas, anyway.
> > Does any of the ABI documents contain any specific
> > comment on a special treatment of the range? Why do you think such an
> > overflow check should be done -- what advantages are there? Certainly
> > "addu" and "addiu" cannot result in improper sign-extension of low 32-bit
> > halfs of registers.
>
> Right, the idea of catching improper sign-extension was only valid
> for n64 (where it isn't done). I'll fix the comment.
Well, then the same note applies to 0x7fffffffffff8000 -
0x7fffffffffffffff (invalid for old 64-bit processors such as R4k or R10k,
but perfectly fine for the MIPS64 ISA) and 0xffffffffffff8000 -
0xffffffffffffffff. I fail to see any advantage for trapping on address
loads for these, too.
--
+ Maciej W. Rozycki, Technical University of Gdansk, Poland +
+--------------------------------------------------------------+
+ e-mail: macro@ds2.pg.gda.pl, PGP key available +
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] MIPS gas: Cleanup address insn conditionals
2003-06-16 14:30 ` Maciej W. Rozycki
@ 2003-06-20 4:14 ` Thiemo Seufer
2003-06-20 17:38 ` Alexandre Oliva
0 siblings, 1 reply; 13+ messages in thread
From: Thiemo Seufer @ 2003-06-20 4:14 UTC (permalink / raw)
To: Maciej W. Rozycki; +Cc: Alexandre Oliva, Eric Christopher, binutils
Maciej W. Rozycki wrote:
> On Mon, 16 Jun 2003, Thiemo Seufer wrote:
>
> > > Hmm, this effectively disables addresses in the ranges of 0x7fff8000 -
> > > 0x7fffffff and 0xffff8000 - 0xffffffff for certain operations for the n32
> > > ABI. The latter is probably out of the scope of the ABI, but the former
> > > certainly is not.
> >
> > Well, IRIX works this way, and the n32 ABI documentation mandates the
> > use of add/addi.
>
> The only n32 reference I have is "MIPSPro N32 ABI Handbook" and it indeed
> uses trapping instructions, namely "add" and "sub", but only for address
> arithmetics and not loading. Which seems to make more sense; actually
> regardless of the ABI used. But only a little, as such a trap would only
> be of any use for a kernel; for userland an address error exception would
> be triggered if the resulting address was ever used. And that's the job
> of a compiler, not gas, anyway.
I have to correct myself: IRIX works _not_ that way. It happily uses the
non-overflowing variants, and sys/asm.h doesn't distinguish between o32
and n32 WRT.
> > > Does any of the ABI documents contain any specific
> > > comment on a special treatment of the range? Why do you think such an
> > > overflow check should be done -- what advantages are there? Certainly
> > > "addu" and "addiu" cannot result in improper sign-extension of low 32-bit
> > > halfs of registers.
> >
> > Right, the idea of catching improper sign-extension was only valid
> > for n64 (where it isn't done). I'll fix the comment.
>
> Well, then the same note applies to 0x7fffffffffff8000 -
> 0x7fffffffffffffff (invalid for old 64-bit processors such as R4k or R10k,
> but perfectly fine for the MIPS64 ISA) and 0xffffffffffff8000 -
> 0xffffffffffffffff. I fail to see any advantage for trapping on address
> loads for these, too.
Well, AFAICS there actually isn't much benefit, a kernel or standalone
program could probably trap address overflows easier, but even that
sounds a bit dubious.
Alexandre, when you changed the NewABI addressing, was there a reason
for it besides the N32 ABI Handbook?
Thiemo
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] MIPS gas: Cleanup address insn conditionals
2003-06-20 4:14 ` Thiemo Seufer
@ 2003-06-20 17:38 ` Alexandre Oliva
2003-06-20 23:12 ` Thiemo Seufer
0 siblings, 1 reply; 13+ messages in thread
From: Alexandre Oliva @ 2003-06-20 17:38 UTC (permalink / raw)
To: Thiemo Seufer; +Cc: Maciej W. Rozycki, Eric Christopher, binutils
On Jun 20, 2003, Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de> wrote:
> Alexandre, when you changed the NewABI addressing, was there a reason
> for it besides the N32 ABI Handbook?
Nope.
--
Alexandre Oliva Enjoy Guarana', see http://www.ic.unicamp.br/~oliva/
Red Hat GCC Developer aoliva@{redhat.com, gcc.gnu.org}
CS PhD student at IC-Unicamp oliva@{lsd.ic.unicamp.br, gnu.org}
Free Software Evangelist Professional serial bug killer
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] MIPS gas: Cleanup address insn conditionals
2003-06-20 17:38 ` Alexandre Oliva
@ 2003-06-20 23:12 ` Thiemo Seufer
2003-06-26 22:16 ` Eric Christopher
0 siblings, 1 reply; 13+ messages in thread
From: Thiemo Seufer @ 2003-06-20 23:12 UTC (permalink / raw)
To: Alexandre Oliva; +Cc: Maciej W. Rozycki, Eric Christopher, binutils
Alexandre Oliva wrote:
> On Jun 20, 2003, Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de> wrote:
>
> > Alexandre, when you changed the NewABI addressing, was there a reason
> > for it besides the N32 ABI Handbook?
>
> Nope.
Then I'd like to remove the n32 special handling.
Thiemo
2003-06-21 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
/gas/ChangeLog
* config/tc-mips.c (ADDRESS_ADD_INSN,ADDRESS_ADDI_INSN): Remove
special handling for n32 ABI.
(macro): Likewise.
/gas/testsuite/ChangeLog
* gas/mips/elf-rel-got-n32.d: Remove special handling for n32 ABI.
* gas/mips/elf-rel-xgot-n32.d: Likewise.
* gas/mips/jal-newabi.d: Likewise.
/ld/testsuite/ChangeLog
* ld-mips-elf/elf-rel-got-n32.d: Remove special handling for n32 ABI.
* ld-mips-elf/elf-rel-xgot-n32.d: Likewise.
diff -BurpNX /bigdisk/src/gcc-exclude source-orig/gas/config/tc-mips.c source/gas/config/tc-mips.c
--- source-orig/gas/config/tc-mips.c Fri Jun 20 23:52:56 2003
+++ source/gas/config/tc-mips.c Sat Jun 21 00:25:19 2003
@@ -300,15 +300,14 @@ static int mips_32bitmode = 0;
#define HAVE_64BIT_ADDRESS_CONSTANTS (HAVE_64BIT_ADDRESSES \
|| HAVE_64BIT_GPRS)
-/* Addresses are loaded in different ways, depending on the address
- size in use and the ABI. N32_ABI uses additions with overflow
- checking, this allows to catch code generation errors which would
- distort the proper sign extension of the 64-bit wide registers. */
+/* Addresses are loaded in different ways, depending on the address size
+ in use. The n32 ABI Documentation also mandates the use of additions
+ with overflow checking, but existing implementations don't follow it. */
#define ADDRESS_ADD_INSN \
- (HAVE_32BIT_ADDRESSES ? (HAVE_NEWABI ? "add" : "addu") : "daddu")
+ (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
#define ADDRESS_ADDI_INSN \
- (HAVE_32BIT_ADDRESSES ? (HAVE_NEWABI ? "addi" : "addiu") : "daddiu")
+ (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
#define ADDRESS_LOAD_INSN \
(HAVE_32BIT_ADDRESSES ? "lw" : "ld")
@@ -4851,8 +4850,7 @@ macro (ip)
&& offset_expr.X_add_number < 0x8000)
{
macro_build ((char *) NULL, &icnt, &offset_expr,
- (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" :
- HAVE_NEWABI ? "addi" : "addiu",
+ (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
"t,r,j", treg, sreg, (int) BFD_RELOC_LO16);
return;
}
@@ -5618,8 +5616,7 @@ macro (ip)
char *s;
if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
- s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" :
- HAVE_NEWABI ? "add" : "addu";
+ s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
else
s = ADDRESS_ADD_INSN;
@@ -6063,7 +6060,7 @@ macro (ip)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
|| ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? HAVE_NEWABI ? "add" : "addu" : "daddu"),
+ ? "addu" : "daddu"),
"d,v,t", tempreg, tempreg, breg);
macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, treg,
(int) BFD_RELOC_PCREL_LO16, tempreg);
diff -BurpNX /bigdisk/src/gcc-exclude source-orig/gas/testsuite/gas/mips/elf-rel-got-n32.d source/gas/testsuite/gas/mips/elf-rel-got-n32.d
--- source-orig/gas/testsuite/gas/mips/elf-rel-got-n32.d Fri Apr 11 03:56:51 2003
+++ source/gas/testsuite/gas/mips/elf-rel-got-n32.d Sat Jun 21 00:01:23 2003
@@ -9,25 +9,25 @@ Disassembly of section \.text:
0: R_MIPS_GOT_DISP dg1
00000004 <fn\+0x4> 8f850000 lw a1,0\(gp\)
4: R_MIPS_GOT_DISP dg1
-00000008 <fn\+0x8> 20a5000c addi a1,a1,12
+00000008 <fn\+0x8> 24a5000c addiu a1,a1,12
0000000c <fn\+0xc> 8f850000 lw a1,0\(gp\)
c: R_MIPS_GOT_DISP dg1
00000010 <fn\+0x10> 3c010002 lui at,0x2
-00000014 <fn\+0x14> 2021e240 addi at,at,-7616
-00000018 <fn\+0x18> 00a12820 add a1,a1,at
+00000014 <fn\+0x14> 2421e240 addiu at,at,-7616
+00000018 <fn\+0x18> 00a12821 addu a1,a1,at
0000001c <fn\+0x1c> 8f850000 lw a1,0\(gp\)
1c: R_MIPS_GOT_DISP dg1
-00000020 <fn\+0x20> 00b12820 add a1,a1,s1
+00000020 <fn\+0x20> 00b12821 addu a1,a1,s1
00000024 <fn\+0x24> 8f850000 lw a1,0\(gp\)
24: R_MIPS_GOT_DISP dg1
-00000028 <fn\+0x28> 20a5000c addi a1,a1,12
-0000002c <fn\+0x2c> 00b12820 add a1,a1,s1
+00000028 <fn\+0x28> 24a5000c addiu a1,a1,12
+0000002c <fn\+0x2c> 00b12821 addu a1,a1,s1
00000030 <fn\+0x30> 8f850000 lw a1,0\(gp\)
30: R_MIPS_GOT_DISP dg1
00000034 <fn\+0x34> 3c010002 lui at,0x2
-00000038 <fn\+0x38> 2021e240 addi at,at,-7616
-0000003c <fn\+0x3c> 00a12820 add a1,a1,at
-00000040 <fn\+0x40> 00b12820 add a1,a1,s1
+00000038 <fn\+0x38> 2421e240 addiu at,at,-7616
+0000003c <fn\+0x3c> 00a12821 addu a1,a1,at
+00000040 <fn\+0x40> 00b12821 addu a1,a1,s1
00000044 <fn\+0x44> 8f850000 lw a1,0\(gp\)
44: R_MIPS_GOT_PAGE dg1
00000048 <fn\+0x48> 8ca50000 lw a1,0\(a1\)
@@ -38,22 +38,22 @@ Disassembly of section \.text:
50: R_MIPS_GOT_OFST dg1\+0xc
00000054 <fn\+0x54> 8f850000 lw a1,0\(gp\)
54: R_MIPS_GOT_PAGE dg1
-00000058 <fn\+0x58> 00b12820 add a1,a1,s1
+00000058 <fn\+0x58> 00b12821 addu a1,a1,s1
0000005c <fn\+0x5c> 8ca50000 lw a1,0\(a1\)
5c: R_MIPS_GOT_OFST dg1
00000060 <fn\+0x60> 8f850000 lw a1,0\(gp\)
60: R_MIPS_GOT_PAGE dg1\+0xc
-00000064 <fn\+0x64> 00b12820 add a1,a1,s1
+00000064 <fn\+0x64> 00b12821 addu a1,a1,s1
00000068 <fn\+0x68> 8ca50000 lw a1,0\(a1\)
68: R_MIPS_GOT_OFST dg1\+0xc
0000006c <fn\+0x6c> 8f810000 lw at,0\(gp\)
6c: R_MIPS_GOT_PAGE dg1\+0x22
-00000070 <fn\+0x70> 00250820 add at,at,a1
+00000070 <fn\+0x70> 00250821 addu at,at,a1
00000074 <fn\+0x74> 8c250000 lw a1,0\(at\)
74: R_MIPS_GOT_OFST dg1\+0x22
00000078 <fn\+0x78> 8f810000 lw at,0\(gp\)
78: R_MIPS_GOT_PAGE dg1\+0x38
-0000007c <fn\+0x7c> 00250820 add at,at,a1
+0000007c <fn\+0x7c> 00250821 addu at,at,a1
00000080 <fn\+0x80> ac250000 sw a1,0\(at\)
80: R_MIPS_GOT_OFST dg1\+0x38
00000084 <fn\+0x84> 8f810000 lw at,0\(gp\)
@@ -62,30 +62,30 @@ Disassembly of section \.text:
0000008c <fn\+0x8c> 98250003 lwr a1,3\(at\)
00000090 <fn\+0x90> 8f810000 lw at,0\(gp\)
90: R_MIPS_GOT_DISP dg1
-00000094 <fn\+0x94> 2021000c addi at,at,12
+00000094 <fn\+0x94> 2421000c addiu at,at,12
00000098 <fn\+0x98> 88250000 lwl a1,0\(at\)
0000009c <fn\+0x9c> 98250003 lwr a1,3\(at\)
000000a0 <fn\+0xa0> 8f810000 lw at,0\(gp\)
a0: R_MIPS_GOT_DISP dg1
-000000a4 <fn\+0xa4> 00310820 add at,at,s1
+000000a4 <fn\+0xa4> 00310821 addu at,at,s1
000000a8 <fn\+0xa8> 88250000 lwl a1,0\(at\)
000000ac <fn\+0xac> 98250003 lwr a1,3\(at\)
000000b0 <fn\+0xb0> 8f810000 lw at,0\(gp\)
b0: R_MIPS_GOT_DISP dg1
-000000b4 <fn\+0xb4> 2021000c addi at,at,12
-000000b8 <fn\+0xb8> 00310820 add at,at,s1
+000000b4 <fn\+0xb4> 2421000c addiu at,at,12
+000000b8 <fn\+0xb8> 00310821 addu at,at,s1
000000bc <fn\+0xbc> 88250000 lwl a1,0\(at\)
000000c0 <fn\+0xc0> 98250003 lwr a1,3\(at\)
000000c4 <fn\+0xc4> 8f810000 lw at,0\(gp\)
c4: R_MIPS_GOT_DISP dg1
-000000c8 <fn\+0xc8> 20210022 addi at,at,34
-000000cc <fn\+0xcc> 00250820 add at,at,a1
+000000c8 <fn\+0xc8> 24210022 addiu at,at,34
+000000cc <fn\+0xcc> 00250821 addu at,at,a1
000000d0 <fn\+0xd0> 88250000 lwl a1,0\(at\)
000000d4 <fn\+0xd4> 98250003 lwr a1,3\(at\)
000000d8 <fn\+0xd8> 8f810000 lw at,0\(gp\)
d8: R_MIPS_GOT_DISP dg1
-000000dc <fn\+0xdc> 20210038 addi at,at,56
-000000e0 <fn\+0xe0> 00250820 add at,at,a1
+000000dc <fn\+0xdc> 24210038 addiu at,at,56
+000000e0 <fn\+0xe0> 00250821 addu at,at,a1
000000e4 <fn\+0xe4> a8250000 swl a1,0\(at\)
000000e8 <fn\+0xe8> b8250003 swr a1,3\(at\)
000000ec <fn\+0xec> 8f850000 lw a1,0\(gp\)
@@ -96,13 +96,13 @@ Disassembly of section \.text:
f4: R_MIPS_GOT_DISP \.data\+0x1e27c
000000f8 <fn\+0xf8> 8f850000 lw a1,0\(gp\)
f8: R_MIPS_GOT_DISP \.data\+0x3c
-000000fc <fn\+0xfc> 00b12820 add a1,a1,s1
+000000fc <fn\+0xfc> 00b12821 addu a1,a1,s1
00000100 <fn\+0x100> 8f850000 lw a1,0\(gp\)
100: R_MIPS_GOT_DISP \.data\+0x48
-00000104 <fn\+0x104> 00b12820 add a1,a1,s1
+00000104 <fn\+0x104> 00b12821 addu a1,a1,s1
00000108 <fn\+0x108> 8f850000 lw a1,0\(gp\)
108: R_MIPS_GOT_DISP \.data\+0x1e27c
-0000010c <fn\+0x10c> 00b12820 add a1,a1,s1
+0000010c <fn\+0x10c> 00b12821 addu a1,a1,s1
00000110 <fn\+0x110> 8f850000 lw a1,0\(gp\)
110: R_MIPS_GOT_PAGE \.data\+0x3c
00000114 <fn\+0x114> 8ca50000 lw a1,0\(a1\)
@@ -113,22 +113,22 @@ Disassembly of section \.text:
11c: R_MIPS_GOT_OFST \.data\+0x48
00000120 <fn\+0x120> 8f850000 lw a1,0\(gp\)
120: R_MIPS_GOT_PAGE \.data\+0x3c
-00000124 <fn\+0x124> 00b12820 add a1,a1,s1
+00000124 <fn\+0x124> 00b12821 addu a1,a1,s1
00000128 <fn\+0x128> 8ca50000 lw a1,0\(a1\)
128: R_MIPS_GOT_OFST \.data\+0x3c
0000012c <fn\+0x12c> 8f850000 lw a1,0\(gp\)
12c: R_MIPS_GOT_PAGE \.data\+0x48
-00000130 <fn\+0x130> 00b12820 add a1,a1,s1
+00000130 <fn\+0x130> 00b12821 addu a1,a1,s1
00000134 <fn\+0x134> 8ca50000 lw a1,0\(a1\)
134: R_MIPS_GOT_OFST \.data\+0x48
00000138 <fn\+0x138> 8f810000 lw at,0\(gp\)
138: R_MIPS_GOT_PAGE \.data\+0x5e
-0000013c <fn\+0x13c> 00250820 add at,at,a1
+0000013c <fn\+0x13c> 00250821 addu at,at,a1
00000140 <fn\+0x140> 8c250000 lw a1,0\(at\)
140: R_MIPS_GOT_OFST \.data\+0x5e
00000144 <fn\+0x144> 8f810000 lw at,0\(gp\)
144: R_MIPS_GOT_PAGE \.data\+0x74
-00000148 <fn\+0x148> 00250820 add at,at,a1
+00000148 <fn\+0x148> 00250821 addu at,at,a1
0000014c <fn\+0x14c> ac250000 sw a1,0\(at\)
14c: R_MIPS_GOT_OFST \.data\+0x74
00000150 <fn\+0x150> 8f810000 lw at,0\(gp\)
@@ -141,22 +141,22 @@ Disassembly of section \.text:
00000164 <fn\+0x164> 98250003 lwr a1,3\(at\)
00000168 <fn\+0x168> 8f810000 lw at,0\(gp\)
168: R_MIPS_GOT_DISP \.data\+0x3c
-0000016c <fn\+0x16c> 00310820 add at,at,s1
+0000016c <fn\+0x16c> 00310821 addu at,at,s1
00000170 <fn\+0x170> 88250000 lwl a1,0\(at\)
00000174 <fn\+0x174> 98250003 lwr a1,3\(at\)
00000178 <fn\+0x178> 8f810000 lw at,0\(gp\)
178: R_MIPS_GOT_DISP \.data\+0x48
-0000017c <fn\+0x17c> 00310820 add at,at,s1
+0000017c <fn\+0x17c> 00310821 addu at,at,s1
00000180 <fn\+0x180> 88250000 lwl a1,0\(at\)
00000184 <fn\+0x184> 98250003 lwr a1,3\(at\)
00000188 <fn\+0x188> 8f810000 lw at,0\(gp\)
188: R_MIPS_GOT_DISP \.data\+0x5e
-0000018c <fn\+0x18c> 00250820 add at,at,a1
+0000018c <fn\+0x18c> 00250821 addu at,at,a1
00000190 <fn\+0x190> 88250000 lwl a1,0\(at\)
00000194 <fn\+0x194> 98250003 lwr a1,3\(at\)
00000198 <fn\+0x198> 8f810000 lw at,0\(gp\)
198: R_MIPS_GOT_DISP \.data\+0x74
-0000019c <fn\+0x19c> 00250820 add at,at,a1
+0000019c <fn\+0x19c> 00250821 addu at,at,a1
000001a0 <fn\+0x1a0> a8250000 swl a1,0\(at\)
000001a4 <fn\+0x1a4> b8250003 swr a1,3\(at\)
000001a8 <fn\+0x1a8> 8f850000 lw a1,0\(gp\)
@@ -181,25 +181,25 @@ Disassembly of section \.text:
1d0: R_MIPS_GOT_DISP dg2
000001d4 <fn\+0x1d4> 8f850000 lw a1,0\(gp\)
1d4: R_MIPS_GOT_DISP dg2
-000001d8 <fn\+0x1d8> 20a5000c addi a1,a1,12
+000001d8 <fn\+0x1d8> 24a5000c addiu a1,a1,12
000001dc <fn\+0x1dc> 8f850000 lw a1,0\(gp\)
1dc: R_MIPS_GOT_DISP dg2
000001e0 <fn\+0x1e0> 3c010002 lui at,0x2
-000001e4 <fn\+0x1e4> 2021e240 addi at,at,-7616
-000001e8 <fn\+0x1e8> 00a12820 add a1,a1,at
+000001e4 <fn\+0x1e4> 2421e240 addiu at,at,-7616
+000001e8 <fn\+0x1e8> 00a12821 addu a1,a1,at
000001ec <fn\+0x1ec> 8f850000 lw a1,0\(gp\)
1ec: R_MIPS_GOT_DISP dg2
-000001f0 <fn\+0x1f0> 00b12820 add a1,a1,s1
+000001f0 <fn\+0x1f0> 00b12821 addu a1,a1,s1
000001f4 <fn\+0x1f4> 8f850000 lw a1,0\(gp\)
1f4: R_MIPS_GOT_DISP dg2
-000001f8 <fn\+0x1f8> 20a5000c addi a1,a1,12
-000001fc <fn\+0x1fc> 00b12820 add a1,a1,s1
+000001f8 <fn\+0x1f8> 24a5000c addiu a1,a1,12
+000001fc <fn\+0x1fc> 00b12821 addu a1,a1,s1
00000200 <fn\+0x200> 8f850000 lw a1,0\(gp\)
200: R_MIPS_GOT_DISP dg2
00000204 <fn\+0x204> 3c010002 lui at,0x2
-00000208 <fn\+0x208> 2021e240 addi at,at,-7616
-0000020c <fn\+0x20c> 00a12820 add a1,a1,at
-00000210 <fn\+0x210> 00b12820 add a1,a1,s1
+00000208 <fn\+0x208> 2421e240 addiu at,at,-7616
+0000020c <fn\+0x20c> 00a12821 addu a1,a1,at
+00000210 <fn\+0x210> 00b12821 addu a1,a1,s1
00000214 <fn\+0x214> 8f850000 lw a1,0\(gp\)
214: R_MIPS_GOT_PAGE dg2
00000218 <fn\+0x218> 8ca50000 lw a1,0\(a1\)
@@ -210,22 +210,22 @@ Disassembly of section \.text:
220: R_MIPS_GOT_OFST dg2\+0xc
00000224 <fn\+0x224> 8f850000 lw a1,0\(gp\)
224: R_MIPS_GOT_PAGE dg2
-00000228 <fn\+0x228> 00b12820 add a1,a1,s1
+00000228 <fn\+0x228> 00b12821 addu a1,a1,s1
0000022c <fn\+0x22c> 8ca50000 lw a1,0\(a1\)
22c: R_MIPS_GOT_OFST dg2
00000230 <fn\+0x230> 8f850000 lw a1,0\(gp\)
230: R_MIPS_GOT_PAGE dg2\+0xc
-00000234 <fn\+0x234> 00b12820 add a1,a1,s1
+00000234 <fn\+0x234> 00b12821 addu a1,a1,s1
00000238 <fn\+0x238> 8ca50000 lw a1,0\(a1\)
238: R_MIPS_GOT_OFST dg2\+0xc
0000023c <fn\+0x23c> 8f810000 lw at,0\(gp\)
23c: R_MIPS_GOT_PAGE dg2\+0x22
-00000240 <fn\+0x240> 00250820 add at,at,a1
+00000240 <fn\+0x240> 00250821 addu at,at,a1
00000244 <fn\+0x244> 8c250000 lw a1,0\(at\)
244: R_MIPS_GOT_OFST dg2\+0x22
00000248 <fn\+0x248> 8f810000 lw at,0\(gp\)
248: R_MIPS_GOT_PAGE dg2\+0x38
-0000024c <fn\+0x24c> 00250820 add at,at,a1
+0000024c <fn\+0x24c> 00250821 addu at,at,a1
00000250 <fn\+0x250> ac250000 sw a1,0\(at\)
250: R_MIPS_GOT_OFST dg2\+0x38
00000254 <fn\+0x254> 8f810000 lw at,0\(gp\)
@@ -234,30 +234,30 @@ Disassembly of section \.text:
0000025c <fn\+0x25c> 98250003 lwr a1,3\(at\)
00000260 <fn\+0x260> 8f810000 lw at,0\(gp\)
260: R_MIPS_GOT_DISP dg2
-00000264 <fn\+0x264> 2021000c addi at,at,12
+00000264 <fn\+0x264> 2421000c addiu at,at,12
00000268 <fn\+0x268> 88250000 lwl a1,0\(at\)
0000026c <fn\+0x26c> 98250003 lwr a1,3\(at\)
00000270 <fn\+0x270> 8f810000 lw at,0\(gp\)
270: R_MIPS_GOT_DISP dg2
-00000274 <fn\+0x274> 00310820 add at,at,s1
+00000274 <fn\+0x274> 00310821 addu at,at,s1
00000278 <fn\+0x278> 88250000 lwl a1,0\(at\)
0000027c <fn\+0x27c> 98250003 lwr a1,3\(at\)
00000280 <fn\+0x280> 8f810000 lw at,0\(gp\)
280: R_MIPS_GOT_DISP dg2
-00000284 <fn\+0x284> 2021000c addi at,at,12
-00000288 <fn\+0x288> 00310820 add at,at,s1
+00000284 <fn\+0x284> 2421000c addiu at,at,12
+00000288 <fn\+0x288> 00310821 addu at,at,s1
0000028c <fn\+0x28c> 88250000 lwl a1,0\(at\)
00000290 <fn\+0x290> 98250003 lwr a1,3\(at\)
00000294 <fn\+0x294> 8f810000 lw at,0\(gp\)
294: R_MIPS_GOT_DISP dg2
-00000298 <fn\+0x298> 20210022 addi at,at,34
-0000029c <fn\+0x29c> 00250820 add at,at,a1
+00000298 <fn\+0x298> 24210022 addiu at,at,34
+0000029c <fn\+0x29c> 00250821 addu at,at,a1
000002a0 <fn\+0x2a0> 88250000 lwl a1,0\(at\)
000002a4 <fn\+0x2a4> 98250003 lwr a1,3\(at\)
000002a8 <fn\+0x2a8> 8f810000 lw at,0\(gp\)
2a8: R_MIPS_GOT_DISP dg2
-000002ac <fn\+0x2ac> 20210038 addi at,at,56
-000002b0 <fn\+0x2b0> 00250820 add at,at,a1
+000002ac <fn\+0x2ac> 24210038 addiu at,at,56
+000002b0 <fn\+0x2b0> 00250821 addu at,at,a1
000002b4 <fn\+0x2b4> a8250000 swl a1,0\(at\)
000002b8 <fn\+0x2b8> b8250003 swr a1,3\(at\)
000002bc <fn\+0x2bc> 8f850000 lw a1,0\(gp\)
@@ -268,13 +268,13 @@ Disassembly of section \.text:
2c4: R_MIPS_GOT_DISP \.data\+0x1e2f4
000002c8 <fn\+0x2c8> 8f850000 lw a1,0\(gp\)
2c8: R_MIPS_GOT_DISP \.data\+0xb4
-000002cc <fn\+0x2cc> 00b12820 add a1,a1,s1
+000002cc <fn\+0x2cc> 00b12821 addu a1,a1,s1
000002d0 <fn\+0x2d0> 8f850000 lw a1,0\(gp\)
2d0: R_MIPS_GOT_DISP \.data\+0xc0
-000002d4 <fn\+0x2d4> 00b12820 add a1,a1,s1
+000002d4 <fn\+0x2d4> 00b12821 addu a1,a1,s1
000002d8 <fn\+0x2d8> 8f850000 lw a1,0\(gp\)
2d8: R_MIPS_GOT_DISP \.data\+0x1e2f4
-000002dc <fn\+0x2dc> 00b12820 add a1,a1,s1
+000002dc <fn\+0x2dc> 00b12821 addu a1,a1,s1
000002e0 <fn\+0x2e0> 8f850000 lw a1,0\(gp\)
2e0: R_MIPS_GOT_PAGE \.data\+0xb4
000002e4 <fn\+0x2e4> 8ca50000 lw a1,0\(a1\)
@@ -285,22 +285,22 @@ Disassembly of section \.text:
2ec: R_MIPS_GOT_OFST \.data\+0xc0
000002f0 <fn\+0x2f0> 8f850000 lw a1,0\(gp\)
2f0: R_MIPS_GOT_PAGE \.data\+0xb4
-000002f4 <fn\+0x2f4> 00b12820 add a1,a1,s1
+000002f4 <fn\+0x2f4> 00b12821 addu a1,a1,s1
000002f8 <fn\+0x2f8> 8ca50000 lw a1,0\(a1\)
2f8: R_MIPS_GOT_OFST \.data\+0xb4
000002fc <fn\+0x2fc> 8f850000 lw a1,0\(gp\)
2fc: R_MIPS_GOT_PAGE \.data\+0xc0
-00000300 <fn\+0x300> 00b12820 add a1,a1,s1
+00000300 <fn\+0x300> 00b12821 addu a1,a1,s1
00000304 <fn\+0x304> 8ca50000 lw a1,0\(a1\)
304: R_MIPS_GOT_OFST \.data\+0xc0
00000308 <fn\+0x308> 8f810000 lw at,0\(gp\)
308: R_MIPS_GOT_PAGE \.data\+0xd6
-0000030c <fn\+0x30c> 00250820 add at,at,a1
+0000030c <fn\+0x30c> 00250821 addu at,at,a1
00000310 <fn\+0x310> 8c250000 lw a1,0\(at\)
310: R_MIPS_GOT_OFST \.data\+0xd6
00000314 <fn\+0x314> 8f810000 lw at,0\(gp\)
314: R_MIPS_GOT_PAGE \.data\+0xec
-00000318 <fn\+0x318> 00250820 add at,at,a1
+00000318 <fn\+0x318> 00250821 addu at,at,a1
0000031c <fn\+0x31c> ac250000 sw a1,0\(at\)
31c: R_MIPS_GOT_OFST \.data\+0xec
00000320 <fn\+0x320> 8f810000 lw at,0\(gp\)
@@ -313,22 +313,22 @@ Disassembly of section \.text:
00000334 <fn\+0x334> 98250003 lwr a1,3\(at\)
00000338 <fn\+0x338> 8f810000 lw at,0\(gp\)
338: R_MIPS_GOT_DISP \.data\+0xb4
-0000033c <fn\+0x33c> 00310820 add at,at,s1
+0000033c <fn\+0x33c> 00310821 addu at,at,s1
00000340 <fn\+0x340> 88250000 lwl a1,0\(at\)
00000344 <fn\+0x344> 98250003 lwr a1,3\(at\)
00000348 <fn\+0x348> 8f810000 lw at,0\(gp\)
348: R_MIPS_GOT_DISP \.data\+0xc0
-0000034c <fn\+0x34c> 00310820 add at,at,s1
+0000034c <fn\+0x34c> 00310821 addu at,at,s1
00000350 <fn\+0x350> 88250000 lwl a1,0\(at\)
00000354 <fn\+0x354> 98250003 lwr a1,3\(at\)
00000358 <fn\+0x358> 8f810000 lw at,0\(gp\)
358: R_MIPS_GOT_DISP \.data\+0xd6
-0000035c <fn\+0x35c> 00250820 add at,at,a1
+0000035c <fn\+0x35c> 00250821 addu at,at,a1
00000360 <fn\+0x360> 88250000 lwl a1,0\(at\)
00000364 <fn\+0x364> 98250003 lwr a1,3\(at\)
00000368 <fn\+0x368> 8f810000 lw at,0\(gp\)
368: R_MIPS_GOT_DISP \.data\+0xec
-0000036c <fn\+0x36c> 00250820 add at,at,a1
+0000036c <fn\+0x36c> 00250821 addu at,at,a1
00000370 <fn\+0x370> a8250000 swl a1,0\(at\)
00000374 <fn\+0x374> b8250003 swr a1,3\(at\)
00000378 <fn\+0x378> 8f850000 lw a1,0\(gp\)
@@ -380,7 +380,7 @@ Disassembly of section \.text:
3e8: R_MIPS_GOT_OFST \.data\+0x48
000003ec <fn\+0x3ec> 8f810000 lw at,0\(gp\)
3ec: R_MIPS_GOT_PAGE \.data\+0xd6
-000003f0 <fn\+0x3f0> 00250820 add at,at,a1
+000003f0 <fn\+0x3f0> 00250821 addu at,at,a1
000003f4 <fn\+0x3f4> 10000003 b 00000404 <fn2>
000003f8 <fn\+0x3f8> 8c250000 lw a1,0\(at\)
3f8: R_MIPS_GOT_OFST \.data\+0xd6
diff -BurpNX /bigdisk/src/gcc-exclude source-orig/gas/testsuite/gas/mips/elf-rel-xgot-n32.d source/gas/testsuite/gas/mips/elf-rel-xgot-n32.d
--- source-orig/gas/testsuite/gas/mips/elf-rel-xgot-n32.d Fri Apr 11 03:56:51 2003
+++ source/gas/testsuite/gas/mips/elf-rel-xgot-n32.d Sat Jun 21 00:06:18 2003
@@ -8,162 +8,162 @@
Disassembly of section \.text:
00000000 <fn> 3c050000 lui a1,0x0
0: R_MIPS_GOT_HI16 dg1
-00000004 <fn\+0x4> 00bc2820 add a1,a1,gp
+00000004 <fn\+0x4> 00bc2821 addu a1,a1,gp
00000008 <fn\+0x8> 8ca50000 lw a1,0\(a1\)
8: R_MIPS_GOT_LO16 dg1
0000000c <fn\+0xc> 3c050000 lui a1,0x0
c: R_MIPS_GOT_HI16 dg1
-00000010 <fn\+0x10> 00bc2820 add a1,a1,gp
+00000010 <fn\+0x10> 00bc2821 addu a1,a1,gp
00000014 <fn\+0x14> 8ca50000 lw a1,0\(a1\)
14: R_MIPS_GOT_LO16 dg1
-00000018 <fn\+0x18> 20a5000c addi a1,a1,12
+00000018 <fn\+0x18> 24a5000c addiu a1,a1,12
0000001c <fn\+0x1c> 3c050000 lui a1,0x0
1c: R_MIPS_GOT_HI16 dg1
-00000020 <fn\+0x20> 00bc2820 add a1,a1,gp
+00000020 <fn\+0x20> 00bc2821 addu a1,a1,gp
00000024 <fn\+0x24> 8ca50000 lw a1,0\(a1\)
24: R_MIPS_GOT_LO16 dg1
00000028 <fn\+0x28> 3c010002 lui at,0x2
-0000002c <fn\+0x2c> 2021e240 addi at,at,-7616
-00000030 <fn\+0x30> 00a12820 add a1,a1,at
+0000002c <fn\+0x2c> 2421e240 addiu at,at,-7616
+00000030 <fn\+0x30> 00a12821 addu a1,a1,at
00000034 <fn\+0x34> 3c050000 lui a1,0x0
34: R_MIPS_GOT_HI16 dg1
-00000038 <fn\+0x38> 00bc2820 add a1,a1,gp
+00000038 <fn\+0x38> 00bc2821 addu a1,a1,gp
0000003c <fn\+0x3c> 8ca50000 lw a1,0\(a1\)
3c: R_MIPS_GOT_LO16 dg1
-00000040 <fn\+0x40> 00b12820 add a1,a1,s1
+00000040 <fn\+0x40> 00b12821 addu a1,a1,s1
00000044 <fn\+0x44> 3c050000 lui a1,0x0
44: R_MIPS_GOT_HI16 dg1
-00000048 <fn\+0x48> 00bc2820 add a1,a1,gp
+00000048 <fn\+0x48> 00bc2821 addu a1,a1,gp
0000004c <fn\+0x4c> 8ca50000 lw a1,0\(a1\)
4c: R_MIPS_GOT_LO16 dg1
-00000050 <fn\+0x50> 20a5000c addi a1,a1,12
-00000054 <fn\+0x54> 00b12820 add a1,a1,s1
+00000050 <fn\+0x50> 24a5000c addiu a1,a1,12
+00000054 <fn\+0x54> 00b12821 addu a1,a1,s1
00000058 <fn\+0x58> 3c050000 lui a1,0x0
58: R_MIPS_GOT_HI16 dg1
-0000005c <fn\+0x5c> 00bc2820 add a1,a1,gp
+0000005c <fn\+0x5c> 00bc2821 addu a1,a1,gp
00000060 <fn\+0x60> 8ca50000 lw a1,0\(a1\)
60: R_MIPS_GOT_LO16 dg1
00000064 <fn\+0x64> 3c010002 lui at,0x2
-00000068 <fn\+0x68> 2021e240 addi at,at,-7616
-0000006c <fn\+0x6c> 00a12820 add a1,a1,at
-00000070 <fn\+0x70> 00b12820 add a1,a1,s1
+00000068 <fn\+0x68> 2421e240 addiu at,at,-7616
+0000006c <fn\+0x6c> 00a12821 addu a1,a1,at
+00000070 <fn\+0x70> 00b12821 addu a1,a1,s1
00000074 <fn\+0x74> 3c050000 lui a1,0x0
74: R_MIPS_GOT_HI16 dg1
-00000078 <fn\+0x78> 00bc2820 add a1,a1,gp
+00000078 <fn\+0x78> 00bc2821 addu a1,a1,gp
0000007c <fn\+0x7c> 8ca50000 lw a1,0\(a1\)
7c: R_MIPS_GOT_LO16 dg1
00000080 <fn\+0x80> 8ca50000 lw a1,0\(a1\)
00000084 <fn\+0x84> 3c050000 lui a1,0x0
84: R_MIPS_GOT_HI16 dg1
-00000088 <fn\+0x88> 00bc2820 add a1,a1,gp
+00000088 <fn\+0x88> 00bc2821 addu a1,a1,gp
0000008c <fn\+0x8c> 8ca50000 lw a1,0\(a1\)
8c: R_MIPS_GOT_LO16 dg1
00000090 <fn\+0x90> 8ca5000c lw a1,12\(a1\)
00000094 <fn\+0x94> 3c050000 lui a1,0x0
94: R_MIPS_GOT_HI16 dg1
-00000098 <fn\+0x98> 00bc2820 add a1,a1,gp
+00000098 <fn\+0x98> 00bc2821 addu a1,a1,gp
0000009c <fn\+0x9c> 8ca50000 lw a1,0\(a1\)
9c: R_MIPS_GOT_LO16 dg1
-000000a0 <fn\+0xa0> 00b12820 add a1,a1,s1
+000000a0 <fn\+0xa0> 00b12821 addu a1,a1,s1
000000a4 <fn\+0xa4> 8ca50000 lw a1,0\(a1\)
000000a8 <fn\+0xa8> 3c050000 lui a1,0x0
a8: R_MIPS_GOT_HI16 dg1
-000000ac <fn\+0xac> 00bc2820 add a1,a1,gp
+000000ac <fn\+0xac> 00bc2821 addu a1,a1,gp
000000b0 <fn\+0xb0> 8ca50000 lw a1,0\(a1\)
b0: R_MIPS_GOT_LO16 dg1
-000000b4 <fn\+0xb4> 00b12820 add a1,a1,s1
+000000b4 <fn\+0xb4> 00b12821 addu a1,a1,s1
000000b8 <fn\+0xb8> 8ca5000c lw a1,12\(a1\)
000000bc <fn\+0xbc> 3c010000 lui at,0x0
bc: R_MIPS_GOT_HI16 dg1
-000000c0 <fn\+0xc0> 003c0820 add at,at,gp
+000000c0 <fn\+0xc0> 003c0821 addu at,at,gp
000000c4 <fn\+0xc4> 8c210000 lw at,0\(at\)
c4: R_MIPS_GOT_LO16 dg1
-000000c8 <fn\+0xc8> 00250820 add at,at,a1
+000000c8 <fn\+0xc8> 00250821 addu at,at,a1
000000cc <fn\+0xcc> 8c250022 lw a1,34\(at\)
000000d0 <fn\+0xd0> 3c010000 lui at,0x0
d0: R_MIPS_GOT_HI16 dg1
-000000d4 <fn\+0xd4> 003c0820 add at,at,gp
+000000d4 <fn\+0xd4> 003c0821 addu at,at,gp
000000d8 <fn\+0xd8> 8c210000 lw at,0\(at\)
d8: R_MIPS_GOT_LO16 dg1
-000000dc <fn\+0xdc> 00250820 add at,at,a1
+000000dc <fn\+0xdc> 00250821 addu at,at,a1
000000e0 <fn\+0xe0> ac250038 sw a1,56\(at\)
000000e4 <fn\+0xe4> 3c010000 lui at,0x0
e4: R_MIPS_GOT_HI16 dg1
-000000e8 <fn\+0xe8> 003c0820 add at,at,gp
+000000e8 <fn\+0xe8> 003c0821 addu at,at,gp
000000ec <fn\+0xec> 8c210000 lw at,0\(at\)
ec: R_MIPS_GOT_LO16 dg1
000000f0 <fn\+0xf0> 88250000 lwl a1,0\(at\)
000000f4 <fn\+0xf4> 98250003 lwr a1,3\(at\)
000000f8 <fn\+0xf8> 3c010000 lui at,0x0
f8: R_MIPS_GOT_HI16 dg1
-000000fc <fn\+0xfc> 003c0820 add at,at,gp
+000000fc <fn\+0xfc> 003c0821 addu at,at,gp
00000100 <fn\+0x100> 8c210000 lw at,0\(at\)
100: R_MIPS_GOT_LO16 dg1
-00000104 <fn\+0x104> 2021000c addi at,at,12
+00000104 <fn\+0x104> 2421000c addiu at,at,12
00000108 <fn\+0x108> 88250000 lwl a1,0\(at\)
0000010c <fn\+0x10c> 98250003 lwr a1,3\(at\)
00000110 <fn\+0x110> 3c010000 lui at,0x0
110: R_MIPS_GOT_HI16 dg1
-00000114 <fn\+0x114> 003c0820 add at,at,gp
+00000114 <fn\+0x114> 003c0821 addu at,at,gp
00000118 <fn\+0x118> 8c210000 lw at,0\(at\)
118: R_MIPS_GOT_LO16 dg1
-0000011c <fn\+0x11c> 00310820 add at,at,s1
+0000011c <fn\+0x11c> 00310821 addu at,at,s1
00000120 <fn\+0x120> 88250000 lwl a1,0\(at\)
00000124 <fn\+0x124> 98250003 lwr a1,3\(at\)
00000128 <fn\+0x128> 3c010000 lui at,0x0
128: R_MIPS_GOT_HI16 dg1
-0000012c <fn\+0x12c> 003c0820 add at,at,gp
+0000012c <fn\+0x12c> 003c0821 addu at,at,gp
00000130 <fn\+0x130> 8c210000 lw at,0\(at\)
130: R_MIPS_GOT_LO16 dg1
-00000134 <fn\+0x134> 2021000c addi at,at,12
-00000138 <fn\+0x138> 00310820 add at,at,s1
+00000134 <fn\+0x134> 2421000c addiu at,at,12
+00000138 <fn\+0x138> 00310821 addu at,at,s1
0000013c <fn\+0x13c> 88250000 lwl a1,0\(at\)
00000140 <fn\+0x140> 98250003 lwr a1,3\(at\)
00000144 <fn\+0x144> 3c010000 lui at,0x0
144: R_MIPS_GOT_HI16 dg1
-00000148 <fn\+0x148> 003c0820 add at,at,gp
+00000148 <fn\+0x148> 003c0821 addu at,at,gp
0000014c <fn\+0x14c> 8c210000 lw at,0\(at\)
14c: R_MIPS_GOT_LO16 dg1
-00000150 <fn\+0x150> 20210022 addi at,at,34
-00000154 <fn\+0x154> 00250820 add at,at,a1
+00000150 <fn\+0x150> 24210022 addiu at,at,34
+00000154 <fn\+0x154> 00250821 addu at,at,a1
00000158 <fn\+0x158> 88250000 lwl a1,0\(at\)
0000015c <fn\+0x15c> 98250003 lwr a1,3\(at\)
00000160 <fn\+0x160> 3c010000 lui at,0x0
160: R_MIPS_GOT_HI16 dg1
-00000164 <fn\+0x164> 003c0820 add at,at,gp
+00000164 <fn\+0x164> 003c0821 addu at,at,gp
00000168 <fn\+0x168> 8c210000 lw at,0\(at\)
168: R_MIPS_GOT_LO16 dg1
-0000016c <fn\+0x16c> 20210038 addi at,at,56
-00000170 <fn\+0x170> 00250820 add at,at,a1
+0000016c <fn\+0x16c> 24210038 addiu at,at,56
+00000170 <fn\+0x170> 00250821 addu at,at,a1
00000174 <fn\+0x174> a8250000 swl a1,0\(at\)
00000178 <fn\+0x178> b8250003 swr a1,3\(at\)
0000017c <fn\+0x17c> 8f850000 lw a1,0\(gp\)
17c: R_MIPS_GOT_PAGE \.data\+0x3c
-00000180 <fn\+0x180> 20a50000 addi a1,a1,0
+00000180 <fn\+0x180> 24a50000 addiu a1,a1,0
180: R_MIPS_GOT_OFST \.data\+0x3c
00000184 <fn\+0x184> 8f850000 lw a1,0\(gp\)
184: R_MIPS_GOT_PAGE \.data\+0x48
-00000188 <fn\+0x188> 20a50000 addi a1,a1,0
+00000188 <fn\+0x188> 24a50000 addiu a1,a1,0
188: R_MIPS_GOT_OFST \.data\+0x48
0000018c <fn\+0x18c> 8f850000 lw a1,0\(gp\)
18c: R_MIPS_GOT_PAGE \.data\+0x1e27c
-00000190 <fn\+0x190> 20a50000 addi a1,a1,0
+00000190 <fn\+0x190> 24a50000 addiu a1,a1,0
190: R_MIPS_GOT_OFST \.data\+0x1e27c
00000194 <fn\+0x194> 8f850000 lw a1,0\(gp\)
194: R_MIPS_GOT_PAGE \.data\+0x3c
-00000198 <fn\+0x198> 20a50000 addi a1,a1,0
+00000198 <fn\+0x198> 24a50000 addiu a1,a1,0
198: R_MIPS_GOT_OFST \.data\+0x3c
-0000019c <fn\+0x19c> 00b12820 add a1,a1,s1
+0000019c <fn\+0x19c> 00b12821 addu a1,a1,s1
000001a0 <fn\+0x1a0> 8f850000 lw a1,0\(gp\)
1a0: R_MIPS_GOT_PAGE \.data\+0x48
-000001a4 <fn\+0x1a4> 20a50000 addi a1,a1,0
+000001a4 <fn\+0x1a4> 24a50000 addiu a1,a1,0
1a4: R_MIPS_GOT_OFST \.data\+0x48
-000001a8 <fn\+0x1a8> 00b12820 add a1,a1,s1
+000001a8 <fn\+0x1a8> 00b12821 addu a1,a1,s1
000001ac <fn\+0x1ac> 8f850000 lw a1,0\(gp\)
1ac: R_MIPS_GOT_PAGE \.data\+0x1e27c
-000001b0 <fn\+0x1b0> 20a50000 addi a1,a1,0
+000001b0 <fn\+0x1b0> 24a50000 addiu a1,a1,0
1b0: R_MIPS_GOT_OFST \.data\+0x1e27c
-000001b4 <fn\+0x1b4> 00b12820 add a1,a1,s1
+000001b4 <fn\+0x1b4> 00b12821 addu a1,a1,s1
000001b8 <fn\+0x1b8> 8f850000 lw a1,0\(gp\)
1b8: R_MIPS_GOT_PAGE \.data\+0x3c
000001bc <fn\+0x1bc> 8ca50000 lw a1,0\(a1\)
@@ -174,85 +174,85 @@ Disassembly of section \.text:
1c4: R_MIPS_GOT_OFST \.data\+0x48
000001c8 <fn\+0x1c8> 8f850000 lw a1,0\(gp\)
1c8: R_MIPS_GOT_PAGE \.data\+0x3c
-000001cc <fn\+0x1cc> 00b12820 add a1,a1,s1
+000001cc <fn\+0x1cc> 00b12821 addu a1,a1,s1
000001d0 <fn\+0x1d0> 8ca50000 lw a1,0\(a1\)
1d0: R_MIPS_GOT_OFST \.data\+0x3c
000001d4 <fn\+0x1d4> 8f850000 lw a1,0\(gp\)
1d4: R_MIPS_GOT_PAGE \.data\+0x48
-000001d8 <fn\+0x1d8> 00b12820 add a1,a1,s1
+000001d8 <fn\+0x1d8> 00b12821 addu a1,a1,s1
000001dc <fn\+0x1dc> 8ca50000 lw a1,0\(a1\)
1dc: R_MIPS_GOT_OFST \.data\+0x48
000001e0 <fn\+0x1e0> 8f810000 lw at,0\(gp\)
1e0: R_MIPS_GOT_PAGE \.data\+0x5e
-000001e4 <fn\+0x1e4> 00250820 add at,at,a1
+000001e4 <fn\+0x1e4> 00250821 addu at,at,a1
000001e8 <fn\+0x1e8> 8c250000 lw a1,0\(at\)
1e8: R_MIPS_GOT_OFST \.data\+0x5e
000001ec <fn\+0x1ec> 8f810000 lw at,0\(gp\)
1ec: R_MIPS_GOT_PAGE \.data\+0x74
-000001f0 <fn\+0x1f0> 00250820 add at,at,a1
+000001f0 <fn\+0x1f0> 00250821 addu at,at,a1
000001f4 <fn\+0x1f4> ac250000 sw a1,0\(at\)
1f4: R_MIPS_GOT_OFST \.data\+0x74
000001f8 <fn\+0x1f8> 8f810000 lw at,0\(gp\)
1f8: R_MIPS_GOT_PAGE \.data\+0x3c
-000001fc <fn\+0x1fc> 20210000 addi at,at,0
+000001fc <fn\+0x1fc> 24210000 addiu at,at,0
1fc: R_MIPS_GOT_OFST \.data\+0x3c
00000200 <fn\+0x200> 88250000 lwl a1,0\(at\)
00000204 <fn\+0x204> 98250003 lwr a1,3\(at\)
00000208 <fn\+0x208> 8f810000 lw at,0\(gp\)
208: R_MIPS_GOT_PAGE \.data\+0x48
-0000020c <fn\+0x20c> 20210000 addi at,at,0
+0000020c <fn\+0x20c> 24210000 addiu at,at,0
20c: R_MIPS_GOT_OFST \.data\+0x48
00000210 <fn\+0x210> 88250000 lwl a1,0\(at\)
00000214 <fn\+0x214> 98250003 lwr a1,3\(at\)
00000218 <fn\+0x218> 8f810000 lw at,0\(gp\)
218: R_MIPS_GOT_PAGE \.data\+0x3c
-0000021c <fn\+0x21c> 20210000 addi at,at,0
+0000021c <fn\+0x21c> 24210000 addiu at,at,0
21c: R_MIPS_GOT_OFST \.data\+0x3c
-00000220 <fn\+0x220> 00310820 add at,at,s1
+00000220 <fn\+0x220> 00310821 addu at,at,s1
00000224 <fn\+0x224> 88250000 lwl a1,0\(at\)
00000228 <fn\+0x228> 98250003 lwr a1,3\(at\)
0000022c <fn\+0x22c> 8f810000 lw at,0\(gp\)
22c: R_MIPS_GOT_PAGE \.data\+0x48
-00000230 <fn\+0x230> 20210000 addi at,at,0
+00000230 <fn\+0x230> 24210000 addiu at,at,0
230: R_MIPS_GOT_OFST \.data\+0x48
-00000234 <fn\+0x234> 00310820 add at,at,s1
+00000234 <fn\+0x234> 00310821 addu at,at,s1
00000238 <fn\+0x238> 88250000 lwl a1,0\(at\)
0000023c <fn\+0x23c> 98250003 lwr a1,3\(at\)
00000240 <fn\+0x240> 8f810000 lw at,0\(gp\)
240: R_MIPS_GOT_PAGE \.data\+0x5e
-00000244 <fn\+0x244> 20210000 addi at,at,0
+00000244 <fn\+0x244> 24210000 addiu at,at,0
244: R_MIPS_GOT_OFST \.data\+0x5e
-00000248 <fn\+0x248> 00250820 add at,at,a1
+00000248 <fn\+0x248> 00250821 addu at,at,a1
0000024c <fn\+0x24c> 88250000 lwl a1,0\(at\)
00000250 <fn\+0x250> 98250003 lwr a1,3\(at\)
00000254 <fn\+0x254> 8f810000 lw at,0\(gp\)
254: R_MIPS_GOT_PAGE \.data\+0x74
-00000258 <fn\+0x258> 20210000 addi at,at,0
+00000258 <fn\+0x258> 24210000 addiu at,at,0
258: R_MIPS_GOT_OFST \.data\+0x74
-0000025c <fn\+0x25c> 00250820 add at,at,a1
+0000025c <fn\+0x25c> 00250821 addu at,at,a1
00000260 <fn\+0x260> a8250000 swl a1,0\(at\)
00000264 <fn\+0x264> b8250003 swr a1,3\(at\)
00000268 <fn\+0x268> 3c050000 lui a1,0x0
268: R_MIPS_GOT_HI16 fn
-0000026c <fn\+0x26c> 00bc2820 add a1,a1,gp
+0000026c <fn\+0x26c> 00bc2821 addu a1,a1,gp
00000270 <fn\+0x270> 8ca50000 lw a1,0\(a1\)
270: R_MIPS_GOT_LO16 fn
00000274 <fn\+0x274> 8f850000 lw a1,0\(gp\)
274: R_MIPS_GOT_PAGE \.text
-00000278 <fn\+0x278> 20a50000 addi a1,a1,0
+00000278 <fn\+0x278> 24a50000 addiu a1,a1,0
278: R_MIPS_GOT_OFST \.text
0000027c <fn\+0x27c> 3c190000 lui t9,0x0
27c: R_MIPS_CALL_HI16 fn
-00000280 <fn\+0x280> 033cc820 add t9,t9,gp
+00000280 <fn\+0x280> 033cc821 addu t9,t9,gp
00000284 <fn\+0x284> 8f390000 lw t9,0\(t9\)
284: R_MIPS_CALL_LO16 fn
00000288 <fn\+0x288> 8f990000 lw t9,0\(gp\)
288: R_MIPS_GOT_PAGE \.text
-0000028c <fn\+0x28c> 23390000 addi t9,t9,0
+0000028c <fn\+0x28c> 27390000 addiu t9,t9,0
28c: R_MIPS_GOT_OFST \.text
00000290 <fn\+0x290> 3c190000 lui t9,0x0
290: R_MIPS_CALL_HI16 fn
-00000294 <fn\+0x294> 033cc820 add t9,t9,gp
+00000294 <fn\+0x294> 033cc821 addu t9,t9,gp
00000298 <fn\+0x298> 8f390000 lw t9,0\(t9\)
298: R_MIPS_CALL_LO16 fn
0000029c <fn\+0x29c> 0320f809 jalr t9
@@ -260,169 +260,169 @@ Disassembly of section \.text:
000002a0 <fn\+0x2a0> 00000000 nop
000002a4 <fn\+0x2a4> 8f990000 lw t9,0\(gp\)
2a4: R_MIPS_GOT_PAGE \.text
-000002a8 <fn\+0x2a8> 23390000 addi t9,t9,0
+000002a8 <fn\+0x2a8> 27390000 addiu t9,t9,0
2a8: R_MIPS_GOT_OFST \.text
000002ac <fn\+0x2ac> 0320f809 jalr t9
2ac: R_MIPS_JALR \.text
000002b0 <fn\+0x2b0> 00000000 nop
000002b4 <fn\+0x2b4> 3c050000 lui a1,0x0
2b4: R_MIPS_GOT_HI16 dg2
-000002b8 <fn\+0x2b8> 00bc2820 add a1,a1,gp
+000002b8 <fn\+0x2b8> 00bc2821 addu a1,a1,gp
000002bc <fn\+0x2bc> 8ca50000 lw a1,0\(a1\)
2bc: R_MIPS_GOT_LO16 dg2
000002c0 <fn\+0x2c0> 3c050000 lui a1,0x0
2c0: R_MIPS_GOT_HI16 dg2
-000002c4 <fn\+0x2c4> 00bc2820 add a1,a1,gp
+000002c4 <fn\+0x2c4> 00bc2821 addu a1,a1,gp
000002c8 <fn\+0x2c8> 8ca50000 lw a1,0\(a1\)
2c8: R_MIPS_GOT_LO16 dg2
-000002cc <fn\+0x2cc> 20a5000c addi a1,a1,12
+000002cc <fn\+0x2cc> 24a5000c addiu a1,a1,12
000002d0 <fn\+0x2d0> 3c050000 lui a1,0x0
2d0: R_MIPS_GOT_HI16 dg2
-000002d4 <fn\+0x2d4> 00bc2820 add a1,a1,gp
+000002d4 <fn\+0x2d4> 00bc2821 addu a1,a1,gp
000002d8 <fn\+0x2d8> 8ca50000 lw a1,0\(a1\)
2d8: R_MIPS_GOT_LO16 dg2
000002dc <fn\+0x2dc> 3c010002 lui at,0x2
-000002e0 <fn\+0x2e0> 2021e240 addi at,at,-7616
-000002e4 <fn\+0x2e4> 00a12820 add a1,a1,at
+000002e0 <fn\+0x2e0> 2421e240 addiu at,at,-7616
+000002e4 <fn\+0x2e4> 00a12821 addu a1,a1,at
000002e8 <fn\+0x2e8> 3c050000 lui a1,0x0
2e8: R_MIPS_GOT_HI16 dg2
-000002ec <fn\+0x2ec> 00bc2820 add a1,a1,gp
+000002ec <fn\+0x2ec> 00bc2821 addu a1,a1,gp
000002f0 <fn\+0x2f0> 8ca50000 lw a1,0\(a1\)
2f0: R_MIPS_GOT_LO16 dg2
-000002f4 <fn\+0x2f4> 00b12820 add a1,a1,s1
+000002f4 <fn\+0x2f4> 00b12821 addu a1,a1,s1
000002f8 <fn\+0x2f8> 3c050000 lui a1,0x0
2f8: R_MIPS_GOT_HI16 dg2
-000002fc <fn\+0x2fc> 00bc2820 add a1,a1,gp
+000002fc <fn\+0x2fc> 00bc2821 addu a1,a1,gp
00000300 <fn\+0x300> 8ca50000 lw a1,0\(a1\)
300: R_MIPS_GOT_LO16 dg2
-00000304 <fn\+0x304> 20a5000c addi a1,a1,12
-00000308 <fn\+0x308> 00b12820 add a1,a1,s1
+00000304 <fn\+0x304> 24a5000c addiu a1,a1,12
+00000308 <fn\+0x308> 00b12821 addu a1,a1,s1
0000030c <fn\+0x30c> 3c050000 lui a1,0x0
30c: R_MIPS_GOT_HI16 dg2
-00000310 <fn\+0x310> 00bc2820 add a1,a1,gp
+00000310 <fn\+0x310> 00bc2821 addu a1,a1,gp
00000314 <fn\+0x314> 8ca50000 lw a1,0\(a1\)
314: R_MIPS_GOT_LO16 dg2
00000318 <fn\+0x318> 3c010002 lui at,0x2
-0000031c <fn\+0x31c> 2021e240 addi at,at,-7616
-00000320 <fn\+0x320> 00a12820 add a1,a1,at
-00000324 <fn\+0x324> 00b12820 add a1,a1,s1
+0000031c <fn\+0x31c> 2421e240 addiu at,at,-7616
+00000320 <fn\+0x320> 00a12821 addu a1,a1,at
+00000324 <fn\+0x324> 00b12821 addu a1,a1,s1
00000328 <fn\+0x328> 3c050000 lui a1,0x0
328: R_MIPS_GOT_HI16 dg2
-0000032c <fn\+0x32c> 00bc2820 add a1,a1,gp
+0000032c <fn\+0x32c> 00bc2821 addu a1,a1,gp
00000330 <fn\+0x330> 8ca50000 lw a1,0\(a1\)
330: R_MIPS_GOT_LO16 dg2
00000334 <fn\+0x334> 8ca50000 lw a1,0\(a1\)
00000338 <fn\+0x338> 3c050000 lui a1,0x0
338: R_MIPS_GOT_HI16 dg2
-0000033c <fn\+0x33c> 00bc2820 add a1,a1,gp
+0000033c <fn\+0x33c> 00bc2821 addu a1,a1,gp
00000340 <fn\+0x340> 8ca50000 lw a1,0\(a1\)
340: R_MIPS_GOT_LO16 dg2
00000344 <fn\+0x344> 8ca5000c lw a1,12\(a1\)
00000348 <fn\+0x348> 3c050000 lui a1,0x0
348: R_MIPS_GOT_HI16 dg2
-0000034c <fn\+0x34c> 00bc2820 add a1,a1,gp
+0000034c <fn\+0x34c> 00bc2821 addu a1,a1,gp
00000350 <fn\+0x350> 8ca50000 lw a1,0\(a1\)
350: R_MIPS_GOT_LO16 dg2
-00000354 <fn\+0x354> 00b12820 add a1,a1,s1
+00000354 <fn\+0x354> 00b12821 addu a1,a1,s1
00000358 <fn\+0x358> 8ca50000 lw a1,0\(a1\)
0000035c <fn\+0x35c> 3c050000 lui a1,0x0
35c: R_MIPS_GOT_HI16 dg2
-00000360 <fn\+0x360> 00bc2820 add a1,a1,gp
+00000360 <fn\+0x360> 00bc2821 addu a1,a1,gp
00000364 <fn\+0x364> 8ca50000 lw a1,0\(a1\)
364: R_MIPS_GOT_LO16 dg2
-00000368 <fn\+0x368> 00b12820 add a1,a1,s1
+00000368 <fn\+0x368> 00b12821 addu a1,a1,s1
0000036c <fn\+0x36c> 8ca5000c lw a1,12\(a1\)
00000370 <fn\+0x370> 3c010000 lui at,0x0
370: R_MIPS_GOT_HI16 dg2
-00000374 <fn\+0x374> 003c0820 add at,at,gp
+00000374 <fn\+0x374> 003c0821 addu at,at,gp
00000378 <fn\+0x378> 8c210000 lw at,0\(at\)
378: R_MIPS_GOT_LO16 dg2
-0000037c <fn\+0x37c> 00250820 add at,at,a1
+0000037c <fn\+0x37c> 00250821 addu at,at,a1
00000380 <fn\+0x380> 8c250022 lw a1,34\(at\)
00000384 <fn\+0x384> 3c010000 lui at,0x0
384: R_MIPS_GOT_HI16 dg2
-00000388 <fn\+0x388> 003c0820 add at,at,gp
+00000388 <fn\+0x388> 003c0821 addu at,at,gp
0000038c <fn\+0x38c> 8c210000 lw at,0\(at\)
38c: R_MIPS_GOT_LO16 dg2
-00000390 <fn\+0x390> 00250820 add at,at,a1
+00000390 <fn\+0x390> 00250821 addu at,at,a1
00000394 <fn\+0x394> ac250038 sw a1,56\(at\)
00000398 <fn\+0x398> 3c010000 lui at,0x0
398: R_MIPS_GOT_HI16 dg2
-0000039c <fn\+0x39c> 003c0820 add at,at,gp
+0000039c <fn\+0x39c> 003c0821 addu at,at,gp
000003a0 <fn\+0x3a0> 8c210000 lw at,0\(at\)
3a0: R_MIPS_GOT_LO16 dg2
000003a4 <fn\+0x3a4> 88250000 lwl a1,0\(at\)
000003a8 <fn\+0x3a8> 98250003 lwr a1,3\(at\)
000003ac <fn\+0x3ac> 3c010000 lui at,0x0
3ac: R_MIPS_GOT_HI16 dg2
-000003b0 <fn\+0x3b0> 003c0820 add at,at,gp
+000003b0 <fn\+0x3b0> 003c0821 addu at,at,gp
000003b4 <fn\+0x3b4> 8c210000 lw at,0\(at\)
3b4: R_MIPS_GOT_LO16 dg2
-000003b8 <fn\+0x3b8> 2021000c addi at,at,12
+000003b8 <fn\+0x3b8> 2421000c addiu at,at,12
000003bc <fn\+0x3bc> 88250000 lwl a1,0\(at\)
000003c0 <fn\+0x3c0> 98250003 lwr a1,3\(at\)
000003c4 <fn\+0x3c4> 3c010000 lui at,0x0
3c4: R_MIPS_GOT_HI16 dg2
-000003c8 <fn\+0x3c8> 003c0820 add at,at,gp
+000003c8 <fn\+0x3c8> 003c0821 addu at,at,gp
000003cc <fn\+0x3cc> 8c210000 lw at,0\(at\)
3cc: R_MIPS_GOT_LO16 dg2
-000003d0 <fn\+0x3d0> 00310820 add at,at,s1
+000003d0 <fn\+0x3d0> 00310821 addu at,at,s1
000003d4 <fn\+0x3d4> 88250000 lwl a1,0\(at\)
000003d8 <fn\+0x3d8> 98250003 lwr a1,3\(at\)
000003dc <fn\+0x3dc> 3c010000 lui at,0x0
3dc: R_MIPS_GOT_HI16 dg2
-000003e0 <fn\+0x3e0> 003c0820 add at,at,gp
+000003e0 <fn\+0x3e0> 003c0821 addu at,at,gp
000003e4 <fn\+0x3e4> 8c210000 lw at,0\(at\)
3e4: R_MIPS_GOT_LO16 dg2
-000003e8 <fn\+0x3e8> 2021000c addi at,at,12
-000003ec <fn\+0x3ec> 00310820 add at,at,s1
+000003e8 <fn\+0x3e8> 2421000c addiu at,at,12
+000003ec <fn\+0x3ec> 00310821 addu at,at,s1
000003f0 <fn\+0x3f0> 88250000 lwl a1,0\(at\)
000003f4 <fn\+0x3f4> 98250003 lwr a1,3\(at\)
000003f8 <fn\+0x3f8> 3c010000 lui at,0x0
3f8: R_MIPS_GOT_HI16 dg2
-000003fc <fn\+0x3fc> 003c0820 add at,at,gp
+000003fc <fn\+0x3fc> 003c0821 addu at,at,gp
00000400 <fn\+0x400> 8c210000 lw at,0\(at\)
400: R_MIPS_GOT_LO16 dg2
-00000404 <fn\+0x404> 20210022 addi at,at,34
-00000408 <fn\+0x408> 00250820 add at,at,a1
+00000404 <fn\+0x404> 24210022 addiu at,at,34
+00000408 <fn\+0x408> 00250821 addu at,at,a1
0000040c <fn\+0x40c> 88250000 lwl a1,0\(at\)
00000410 <fn\+0x410> 98250003 lwr a1,3\(at\)
00000414 <fn\+0x414> 3c010000 lui at,0x0
414: R_MIPS_GOT_HI16 dg2
-00000418 <fn\+0x418> 003c0820 add at,at,gp
+00000418 <fn\+0x418> 003c0821 addu at,at,gp
0000041c <fn\+0x41c> 8c210000 lw at,0\(at\)
41c: R_MIPS_GOT_LO16 dg2
-00000420 <fn\+0x420> 20210038 addi at,at,56
-00000424 <fn\+0x424> 00250820 add at,at,a1
+00000420 <fn\+0x420> 24210038 addiu at,at,56
+00000424 <fn\+0x424> 00250821 addu at,at,a1
00000428 <fn\+0x428> a8250000 swl a1,0\(at\)
0000042c <fn\+0x42c> b8250003 swr a1,3\(at\)
00000430 <fn\+0x430> 8f850000 lw a1,0\(gp\)
430: R_MIPS_GOT_PAGE \.data\+0xb4
-00000434 <fn\+0x434> 20a50000 addi a1,a1,0
+00000434 <fn\+0x434> 24a50000 addiu a1,a1,0
434: R_MIPS_GOT_OFST \.data\+0xb4
00000438 <fn\+0x438> 8f850000 lw a1,0\(gp\)
438: R_MIPS_GOT_PAGE \.data\+0xc0
-0000043c <fn\+0x43c> 20a50000 addi a1,a1,0
+0000043c <fn\+0x43c> 24a50000 addiu a1,a1,0
43c: R_MIPS_GOT_OFST \.data\+0xc0
00000440 <fn\+0x440> 8f850000 lw a1,0\(gp\)
440: R_MIPS_GOT_PAGE \.data\+0x1e2f4
-00000444 <fn\+0x444> 20a50000 addi a1,a1,0
+00000444 <fn\+0x444> 24a50000 addiu a1,a1,0
444: R_MIPS_GOT_OFST \.data\+0x1e2f4
00000448 <fn\+0x448> 8f850000 lw a1,0\(gp\)
448: R_MIPS_GOT_PAGE \.data\+0xb4
-0000044c <fn\+0x44c> 20a50000 addi a1,a1,0
+0000044c <fn\+0x44c> 24a50000 addiu a1,a1,0
44c: R_MIPS_GOT_OFST \.data\+0xb4
-00000450 <fn\+0x450> 00b12820 add a1,a1,s1
+00000450 <fn\+0x450> 00b12821 addu a1,a1,s1
00000454 <fn\+0x454> 8f850000 lw a1,0\(gp\)
454: R_MIPS_GOT_PAGE \.data\+0xc0
-00000458 <fn\+0x458> 20a50000 addi a1,a1,0
+00000458 <fn\+0x458> 24a50000 addiu a1,a1,0
458: R_MIPS_GOT_OFST \.data\+0xc0
-0000045c <fn\+0x45c> 00b12820 add a1,a1,s1
+0000045c <fn\+0x45c> 00b12821 addu a1,a1,s1
00000460 <fn\+0x460> 8f850000 lw a1,0\(gp\)
460: R_MIPS_GOT_PAGE \.data\+0x1e2f4
-00000464 <fn\+0x464> 20a50000 addi a1,a1,0
+00000464 <fn\+0x464> 24a50000 addiu a1,a1,0
464: R_MIPS_GOT_OFST \.data\+0x1e2f4
-00000468 <fn\+0x468> 00b12820 add a1,a1,s1
+00000468 <fn\+0x468> 00b12821 addu a1,a1,s1
0000046c <fn\+0x46c> 8f850000 lw a1,0\(gp\)
46c: R_MIPS_GOT_PAGE \.data\+0xb4
00000470 <fn\+0x470> 8ca50000 lw a1,0\(a1\)
@@ -433,85 +433,85 @@ Disassembly of section \.text:
478: R_MIPS_GOT_OFST \.data\+0xc0
0000047c <fn\+0x47c> 8f850000 lw a1,0\(gp\)
47c: R_MIPS_GOT_PAGE \.data\+0xb4
-00000480 <fn\+0x480> 00b12820 add a1,a1,s1
+00000480 <fn\+0x480> 00b12821 addu a1,a1,s1
00000484 <fn\+0x484> 8ca50000 lw a1,0\(a1\)
484: R_MIPS_GOT_OFST \.data\+0xb4
00000488 <fn\+0x488> 8f850000 lw a1,0\(gp\)
488: R_MIPS_GOT_PAGE \.data\+0xc0
-0000048c <fn\+0x48c> 00b12820 add a1,a1,s1
+0000048c <fn\+0x48c> 00b12821 addu a1,a1,s1
00000490 <fn\+0x490> 8ca50000 lw a1,0\(a1\)
490: R_MIPS_GOT_OFST \.data\+0xc0
00000494 <fn\+0x494> 8f810000 lw at,0\(gp\)
494: R_MIPS_GOT_PAGE \.data\+0xb4
-00000498 <fn\+0x498> 00250820 add at,at,a1
+00000498 <fn\+0x498> 00250821 addu at,at,a1
0000049c <fn\+0x49c> 8c250000 lw a1,0\(at\)
49c: R_MIPS_GOT_OFST \.data\+0xb4
000004a0 <fn\+0x4a0> 8f810000 lw at,0\(gp\)
4a0: R_MIPS_GOT_PAGE \.data\+0xec
-000004a4 <fn\+0x4a4> 00250820 add at,at,a1
+000004a4 <fn\+0x4a4> 00250821 addu at,at,a1
000004a8 <fn\+0x4a8> ac250000 sw a1,0\(at\)
4a8: R_MIPS_GOT_OFST \.data\+0xec
000004ac <fn\+0x4ac> 8f810000 lw at,0\(gp\)
4ac: R_MIPS_GOT_PAGE \.data\+0xb4
-000004b0 <fn\+0x4b0> 20210000 addi at,at,0
+000004b0 <fn\+0x4b0> 24210000 addiu at,at,0
4b0: R_MIPS_GOT_OFST \.data\+0xb4
000004b4 <fn\+0x4b4> 88250000 lwl a1,0\(at\)
000004b8 <fn\+0x4b8> 98250003 lwr a1,3\(at\)
000004bc <fn\+0x4bc> 8f810000 lw at,0\(gp\)
4bc: R_MIPS_GOT_PAGE \.data\+0xc0
-000004c0 <fn\+0x4c0> 20210000 addi at,at,0
+000004c0 <fn\+0x4c0> 24210000 addiu at,at,0
4c0: R_MIPS_GOT_OFST \.data\+0xc0
000004c4 <fn\+0x4c4> 88250000 lwl a1,0\(at\)
000004c8 <fn\+0x4c8> 98250003 lwr a1,3\(at\)
000004cc <fn\+0x4cc> 8f810000 lw at,0\(gp\)
4cc: R_MIPS_GOT_PAGE \.data\+0xb4
-000004d0 <fn\+0x4d0> 20210000 addi at,at,0
+000004d0 <fn\+0x4d0> 24210000 addiu at,at,0
4d0: R_MIPS_GOT_OFST \.data\+0xb4
-000004d4 <fn\+0x4d4> 00310820 add at,at,s1
+000004d4 <fn\+0x4d4> 00310821 addu at,at,s1
000004d8 <fn\+0x4d8> 88250000 lwl a1,0\(at\)
000004dc <fn\+0x4dc> 98250003 lwr a1,3\(at\)
000004e0 <fn\+0x4e0> 8f810000 lw at,0\(gp\)
4e0: R_MIPS_GOT_PAGE \.data\+0xc0
-000004e4 <fn\+0x4e4> 20210000 addi at,at,0
+000004e4 <fn\+0x4e4> 24210000 addiu at,at,0
4e4: R_MIPS_GOT_OFST \.data\+0xc0
-000004e8 <fn\+0x4e8> 00310820 add at,at,s1
+000004e8 <fn\+0x4e8> 00310821 addu at,at,s1
000004ec <fn\+0x4ec> 88250000 lwl a1,0\(at\)
000004f0 <fn\+0x4f0> 98250003 lwr a1,3\(at\)
000004f4 <fn\+0x4f4> 8f810000 lw at,0\(gp\)
4f4: R_MIPS_GOT_PAGE \.data\+0xd6
-000004f8 <fn\+0x4f8> 20210000 addi at,at,0
+000004f8 <fn\+0x4f8> 24210000 addiu at,at,0
4f8: R_MIPS_GOT_OFST \.data\+0xd6
-000004fc <fn\+0x4fc> 00250820 add at,at,a1
+000004fc <fn\+0x4fc> 00250821 addu at,at,a1
00000500 <fn\+0x500> 88250000 lwl a1,0\(at\)
00000504 <fn\+0x504> 98250003 lwr a1,3\(at\)
00000508 <fn\+0x508> 8f810000 lw at,0\(gp\)
508: R_MIPS_GOT_PAGE \.data\+0xec
-0000050c <fn\+0x50c> 20210000 addi at,at,0
+0000050c <fn\+0x50c> 24210000 addiu at,at,0
50c: R_MIPS_GOT_OFST \.data\+0xec
-00000510 <fn\+0x510> 00250820 add at,at,a1
+00000510 <fn\+0x510> 00250821 addu at,at,a1
00000514 <fn\+0x514> a8250000 swl a1,0\(at\)
00000518 <fn\+0x518> b8250003 swr a1,3\(at\)
0000051c <fn\+0x51c> 3c050000 lui a1,0x0
51c: R_MIPS_GOT_HI16 fn2
-00000520 <fn\+0x520> 00bc2820 add a1,a1,gp
+00000520 <fn\+0x520> 00bc2821 addu a1,a1,gp
00000524 <fn\+0x524> 8ca50000 lw a1,0\(a1\)
524: R_MIPS_GOT_LO16 fn2
00000528 <fn\+0x528> 8f850000 lw a1,0\(gp\)
528: R_MIPS_GOT_PAGE \.text\+0x600
-0000052c <fn\+0x52c> 20a50000 addi a1,a1,0
+0000052c <fn\+0x52c> 24a50000 addiu a1,a1,0
52c: R_MIPS_GOT_OFST \.text\+0x600
00000530 <fn\+0x530> 3c190000 lui t9,0x0
530: R_MIPS_CALL_HI16 fn2
-00000534 <fn\+0x534> 033cc820 add t9,t9,gp
+00000534 <fn\+0x534> 033cc821 addu t9,t9,gp
00000538 <fn\+0x538> 8f390000 lw t9,0\(t9\)
538: R_MIPS_CALL_LO16 fn2
0000053c <fn\+0x53c> 8f990000 lw t9,0\(gp\)
53c: R_MIPS_GOT_PAGE \.text\+0x600
-00000540 <fn\+0x540> 23390000 addi t9,t9,0
+00000540 <fn\+0x540> 27390000 addiu t9,t9,0
540: R_MIPS_GOT_OFST \.text\+0x600
00000544 <fn\+0x544> 3c190000 lui t9,0x0
544: R_MIPS_CALL_HI16 fn2
-00000548 <fn\+0x548> 033cc820 add t9,t9,gp
+00000548 <fn\+0x548> 033cc821 addu t9,t9,gp
0000054c <fn\+0x54c> 8f390000 lw t9,0\(t9\)
54c: R_MIPS_CALL_LO16 fn2
00000550 <fn\+0x550> 0320f809 jalr t9
@@ -519,21 +519,21 @@ Disassembly of section \.text:
00000554 <fn\+0x554> 00000000 nop
00000558 <fn\+0x558> 8f990000 lw t9,0\(gp\)
558: R_MIPS_GOT_PAGE \.text\+0x600
-0000055c <fn\+0x55c> 23390000 addi t9,t9,0
+0000055c <fn\+0x55c> 27390000 addiu t9,t9,0
55c: R_MIPS_GOT_OFST \.text\+0x600
00000560 <fn\+0x560> 0320f809 jalr t9
560: R_MIPS_JALR \.text\+0x600
00000564 <fn\+0x564> 00000000 nop
00000568 <fn\+0x568> 3c050000 lui a1,0x0
568: R_MIPS_GOT_HI16 dg1
-0000056c <fn\+0x56c> 00bc2820 add a1,a1,gp
+0000056c <fn\+0x56c> 00bc2821 addu a1,a1,gp
00000570 <fn\+0x570> 8ca50000 lw a1,0\(a1\)
570: R_MIPS_GOT_LO16 dg1
00000574 <fn\+0x574> 1000fea2 b 00000000 <fn>
00000578 <fn\+0x578> 00000000 nop
0000057c <fn\+0x57c> 3c050000 lui a1,0x0
57c: R_MIPS_GOT_HI16 dg2
-00000580 <fn\+0x580> 00bc2820 add a1,a1,gp
+00000580 <fn\+0x580> 00bc2821 addu a1,a1,gp
00000584 <fn\+0x584> 8ca50000 lw a1,0\(a1\)
584: R_MIPS_GOT_LO16 dg2
00000588 <fn\+0x588> 8ca50000 lw a1,0\(a1\)
@@ -541,19 +541,19 @@ Disassembly of section \.text:
00000590 <fn\+0x590> 00000000 nop
00000594 <fn\+0x594> 8f850000 lw a1,0\(gp\)
594: R_MIPS_GOT_PAGE \.data\+0x3c
-00000598 <fn\+0x598> 20a50000 addi a1,a1,0
+00000598 <fn\+0x598> 24a50000 addiu a1,a1,0
598: R_MIPS_GOT_OFST \.data\+0x3c
0000059c <fn\+0x59c> 1000fe98 b 00000000 <fn>
000005a0 <fn\+0x5a0> 00000000 nop
000005a4 <fn\+0x5a4> 8f850000 lw a1,0\(gp\)
5a4: R_MIPS_GOT_PAGE \.data\+0xc0
-000005a8 <fn\+0x5a8> 20a50000 addi a1,a1,0
+000005a8 <fn\+0x5a8> 24a50000 addiu a1,a1,0
5a8: R_MIPS_GOT_OFST \.data\+0xc0
000005ac <fn\+0x5ac> 10000014 b 00000600 <fn2>
000005b0 <fn\+0x5b0> 00000000 nop
000005b4 <fn\+0x5b4> 8f850000 lw a1,0\(gp\)
5b4: R_MIPS_GOT_PAGE \.data\+0x1e27c
-000005b8 <fn\+0x5b8> 20a50000 addi a1,a1,0
+000005b8 <fn\+0x5b8> 24a50000 addiu a1,a1,0
5b8: R_MIPS_GOT_OFST \.data\+0x1e27c
000005bc <fn\+0x5bc> 1000fe90 b 00000000 <fn>
000005c0 <fn\+0x5c0> 00000000 nop
@@ -571,7 +571,7 @@ Disassembly of section \.text:
000005e0 <fn\+0x5e0> 00000000 nop
000005e4 <fn\+0x5e4> 8f810000 lw at,0\(gp\)
5e4: R_MIPS_GOT_PAGE \.data\+0xd6
-000005e8 <fn\+0x5e8> 00250820 add at,at,a1
+000005e8 <fn\+0x5e8> 00250821 addu at,at,a1
000005ec <fn\+0x5ec> 8c250000 lw a1,0\(at\)
5ec: R_MIPS_GOT_OFST \.data\+0xd6
000005f0 <fn\+0x5f0> 10000003 b 00000600 <fn2>
diff -BurpNX /bigdisk/src/gcc-exclude source-orig/gas/testsuite/gas/mips/jal-newabi.d source/gas/testsuite/gas/mips/jal-newabi.d
--- source-orig/gas/testsuite/gas/mips/jal-newabi.d Thu May 22 14:13:43 2003
+++ source/gas/testsuite/gas/mips/jal-newabi.d Fri Jun 20 23:57:10 2003
@@ -9,7 +9,7 @@ Disassembly of section \.text:
00000004 <label\+0x4> 34845678 ori a0,a0,0x5678
00000008 <label\+0x8> 8f990000 lw t9,0\(gp\)
8: R_MIPS_GOT_PAGE .text
-0000000c <label\+0xc> 23390000 addi t9,t9,0
+0000000c <label\+0xc> 27390000 addiu t9,t9,0
c: R_MIPS_GOT_OFST .text
00000010 <label\+0x10> 0320f809 jalr t9
10: R_MIPS_JALR .text
diff -BurpNX /bigdisk/src/gcc-exclude source-orig/ld/testsuite/ld-mips-elf/elf-rel-got-n32.d source/ld/testsuite/ld-mips-elf/elf-rel-got-n32.d
--- source-orig/ld/testsuite/ld-mips-elf/elf-rel-got-n32.d Fri Apr 11 03:56:49 2003
+++ source/ld/testsuite/ld-mips-elf/elf-rel-got-n32.d Fri Jun 20 23:14:03 2003
@@ -11,87 +11,87 @@ Disassembly of section \.text:
100000a0 <fn>:
100000a0: 8f858064 lw a1,-32668\(gp\)
100000a4: 8f858064 lw a1,-32668\(gp\)
-100000a8: 20a5000c addi a1,a1,12
+100000a8: 24a5000c addiu a1,a1,12
100000ac: 8f858064 lw a1,-32668\(gp\)
100000b0: 3c010002 lui at,0x2
-100000b4: 2021e240 addi at,at,-7616
-100000b8: 00a12820 add a1,a1,at
+100000b4: 2421e240 addiu at,at,-7616
+100000b8: 00a12821 addu a1,a1,at
100000bc: 8f858064 lw a1,-32668\(gp\)
-100000c0: 00b12820 add a1,a1,s1
+100000c0: 00b12821 addu a1,a1,s1
100000c4: 8f858064 lw a1,-32668\(gp\)
-100000c8: 20a5000c addi a1,a1,12
-100000cc: 00b12820 add a1,a1,s1
+100000c8: 24a5000c addiu a1,a1,12
+100000cc: 00b12821 addu a1,a1,s1
100000d0: 8f858064 lw a1,-32668\(gp\)
100000d4: 3c010002 lui at,0x2
-100000d8: 2021e240 addi at,at,-7616
-100000dc: 00a12820 add a1,a1,at
-100000e0: 00b12820 add a1,a1,s1
+100000d8: 2421e240 addiu at,at,-7616
+100000dc: 00a12821 addu a1,a1,at
+100000e0: 00b12821 addu a1,a1,s1
100000e4: 8f858064 lw a1,-32668\(gp\)
100000e8: 8ca50000 lw a1,0\(a1\)
100000ec: 8f858064 lw a1,-32668\(gp\)
100000f0: 8ca5000c lw a1,12\(a1\)
100000f4: 8f858064 lw a1,-32668\(gp\)
-100000f8: 00b12820 add a1,a1,s1
+100000f8: 00b12821 addu a1,a1,s1
100000fc: 8ca50000 lw a1,0\(a1\)
10000100: 8f858064 lw a1,-32668\(gp\)
-10000104: 00b12820 add a1,a1,s1
+10000104: 00b12821 addu a1,a1,s1
10000108: 8ca5000c lw a1,12\(a1\)
1000010c: 8f818064 lw at,-32668\(gp\)
-10000110: 00250820 add at,at,a1
+10000110: 00250821 addu at,at,a1
10000114: 8c250022 lw a1,34\(at\)
10000118: 8f818064 lw at,-32668\(gp\)
-1000011c: 00250820 add at,at,a1
+1000011c: 00250821 addu at,at,a1
10000120: ac250038 sw a1,56\(at\)
10000124: 8f818064 lw at,-32668\(gp\)
10000128: 88250000 lwl a1,0\(at\)
1000012c: 98250003 lwr a1,3\(at\)
10000130: 8f818064 lw at,-32668\(gp\)
-10000134: 2021000c addi at,at,12
+10000134: 2421000c addiu at,at,12
10000138: 88250000 lwl a1,0\(at\)
1000013c: 98250003 lwr a1,3\(at\)
10000140: 8f818064 lw at,-32668\(gp\)
-10000144: 00310820 add at,at,s1
+10000144: 00310821 addu at,at,s1
10000148: 88250000 lwl a1,0\(at\)
1000014c: 98250003 lwr a1,3\(at\)
10000150: 8f818064 lw at,-32668\(gp\)
-10000154: 2021000c addi at,at,12
-10000158: 00310820 add at,at,s1
+10000154: 2421000c addiu at,at,12
+10000158: 00310821 addu at,at,s1
1000015c: 88250000 lwl a1,0\(at\)
10000160: 98250003 lwr a1,3\(at\)
10000164: 8f818064 lw at,-32668\(gp\)
-10000168: 20210022 addi at,at,34
-1000016c: 00250820 add at,at,a1
+10000168: 24210022 addiu at,at,34
+1000016c: 00250821 addu at,at,a1
10000170: 88250000 lwl a1,0\(at\)
10000174: 98250003 lwr a1,3\(at\)
10000178: 8f818064 lw at,-32668\(gp\)
-1000017c: 20210038 addi at,at,56
-10000180: 00250820 add at,at,a1
+1000017c: 24210038 addiu at,at,56
+10000180: 00250821 addu at,at,a1
10000184: a8250000 swl a1,0\(at\)
10000188: b8250003 swr a1,3\(at\)
1000018c: 8f858018 lw a1,-32744\(gp\)
10000190: 8f85801c lw a1,-32740\(gp\)
10000194: 8f858020 lw a1,-32736\(gp\)
10000198: 8f858018 lw a1,-32744\(gp\)
-1000019c: 00b12820 add a1,a1,s1
+1000019c: 00b12821 addu a1,a1,s1
100001a0: 8f85801c lw a1,-32740\(gp\)
-100001a4: 00b12820 add a1,a1,s1
+100001a4: 00b12821 addu a1,a1,s1
100001a8: 8f858020 lw a1,-32736\(gp\)
-100001ac: 00b12820 add a1,a1,s1
+100001ac: 00b12821 addu a1,a1,s1
100001b0: 8f858024 lw a1,-32732\(gp\)
100001b4: 8ca5050c lw a1,1292\(a1\)
100001b8: 8f858024 lw a1,-32732\(gp\)
100001bc: 8ca50518 lw a1,1304\(a1\)
100001c0: 8f858024 lw a1,-32732\(gp\)
-100001c4: 00b12820 add a1,a1,s1
+100001c4: 00b12821 addu a1,a1,s1
100001c8: 8ca5050c lw a1,1292\(a1\)
100001cc: 8f858024 lw a1,-32732\(gp\)
-100001d0: 00b12820 add a1,a1,s1
+100001d0: 00b12821 addu a1,a1,s1
100001d4: 8ca50518 lw a1,1304\(a1\)
100001d8: 8f818024 lw at,-32732\(gp\)
-100001dc: 00250820 add at,at,a1
+100001dc: 00250821 addu at,at,a1
100001e0: 8c25052e lw a1,1326\(at\)
100001e4: 8f818024 lw at,-32732\(gp\)
-100001e8: 00250820 add at,at,a1
+100001e8: 00250821 addu at,at,a1
100001ec: ac250544 sw a1,1348\(at\)
100001f0: 8f818018 lw at,-32744\(gp\)
100001f4: 88250000 lwl a1,0\(at\)
@@ -100,19 +100,19 @@ Disassembly of section \.text:
10000200: 88250000 lwl a1,0\(at\)
10000204: 98250003 lwr a1,3\(at\)
10000208: 8f818018 lw at,-32744\(gp\)
-1000020c: 00310820 add at,at,s1
+1000020c: 00310821 addu at,at,s1
10000210: 88250000 lwl a1,0\(at\)
10000214: 98250003 lwr a1,3\(at\)
10000218: 8f81801c lw at,-32740\(gp\)
-1000021c: 00310820 add at,at,s1
+1000021c: 00310821 addu at,at,s1
10000220: 88250000 lwl a1,0\(at\)
10000224: 98250003 lwr a1,3\(at\)
10000228: 8f818028 lw at,-32728\(gp\)
-1000022c: 00250820 add at,at,a1
+1000022c: 00250821 addu at,at,a1
10000230: 88250000 lwl a1,0\(at\)
10000234: 98250003 lwr a1,3\(at\)
10000238: 8f81802c lw at,-32724\(gp\)
-1000023c: 00250820 add at,at,a1
+1000023c: 00250821 addu at,at,a1
10000240: a8250000 swl a1,0\(at\)
10000244: b8250003 swr a1,3\(at\)
10000248: 8f85805c lw a1,-32676\(gp\)
@@ -127,87 +127,87 @@ Disassembly of section \.text:
1000026c: 00000000 nop
10000270: 8f858068 lw a1,-32664\(gp\)
10000274: 8f858068 lw a1,-32664\(gp\)
-10000278: 20a5000c addi a1,a1,12
+10000278: 24a5000c addiu a1,a1,12
1000027c: 8f858068 lw a1,-32664\(gp\)
10000280: 3c010002 lui at,0x2
-10000284: 2021e240 addi at,at,-7616
-10000288: 00a12820 add a1,a1,at
+10000284: 2421e240 addiu at,at,-7616
+10000288: 00a12821 addu a1,a1,at
1000028c: 8f858068 lw a1,-32664\(gp\)
-10000290: 00b12820 add a1,a1,s1
+10000290: 00b12821 addu a1,a1,s1
10000294: 8f858068 lw a1,-32664\(gp\)
-10000298: 20a5000c addi a1,a1,12
-1000029c: 00b12820 add a1,a1,s1
+10000298: 24a5000c addiu a1,a1,12
+1000029c: 00b12821 addu a1,a1,s1
100002a0: 8f858068 lw a1,-32664\(gp\)
100002a4: 3c010002 lui at,0x2
-100002a8: 2021e240 addi at,at,-7616
-100002ac: 00a12820 add a1,a1,at
-100002b0: 00b12820 add a1,a1,s1
+100002a8: 2421e240 addiu at,at,-7616
+100002ac: 00a12821 addu a1,a1,at
+100002b0: 00b12821 addu a1,a1,s1
100002b4: 8f858068 lw a1,-32664\(gp\)
100002b8: 8ca50000 lw a1,0\(a1\)
100002bc: 8f858068 lw a1,-32664\(gp\)
100002c0: 8ca5000c lw a1,12\(a1\)
100002c4: 8f858068 lw a1,-32664\(gp\)
-100002c8: 00b12820 add a1,a1,s1
+100002c8: 00b12821 addu a1,a1,s1
100002cc: 8ca50000 lw a1,0\(a1\)
100002d0: 8f858068 lw a1,-32664\(gp\)
-100002d4: 00b12820 add a1,a1,s1
+100002d4: 00b12821 addu a1,a1,s1
100002d8: 8ca5000c lw a1,12\(a1\)
100002dc: 8f818068 lw at,-32664\(gp\)
-100002e0: 00250820 add at,at,a1
+100002e0: 00250821 addu at,at,a1
100002e4: 8c250022 lw a1,34\(at\)
100002e8: 8f818068 lw at,-32664\(gp\)
-100002ec: 00250820 add at,at,a1
+100002ec: 00250821 addu at,at,a1
100002f0: ac250038 sw a1,56\(at\)
100002f4: 8f818068 lw at,-32664\(gp\)
100002f8: 88250000 lwl a1,0\(at\)
100002fc: 98250003 lwr a1,3\(at\)
10000300: 8f818068 lw at,-32664\(gp\)
-10000304: 2021000c addi at,at,12
+10000304: 2421000c addiu at,at,12
10000308: 88250000 lwl a1,0\(at\)
1000030c: 98250003 lwr a1,3\(at\)
10000310: 8f818068 lw at,-32664\(gp\)
-10000314: 00310820 add at,at,s1
+10000314: 00310821 addu at,at,s1
10000318: 88250000 lwl a1,0\(at\)
1000031c: 98250003 lwr a1,3\(at\)
10000320: 8f818068 lw at,-32664\(gp\)
-10000324: 2021000c addi at,at,12
-10000328: 00310820 add at,at,s1
+10000324: 2421000c addiu at,at,12
+10000328: 00310821 addu at,at,s1
1000032c: 88250000 lwl a1,0\(at\)
10000330: 98250003 lwr a1,3\(at\)
10000334: 8f818068 lw at,-32664\(gp\)
-10000338: 20210022 addi at,at,34
-1000033c: 00250820 add at,at,a1
+10000338: 24210022 addiu at,at,34
+1000033c: 00250821 addu at,at,a1
10000340: 88250000 lwl a1,0\(at\)
10000344: 98250003 lwr a1,3\(at\)
10000348: 8f818068 lw at,-32664\(gp\)
-1000034c: 20210038 addi at,at,56
-10000350: 00250820 add at,at,a1
+1000034c: 24210038 addiu at,at,56
+10000350: 00250821 addu at,at,a1
10000354: a8250000 swl a1,0\(at\)
10000358: b8250003 swr a1,3\(at\)
1000035c: 8f858034 lw a1,-32716\(gp\)
10000360: 8f858038 lw a1,-32712\(gp\)
10000364: 8f85803c lw a1,-32708\(gp\)
10000368: 8f858034 lw a1,-32716\(gp\)
-1000036c: 00b12820 add a1,a1,s1
+1000036c: 00b12821 addu a1,a1,s1
10000370: 8f858038 lw a1,-32712\(gp\)
-10000374: 00b12820 add a1,a1,s1
+10000374: 00b12821 addu a1,a1,s1
10000378: 8f85803c lw a1,-32708\(gp\)
-1000037c: 00b12820 add a1,a1,s1
+1000037c: 00b12821 addu a1,a1,s1
10000380: 8f858024 lw a1,-32732\(gp\)
10000384: 8ca50584 lw a1,1412\(a1\)
10000388: 8f858024 lw a1,-32732\(gp\)
1000038c: 8ca50590 lw a1,1424\(a1\)
10000390: 8f858024 lw a1,-32732\(gp\)
-10000394: 00b12820 add a1,a1,s1
+10000394: 00b12821 addu a1,a1,s1
10000398: 8ca50584 lw a1,1412\(a1\)
1000039c: 8f858024 lw a1,-32732\(gp\)
-100003a0: 00b12820 add a1,a1,s1
+100003a0: 00b12821 addu a1,a1,s1
100003a4: 8ca50590 lw a1,1424\(a1\)
100003a8: 8f818024 lw at,-32732\(gp\)
-100003ac: 00250820 add at,at,a1
+100003ac: 00250821 addu at,at,a1
100003b0: 8c2505a6 lw a1,1446\(at\)
100003b4: 8f818024 lw at,-32732\(gp\)
-100003b8: 00250820 add at,at,a1
+100003b8: 00250821 addu at,at,a1
100003bc: ac2505bc sw a1,1468\(at\)
100003c0: 8f818034 lw at,-32716\(gp\)
100003c4: 88250000 lwl a1,0\(at\)
@@ -216,19 +216,19 @@ Disassembly of section \.text:
100003d0: 88250000 lwl a1,0\(at\)
100003d4: 98250003 lwr a1,3\(at\)
100003d8: 8f818034 lw at,-32716\(gp\)
-100003dc: 00310820 add at,at,s1
+100003dc: 00310821 addu at,at,s1
100003e0: 88250000 lwl a1,0\(at\)
100003e4: 98250003 lwr a1,3\(at\)
100003e8: 8f818038 lw at,-32712\(gp\)
-100003ec: 00310820 add at,at,s1
+100003ec: 00310821 addu at,at,s1
100003f0: 88250000 lwl a1,0\(at\)
100003f4: 98250003 lwr a1,3\(at\)
100003f8: 8f818040 lw at,-32704\(gp\)
-100003fc: 00250820 add at,at,a1
+100003fc: 00250821 addu at,at,a1
10000400: 88250000 lwl a1,0\(at\)
10000404: 98250003 lwr a1,3\(at\)
10000408: 8f818044 lw at,-32700\(gp\)
-1000040c: 00250820 add at,at,a1
+1000040c: 00250821 addu at,at,a1
10000410: a8250000 swl a1,0\(at\)
10000414: b8250003 swr a1,3\(at\)
10000418: 8f858060 lw a1,-32672\(gp\)
@@ -261,7 +261,7 @@ Disassembly of section \.text:
10000484: 1000ff06 b 100000a0 <fn>
10000488: 8ca50518 lw a1,1304\(a1\)
1000048c: 8f818024 lw at,-32732\(gp\)
-10000490: 00250820 add at,at,a1
+10000490: 00250821 addu at,at,a1
10000494: 10000003 b 100004a4 <fn2>
10000498: 8c2505a6 lw a1,1446\(at\)
\.\.\.
diff -BurpNX /bigdisk/src/gcc-exclude source-orig/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32.d source/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32.d
--- source-orig/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32.d Fri Apr 11 03:56:49 2003
+++ source/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32.d Fri Jun 20 23:39:00 2003
@@ -10,372 +10,372 @@ Disassembly of section \.text:
100000a0 <fn>:
100000a0: 3c050000 lui a1,0x0
-100000a4: 00bc2820 add a1,a1,gp
+100000a4: 00bc2821 addu a1,a1,gp
100000a8: 8ca58034 lw a1,-32716\(a1\)
100000ac: 3c050000 lui a1,0x0
-100000b0: 00bc2820 add a1,a1,gp
+100000b0: 00bc2821 addu a1,a1,gp
100000b4: 8ca58034 lw a1,-32716\(a1\)
-100000b8: 20a5000c addi a1,a1,12
+100000b8: 24a5000c addiu a1,a1,12
100000bc: 3c050000 lui a1,0x0
-100000c0: 00bc2820 add a1,a1,gp
+100000c0: 00bc2821 addu a1,a1,gp
100000c4: 8ca58034 lw a1,-32716\(a1\)
100000c8: 3c010002 lui at,0x2
-100000cc: 2021e240 addi at,at,-7616
-100000d0: 00a12820 add a1,a1,at
+100000cc: 2421e240 addiu at,at,-7616
+100000d0: 00a12821 addu a1,a1,at
100000d4: 3c050000 lui a1,0x0
-100000d8: 00bc2820 add a1,a1,gp
+100000d8: 00bc2821 addu a1,a1,gp
100000dc: 8ca58034 lw a1,-32716\(a1\)
-100000e0: 00b12820 add a1,a1,s1
+100000e0: 00b12821 addu a1,a1,s1
100000e4: 3c050000 lui a1,0x0
-100000e8: 00bc2820 add a1,a1,gp
+100000e8: 00bc2821 addu a1,a1,gp
100000ec: 8ca58034 lw a1,-32716\(a1\)
-100000f0: 20a5000c addi a1,a1,12
-100000f4: 00b12820 add a1,a1,s1
+100000f0: 24a5000c addiu a1,a1,12
+100000f4: 00b12821 addu a1,a1,s1
100000f8: 3c050000 lui a1,0x0
-100000fc: 00bc2820 add a1,a1,gp
+100000fc: 00bc2821 addu a1,a1,gp
10000100: 8ca58034 lw a1,-32716\(a1\)
10000104: 3c010002 lui at,0x2
-10000108: 2021e240 addi at,at,-7616
-1000010c: 00a12820 add a1,a1,at
-10000110: 00b12820 add a1,a1,s1
+10000108: 2421e240 addiu at,at,-7616
+1000010c: 00a12821 addu a1,a1,at
+10000110: 00b12821 addu a1,a1,s1
10000114: 3c050000 lui a1,0x0
-10000118: 00bc2820 add a1,a1,gp
+10000118: 00bc2821 addu a1,a1,gp
1000011c: 8ca58034 lw a1,-32716\(a1\)
10000120: 8ca50000 lw a1,0\(a1\)
10000124: 3c050000 lui a1,0x0
-10000128: 00bc2820 add a1,a1,gp
+10000128: 00bc2821 addu a1,a1,gp
1000012c: 8ca58034 lw a1,-32716\(a1\)
10000130: 8ca5000c lw a1,12\(a1\)
10000134: 3c050000 lui a1,0x0
-10000138: 00bc2820 add a1,a1,gp
+10000138: 00bc2821 addu a1,a1,gp
1000013c: 8ca58034 lw a1,-32716\(a1\)
-10000140: 00b12820 add a1,a1,s1
+10000140: 00b12821 addu a1,a1,s1
10000144: 8ca50000 lw a1,0\(a1\)
10000148: 3c050000 lui a1,0x0
-1000014c: 00bc2820 add a1,a1,gp
+1000014c: 00bc2821 addu a1,a1,gp
10000150: 8ca58034 lw a1,-32716\(a1\)
-10000154: 00b12820 add a1,a1,s1
+10000154: 00b12821 addu a1,a1,s1
10000158: 8ca5000c lw a1,12\(a1\)
1000015c: 3c010000 lui at,0x0
-10000160: 003c0820 add at,at,gp
+10000160: 003c0821 addu at,at,gp
10000164: 8c218034 lw at,-32716\(at\)
-10000168: 00250820 add at,at,a1
+10000168: 00250821 addu at,at,a1
1000016c: 8c250022 lw a1,34\(at\)
10000170: 3c010000 lui at,0x0
-10000174: 003c0820 add at,at,gp
+10000174: 003c0821 addu at,at,gp
10000178: 8c218034 lw at,-32716\(at\)
-1000017c: 00250820 add at,at,a1
+1000017c: 00250821 addu at,at,a1
10000180: ac250038 sw a1,56\(at\)
10000184: 3c010000 lui at,0x0
-10000188: 003c0820 add at,at,gp
+10000188: 003c0821 addu at,at,gp
1000018c: 8c218034 lw at,-32716\(at\)
10000190: 88250000 lwl a1,0\(at\)
10000194: 98250003 lwr a1,3\(at\)
10000198: 3c010000 lui at,0x0
-1000019c: 003c0820 add at,at,gp
+1000019c: 003c0821 addu at,at,gp
100001a0: 8c218034 lw at,-32716\(at\)
-100001a4: 2021000c addi at,at,12
+100001a4: 2421000c addiu at,at,12
100001a8: 88250000 lwl a1,0\(at\)
100001ac: 98250003 lwr a1,3\(at\)
100001b0: 3c010000 lui at,0x0
-100001b4: 003c0820 add at,at,gp
+100001b4: 003c0821 addu at,at,gp
100001b8: 8c218034 lw at,-32716\(at\)
-100001bc: 00310820 add at,at,s1
+100001bc: 00310821 addu at,at,s1
100001c0: 88250000 lwl a1,0\(at\)
100001c4: 98250003 lwr a1,3\(at\)
100001c8: 3c010000 lui at,0x0
-100001cc: 003c0820 add at,at,gp
+100001cc: 003c0821 addu at,at,gp
100001d0: 8c218034 lw at,-32716\(at\)
-100001d4: 2021000c addi at,at,12
-100001d8: 00310820 add at,at,s1
+100001d4: 2421000c addiu at,at,12
+100001d8: 00310821 addu at,at,s1
100001dc: 88250000 lwl a1,0\(at\)
100001e0: 98250003 lwr a1,3\(at\)
100001e4: 3c010000 lui at,0x0
-100001e8: 003c0820 add at,at,gp
+100001e8: 003c0821 addu at,at,gp
100001ec: 8c218034 lw at,-32716\(at\)
-100001f0: 20210022 addi at,at,34
-100001f4: 00250820 add at,at,a1
+100001f0: 24210022 addiu at,at,34
+100001f4: 00250821 addu at,at,a1
100001f8: 88250000 lwl a1,0\(at\)
100001fc: 98250003 lwr a1,3\(at\)
10000200: 3c010000 lui at,0x0
-10000204: 003c0820 add at,at,gp
+10000204: 003c0821 addu at,at,gp
10000208: 8c218034 lw at,-32716\(at\)
-1000020c: 20210038 addi at,at,56
-10000210: 00250820 add at,at,a1
+1000020c: 24210038 addiu at,at,56
+10000210: 00250821 addu at,at,a1
10000214: a8250000 swl a1,0\(at\)
10000218: b8250003 swr a1,3\(at\)
1000021c: 8f858018 lw a1,-32744\(gp\)
-10000220: 20a506fc addi a1,a1,1788
+10000220: 24a506fc addiu a1,a1,1788
10000224: 8f858018 lw a1,-32744\(gp\)
-10000228: 20a50708 addi a1,a1,1800
+10000228: 24a50708 addiu a1,a1,1800
1000022c: 8f85801c lw a1,-32740\(gp\)
-10000230: 20a5e93c addi a1,a1,-5828
+10000230: 24a5e93c addiu a1,a1,-5828
10000234: 8f858018 lw a1,-32744\(gp\)
-10000238: 20a506fc addi a1,a1,1788
-1000023c: 00b12820 add a1,a1,s1
+10000238: 24a506fc addiu a1,a1,1788
+1000023c: 00b12821 addu a1,a1,s1
10000240: 8f858018 lw a1,-32744\(gp\)
-10000244: 20a50708 addi a1,a1,1800
-10000248: 00b12820 add a1,a1,s1
+10000244: 24a50708 addiu a1,a1,1800
+10000248: 00b12821 addu a1,a1,s1
1000024c: 8f85801c lw a1,-32740\(gp\)
-10000250: 20a5e93c addi a1,a1,-5828
-10000254: 00b12820 add a1,a1,s1
+10000250: 24a5e93c addiu a1,a1,-5828
+10000254: 00b12821 addu a1,a1,s1
10000258: 8f858018 lw a1,-32744\(gp\)
1000025c: 8ca506fc lw a1,1788\(a1\)
10000260: 8f858018 lw a1,-32744\(gp\)
10000264: 8ca50708 lw a1,1800\(a1\)
10000268: 8f858018 lw a1,-32744\(gp\)
-1000026c: 00b12820 add a1,a1,s1
+1000026c: 00b12821 addu a1,a1,s1
10000270: 8ca506fc lw a1,1788\(a1\)
10000274: 8f858018 lw a1,-32744\(gp\)
-10000278: 00b12820 add a1,a1,s1
+10000278: 00b12821 addu a1,a1,s1
1000027c: 8ca50708 lw a1,1800\(a1\)
10000280: 8f818018 lw at,-32744\(gp\)
-10000284: 00250820 add at,at,a1
+10000284: 00250821 addu at,at,a1
10000288: 8c25071e lw a1,1822\(at\)
1000028c: 8f818018 lw at,-32744\(gp\)
-10000290: 00250820 add at,at,a1
+10000290: 00250821 addu at,at,a1
10000294: ac250734 sw a1,1844\(at\)
10000298: 8f818018 lw at,-32744\(gp\)
-1000029c: 202106fc addi at,at,1788
+1000029c: 242106fc addiu at,at,1788
100002a0: 88250000 lwl a1,0\(at\)
100002a4: 98250003 lwr a1,3\(at\)
100002a8: 8f818018 lw at,-32744\(gp\)
-100002ac: 20210708 addi at,at,1800
+100002ac: 24210708 addiu at,at,1800
100002b0: 88250000 lwl a1,0\(at\)
100002b4: 98250003 lwr a1,3\(at\)
100002b8: 8f818018 lw at,-32744\(gp\)
-100002bc: 202106fc addi at,at,1788
-100002c0: 00310820 add at,at,s1
+100002bc: 242106fc addiu at,at,1788
+100002c0: 00310821 addu at,at,s1
100002c4: 88250000 lwl a1,0\(at\)
100002c8: 98250003 lwr a1,3\(at\)
100002cc: 8f818018 lw at,-32744\(gp\)
-100002d0: 20210708 addi at,at,1800
-100002d4: 00310820 add at,at,s1
+100002d0: 24210708 addiu at,at,1800
+100002d4: 00310821 addu at,at,s1
100002d8: 88250000 lwl a1,0\(at\)
100002dc: 98250003 lwr a1,3\(at\)
100002e0: 8f818018 lw at,-32744\(gp\)
-100002e4: 2021071e addi at,at,1822
-100002e8: 00250820 add at,at,a1
+100002e4: 2421071e addiu at,at,1822
+100002e8: 00250821 addu at,at,a1
100002ec: 88250000 lwl a1,0\(at\)
100002f0: 98250003 lwr a1,3\(at\)
100002f4: 8f818018 lw at,-32744\(gp\)
-100002f8: 20210734 addi at,at,1844
-100002fc: 00250820 add at,at,a1
+100002f8: 24210734 addiu at,at,1844
+100002fc: 00250821 addu at,at,a1
10000300: a8250000 swl a1,0\(at\)
10000304: b8250003 swr a1,3\(at\)
10000308: 3c050000 lui a1,0x0
-1000030c: 00bc2820 add a1,a1,gp
+1000030c: 00bc2821 addu a1,a1,gp
10000310: 8ca5802c lw a1,-32724\(a1\)
10000314: 8f858020 lw a1,-32736\(gp\)
-10000318: 20a500a0 addi a1,a1,160
+10000318: 24a500a0 addiu a1,a1,160
1000031c: 3c190000 lui t9,0x0
-10000320: 033cc820 add t9,t9,gp
+10000320: 033cc821 addu t9,t9,gp
10000324: 8f39802c lw t9,-32724\(t9\)
10000328: 8f998020 lw t9,-32736\(gp\)
-1000032c: 233900a0 addi t9,t9,160
+1000032c: 273900a0 addiu t9,t9,160
10000330: 3c190000 lui t9,0x0
-10000334: 033cc820 add t9,t9,gp
+10000334: 033cc821 addu t9,t9,gp
10000338: 8f39802c lw t9,-32724\(t9\)
1000033c: 0320f809 jalr t9
10000340: 00000000 nop
10000344: 8f998020 lw t9,-32736\(gp\)
-10000348: 233900a0 addi t9,t9,160
+10000348: 273900a0 addiu t9,t9,160
1000034c: 0320f809 jalr t9
10000350: 00000000 nop
10000354: 3c050000 lui a1,0x0
-10000358: 00bc2820 add a1,a1,gp
+10000358: 00bc2821 addu a1,a1,gp
1000035c: 8ca58038 lw a1,-32712\(a1\)
10000360: 3c050000 lui a1,0x0
-10000364: 00bc2820 add a1,a1,gp
+10000364: 00bc2821 addu a1,a1,gp
10000368: 8ca58038 lw a1,-32712\(a1\)
-1000036c: 20a5000c addi a1,a1,12
+1000036c: 24a5000c addiu a1,a1,12
10000370: 3c050000 lui a1,0x0
-10000374: 00bc2820 add a1,a1,gp
+10000374: 00bc2821 addu a1,a1,gp
10000378: 8ca58038 lw a1,-32712\(a1\)
1000037c: 3c010002 lui at,0x2
-10000380: 2021e240 addi at,at,-7616
-10000384: 00a12820 add a1,a1,at
+10000380: 2421e240 addiu at,at,-7616
+10000384: 00a12821 addu a1,a1,at
10000388: 3c050000 lui a1,0x0
-1000038c: 00bc2820 add a1,a1,gp
+1000038c: 00bc2821 addu a1,a1,gp
10000390: 8ca58038 lw a1,-32712\(a1\)
-10000394: 00b12820 add a1,a1,s1
+10000394: 00b12821 addu a1,a1,s1
10000398: 3c050000 lui a1,0x0
-1000039c: 00bc2820 add a1,a1,gp
+1000039c: 00bc2821 addu a1,a1,gp
100003a0: 8ca58038 lw a1,-32712\(a1\)
-100003a4: 20a5000c addi a1,a1,12
-100003a8: 00b12820 add a1,a1,s1
+100003a4: 24a5000c addiu a1,a1,12
+100003a8: 00b12821 addu a1,a1,s1
100003ac: 3c050000 lui a1,0x0
-100003b0: 00bc2820 add a1,a1,gp
+100003b0: 00bc2821 addu a1,a1,gp
100003b4: 8ca58038 lw a1,-32712\(a1\)
100003b8: 3c010002 lui at,0x2
-100003bc: 2021e240 addi at,at,-7616
-100003c0: 00a12820 add a1,a1,at
-100003c4: 00b12820 add a1,a1,s1
+100003bc: 2421e240 addiu at,at,-7616
+100003c0: 00a12821 addu a1,a1,at
+100003c4: 00b12821 addu a1,a1,s1
100003c8: 3c050000 lui a1,0x0
-100003cc: 00bc2820 add a1,a1,gp
+100003cc: 00bc2821 addu a1,a1,gp
100003d0: 8ca58038 lw a1,-32712\(a1\)
100003d4: 8ca50000 lw a1,0\(a1\)
100003d8: 3c050000 lui a1,0x0
-100003dc: 00bc2820 add a1,a1,gp
+100003dc: 00bc2821 addu a1,a1,gp
100003e0: 8ca58038 lw a1,-32712\(a1\)
100003e4: 8ca5000c lw a1,12\(a1\)
100003e8: 3c050000 lui a1,0x0
-100003ec: 00bc2820 add a1,a1,gp
+100003ec: 00bc2821 addu a1,a1,gp
100003f0: 8ca58038 lw a1,-32712\(a1\)
-100003f4: 00b12820 add a1,a1,s1
+100003f4: 00b12821 addu a1,a1,s1
100003f8: 8ca50000 lw a1,0\(a1\)
100003fc: 3c050000 lui a1,0x0
-10000400: 00bc2820 add a1,a1,gp
+10000400: 00bc2821 addu a1,a1,gp
10000404: 8ca58038 lw a1,-32712\(a1\)
-10000408: 00b12820 add a1,a1,s1
+10000408: 00b12821 addu a1,a1,s1
1000040c: 8ca5000c lw a1,12\(a1\)
10000410: 3c010000 lui at,0x0
-10000414: 003c0820 add at,at,gp
+10000414: 003c0821 addu at,at,gp
10000418: 8c218038 lw at,-32712\(at\)
-1000041c: 00250820 add at,at,a1
+1000041c: 00250821 addu at,at,a1
10000420: 8c250022 lw a1,34\(at\)
10000424: 3c010000 lui at,0x0
-10000428: 003c0820 add at,at,gp
+10000428: 003c0821 addu at,at,gp
1000042c: 8c218038 lw at,-32712\(at\)
-10000430: 00250820 add at,at,a1
+10000430: 00250821 addu at,at,a1
10000434: ac250038 sw a1,56\(at\)
10000438: 3c010000 lui at,0x0
-1000043c: 003c0820 add at,at,gp
+1000043c: 003c0821 addu at,at,gp
10000440: 8c218038 lw at,-32712\(at\)
10000444: 88250000 lwl a1,0\(at\)
10000448: 98250003 lwr a1,3\(at\)
1000044c: 3c010000 lui at,0x0
-10000450: 003c0820 add at,at,gp
+10000450: 003c0821 addu at,at,gp
10000454: 8c218038 lw at,-32712\(at\)
-10000458: 2021000c addi at,at,12
+10000458: 2421000c addiu at,at,12
1000045c: 88250000 lwl a1,0\(at\)
10000460: 98250003 lwr a1,3\(at\)
10000464: 3c010000 lui at,0x0
-10000468: 003c0820 add at,at,gp
+10000468: 003c0821 addu at,at,gp
1000046c: 8c218038 lw at,-32712\(at\)
-10000470: 00310820 add at,at,s1
+10000470: 00310821 addu at,at,s1
10000474: 88250000 lwl a1,0\(at\)
10000478: 98250003 lwr a1,3\(at\)
1000047c: 3c010000 lui at,0x0
-10000480: 003c0820 add at,at,gp
+10000480: 003c0821 addu at,at,gp
10000484: 8c218038 lw at,-32712\(at\)
-10000488: 2021000c addi at,at,12
-1000048c: 00310820 add at,at,s1
+10000488: 2421000c addiu at,at,12
+1000048c: 00310821 addu at,at,s1
10000490: 88250000 lwl a1,0\(at\)
10000494: 98250003 lwr a1,3\(at\)
10000498: 3c010000 lui at,0x0
-1000049c: 003c0820 add at,at,gp
+1000049c: 003c0821 addu at,at,gp
100004a0: 8c218038 lw at,-32712\(at\)
-100004a4: 20210022 addi at,at,34
-100004a8: 00250820 add at,at,a1
+100004a4: 24210022 addiu at,at,34
+100004a8: 00250821 addu at,at,a1
100004ac: 88250000 lwl a1,0\(at\)
100004b0: 98250003 lwr a1,3\(at\)
100004b4: 3c010000 lui at,0x0
-100004b8: 003c0820 add at,at,gp
+100004b8: 003c0821 addu at,at,gp
100004bc: 8c218038 lw at,-32712\(at\)
-100004c0: 20210038 addi at,at,56
-100004c4: 00250820 add at,at,a1
+100004c0: 24210038 addiu at,at,56
+100004c4: 00250821 addu at,at,a1
100004c8: a8250000 swl a1,0\(at\)
100004cc: b8250003 swr a1,3\(at\)
100004d0: 8f858018 lw a1,-32744\(gp\)
-100004d4: 20a50774 addi a1,a1,1908
+100004d4: 24a50774 addiu a1,a1,1908
100004d8: 8f858018 lw a1,-32744\(gp\)
-100004dc: 20a50780 addi a1,a1,1920
+100004dc: 24a50780 addiu a1,a1,1920
100004e0: 8f85801c lw a1,-32740\(gp\)
-100004e4: 20a5e9b4 addi a1,a1,-5708
+100004e4: 24a5e9b4 addiu a1,a1,-5708
100004e8: 8f858018 lw a1,-32744\(gp\)
-100004ec: 20a50774 addi a1,a1,1908
-100004f0: 00b12820 add a1,a1,s1
+100004ec: 24a50774 addiu a1,a1,1908
+100004f0: 00b12821 addu a1,a1,s1
100004f4: 8f858018 lw a1,-32744\(gp\)
-100004f8: 20a50780 addi a1,a1,1920
-100004fc: 00b12820 add a1,a1,s1
+100004f8: 24a50780 addiu a1,a1,1920
+100004fc: 00b12821 addu a1,a1,s1
10000500: 8f85801c lw a1,-32740\(gp\)
-10000504: 20a5e9b4 addi a1,a1,-5708
-10000508: 00b12820 add a1,a1,s1
+10000504: 24a5e9b4 addiu a1,a1,-5708
+10000508: 00b12821 addu a1,a1,s1
1000050c: 8f858018 lw a1,-32744\(gp\)
10000510: 8ca50774 lw a1,1908\(a1\)
10000514: 8f858018 lw a1,-32744\(gp\)
10000518: 8ca50780 lw a1,1920\(a1\)
1000051c: 8f858018 lw a1,-32744\(gp\)
-10000520: 00b12820 add a1,a1,s1
+10000520: 00b12821 addu a1,a1,s1
10000524: 8ca50774 lw a1,1908\(a1\)
10000528: 8f858018 lw a1,-32744\(gp\)
-1000052c: 00b12820 add a1,a1,s1
+1000052c: 00b12821 addu a1,a1,s1
10000530: 8ca50780 lw a1,1920\(a1\)
10000534: 8f818018 lw at,-32744\(gp\)
-10000538: 00250820 add at,at,a1
+10000538: 00250821 addu at,at,a1
1000053c: 8c250774 lw a1,1908\(at\)
10000540: 8f818018 lw at,-32744\(gp\)
-10000544: 00250820 add at,at,a1
+10000544: 00250821 addu at,at,a1
10000548: ac2507ac sw a1,1964\(at\)
1000054c: 8f818018 lw at,-32744\(gp\)
-10000550: 20210774 addi at,at,1908
+10000550: 24210774 addiu at,at,1908
10000554: 88250000 lwl a1,0\(at\)
10000558: 98250003 lwr a1,3\(at\)
1000055c: 8f818018 lw at,-32744\(gp\)
-10000560: 20210780 addi at,at,1920
+10000560: 24210780 addiu at,at,1920
10000564: 88250000 lwl a1,0\(at\)
10000568: 98250003 lwr a1,3\(at\)
1000056c: 8f818018 lw at,-32744\(gp\)
-10000570: 20210774 addi at,at,1908
-10000574: 00310820 add at,at,s1
+10000570: 24210774 addiu at,at,1908
+10000574: 00310821 addu at,at,s1
10000578: 88250000 lwl a1,0\(at\)
1000057c: 98250003 lwr a1,3\(at\)
10000580: 8f818018 lw at,-32744\(gp\)
-10000584: 20210780 addi at,at,1920
-10000588: 00310820 add at,at,s1
+10000584: 24210780 addiu at,at,1920
+10000588: 00310821 addu at,at,s1
1000058c: 88250000 lwl a1,0\(at\)
10000590: 98250003 lwr a1,3\(at\)
10000594: 8f818018 lw at,-32744\(gp\)
-10000598: 20210796 addi at,at,1942
-1000059c: 00250820 add at,at,a1
+10000598: 24210796 addiu at,at,1942
+1000059c: 00250821 addu at,at,a1
100005a0: 88250000 lwl a1,0\(at\)
100005a4: 98250003 lwr a1,3\(at\)
100005a8: 8f818018 lw at,-32744\(gp\)
-100005ac: 202107ac addi at,at,1964
-100005b0: 00250820 add at,at,a1
+100005ac: 242107ac addiu at,at,1964
+100005b0: 00250821 addu at,at,a1
100005b4: a8250000 swl a1,0\(at\)
100005b8: b8250003 swr a1,3\(at\)
100005bc: 3c050000 lui a1,0x0
-100005c0: 00bc2820 add a1,a1,gp
+100005c0: 00bc2821 addu a1,a1,gp
100005c4: 8ca58030 lw a1,-32720\(a1\)
100005c8: 8f858020 lw a1,-32736\(gp\)
-100005cc: 20a506a0 addi a1,a1,1696
+100005cc: 24a506a0 addiu a1,a1,1696
100005d0: 3c190000 lui t9,0x0
-100005d4: 033cc820 add t9,t9,gp
+100005d4: 033cc821 addu t9,t9,gp
100005d8: 8f398030 lw t9,-32720\(t9\)
100005dc: 8f998020 lw t9,-32736\(gp\)
-100005e0: 233906a0 addi t9,t9,1696
+100005e0: 273906a0 addiu t9,t9,1696
100005e4: 3c190000 lui t9,0x0
-100005e8: 033cc820 add t9,t9,gp
+100005e8: 033cc821 addu t9,t9,gp
100005ec: 8f398030 lw t9,-32720\(t9\)
100005f0: 0320f809 jalr t9
100005f4: 00000000 nop
100005f8: 8f998020 lw t9,-32736\(gp\)
-100005fc: 233906a0 addi t9,t9,1696
+100005fc: 273906a0 addiu t9,t9,1696
10000600: 0320f809 jalr t9
10000604: 00000000 nop
10000608: 3c050000 lui a1,0x0
-1000060c: 00bc2820 add a1,a1,gp
+1000060c: 00bc2821 addu a1,a1,gp
10000610: 8ca58034 lw a1,-32716\(a1\)
10000614: 1000fea2 b 100000a0 <fn>
10000618: 00000000 nop
1000061c: 3c050000 lui a1,0x0
-10000620: 00bc2820 add a1,a1,gp
+10000620: 00bc2821 addu a1,a1,gp
10000624: 8ca58038 lw a1,-32712\(a1\)
10000628: 8ca50000 lw a1,0\(a1\)
1000062c: 1000001c b 100006a0 <fn2>
10000630: 00000000 nop
10000634: 8f858018 lw a1,-32744\(gp\)
-10000638: 20a506fc addi a1,a1,1788
+10000638: 24a506fc addiu a1,a1,1788
1000063c: 1000fe98 b 100000a0 <fn>
10000640: 00000000 nop
10000644: 8f858018 lw a1,-32744\(gp\)
-10000648: 20a50780 addi a1,a1,1920
+10000648: 24a50780 addiu a1,a1,1920
1000064c: 10000014 b 100006a0 <fn2>
10000650: 00000000 nop
10000654: 8f85801c lw a1,-32740\(gp\)
-10000658: 20a5e93c addi a1,a1,-5828
+10000658: 24a5e93c addiu a1,a1,-5828
1000065c: 1000fe90 b 100000a0 <fn>
10000660: 00000000 nop
10000664: 8f858018 lw a1,-32744\(gp\)
@@ -387,7 +387,7 @@ Disassembly of section \.text:
1000067c: 1000fe88 b 100000a0 <fn>
10000680: 00000000 nop
10000684: 8f818018 lw at,-32744\(gp\)
-10000688: 00250820 add at,at,a1
+10000688: 00250821 addu at,at,a1
1000068c: 8c250796 lw a1,1942\(at\)
10000690: 10000003 b 100006a0 <fn2>
10000694: 00000000 nop
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] MIPS gas: Cleanup address insn conditionals
2003-06-20 23:12 ` Thiemo Seufer
@ 2003-06-26 22:16 ` Eric Christopher
2003-06-26 22:49 ` Thiemo Seufer
0 siblings, 1 reply; 13+ messages in thread
From: Eric Christopher @ 2003-06-26 22:16 UTC (permalink / raw)
To: Thiemo Seufer; +Cc: Alexandre Oliva, Maciej W. Rozycki, binutils
On Fri, 2003-06-20 at 16:11, Thiemo Seufer wrote:
> Alexandre Oliva wrote:
> > On Jun 20, 2003, Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de> wrote:
> >
> > > Alexandre, when you changed the NewABI addressing, was there a reason
> > > for it besides the N32 ABI Handbook?
> >
> > Nope.
>
> Then I'd like to remove the n32 special handling.
>
Seems reasonable. Did you check the performance before/after? (shouldn't
make any difference, but...)
-eric
--
Eric Christopher <echristo@redhat.com>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] MIPS gas: Cleanup address insn conditionals
2003-06-26 22:16 ` Eric Christopher
@ 2003-06-26 22:49 ` Thiemo Seufer
2003-06-26 22:58 ` Eric Christopher
0 siblings, 1 reply; 13+ messages in thread
From: Thiemo Seufer @ 2003-06-26 22:49 UTC (permalink / raw)
To: Eric Christopher; +Cc: Alexandre Oliva, Maciej W. Rozycki, binutils
Eric Christopher wrote:
> On Fri, 2003-06-20 at 16:11, Thiemo Seufer wrote:
> > Alexandre Oliva wrote:
> > > On Jun 20, 2003, Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de> wrote:
> > >
> > > > Alexandre, when you changed the NewABI addressing, was there a reason
> > > > for it besides the N32 ABI Handbook?
> > >
> > > Nope.
> >
> > Then I'd like to remove the n32 special handling.
> >
>
> Seems reasonable. Did you check the performance before/after? (shouldn't
> make any difference, but...)
I didn't, but assembly speed will slightly increase due to fewer
conditionals to check, and execution speed of the generated code
will remain the same (1 cycle for all MIPS CPUs I know of).
Thiemo
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] MIPS gas: Cleanup address insn conditionals
2003-06-26 22:49 ` Thiemo Seufer
@ 2003-06-26 22:58 ` Eric Christopher
0 siblings, 0 replies; 13+ messages in thread
From: Eric Christopher @ 2003-06-26 22:58 UTC (permalink / raw)
To: Thiemo Seufer; +Cc: Alexandre Oliva, Maciej W. Rozycki, binutils
> I didn't, but assembly speed will slightly increase due to fewer
> conditionals to check, and execution speed of the generated code
> will remain the same (1 cycle for all MIPS CPUs I know of).
Yeah. That's what I was thinking. :)
-eric
--
Eric Christopher <echristo@redhat.com>
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2003-06-26 22:58 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2003-06-15 20:22 [PATCH] MIPS gas: Cleanup address insn conditionals Thiemo Seufer
[not found] ` <mailpost.1055708605.24715@news-sj1-1>
2003-06-16 4:52 ` cgd
2003-06-16 7:00 ` Eric Christopher
2003-06-16 12:11 ` Thiemo Seufer
2003-06-16 13:15 ` Maciej W. Rozycki
2003-06-16 14:02 ` Thiemo Seufer
2003-06-16 14:30 ` Maciej W. Rozycki
2003-06-20 4:14 ` Thiemo Seufer
2003-06-20 17:38 ` Alexandre Oliva
2003-06-20 23:12 ` Thiemo Seufer
2003-06-26 22:16 ` Eric Christopher
2003-06-26 22:49 ` Thiemo Seufer
2003-06-26 22:58 ` Eric Christopher
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).