From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 25481 invoked by alias); 15 Mar 2005 10:07:36 -0000 Mailing-List: contact binutils-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sources.redhat.com Received: (qmail 25040 invoked from network); 15 Mar 2005 10:07:26 -0000 Received: from unknown (HELO cam-admin0.cambridge.arm.com) (193.131.176.58) by sourceware.org with SMTP; 15 Mar 2005 10:07:26 -0000 Received: from pc960.cambridge.arm.com (pc960.cambridge.arm.com [10.1.205.4]) by cam-admin0.cambridge.arm.com (8.12.10/8.12.10) with ESMTP id j2FA7F4G007400; Tue, 15 Mar 2005 10:07:15 GMT Received: from pc960.cambridge.arm.com (localhost.localdomain [127.0.0.1]) by pc960.cambridge.arm.com (8.12.8/8.12.8) with ESMTP id j2FA7OIF025919; Tue, 15 Mar 2005 10:07:24 GMT Received: (from rearnsha@localhost) by pc960.cambridge.arm.com (8.12.8/8.12.8/Submit) id j2FA7N8T025917; Tue, 15 Mar 2005 10:07:23 GMT X-Authentication-Warning: pc960.cambridge.arm.com: rearnsha set sender to rearnsha@gcc.gnu.org using -f Subject: Re: ARMv6T2 ARM instructions - assembler support From: Richard Earnshaw To: Zack Weinberg Cc: binutils@sources.redhat.com In-Reply-To: <87ekehvmnr.fsf@codesourcery.com> References: <87ekehvmnr.fsf@codesourcery.com> Content-Type: text/plain Content-Transfer-Encoding: 7bit Organization: GNU Message-Id: <1110881242.1640.109.camel@pc960.cambridge.arm.com> Mime-Version: 1.0 Date: Tue, 15 Mar 2005 10:07:00 -0000 X-SW-Source: 2005-03/txt/msg00406.txt.bz2 On Mon, 2005-03-14 at 23:21, Zack Weinberg wrote: > This patch adds assembler support for the new ARM-format instructions > in ARMv6T2, and tests for them (and hence also for the disassembler > patch I committed last week). > > zw > > gas: > * config/tc-arm.c (do_mla): Rename to do_mlas, take second > is_mls parameter. > (do_mla, do_mls, five_bit_unsigned_immediate, bfci_lsb_and_width) > (do_bfc, do_bfi, do_bfx, do_rbit, do_mov16, do_ldsttv4): New functions. > (insns): Add ARMv6T2 instructions: > bfc bfi mls movw movt rbit sbfx ubfx ldrht ldrsht ldrsbt strht. > (arm_archs): Add V6T2 variants. > gas/testsuite: > * gas/arm/archv6t2.d, gas/arm/archv6t2.s: New dump test. > * gas/arm/archv6t2-bad.l, gas/arm/archv6t2-bad.l: New errors test. > * gas/arm/arm.exp: Run them. > > @@ -2847,7 +2847,12 @@ do_mla (char * str) > } > > if (rm == rd) > - as_tsktsk (_("rd and rm should be different in mla")); > + { > + if (is_mls) > + as_tsktsk (_("rd and rm should be different in mls")); > + else > + as_tsktsk (_("rd and rm should be different in mla")); > + } > mls doesn't have this restriction. v6 lifted the restriction for mla too, and in practice all v4 or later cores don't have it either, but that's hard to fix with the current -mcpu=all implementation. OK apart from that. R. PS. Just a note on the way I normally write tests. For each class of instruction (a do_xxx function) I try to write a test pattern that sets the minimal number of bits in the insn (eg uses r0 everywhere possible) and then one pattern for each register (to check that each register is setting the right bits). Finally, if the instruction is conditional, at least one pattern should test this case.