From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 19039 invoked by alias); 26 Mar 2007 14:59:32 -0000 Received: (qmail 19027 invoked by uid 22791); 26 Mar 2007 14:59:30 -0000 X-Spam-Check-By: sourceware.org Received: from mx1.redhat.com (HELO mx1.redhat.com) (66.187.233.31) by sourceware.org (qpsmtpd/0.31) with ESMTP; Mon, 26 Mar 2007 15:59:23 +0100 Received: from int-mx1.corp.redhat.com (int-mx1.corp.redhat.com [172.16.52.254]) by mx1.redhat.com (8.13.1/8.13.1) with ESMTP id l2QExLth002741 for ; Mon, 26 Mar 2007 10:59:21 -0400 Received: from pobox.corp.redhat.com (pobox.corp.redhat.com [10.11.255.20]) by int-mx1.corp.redhat.com (8.13.1/8.13.1) with ESMTP id l2QExLdx005393 for ; Mon, 26 Mar 2007 10:59:21 -0400 Received: from [10.13.248.87] (vpn-248-87.boston.redhat.com [10.13.248.87]) by pobox.corp.redhat.com (8.13.1/8.13.1) with ESMTP id l2QExKbi003076 for ; Mon, 26 Mar 2007 10:59:20 -0400 Subject: FRV registers patch From: Mark Salter To: binutils@sourceware.org Content-Type: text/plain Date: Mon, 26 Mar 2007 14:59:00 -0000 Message-Id: <1174921160.9115.29.camel@sadr.localdomain> Mime-Version: 1.0 X-Mailer: Evolution 2.8.3 (2.8.3-1.fc6) Content-Transfer-Encoding: 7bit Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org X-SW-Source: 2007-03/txt/msg00376.txt.bz2 The following patch adds definitions for new special-purpose registers in new FR-V family CPUs. It also renumbers a few registers which were incorrectly numbered (but never before used/implemented in silicon). --Mark 2007-03-26 Mark Salter cpu/ * frv.cpu (spr-names): New coprocessor related SPRs. opcodes/ * frv-desc.c: Regenerated. * frv-desc.h: Regenerated. Index: cpu/frv.cpu =================================================================== RCS file: /cvs/src/src/cpu/frv.cpu,v retrieving revision 1.22 diff -p -U3 -r1.22 frv.cpu --- cpu/frv.cpu 10 May 2005 10:21:06 -0000 1.22 +++ cpu/frv.cpu 23 Mar 2007 02:05:40 -0000 @@ -2808,12 +2808,21 @@ (dbmr20 2084) (dbmr21 2085) (dbmr22 2086) (dbmr23 2087) (dbmr30 2088) (dbmr31 2089) (dbmr32 2090) (dbmr33 2091) - (cpcfr 2092) (cpcr 2093) (cpsr 2094) + (cpcfr 2304) (cpcr 2305) (cpsr 2306) (cptr 2307) + (cphsr0 2308) (cphsr1 2309) (cpesr0 2320) (cpesr1 2321) + (cpemr0 2322) (cpemr1 2323) - (cpesr0 2096) (cpesr1 2097) - (cpemr0 2098) (cpemr1 2099) + (iperr0 2324) (iperr1 2325) (ipjsr 2326) (ipjrr 2327) + (ipcsr0 2336) (ipcsr1 2337) (ipcwer0 2338) (ipcwer1 2339) + (ipcwr 2340) - (ihsr8 3848) + (mbhsr 2352) (mbssr 2353) (mbrsr 2354) (mbsdr 2355) + (mbrdr 2356) (mbsmr 2357) (mbstr0 2359) (mbstr1 2360) + + (slpr 2368) (sldr 2369) (slhsr 2370) (sltr 2371) + (slwr 2372) + + (ihsr8 3848) (ihsr9 3849) (ihsr10 3850) ) ) Index: opcodes/frv-desc.c =================================================================== RCS file: /cvs/src/src/opcodes/frv-desc.c,v retrieving revision 1.22 diff -p -U3 -r1.22 frv-desc.c --- opcodes/frv-desc.c 28 Oct 2005 19:49:21 -0000 1.22 +++ opcodes/frv-desc.c 23 Mar 2007 02:05:40 -0000 @@ -1537,20 +1537,47 @@ static CGEN_KEYWORD_ENTRY frv_cgen_opval { "dbmr31", 2089, {0, {{{0, 0}}}}, 0, 0 }, { "dbmr32", 2090, {0, {{{0, 0}}}}, 0, 0 }, { "dbmr33", 2091, {0, {{{0, 0}}}}, 0, 0 }, - { "cpcfr", 2092, {0, {{{0, 0}}}}, 0, 0 }, - { "cpcr", 2093, {0, {{{0, 0}}}}, 0, 0 }, - { "cpsr", 2094, {0, {{{0, 0}}}}, 0, 0 }, - { "cpesr0", 2096, {0, {{{0, 0}}}}, 0, 0 }, - { "cpesr1", 2097, {0, {{{0, 0}}}}, 0, 0 }, - { "cpemr0", 2098, {0, {{{0, 0}}}}, 0, 0 }, - { "cpemr1", 2099, {0, {{{0, 0}}}}, 0, 0 }, - { "ihsr8", 3848, {0, {{{0, 0}}}}, 0, 0 } + { "cpcfr", 2304, {0, {{{0, 0}}}}, 0, 0 }, + { "cpcr", 2305, {0, {{{0, 0}}}}, 0, 0 }, + { "cpsr", 2306, {0, {{{0, 0}}}}, 0, 0 }, + { "cptr", 2307, {0, {{{0, 0}}}}, 0, 0 }, + { "cphsr0", 2308, {0, {{{0, 0}}}}, 0, 0 }, + { "cphsr1", 2309, {0, {{{0, 0}}}}, 0, 0 }, + { "cpesr0", 2320, {0, {{{0, 0}}}}, 0, 0 }, + { "cpesr1", 2321, {0, {{{0, 0}}}}, 0, 0 }, + { "cpemr0", 2322, {0, {{{0, 0}}}}, 0, 0 }, + { "cpemr1", 2323, {0, {{{0, 0}}}}, 0, 0 }, + { "iperr0", 2324, {0, {{{0, 0}}}}, 0, 0 }, + { "iperr1", 2325, {0, {{{0, 0}}}}, 0, 0 }, + { "ipjsr", 2326, {0, {{{0, 0}}}}, 0, 0 }, + { "ipjrr", 2327, {0, {{{0, 0}}}}, 0, 0 }, + { "ipcsr0", 2336, {0, {{{0, 0}}}}, 0, 0 }, + { "ipcsr1", 2337, {0, {{{0, 0}}}}, 0, 0 }, + { "ipcwer0", 2338, {0, {{{0, 0}}}}, 0, 0 }, + { "ipcwer1", 2339, {0, {{{0, 0}}}}, 0, 0 }, + { "ipcwr", 2340, {0, {{{0, 0}}}}, 0, 0 }, + { "mbhsr", 2352, {0, {{{0, 0}}}}, 0, 0 }, + { "mbssr", 2353, {0, {{{0, 0}}}}, 0, 0 }, + { "mbrsr", 2354, {0, {{{0, 0}}}}, 0, 0 }, + { "mbsdr", 2355, {0, {{{0, 0}}}}, 0, 0 }, + { "mbrdr", 2356, {0, {{{0, 0}}}}, 0, 0 }, + { "mbsmr", 2357, {0, {{{0, 0}}}}, 0, 0 }, + { "mbstr0", 2359, {0, {{{0, 0}}}}, 0, 0 }, + { "mbstr1", 2360, {0, {{{0, 0}}}}, 0, 0 }, + { "slpr", 2368, {0, {{{0, 0}}}}, 0, 0 }, + { "sldr", 2369, {0, {{{0, 0}}}}, 0, 0 }, + { "slhsr", 2370, {0, {{{0, 0}}}}, 0, 0 }, + { "sltr", 2371, {0, {{{0, 0}}}}, 0, 0 }, + { "slwr", 2372, {0, {{{0, 0}}}}, 0, 0 }, + { "ihsr8", 3848, {0, {{{0, 0}}}}, 0, 0 }, + { "ihsr9", 3849, {0, {{{0, 0}}}}, 0, 0 }, + { "ihsr10", 3850, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD frv_cgen_opval_spr_names = { & frv_cgen_opval_spr_names_entries[0], - 1022, + 1049, 0, 0, 0, 0, "" }; Index: opcodes/frv-desc.h =================================================================== RCS file: /cvs/src/src/opcodes/frv-desc.h,v retrieving revision 1.14 diff -p -U3 -r1.14 frv-desc.h --- opcodes/frv-desc.h 28 Oct 2005 19:49:21 -0000 1.14 +++ opcodes/frv-desc.h 23 Mar 2007 02:05:41 -0000 @@ -470,9 +470,16 @@ typedef enum spr_names { , H_SPR_DBMR02 = 2078, H_SPR_DBMR03 = 2079, H_SPR_DBMR10 = 2080, H_SPR_DBMR11 = 2081 , H_SPR_DBMR12 = 2082, H_SPR_DBMR13 = 2083, H_SPR_DBMR20 = 2084, H_SPR_DBMR21 = 2085 , H_SPR_DBMR22 = 2086, H_SPR_DBMR23 = 2087, H_SPR_DBMR30 = 2088, H_SPR_DBMR31 = 2089 - , H_SPR_DBMR32 = 2090, H_SPR_DBMR33 = 2091, H_SPR_CPCFR = 2092, H_SPR_CPCR = 2093 - , H_SPR_CPSR = 2094, H_SPR_CPESR0 = 2096, H_SPR_CPESR1 = 2097, H_SPR_CPEMR0 = 2098 - , H_SPR_CPEMR1 = 2099, H_SPR_IHSR8 = 3848 + , H_SPR_DBMR32 = 2090, H_SPR_DBMR33 = 2091, H_SPR_CPCFR = 2304, H_SPR_CPCR = 2305 + , H_SPR_CPSR = 2306, H_SPR_CPTR = 2307, H_SPR_CPHSR0 = 2308, H_SPR_CPHSR1 = 2309 + , H_SPR_CPESR0 = 2320, H_SPR_CPESR1 = 2321, H_SPR_CPEMR0 = 2322, H_SPR_CPEMR1 = 2323 + , H_SPR_IPERR0 = 2324, H_SPR_IPERR1 = 2325, H_SPR_IPJSR = 2326, H_SPR_IPJRR = 2327 + , H_SPR_IPCSR0 = 2336, H_SPR_IPCSR1 = 2337, H_SPR_IPCWER0 = 2338, H_SPR_IPCWER1 = 2339 + , H_SPR_IPCWR = 2340, H_SPR_MBHSR = 2352, H_SPR_MBSSR = 2353, H_SPR_MBRSR = 2354 + , H_SPR_MBSDR = 2355, H_SPR_MBRDR = 2356, H_SPR_MBSMR = 2357, H_SPR_MBSTR0 = 2359 + , H_SPR_MBSTR1 = 2360, H_SPR_SLPR = 2368, H_SPR_SLDR = 2369, H_SPR_SLHSR = 2370 + , H_SPR_SLTR = 2371, H_SPR_SLWR = 2372, H_SPR_IHSR8 = 3848, H_SPR_IHSR9 = 3849 + , H_SPR_IHSR10 = 3850 } SPR_NAMES; /* Enum declaration for . */