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From: Jan Beulich <jbeulich@suse.com>
To: Binutils <binutils@sourceware.org>
Subject: [PATCH 01/12] x86: drop OP_Mask()
Date: Wed, 21 Jul 2021 12:18:36 +0200	[thread overview]
Message-ID: <128d6e60-3fd9-ed03-4b97-d1b52cf6c754@suse.com> (raw)
In-Reply-To: <286bff10-f2d7-e1f5-e171-17565a143ced@suse.com>

By moving its vex.r check there it becomes fully redundant with OP_G().

--- a/opcodes/i386-dis-evex-prefix.h
+++ b/opcodes/i386-dis-evex-prefix.h
@@ -151,9 +151,9 @@
   },
   /* PREFIX_EVEX_0FC2 */
   {
-    { "vcmppX",	{ XMask, Vex, EXx, EXxEVexS, CMP }, PREFIX_OPCODE },
+    { "vcmppX",	{ MaskG, Vex, EXx, EXxEVexS, CMP }, PREFIX_OPCODE },
     { VEX_W_TABLE (EVEX_W_0FC2_P_1) },
-    { "vcmppX",	{ XMask, Vex, EXx, EXxEVexS, CMP }, PREFIX_OPCODE },
+    { "vcmppX",	{ MaskG, Vex, EXx, EXxEVexS, CMP }, PREFIX_OPCODE },
     { VEX_W_TABLE (EVEX_W_0FC2_P_3) },
   },
   /* PREFIX_EVEX_0FE6 */
@@ -238,14 +238,14 @@
   /* PREFIX_EVEX_0F3826 */
   {
     { Bad_Opcode },
-    { "vptestnm%BW",	{ XMask, Vex, EXx }, 0 },
-    { "vptestm%BW",	{ XMask, Vex, EXx }, 0 },
+    { "vptestnm%BW",	{ MaskG, Vex, EXx }, 0 },
+    { "vptestm%BW",	{ MaskG, Vex, EXx }, 0 },
   },
   /* PREFIX_EVEX_0F3827 */
   {
     { Bad_Opcode },
-    { "vptestnm%DQ",	{ XMask, Vex, EXx }, 0 },
-    { "vptestm%DQ",	{ XMask, Vex, EXx }, 0 },
+    { "vptestnm%DQ",	{ MaskG, Vex, EXx }, 0 },
+    { "vptestm%DQ",	{ MaskG, Vex, EXx }, 0 },
   },
   /* PREFIX_EVEX_0F3828 */
   {
@@ -256,7 +256,7 @@
   /* PREFIX_EVEX_0F3829 */
   {
     { Bad_Opcode },
-    { "vpmov%BW2m",	{ XMask, EXx }, 0 },
+    { "vpmov%BW2m",	{ MaskG, EXx }, 0 },
     { VEX_W_TABLE (EVEX_W_0F3829_P_2) },
   },
   /* PREFIX_EVEX_0F382A */
@@ -310,7 +310,7 @@
   /* PREFIX_EVEX_0F3839 */
   {
     { Bad_Opcode },
-    { "vpmov%DQ2m",	{ XMask, EXx }, 0 },
+    { "vpmov%DQ2m",	{ MaskG, EXx }, 0 },
     { "vpmins%DQ",	{ XM, Vex, EXx }, 0 },
   },
   /* PREFIX_EVEX_0F383A */
@@ -338,7 +338,7 @@
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
-    { "vp2intersect%DQ", { XMask, Vex, EXx, EXxEVexS }, 0 },
+    { "vp2intersect%DQ", { MaskG, Vex, EXx, EXxEVexS }, 0 },
   },
   /* PREFIX_EVEX_0F3872 */
   {
--- a/opcodes/i386-dis-evex-w.h
+++ b/opcodes/i386-dis-evex-w.h
@@ -142,7 +142,7 @@
   },
   /* EVEX_W_0F66 */
   {
-    { "vpcmpgtd",	{ XMask, Vex, EXx }, PREFIX_DATA },
+    { "vpcmpgtd",	{ MaskG, Vex, EXx }, PREFIX_DATA },
   },
   /* EVEX_W_0F6A */
   {
@@ -201,7 +201,7 @@
   },
   /* EVEX_W_0F76 */
   {
-    { "vpcmpeqd",	{ XMask, Vex, EXx }, PREFIX_DATA },
+    { "vpcmpeqd",	{ MaskG, Vex, EXx }, PREFIX_DATA },
   },
   /* EVEX_W_0F78_P_0 */
   {
@@ -270,12 +270,12 @@
   },
   /* EVEX_W_0FC2_P_1 */
   {
-    { "vcmpss",	{ XMask, VexScalar, EXxmm_md, EXxEVexS, CMP }, 0 },
+    { "vcmpss",	{ MaskG, VexScalar, EXxmm_md, EXxEVexS, CMP }, 0 },
   },
   /* EVEX_W_0FC2_P_3 */
   {
     { Bad_Opcode },
-    { "vcmpsd",	{ XMask, VexScalar, EXxmm_mq, EXxEVexS, CMP }, 0 },
+    { "vcmpsd",	{ MaskG, VexScalar, EXxmm_mq, EXxEVexS, CMP }, 0 },
   },
   /* EVEX_W_0FD2 */
   {
@@ -450,7 +450,7 @@
   /* EVEX_W_0F3829_P_2 */
   {
     { Bad_Opcode },
-    { "vpcmpeqq",	{ XMask, Vex, EXx }, 0 },
+    { "vpcmpeqq",	{ MaskG, Vex, EXx }, 0 },
   },
   /* EVEX_W_0F382A_P_1 */
   {
@@ -496,7 +496,7 @@
   /* EVEX_W_0F3837 */
   {
     { Bad_Opcode },
-    { "vpcmpgtq",	{ XMask, Vex, EXx }, PREFIX_DATA },
+    { "vpcmpgtq",	{ MaskG, Vex, EXx }, PREFIX_DATA },
   },
   /* EVEX_W_0F383A_P_1 */
   {
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -114,8 +114,8 @@ static const struct dis386 evex_table[][
     { "vpunpcklwd",	{ XM, Vex, EXx }, PREFIX_DATA },
     { VEX_W_TABLE (EVEX_W_0F62) },
     { "vpacksswb",	{ XM, Vex, EXx }, PREFIX_DATA },
-    { "vpcmpgtb",	{ XMask, Vex, EXx }, PREFIX_DATA },
-    { "vpcmpgtw",	{ XMask, Vex, EXx }, PREFIX_DATA },
+    { "vpcmpgtb",	{ MaskG, Vex, EXx }, PREFIX_DATA },
+    { "vpcmpgtw",	{ MaskG, Vex, EXx }, PREFIX_DATA },
     { VEX_W_TABLE (EVEX_W_0F66) },
     { "vpackuswb",	{ XM, Vex, EXx }, PREFIX_DATA },
     /* 68 */
@@ -132,8 +132,8 @@ static const struct dis386 evex_table[][
     { REG_TABLE (REG_EVEX_0F71) },
     { REG_TABLE (REG_EVEX_0F72) },
     { REG_TABLE (REG_EVEX_0F73) },
-    { "vpcmpeqb",	{ XMask, Vex, EXx }, PREFIX_DATA },
-    { "vpcmpeqw",	{ XMask, Vex, EXx }, PREFIX_DATA },
+    { "vpcmpeqb",	{ MaskG, Vex, EXx }, PREFIX_DATA },
+    { "vpcmpeqw",	{ MaskG, Vex, EXx }, PREFIX_DATA },
     { VEX_W_TABLE (EVEX_W_0F76) },
     { Bad_Opcode },
     /* 78 */
@@ -453,7 +453,7 @@ static const struct dis386 evex_table[][
     { Bad_Opcode },
     { "vperm%BW",	{ XM, Vex, EXx }, PREFIX_DATA },
     { Bad_Opcode },
-    { "vpshufbitqmb",  { XMask, Vex, EXx }, PREFIX_DATA },
+    { "vpshufbitqmb",  { MaskG, Vex, EXx }, PREFIX_DATA },
     /* 90 */
     { "vpgatherd%DQ",	{ XMGatherD, MVexVSIBDWpX }, PREFIX_DATA },
     { "vpgatherq%DQ",	{ XMGatherQ, MVexVSIBQWpX }, PREFIX_DATA },
@@ -617,8 +617,8 @@ static const struct dis386 evex_table[][
     { EVEX_LEN_TABLE (EVEX_LEN_0F3A1B) },
     { Bad_Opcode },
     { VEX_W_TABLE (VEX_W_0F3A1D) },
-    { "vpcmpu%DQ",	{ XMask, Vex, EXx, VPCMP }, PREFIX_DATA },
-    { "vpcmp%DQ",	{ XMask, Vex, EXx, VPCMP }, PREFIX_DATA },
+    { "vpcmpu%DQ",	{ MaskG, Vex, EXx, VPCMP }, PREFIX_DATA },
+    { "vpcmp%DQ",	{ MaskG, Vex, EXx, VPCMP }, PREFIX_DATA },
     /* 20 */
     { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
     { VEX_W_TABLE (EVEX_W_0F3A21) },
@@ -653,8 +653,8 @@ static const struct dis386 evex_table[][
     { EVEX_LEN_TABLE (EVEX_LEN_0F3A3B) },
     { Bad_Opcode },
     { Bad_Opcode },
-    { "vpcmpu%BW",	{ XMask, Vex, EXx, VPCMP }, PREFIX_DATA },
-    { "vpcmp%BW",	{ XMask, Vex, EXx, VPCMP }, PREFIX_DATA },
+    { "vpcmpu%BW",	{ MaskG, Vex, EXx, VPCMP }, PREFIX_DATA },
+    { "vpcmp%BW",	{ MaskG, Vex, EXx, VPCMP }, PREFIX_DATA },
     /* 40 */
     { Bad_Opcode },
     { Bad_Opcode },
@@ -698,8 +698,8 @@ static const struct dis386 evex_table[][
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
-    { "vfpclassp%XW%XZ",	{ XMask, EXx, Ib }, PREFIX_DATA },
-    { "vfpclasss%XW",	{ XMask, EXVexWdqScalar, Ib }, PREFIX_DATA },
+    { "vfpclassp%XW%XZ",	{ MaskG, EXx, Ib }, PREFIX_DATA },
+    { "vfpclasss%XW",	{ MaskG, EXVexWdqScalar, Ib }, PREFIX_DATA },
     /* 68 */
     { Bad_Opcode },
     { Bad_Opcode },
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -116,8 +116,6 @@ static void FXSAVE_Fixup (int, int);
 
 static void MOVSXD_Fixup (int, int);
 
-static void OP_Mask (int, int);
-
 struct dis_private {
   /* Points to first byte not fetched.  */
   bfd_byte *max_fetched;
@@ -406,7 +404,6 @@ fetch_data (struct disassemble_info *inf
 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 
-#define XMask { OP_Mask, mask_mode }
 #define MaskG { OP_G, mask_mode }
 #define MaskE { OP_E, mask_mode }
 #define MaskBDE { OP_E, mask_bd_mode }
@@ -12017,12 +12014,12 @@ OP_G (int bytemode, int sizeflag)
       break;
     case mask_bd_mode:
     case mask_mode:
-      if ((modrm.reg + add) > 0x7)
+      if (add || (vex.evex && !vex.r))
 	{
 	  oappend ("(bad)");
 	  return;
 	}
-      oappend (names_mask[modrm.reg + add]);
+      oappend (names_mask[modrm.reg]);
       break;
     default:
       oappend (INTERNAL_DISASSEMBLER_ERROR);
@@ -13721,23 +13718,6 @@ MOVSXD_Fixup (int bytemode, int sizeflag
 }
 
 static void
-OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
-{
-  if (!vex.evex
-      || (bytemode != mask_mode && bytemode != mask_bd_mode))
-    abort ();
-
-  USED_REX (REX_R);
-  if ((rex & REX_R) != 0 || !vex.r)
-    {
-      BadOp ();
-      return;
-    }
-
-  oappend (names_mask [modrm.reg]);
-}
-
-static void
 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
 {
   if (modrm.mod == 3 && vex.b)


  reply	other threads:[~2021-07-21 10:18 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-21 10:07 [PATCH 00/12] x86: disassembler fixes and some consolidation Jan Beulich
2021-07-21 10:18 ` Jan Beulich [this message]
2021-07-21 10:19 ` [PATCH 02/12] x86: correct VCVT{,U}SI2SD rounding mode handling Jan Beulich
2021-07-22 11:18   ` Jan Beulich
2021-07-22 11:31     ` H.J. Lu
2021-07-21 10:19 ` [PATCH 03/12] x86-64: generalize OP_G()'s EVEX.R' handling Jan Beulich
2021-07-21 10:19 ` [PATCH 04/12] x86-64: properly bounds-check %bnd<N> in OP_G() Jan Beulich
2021-07-21 10:20 ` [PATCH 05/12] x86: fold duplicate register printing code Jan Beulich
2021-07-21 10:20 ` [PATCH 06/12] x86: fold duplicate code in MOVSXD_Fixup() Jan Beulich
2021-07-21 10:21 ` [PATCH 07/12] x86: correct EVEX.V' handling outside of 64-bit mode Jan Beulich
2021-07-21 10:22 ` [PATCH 08/12] x86: drop vex_mode and vex_scalar_mode Jan Beulich
2021-07-21 10:22 ` [PATCH 09/12] x86: fold duplicate vector register printing code Jan Beulich
2021-07-21 10:22 ` [PATCH 10/12] x86: drop xmm_m{b,w,d,q}_mode Jan Beulich
2021-07-21 10:23 ` [PATCH 11/12] x86: drop vex_scalar_w_dq_mode Jan Beulich
2021-07-21 10:23 ` [PATCH 12/12] x86: drop dq{b,d}_mode Jan Beulich
2021-07-21 12:56 ` [PATCH 00/12] x86: disassembler fixes and some consolidation H.J. Lu

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