[PATCH] gas: blackfin: catch invalid dest dregs in dsp mult insns

[PATCH] gas: blackfin: catch invalid dest dregs in dsp mult insns

[Mike Frysinger]

While we were catching a few mismatches in vectorized dsp mult insns,
the error we displayed was misleading.  Once we fix that up, we can
convert previously dead code into proper checking for destination
dreg matching.

Committed.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

gas/:
2011-02-13  Mike Frysinger  <vapier@gentoo.org>

	* config/bfin-parse.y (check_macfuncs): Clarify error message when
	P is mismatched.  Check destination regno are off by one when P is
	set, or are equal when P is not set.

gas/testsuite/:
2011-02-13  Mike Frysinger  <vapier@gentoo.org>

	* gas/bfin/expected_errors.s: Add invalid dsp mult insn tests.
	* gas/bfin/expected_errors.l: Add new error messages.
---
 gas/config/bfin-parse.y                  |   12 ++++++++----
 gas/testsuite/gas/bfin/expected_errors.l |    3 +++
 gas/testsuite/gas/bfin/expected_errors.s |    4 ++++
 3 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/gas/config/bfin-parse.y b/gas/config/bfin-parse.y
index eda67c9..803afd1 100644
--- a/gas/config/bfin-parse.y
+++ b/gas/config/bfin-parse.y
@@ -336,11 +336,15 @@ check_macfuncs (Macfunc *aa, Opt_mode *opa,
       aa->s1.regno |= (ab->s1.regno & CODE_MASK);
     }
 
-  if (aa->w == ab->w  && aa->P != ab->P)
+  if (aa->w == ab->w && aa->P != ab->P)
+    return yyerror ("Destination Dreg sizes (full or half) must match");
+
+  if (aa->w && ab->w)
     {
-      return yyerror ("macfuncs must differ");
-      if (aa->w && (aa->dst.regno - ab->dst.regno != 1))
-	return yyerror ("Destination Dregs must differ by one");
+      if (aa->P && (aa->dst.regno - ab->dst.regno) != 1)
+	return yyerror ("Destination Dregs (full) must differ by one");
+      if (!aa->P && aa->dst.regno != ab->dst.regno)
+	return yyerror ("Destination Dregs (half) must match");
     }
 
   /* Make sure mod flags get ORed, too.  */
diff --git a/gas/testsuite/gas/bfin/expected_errors.l b/gas/testsuite/gas/bfin/expected_errors.l
index 25cb690..fdab364 100644
--- a/gas/testsuite/gas/bfin/expected_errors.l
+++ b/gas/testsuite/gas/bfin/expected_errors.l
@@ -90,3 +90,6 @@
 .*:115: Error: Dreg expected for destination operand. Input text was \).
 .*:117: Error: Illegal dest register combination. Input text was \).
 .*:118: Error: Illegal source register combination. Input text was \).
+.*:120: Error: Destination Dregs \(full\) must differ by one.
+.*:121: Error: Destination Dregs \(half\) must match.
+.*:122: Error: Destination Dreg sizes \(full or half\) must match.
diff --git a/gas/testsuite/gas/bfin/expected_errors.s b/gas/testsuite/gas/bfin/expected_errors.s
index 812c2d9..7086526 100644
--- a/gas/testsuite/gas/bfin/expected_errors.s
+++ b/gas/testsuite/gas/bfin/expected_errors.s
@@ -113,3 +113,7 @@
 
 	(R3, R3) = SEARCH R0 (GE);
 	BITMUX (R4, R4, A0) (ASR);
+
+	R0 = A0, R3 = A1;
+	R0.L = A0, R1.H = A1;
+	R0 = A0, R1.H = A1;
-- 
1.7.4.1