diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 04f6ade830b21c12ecd07e4f57373cfe27de7ce3..d460c5da74e1d4cb5ec45eab3c9972cd2a346ab0 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -6512,7 +6512,13 @@ parse_sys_vldr_vstr (char **str)
     {"VPR",		0x4, 0x1},
     {"P0",		0x5, 0x1},
     {"FPCXTNS",		0x6, 0x1},
-    {"FPCXTS",		0x7, 0x1}
+    {"FPCXT_NS",	0x6, 0x1},
+    {"fpcxtns",		0x6, 0x1},
+    {"fpcxt_ns",	0x6, 0x1},
+    {"FPCXTS",		0x7, 0x1},
+    {"FPCXT_S",		0x7, 0x1},
+    {"fpcxts",		0x7, 0x1},
+    {"fpcxt_s",		0x7, 0x1}
   };
   char *op_end = strchr (*str, ',');
   size_t op_strlen = op_end - *str;
@@ -10171,8 +10177,8 @@ do_vmsr (void)
 		  _(BAD_FPU));
       break;
 
-    case 14: /* fpcxt_ns.  */
-    case 15: /* fpcxt_s.  */
+    case 14: /* fpcxt_ns, fpcxtns, FPCXT_NS, FPCXTNS.  */
+    case 15: /* fpcxt_s, fpcxts, FPCXT_S, FPCXTS.  */
       constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main),
 		  _("selected processor does not support instruction"));
       break;
@@ -23938,6 +23944,8 @@ static const struct reg_entry reg_names[] =
   REGDEF(vpr,12,VFC), REGDEF(VPR,12,VFC),
   REGDEF(fpcxt_ns,14,VFC), REGDEF(FPCXT_NS,14,VFC),
   REGDEF(fpcxt_s,15,VFC), REGDEF(FPCXT_S,15,VFC),
+  REGDEF(fpcxtns,14,VFC), REGDEF(FPCXTNS,14,VFC),
+  REGDEF(fpcxts,15,VFC), REGDEF(FPCXTS,15,VFC),
 
   /* Maverick DSP coprocessor registers.  */
   REGSET(mvf,MVF),  REGSET(mvd,MVD),  REGSET(mvfx,MVFX),  REGSET(mvdx,MVDX),
diff --git a/gas/testsuite/gas/arm/armv8_1-m-fpcxt-reg.d b/gas/testsuite/gas/arm/armv8_1-m-fpcxt-reg.d
new file mode 100644
index 0000000000000000000000000000000000000000..a25bc45c931566ad40ff0e62050184dc3e99370f
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-fpcxt-reg.d
@@ -0,0 +1,40 @@
+#name: Valid Armv8.1-M Mainline FPCXT_NS and FPCXT_S register usage
+#source: armv8_1-m-fpcxt-reg.s
+#as: -march=armv8.1-m.main
+#objdump: -dr --prefix-addresses --show-raw-insn -marmv8.1-m.main
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+[^*]+> ed6d cf81 	vstr	FPCXTNS, \[sp, #-4\]!
+[^*]+> ed6d ef81 	vstr	FPCXTS, \[sp, #-4\]!
+[^*]+> ed6d cf81 	vstr	FPCXTNS, \[sp, #-4\]!
+[^*]+> ed6d ef81 	vstr	FPCXTS, \[sp, #-4\]!
+[^*]+> ed6d cf81 	vstr	FPCXTNS, \[sp, #-4\]!
+[^*]+> ed6d ef81 	vstr	FPCXTS, \[sp, #-4\]!
+[^*]+> ed6d cf81 	vstr	FPCXTNS, \[sp, #-4\]!
+[^*]+> ed6d ef81 	vstr	FPCXTS, \[sp, #-4\]!
+0+.* <[^>]*> edd3 cf80 	vldr	FPCXTNS, \[r3\]
+0+.* <[^>]*> edd3 cf80 	vldr	FPCXTNS, \[r3\]
+0+.* <[^>]*> edd3 cf80 	vldr	FPCXTNS, \[r3\]
+0+.* <[^>]*> edd3 cf80 	vldr	FPCXTNS, \[r3\]
+0+.* <[^>]*> edd3 ef80 	vldr	FPCXTS, \[r3\]
+0+.* <[^>]*> edd3 ef80 	vldr	FPCXTS, \[r3\]
+0+.* <[^>]*> edd3 ef80 	vldr	FPCXTS, \[r3\]
+0+.* <[^>]*> edd3 ef80 	vldr	FPCXTS, \[r3\]
+[^*]+> eefe 4a10 	vmrs	r4, fpcxt_ns
+[^*]+> eefe 4a10 	vmrs	r4, fpcxt_ns
+[^*]+> eeff 5a10 	vmrs	r5, fpcxt_s
+[^*]+> eeff 5a10 	vmrs	r5, fpcxt_s
+[^*]+> eefe 4a10 	vmrs	r4, fpcxt_ns
+[^*]+> eefe 4a10 	vmrs	r4, fpcxt_ns
+[^*]+> eeff 5a10 	vmrs	r5, fpcxt_s
+[^*]+> eeff 5a10 	vmrs	r5, fpcxt_s
+[^*]+> eeee 4a10 	vmsr	fpcxt_ns, r4
+[^*]+> eeee 4a10 	vmsr	fpcxt_ns, r4
+[^*]+> eeef 5a10 	vmsr	fpcxt_s, r5
+[^*]+> eeef 5a10 	vmsr	fpcxt_s, r5
+[^*]+> eeee 4a10 	vmsr	fpcxt_ns, r4
+[^*]+> eeee 4a10 	vmsr	fpcxt_ns, r4
+[^*]+> eeef 5a10 	vmsr	fpcxt_s, r5
+[^*]+> eeef 5a10 	vmsr	fpcxt_s, r5
diff --git a/gas/testsuite/gas/arm/armv8_1-m-fpcxt-reg.s b/gas/testsuite/gas/arm/armv8_1-m-fpcxt-reg.s
new file mode 100644
index 0000000000000000000000000000000000000000..6863c328b7015c0580e34a7d5a398458d5c557da
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-fpcxt-reg.s
@@ -0,0 +1,37 @@
+	.syntax unified
+func:
+	vstr fpcxtns,[sp,#-4]!
+	vstr fpcxts,[sp,#-4]!
+	vstr FPCXTNS,[sp,#-4]!
+	vstr FPCXTS,[sp,#-4]!
+	vstr fpcxt_ns,[sp,#-4]!
+	vstr fpcxt_s,[sp,#-4]!
+	vstr FPCXT_NS,[sp,#-4]!
+	vstr FPCXT_S,[sp,#-4]!
+
+	vldr FPCXTNS, [r3]
+	vldr FPCXT_NS, [r3]
+	vldr fpcxtns, [r3]
+	vldr fpcxt_ns, [r3]
+	vldr FPCXTS, [r3]
+	vldr FPCXT_S, [r3]
+	vldr fpcxt_s, [r3]
+	vldr fpcxts, [r3]
+
+	vmrs r4, FPCXT_NS
+	vmrs r4, FPCXTNS
+	vmrs r5, FPCXTS
+	vmrs r5, FPCXT_S
+	vmrs r4, fpcxt_ns
+	vmrs r4, fpcxtns
+	vmrs r5, fpcxts
+	vmrs r5, fpcxt_s
+
+	vmsr FPCXT_NS, r4
+	vmsr FPCXTNS, r4
+	vmsr FPCXTS, r5
+	vmsr FPCXT_S, r5
+	vmsr fpcxt_ns, r4
+	vmsr fpcxtns, r4
+	vmsr fpcxts, r5
+	vmsr fpcxt_s, r5