* [PATCH 0/3] x86: drop VexSources attribute
@ 2023-02-03 7:43 Jan Beulich
2023-02-03 7:44 ` [PATCH 1/3] x86: limit use of XOP2SOURCES Jan Beulich
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Jan Beulich @ 2023-02-03 7:43 UTC (permalink / raw)
To: Binutils; +Cc: H.J. Lu
This attribute's existence has been bothering me for years; I merely never
dared to touch it because the hackery looked pretty fragile. In the course
of trying to get .insn to work sensibly (and without overly intrusive
changes to the assembler), I finally had to properly understand what the
special case code does. And voila - XOP2SOURCES is fully redundant with
other (in part special case) handling we have, while VEX3SOURCES uses can
easily be expressed differently.
1: limit use of XOP2SOURCES
2: drop use of XOP2SOURCES
3: drop use of VEX3SOURCES
While I don't think there are any conflicts (except in generated files),
if in doubt this is assumed to go on top of "x86: assorted opcode
processing adjustments".
Jan
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 1/3] x86: limit use of XOP2SOURCES
2023-02-03 7:43 [PATCH 0/3] x86: drop VexSources attribute Jan Beulich
@ 2023-02-03 7:44 ` Jan Beulich
2023-02-03 7:45 ` [PATCH 2/3] x86: drop " Jan Beulich
2023-02-03 7:46 ` [PATCH 3/3] x86: drop use of VEX3SOURCES Jan Beulich
2 siblings, 0 replies; 4+ messages in thread
From: Jan Beulich @ 2023-02-03 7:44 UTC (permalink / raw)
To: Binutils; +Cc: H.J. Lu
The VPROT* forms with an immediate operand are entirely standard in the
way their ModR/M bytes are built. There's no reason to invoke special
case code. With that the handling of an immediate there can also be
dropped; it was partially bogus anyway, as in its "no memory operands"
portion it ignores the possibility of an immediate operand (which was
okay only because that case was already handled by more generic code).
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -8620,17 +8620,11 @@ build_modrm_byte (void)
if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
{
- if (operand_type_check (i.types[0], imm))
- i.vex.register_specifier = NULL;
+ /* VEX.vvvv encodes one of the sources. */
+ if (i.tm.opcode_modifier.vexw == VEXW0)
+ i.vex.register_specifier = i.op[0].regs;
else
- {
- /* VEX.vvvv encodes one of the sources when the first
- operand is not an immediate. */
- if (i.tm.opcode_modifier.vexw == VEXW0)
- i.vex.register_specifier = i.op[0].regs;
- else
- i.vex.register_specifier = i.op[1].regs;
- }
+ i.vex.register_specifier = i.op[1].regs;
/* Destination is a XMM register encoded in the ModRM.reg
and VEX.R bit. */
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -1877,7 +1877,7 @@ vpmadcsswd, 0xa6, XOP, Modrm|SpaceXOP08|
vpmadcswd, 0xb6, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpperm, 0xa3, XOP, D|Modrm|SpaceXOP08|VexSources=2|VexVVVV|VexW0|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vprot<xop>, 0x90 | <xop:opc>, XOP, D|Modrm|Vex128|SpaceXOP09|VexW0|VexSources=1|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
-vprot<xop>, 0xc0 | <xop:opc>, XOP, Modrm|Vex128|SpaceXOP08|VexW0|VexSources=1|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
+vprot<xop>, 0xc0 | <xop:opc>, XOP, Modrm|Vex128|SpaceXOP08|VexW0|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
vpsha<xop>, 0x98 | <xop:opc>, XOP, D|Modrm|Vex128|SpaceXOP09|VexW0|VexSources=1|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
vpshl<xop>, 0x94 | <xop:opc>, XOP, D|Modrm|Vex128|SpaceXOP09|VexW0|VexSources=1|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 2/3] x86: drop use of XOP2SOURCES
2023-02-03 7:43 [PATCH 0/3] x86: drop VexSources attribute Jan Beulich
2023-02-03 7:44 ` [PATCH 1/3] x86: limit use of XOP2SOURCES Jan Beulich
@ 2023-02-03 7:45 ` Jan Beulich
2023-02-03 7:46 ` [PATCH 3/3] x86: drop use of VEX3SOURCES Jan Beulich
2 siblings, 0 replies; 4+ messages in thread
From: Jan Beulich @ 2023-02-03 7:45 UTC (permalink / raw)
To: Binutils; +Cc: H.J. Lu
The few XOP insns which used it wrongly didn't have VexVVVV specified.
With that added, the only further missing piece to use more generic code
elsewhere is SwapSources - see e.g. the BMI2 insns for similar operand
patterns.
With the only users gone, drop the #define as well as the special case
code.
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -2142,9 +2142,9 @@ operand_size_match (const insn_template
{
unsigned int given = i.operands - j - 1;
- /* For 4- and 5-operand insns VEX.W controls just the first two
+ /* For 4-operand and XOP insns VEX.W controls just the first two
register operands. */
- if (t->opcode_modifier.vexsources)
+ if (t->opcode_modifier.vexsources || t->cpu_flags.bitfield.cpuxop)
given = j < 2 ? 1 - j : j;
if (t->operand_types[j].bitfield.class == Reg
@@ -6933,7 +6933,8 @@ match_template (char mnem_suffix)
if (!(size_match & MATCH_REVERSE))
continue;
/* Try reversing direction of operands. */
- j = t->opcode_modifier.vexsources ? 1 : i.operands - 1;
+ j = t->opcode_modifier.vexsources
+ || t->cpu_flags.bitfield.cpuxop ? 1 : i.operands - 1;
overlap0 = operand_type_and (i.types[0], operand_types[j]);
overlap1 = operand_type_and (i.types[j], operand_types[0]);
overlap2 = operand_type_and (i.types[1], operand_types[1]);
@@ -6967,7 +6968,8 @@ match_template (char mnem_suffix)
&& (intel_syntax || intel_mnemonic))
found_reverse_match |= Opcode_FloatR;
}
- else if (t->opcode_modifier.vexsources)
+ else if (t->opcode_modifier.vexsources
+ || t->cpu_flags.bitfield.cpuxop)
{
found_reverse_match = Opcode_VexW;
goto check_operands_345;
@@ -8618,35 +8620,7 @@ build_modrm_byte (void)
else
mem = ~0;
- if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
- {
- /* VEX.vvvv encodes one of the sources. */
- if (i.tm.opcode_modifier.vexw == VEXW0)
- i.vex.register_specifier = i.op[0].regs;
- else
- i.vex.register_specifier = i.op[1].regs;
-
- /* Destination is a XMM register encoded in the ModRM.reg
- and VEX.R bit. */
- i.rm.reg = i.op[2].regs->reg_num;
- if ((i.op[2].regs->reg_flags & RegRex) != 0)
- i.rex |= REX_R;
-
- /* ModRM.rm and VEX.B encodes the other source. */
- if (!i.mem_operands)
- {
- i.rm.mode = 3;
-
- if (i.tm.opcode_modifier.vexw == VEXW0)
- i.rm.regmem = i.op[1].regs->reg_num;
- else
- i.rm.regmem = i.op[0].regs->reg_num;
-
- if ((i.op[1].regs->reg_flags & RegRex) != 0)
- i.rex |= REX_B;
- }
- }
- else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
+ if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
{
i.vex.register_specifier = i.op[2].regs;
if (!i.mem_operands)
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -619,10 +619,8 @@ enum
OpcodePrefix,
/* number of VEX source operands:
0: <= 2 source operands.
- 1: 2 XOP source operands.
2: 3 source operands.
*/
-#define XOP2SOURCES 1
#define VEX3SOURCES 2
VexSources,
/* Instruction with a mandatory SIB byte:
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -1876,10 +1876,10 @@ vpmacsww, 0x95, XOP, Modrm|SpaceXOP08|Ve
vpmadcsswd, 0xa6, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpmadcswd, 0xb6, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpperm, 0xa3, XOP, D|Modrm|SpaceXOP08|VexSources=2|VexVVVV|VexW0|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
-vprot<xop>, 0x90 | <xop:opc>, XOP, D|Modrm|Vex128|SpaceXOP09|VexW0|VexSources=1|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
+vprot<xop>, 0x90 | <xop:opc>, XOP, D|Modrm|Vex128|SpaceXOP09|VexVVVV|SwapSources|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
vprot<xop>, 0xc0 | <xop:opc>, XOP, Modrm|Vex128|SpaceXOP08|VexW0|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
-vpsha<xop>, 0x98 | <xop:opc>, XOP, D|Modrm|Vex128|SpaceXOP09|VexW0|VexSources=1|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
-vpshl<xop>, 0x94 | <xop:opc>, XOP, D|Modrm|Vex128|SpaceXOP09|VexW0|VexSources=1|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
+vpsha<xop>, 0x98 | <xop:opc>, XOP, D|Modrm|Vex128|SpaceXOP09|VexVVVV|SwapSources|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
+vpshl<xop>, 0x94 | <xop:opc>, XOP, D|Modrm|Vex128|SpaceXOP09|VexVVVV|SwapSources|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
<xop>
<irel>
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 3/3] x86: drop use of VEX3SOURCES
2023-02-03 7:43 [PATCH 0/3] x86: drop VexSources attribute Jan Beulich
2023-02-03 7:44 ` [PATCH 1/3] x86: limit use of XOP2SOURCES Jan Beulich
2023-02-03 7:45 ` [PATCH 2/3] x86: drop " Jan Beulich
@ 2023-02-03 7:46 ` Jan Beulich
2 siblings, 0 replies; 4+ messages in thread
From: Jan Beulich @ 2023-02-03 7:46 UTC (permalink / raw)
To: Binutils; +Cc: H.J. Lu
The attribute really specifies that the sum of register and memory
operands is 4. Express it like that in most places, while using the 2nd
(apart from XOP) CPU feature flags (FMA4) in reversed operand matching
logic.
With the use in build_modrm_byte() gone, part of an assertion there
also becomes meaningless - simplify that at the same time.
With all uses of the opcode modifier field gone, also drop that.
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -2135,16 +2135,15 @@ operand_size_match (const insn_template
return match;
/* Check reverse. */
- gas_assert ((i.operands >= 2 && i.operands <= 3)
- || t->opcode_modifier.vexsources);
+ gas_assert (i.operands >= 2);
for (j = 0; j < i.operands; j++)
{
unsigned int given = i.operands - j - 1;
- /* For 4-operand and XOP insns VEX.W controls just the first two
+ /* For FMA4 and XOP insns VEX.W controls just the first two
register operands. */
- if (t->opcode_modifier.vexsources || t->cpu_flags.bitfield.cpuxop)
+ if (t->cpu_flags.bitfield.cpufma4 || t->cpu_flags.bitfield.cpuxop)
given = j < 2 ? 1 - j : j;
if (t->operand_types[j].bitfield.class == Reg
@@ -4665,7 +4664,7 @@ load_insn_p (void)
/* Check fake imm8 operand and 3 source operands. */
if ((i.tm.opcode_modifier.immext
- || i.tm.opcode_modifier.vexsources == VEX3SOURCES)
+ || i.reg_operands + i.mem_operands == 4)
&& i.types[dest].bitfield.imm8)
dest--;
@@ -6933,7 +6932,7 @@ match_template (char mnem_suffix)
if (!(size_match & MATCH_REVERSE))
continue;
/* Try reversing direction of operands. */
- j = t->opcode_modifier.vexsources
+ j = t->cpu_flags.bitfield.cpufma4
|| t->cpu_flags.bitfield.cpuxop ? 1 : i.operands - 1;
overlap0 = operand_type_and (i.types[0], operand_types[j]);
overlap1 = operand_type_and (i.types[j], operand_types[0]);
@@ -6968,7 +6967,7 @@ match_template (char mnem_suffix)
&& (intel_syntax || intel_mnemonic))
found_reverse_match |= Opcode_FloatR;
}
- else if (t->opcode_modifier.vexsources
+ else if (t->cpu_flags.bitfield.cpufma4
|| t->cpu_flags.bitfield.cpuxop)
{
found_reverse_match = Opcode_VexW;
@@ -7930,7 +7929,6 @@ process_operands (void)
if (i.tm.operand_types[0].bitfield.instance == Accum
&& i.tm.operand_types[0].bitfield.xmmword)
{
- gas_assert (i.tm.opcode_modifier.vexsources == VEX3SOURCES);
/* Keep xmm0 for instructions with VEX prefix and 3
sources. */
i.tm.operand_types[0].bitfield.instance = InstanceNone;
@@ -7941,9 +7939,7 @@ process_operands (void)
if (i.tm.opcode_modifier.operandconstraint == IMPLICIT_1ST_XMM0)
{
- gas_assert ((MAX_OPERANDS - 1) > dupl
- && (i.tm.opcode_modifier.vexsources
- == VEX3SOURCES));
+ gas_assert ((MAX_OPERANDS - 1) > dupl);
/* Add the implicit xmm0 for instructions with VEX prefix
and 3 sources. */
@@ -8168,9 +8164,8 @@ build_modrm_byte (void)
{
const reg_entry *default_seg = NULL;
unsigned int source, dest;
- int vex_3_sources;
+ bool vex_3_sources = (i.reg_operands + i.mem_operands == 4);
- vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
if (vex_3_sources)
{
unsigned int nds, reg_slot;
@@ -8186,9 +8181,7 @@ build_modrm_byte (void)
ZMM register.
2. 4 operands: 4 register operands or 3 register operands
plus 1 memory operand, with VexXDS. */
- gas_assert ((i.reg_operands == 4
- || (i.reg_operands == 3 && i.mem_operands == 1))
- && i.tm.opcode_modifier.vexvvvv == VEXXDS
+ gas_assert (i.tm.opcode_modifier.vexvvvv == VEXXDS
&& i.tm.opcode_modifier.vexw
&& i.tm.operand_types[dest].bitfield.class == RegSIMD);
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -431,7 +431,6 @@ static bitfield opcode_modifiers[] =
BITFIELD (VexVVVV),
BITFIELD (VexW),
BITFIELD (OpcodePrefix),
- BITFIELD (VexSources),
BITFIELD (SIB),
BITFIELD (SSE2AVX),
BITFIELD (EVex),
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -617,12 +617,6 @@ enum
#define PREFIX_0XF3 2
#define PREFIX_0XF2 3
OpcodePrefix,
- /* number of VEX source operands:
- 0: <= 2 source operands.
- 2: 3 source operands.
- */
-#define VEX3SOURCES 2
- VexSources,
/* Instruction with a mandatory SIB byte:
1: 128bit vector register.
2: 256bit vector register.
@@ -736,7 +730,6 @@ typedef struct i386_opcode_modifier
unsigned int vexvvvv:2;
unsigned int vexw:2;
unsigned int opcodeprefix:2;
- unsigned int vexsources:2;
unsigned int sib:3;
unsigned int sse2avx:1;
unsigned int evex:3;
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -1338,8 +1338,8 @@ pabsd<ssse3>, 0x<ssse3:pfx>0f381e, <ssse
<sd:ppfx:spfx:opc:vexw:elem, s::f3:0:VexW0:Dword, d:66:f2:1:VexW1:Qword>
blendp<sd><sse41>, 0x660f3a0c | <sd:opc>, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
-blendvp<sd>, 0x664a | <sd:opc>, AVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|VexSources=2|NoSuf|SSE2AVX, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM }
-blendvp<sd>, 0x664a | <sd:opc>, AVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|VexSources=2|NoSuf|Implicit1stXmm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
+blendvp<sd>, 0x664a | <sd:opc>, AVX, Modrm|Vex128|Space0F3A|VexVVVV|VexW0|NoSuf|SSE2AVX, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM }
+blendvp<sd>, 0x664a | <sd:opc>, AVX, Modrm|Vex128|Space0F3A|VexVVVV|VexW0|NoSuf|Implicit1stXmm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
blendvp<sd>, 0x660f3814 | <sd:opc>, SSE4_1, Modrm|NoSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM }
blendvp<sd>, 0x660f3814 | <sd:opc>, SSE4_1, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
dpp<sd><sse41>, 0x660f3a40 | <sd:opc>, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
@@ -1351,8 +1351,8 @@ insertps<sse41>, 0x660f3a21, <sse41:cpu>
movntdqa<sse41>, 0x660f382a, <sse41:cpu>, Modrm|<sse41:attr>|NoSuf, { Xmmword|Unspecified|BaseIndex, RegXMM }
mpsadbw<sse41>, 0x660f3a42, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
packusdw<sse41>, 0x660f382b, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
-pblendvb, 0x664c, AVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|VexSources=2|NoSuf|SSE2AVX, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM }
-pblendvb, 0x664c, AVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|VexSources=2|NoSuf|Implicit1stXmm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
+pblendvb, 0x664c, AVX, Modrm|Vex128|Space0F3A|VexVVVV|VexW0|NoSuf|SSE2AVX, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM }
+pblendvb, 0x664c, AVX, Modrm|Vex128|Space0F3A|VexVVVV|VexW0|NoSuf|Implicit1stXmm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pblendvb, 0x660f3810, SSE4_1, Modrm|NoSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM }
pblendvb, 0x660f3810, SSE4_1, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
pblendw<sse41>, 0x660f3a0e, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
@@ -1485,7 +1485,7 @@ vaddsubps, 0xf2d0, AVX, Modrm|Vex|Space0
vandnp<sd>, 0x<sd:ppfx>55, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vandp<sd>, 0x<sd:ppfx>54, AVX, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vblendp<sd>, 0x660c | <sd:opc>, AVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vblendvp<sd>, 0x664a | <sd:opc>, AVX, Modrm|Vex|Space0F3A|VexVVVV|VexW0|VexSources=2|CheckOperandSize|NoSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
+vblendvp<sd>, 0x664a | <sd:opc>, AVX, Modrm|Vex|Space0F3A|VexVVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vbroadcastf128, 0x661a, AVX, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { Xmmword|Unspecified|BaseIndex, RegYMM }
vbroadcastsd, 0x6619, AVX, Modrm|Vex256|Space0F38|VexW0|NoSuf, { Qword|Unspecified|BaseIndex, RegYMM }
vbroadcastss, 0x6618, AVX, Modrm|Vex128|Space0F38|VexW0|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM|RegYMM }
@@ -1581,7 +1581,7 @@ vpalignr, 0x660f, AVX|AVX2, Modrm|Vex|Sp
vpand, 0x66db, AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpandn, 0x66df, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpavg<bw>, 0x66e0 | (3 * <bw:opc>), AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vpblendvb, 0x664c, AVX|AVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckOperandSize|VexSources=2|NoSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
+vpblendvb, 0x664c, AVX|AVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpblendw, 0x660e, AVX|AVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpcmpeq<bw>, 0x6674 | <bw:opc>, AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpcmpeqd, 0x6676, AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
@@ -1828,16 +1828,16 @@ shrx, 0xf2f7, BMI2, Modrm|CheckOperandSi
// FMA4 instructions
-vfmaddp<sd>, 0x6668 | <sd:opc>, FMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vfmadds<sd>, 0x666a | <sd:opc>, FMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
-vfmaddsubp<sd>, 0x665c | <sd:opc>, FMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vfmsubaddp<sd>, 0x665e | <sd:opc>, FMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vfmsubp<sd>, 0x666c | <sd:opc>, FMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vfmsubs<sd>, 0x666e | <sd:opc>, FMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
-vfnmaddp<sd>, 0x6678 | <sd:opc>, FMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vfnmadds<sd>, 0x667a | <sd:opc>, FMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
-vfnmsubp<sd>, 0x667c | <sd:opc>, FMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vfnmsubs<sd>, 0x667e | <sd:opc>, FMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
+vfmaddp<sd>, 0x6668 | <sd:opc>, FMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
+vfmadds<sd>, 0x666a | <sd:opc>, FMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
+vfmaddsubp<sd>, 0x665c | <sd:opc>, FMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
+vfmsubaddp<sd>, 0x665e | <sd:opc>, FMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
+vfmsubp<sd>, 0x666c | <sd:opc>, FMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
+vfmsubs<sd>, 0x666e | <sd:opc>, FMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
+vfnmaddp<sd>, 0x6678 | <sd:opc>, FMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
+vfnmadds<sd>, 0x667a | <sd:opc>, FMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
+vfnmsubp<sd>, 0x667c | <sd:opc>, FMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
+vfnmsubs<sd>, 0x667e | <sd:opc>, FMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
// XOP instructions
@@ -1847,11 +1847,11 @@ vfnmsubs<sd>, 0x667e | <sd:opc>, FMA4, D
vfrczp<sd>, 0x80 | <sd:opc>, XOP, Modrm|SpaceXOP09|VexW0|CheckOperandSize|NoSuf|Vex, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
vfrczs<sd>, 0x82 | <sd:opc>, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { <sd:elem>|RegXMM|Unspecified|BaseIndex, RegXMM }
-vpcmov, 0xa2, XOP, D|Modrm|SpaceXOP08|VexSources=2|VexVVVV|VexW0|CheckOperandSize|NoSuf|Vex, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
+vpcmov, 0xa2, XOP, D|Modrm|Vex|SpaceXOP08|VexVVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpcom<sign><xop>, 0xcc | 0x<sign:opc> | <xop:opc>, XOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcom<irel><sign><xop>, 0xcc | 0x<sign:opc> | <xop:opc>/<irel:imm>, XOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
-vpermil2p<sd>, 0x6648 | <sd:opc>, XOP, Modrm|Space0F3A|VexVVVV|VexW0|Vex|VexSources=2|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vpermil2p<sd>, 0x6648 | <sd:opc>, XOP, Modrm|Space0F3A|VexVVVV|VexW1|Vex|VexSources=2|CheckOperandSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
+vpermil2p<sd>, 0x6648 | <sd:opc>, XOP, Modrm|Vex|Space0F3A|VexVVVV|VexW0|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
+vpermil2p<sd>, 0x6648 | <sd:opc>, XOP, Modrm|Vex|Space0F3A|VexVVVV|VexW1|CheckOperandSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vphaddb<dq>, 0xc2 | <dq:opc>, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM }
vphaddbw, 0xc1, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM }
vphadddq, 0xcb, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM }
@@ -1863,19 +1863,19 @@ vphaddw<dq>, 0xc6 | <dq:opc>, XOP, Modrm
vphsubbw, 0xe1, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM }
vphsubdq, 0xe3, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM }
vphsubwd, 0xe2, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM }
-vpmacsdd, 0x9e, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
-vpmacsdqh, 0x9f, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
-vpmacsdql, 0x97, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
-vpmacssdd, 0x8e, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
-vpmacssdqh, 0x8f, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
-vpmacssdql, 0x87, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
-vpmacsswd, 0x86, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
-vpmacssww, 0x85, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
-vpmacswd, 0x96, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
-vpmacsww, 0x95, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
-vpmadcsswd, 0xa6, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
-vpmadcswd, 0xb6, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
-vpperm, 0xa3, XOP, D|Modrm|SpaceXOP08|VexSources=2|VexVVVV|VexW0|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
+vpmacsdd, 0x9e, XOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
+vpmacsdqh, 0x9f, XOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
+vpmacsdql, 0x97, XOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
+vpmacssdd, 0x8e, XOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
+vpmacssdqh, 0x8f, XOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
+vpmacssdql, 0x87, XOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
+vpmacsswd, 0x86, XOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
+vpmacssww, 0x85, XOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
+vpmacswd, 0x96, XOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
+vpmacsww, 0x95, XOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
+vpmadcsswd, 0xa6, XOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
+vpmadcswd, 0xb6, XOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
+vpperm, 0xa3, XOP, D|Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vprot<xop>, 0x90 | <xop:opc>, XOP, D|Modrm|Vex128|SpaceXOP09|VexVVVV|SwapSources|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
vprot<xop>, 0xc0 | <xop:opc>, XOP, Modrm|Vex128|SpaceXOP08|VexW0|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
vpsha<xop>, 0x98 | <xop:opc>, XOP, D|Modrm|Vex128|SpaceXOP09|VexVVVV|SwapSources|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2023-02-03 7:46 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2023-02-03 7:43 [PATCH 0/3] x86: drop VexSources attribute Jan Beulich
2023-02-03 7:44 ` [PATCH 1/3] x86: limit use of XOP2SOURCES Jan Beulich
2023-02-03 7:45 ` [PATCH 2/3] x86: drop " Jan Beulich
2023-02-03 7:46 ` [PATCH 3/3] x86: drop use of VEX3SOURCES Jan Beulich
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