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Express it like that in most places, while using the 2nd (apart from XOP) CPU feature flags (FMA4) in reversed operand matching logic. With the use in build_modrm_byte() gone, part of an assertion there also becomes meaningless - simplify that at the same time. With all uses of the opcode modifier field gone, also drop that. --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -2135,16 +2135,15 @@ operand_size_match (const insn_template return match; /* Check reverse. */ - gas_assert ((i.operands >= 2 && i.operands <= 3) - || t->opcode_modifier.vexsources); + gas_assert (i.operands >= 2); for (j = 0; j < i.operands; j++) { unsigned int given = i.operands - j - 1; - /* For 4-operand and XOP insns VEX.W controls just the first two + /* For FMA4 and XOP insns VEX.W controls just the first two register operands. */ - if (t->opcode_modifier.vexsources || t->cpu_flags.bitfield.cpuxop) + if (t->cpu_flags.bitfield.cpufma4 || t->cpu_flags.bitfield.cpuxop) given = j < 2 ? 1 - j : j; if (t->operand_types[j].bitfield.class == Reg @@ -4665,7 +4664,7 @@ load_insn_p (void) /* Check fake imm8 operand and 3 source operands. */ if ((i.tm.opcode_modifier.immext - || i.tm.opcode_modifier.vexsources == VEX3SOURCES) + || i.reg_operands + i.mem_operands == 4) && i.types[dest].bitfield.imm8) dest--; @@ -6933,7 +6932,7 @@ match_template (char mnem_suffix) if (!(size_match & MATCH_REVERSE)) continue; /* Try reversing direction of operands. */ - j = t->opcode_modifier.vexsources + j = t->cpu_flags.bitfield.cpufma4 || t->cpu_flags.bitfield.cpuxop ? 1 : i.operands - 1; overlap0 = operand_type_and (i.types[0], operand_types[j]); overlap1 = operand_type_and (i.types[j], operand_types[0]); @@ -6968,7 +6967,7 @@ match_template (char mnem_suffix) && (intel_syntax || intel_mnemonic)) found_reverse_match |= Opcode_FloatR; } - else if (t->opcode_modifier.vexsources + else if (t->cpu_flags.bitfield.cpufma4 || t->cpu_flags.bitfield.cpuxop) { found_reverse_match = Opcode_VexW; @@ -7930,7 +7929,6 @@ process_operands (void) if (i.tm.operand_types[0].bitfield.instance == Accum && i.tm.operand_types[0].bitfield.xmmword) { - gas_assert (i.tm.opcode_modifier.vexsources == VEX3SOURCES); /* Keep xmm0 for instructions with VEX prefix and 3 sources. */ i.tm.operand_types[0].bitfield.instance = InstanceNone; @@ -7941,9 +7939,7 @@ process_operands (void) if (i.tm.opcode_modifier.operandconstraint == IMPLICIT_1ST_XMM0) { - gas_assert ((MAX_OPERANDS - 1) > dupl - && (i.tm.opcode_modifier.vexsources - == VEX3SOURCES)); + gas_assert ((MAX_OPERANDS - 1) > dupl); /* Add the implicit xmm0 for instructions with VEX prefix and 3 sources. */ @@ -8168,9 +8164,8 @@ build_modrm_byte (void) { const reg_entry *default_seg = NULL; unsigned int source, dest; - int vex_3_sources; + bool vex_3_sources = (i.reg_operands + i.mem_operands == 4); - vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; if (vex_3_sources) { unsigned int nds, reg_slot; @@ -8186,9 +8181,7 @@ build_modrm_byte (void) ZMM register. 2. 4 operands: 4 register operands or 3 register operands plus 1 memory operand, with VexXDS. */ - gas_assert ((i.reg_operands == 4 - || (i.reg_operands == 3 && i.mem_operands == 1)) - && i.tm.opcode_modifier.vexvvvv == VEXXDS + gas_assert (i.tm.opcode_modifier.vexvvvv == VEXXDS && i.tm.opcode_modifier.vexw && i.tm.operand_types[dest].bitfield.class == RegSIMD); --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -431,7 +431,6 @@ static bitfield opcode_modifiers[] = BITFIELD (VexVVVV), BITFIELD (VexW), BITFIELD (OpcodePrefix), - BITFIELD (VexSources), BITFIELD (SIB), BITFIELD (SSE2AVX), BITFIELD (EVex), --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -617,12 +617,6 @@ enum #define PREFIX_0XF3 2 #define PREFIX_0XF2 3 OpcodePrefix, - /* number of VEX source operands: - 0: <= 2 source operands. - 2: 3 source operands. - */ -#define VEX3SOURCES 2 - VexSources, /* Instruction with a mandatory SIB byte: 1: 128bit vector register. 2: 256bit vector register. @@ -736,7 +730,6 @@ typedef struct i386_opcode_modifier unsigned int vexvvvv:2; unsigned int vexw:2; unsigned int opcodeprefix:2; - unsigned int vexsources:2; unsigned int sib:3; unsigned int sse2avx:1; unsigned int evex:3; --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -1338,8 +1338,8 @@ pabsd, 0x0f381e, blendp, 0x660f3a0c | , , Modrm|||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -blendvp, 0x664a | , AVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|VexSources=2|NoSuf|SSE2AVX, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } -blendvp, 0x664a | , AVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|VexSources=2|NoSuf|Implicit1stXmm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM } +blendvp, 0x664a | , AVX, Modrm|Vex128|Space0F3A|VexVVVV|VexW0|NoSuf|SSE2AVX, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } +blendvp, 0x664a | , AVX, Modrm|Vex128|Space0F3A|VexVVVV|VexW0|NoSuf|Implicit1stXmm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM } blendvp, 0x660f3814 | , SSE4_1, Modrm|NoSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } blendvp, 0x660f3814 | , SSE4_1, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } dpp, 0x660f3a40 | , , Modrm|||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } @@ -1351,8 +1351,8 @@ insertps, 0x660f3a21, movntdqa, 0x660f382a, , Modrm||NoSuf, { Xmmword|Unspecified|BaseIndex, RegXMM } mpsadbw, 0x660f3a42, , Modrm|||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } packusdw, 0x660f382b, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pblendvb, 0x664c, AVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|VexSources=2|NoSuf|SSE2AVX, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } -pblendvb, 0x664c, AVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|VexSources=2|NoSuf|Implicit1stXmm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM } +pblendvb, 0x664c, AVX, Modrm|Vex128|Space0F3A|VexVVVV|VexW0|NoSuf|SSE2AVX, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } +pblendvb, 0x664c, AVX, Modrm|Vex128|Space0F3A|VexVVVV|VexW0|NoSuf|Implicit1stXmm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM } pblendvb, 0x660f3810, SSE4_1, Modrm|NoSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } pblendvb, 0x660f3810, SSE4_1, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } pblendw, 0x660f3a0e, , Modrm|||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } @@ -1485,7 +1485,7 @@ vaddsubps, 0xf2d0, AVX, Modrm|Vex|Space0 vandnp, 0x55, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vandp, 0x54, AVX, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vblendp, 0x660c | , AVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vblendvp, 0x664a | , AVX, Modrm|Vex|Space0F3A|VexVVVV|VexW0|VexSources=2|CheckOperandSize|NoSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vblendvp, 0x664a | , AVX, Modrm|Vex|Space0F3A|VexVVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vbroadcastf128, 0x661a, AVX, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { Xmmword|Unspecified|BaseIndex, RegYMM } vbroadcastsd, 0x6619, AVX, Modrm|Vex256|Space0F38|VexW0|NoSuf, { Qword|Unspecified|BaseIndex, RegYMM } vbroadcastss, 0x6618, AVX, Modrm|Vex128|Space0F38|VexW0|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM|RegYMM } @@ -1581,7 +1581,7 @@ vpalignr, 0x660f, AVX|AVX2, Modrm|Vex|Sp vpand, 0x66db, AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpandn, 0x66df, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpavg, 0x66e0 | (3 * ), AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpblendvb, 0x664c, AVX|AVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckOperandSize|VexSources=2|NoSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpblendvb, 0x664c, AVX|AVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpblendw, 0x660e, AVX|AVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpcmpeq, 0x6674 | , AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpcmpeqd, 0x6676, AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } @@ -1828,16 +1828,16 @@ shrx, 0xf2f7, BMI2, Modrm|CheckOperandSi // FMA4 instructions -vfmaddp, 0x6668 | , FMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfmadds, 0x666a | , FMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } -vfmaddsubp, 0x665c | , FMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfmsubaddp, 0x665e | , FMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfmsubp, 0x666c | , FMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfmsubs, 0x666e | , FMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } -vfnmaddp, 0x6678 | , FMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfnmadds, 0x667a | , FMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } -vfnmsubp, 0x667c | , FMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfnmsubs, 0x667e | , FMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } +vfmaddp, 0x6668 | , FMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfmadds, 0x666a | , FMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } +vfmaddsubp, 0x665c | , FMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfmsubaddp, 0x665e | , FMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfmsubp, 0x666c | , FMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfmsubs, 0x666e | , FMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } +vfnmaddp, 0x6678 | , FMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfnmadds, 0x667a | , FMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } +vfnmsubp, 0x667c | , FMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfnmsubs, 0x667e | , FMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } // XOP instructions @@ -1847,11 +1847,11 @@ vfnmsubs, 0x667e | , FMA4, D vfrczp, 0x80 | , XOP, Modrm|SpaceXOP09|VexW0|CheckOperandSize|NoSuf|Vex, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } vfrczs, 0x82 | , XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { |RegXMM|Unspecified|BaseIndex, RegXMM } -vpcmov, 0xa2, XOP, D|Modrm|SpaceXOP08|VexSources=2|VexVVVV|VexW0|CheckOperandSize|NoSuf|Vex, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpcmov, 0xa2, XOP, D|Modrm|Vex|SpaceXOP08|VexVVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpcom, 0xcc | 0x | , XOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } vpcom, 0xcc | 0x | /, XOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpermil2p, 0x6648 | , XOP, Modrm|Space0F3A|VexVVVV|VexW0|Vex|VexSources=2|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpermil2p, 0x6648 | , XOP, Modrm|Space0F3A|VexVVVV|VexW1|Vex|VexSources=2|CheckOperandSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpermil2p, 0x6648 | , XOP, Modrm|Vex|Space0F3A|VexVVVV|VexW0|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpermil2p, 0x6648 | , XOP, Modrm|Vex|Space0F3A|VexVVVV|VexW1|CheckOperandSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vphaddb, 0xc2 | , XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } vphaddbw, 0xc1, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } vphadddq, 0xcb, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } @@ -1863,19 +1863,19 @@ vphaddw, 0xc6 | , XOP, Modrm vphsubbw, 0xe1, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } vphsubdq, 0xe3, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } vphsubwd, 0xe2, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } -vpmacsdd, 0x9e, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacsdqh, 0x9f, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacsdql, 0x97, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacssdd, 0x8e, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacssdqh, 0x8f, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacssdql, 0x87, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacsswd, 0x86, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacssww, 0x85, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacswd, 0x96, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacsww, 0x95, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmadcsswd, 0xa6, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmadcswd, 0xb6, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpperm, 0xa3, XOP, D|Modrm|SpaceXOP08|VexSources=2|VexVVVV|VexW0|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacsdd, 0x9e, XOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacsdqh, 0x9f, XOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacsdql, 0x97, XOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacssdd, 0x8e, XOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacssdqh, 0x8f, XOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacssdql, 0x87, XOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacsswd, 0x86, XOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacssww, 0x85, XOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacswd, 0x96, XOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacsww, 0x95, XOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmadcsswd, 0xa6, XOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmadcswd, 0xb6, XOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpperm, 0xa3, XOP, D|Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } vprot, 0x90 | , XOP, D|Modrm|Vex128|SpaceXOP09|VexVVVV|SwapSources|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM } vprot, 0xc0 | , XOP, Modrm|Vex128|SpaceXOP08|VexW0|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } vpsha, 0x98 | , XOP, D|Modrm|Vex128|SpaceXOP09|VexVVVV|SwapSources|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }