From: "Andre Vieira (lists)" <andre.simoesdiasvieira@arm.com>
To: binutils@sourceware.org
Subject: [PATCH 16/57][Arm][GAS] Add support for MVE instructions: vdup, vddup, vdwdup, vidup and viwdup
Date: Wed, 01 May 2019 17:09:00 -0000 [thread overview]
Message-ID: <137d8ebb-fad6-70ee-4fca-7145ab1bd83f@arm.com> (raw)
In-Reply-To: <19569550-4d2e-0bb3-592a-d91050d490f6@arm.com>
[-- Attachment #1: Type: text/plain, Size: 898 bytes --]
Hi,
This patch adds support for MVE instructions VDUP, VDDUP, VDWDUP, VIDUP,
and VIWDUP.
gas/ChangeLog:
2019-05-01 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (M_MNEM_vddup, M_MNEM_vdwdup, M_MNEM_vidup,
M_MNEM_viwdup): New instruction encodings.
(NEON_SHAPE_DEF): New shapes.
(do_mve_viddup): New encoding function.
(do_neon_dup): Change to support new MVE variants.
(insns): Change existing to accept MVE variants and add new.
* testsuite/gas/arm/mve-vddup-bad.d: New test.
* testsuite/gas/arm/mve-vddup-bad.l: New test.
* testsuite/gas/arm/mve-vddup-bad.s: New test.
* testsuite/gas/arm/mve-vdup-bad.d: New test.
* testsuite/gas/arm/mve-vdup-bad.l: New test.
* testsuite/gas/arm/mve-vdup-bad.s: New test.
* testsuite/gas/arm/mve-vidup-bad.d: New test.
* testsuite/gas/arm/mve-vidup-bad.l: New test.
* testsuite/gas/arm/mve-vidup-bad.s: New test.
[-- Attachment #2: 16.patch --]
[-- Type: text/x-patch, Size: 15205 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index e739c5b94ab1924f65a262e15342a748e2a4dc40..af6550eeb95db17f444acc7e6bfdb73e3dc14f3c 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -14157,6 +14157,10 @@ do_t_loloop (void)
#define M_MNEM_vaddlva 0xee890f20
#define M_MNEM_vaddv 0xeef10f00
#define M_MNEM_vaddva 0xeef10f20
+#define M_MNEM_vddup 0xee011f6e
+#define M_MNEM_vdwdup 0xee011f60
+#define M_MNEM_vidup 0xee010f6e
+#define M_MNEM_viwdup 0xee010f60
/* Neon instruction encoder helpers. */
@@ -14321,8 +14325,10 @@ NEON_ENC_TAB
- a table used to drive neon_select_shape. */
#define NEON_SHAPE_DEF \
+ X(4, (Q, R, R, I), QUAD), \
X(4, (R, R, S, S), QUAD), \
X(4, (S, S, R, R), QUAD), \
+ X(3, (Q, R, I), QUAD), \
X(3, (I, Q, Q), QUAD), \
X(3, (I, Q, R), QUAD), \
X(3, (R, Q, Q), QUAD), \
@@ -15608,6 +15614,49 @@ do_mve_vfmas (void)
inst.is_neon = 1;
}
+static void
+do_mve_viddup (void)
+{
+ if (inst.cond > COND_ALWAYS)
+ inst.pred_insn_type = INSIDE_VPT_INSN;
+ else
+ inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
+
+ unsigned imm = inst.relocs[0].exp.X_add_number;
+ constraint (imm != 1 && imm != 2 && imm != 4 && imm != 8,
+ _("immediate must be either 1, 2, 4 or 8"));
+
+ enum neon_shape rs;
+ struct neon_type_el et;
+ unsigned Rm;
+ if (inst.instruction == M_MNEM_vddup || inst.instruction == M_MNEM_vidup)
+ {
+ rs = neon_select_shape (NS_QRI, NS_NULL);
+ et = neon_check_type (2, rs, N_KEY | N_U8 | N_U16 | N_U32, N_EQK);
+ Rm = 7;
+ }
+ else
+ {
+ constraint ((inst.operands[2].reg % 2) != 1, BAD_EVEN);
+ if (inst.operands[2].reg == REG_SP)
+ as_tsktsk (MVE_BAD_SP);
+ else if (inst.operands[2].reg == REG_PC)
+ first_error (BAD_PC);
+
+ rs = neon_select_shape (NS_QRRI, NS_NULL);
+ et = neon_check_type (3, rs, N_KEY | N_U8 | N_U16 | N_U32, N_EQK, N_EQK);
+ Rm = inst.operands[2].reg >> 1;
+ }
+ inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+ inst.instruction |= neon_logbits (et.size) << 20;
+ inst.instruction |= inst.operands[1].reg << 16;
+ inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+ inst.instruction |= (imm > 2) << 7;
+ inst.instruction |= Rm << 1;
+ inst.instruction |= (imm == 2 || imm == 8);
+ inst.is_neon = 1;
+}
+
static void
do_mve_vcmul (void)
{
@@ -18407,6 +18456,8 @@ do_neon_dup (void)
{
if (inst.operands[1].isscalar)
{
+ constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1),
+ BAD_FPU);
enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
struct neon_type_el et = neon_check_type (2, rs,
N_EQK, N_8 | N_16 | N_32 | N_KEY);
@@ -18434,6 +18485,23 @@ do_neon_dup (void)
enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
struct neon_type_el et = neon_check_type (2, rs,
N_8 | N_16 | N_32 | N_KEY, N_EQK);
+ if (rs == NS_QR)
+ {
+ if (check_simd_pred_availability (0, NEON_CHECK_ARCH))
+ return;
+ }
+ else
+ constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1),
+ BAD_FPU);
+
+ if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
+ {
+ if (inst.operands[1].reg == REG_SP)
+ as_tsktsk (MVE_BAD_SP);
+ else if (inst.operands[1].reg == REG_PC)
+ as_tsktsk (MVE_BAD_PC);
+ }
+
/* Duplicate ARM register to lanes of vector. */
NEON_ENCODE (ARMREG, inst);
switch (et.size)
@@ -23659,7 +23727,6 @@ static const struct asm_opcode insns[] =
NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
/* Vector replicate. Sizes 8 16 32. */
- nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup),
nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
/* VMOVL. Types S8 S16 S32 U8 U16 U32. */
NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
@@ -24221,6 +24288,10 @@ static const struct asm_opcode insns[] =
mCEF(vaddlva, _vaddlva, 3, (RRe, RRo, RMQ), mve_vaddlv),
mCEF(vaddv, _vaddv, 2, (RRe, RMQ), mve_vaddv),
mCEF(vaddva, _vaddva, 2, (RRe, RMQ), mve_vaddv),
+ mCEF(vddup, _vddup, 3, (RMQ, RRe, EXPi), mve_viddup),
+ mCEF(vdwdup, _vdwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup),
+ mCEF(vidup, _vidup, 3, (RMQ, RRe, EXPi), mve_viddup),
+ mCEF(viwdup, _viwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup),
#undef THUMB_VARIANT
#define THUMB_VARIANT & mve_fp_ext
@@ -24283,6 +24354,7 @@ static const struct asm_opcode insns[] =
mnUF(veor, _veor, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_logic),
MNUF(vcls, 1b00400, 2, (RNDQMQ, RNDQMQ), neon_cls),
MNUF(vclz, 1b00480, 2, (RNDQMQ, RNDQMQ), neon_clz),
+ mnCE(vdup, _vdup, 2, (RNDQMQ, RR_RNSC), neon_dup),
#undef ARM_VARIANT
#define ARM_VARIANT & arm_ext_v8_3
diff --git a/gas/testsuite/gas/arm/mve-vddup-bad.d b/gas/testsuite/gas/arm/mve-vddup-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..a6522dc25423352b027d58a0b0f495f7f0705245
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vddup-bad.d
@@ -0,0 +1,6 @@
+#name: bad MVE VDDUP and VDWDUP instructions
+#as: -march=armv8.1-m.main+mve
+#error_output: mve-vddup-bad.l
+
+.*: +file format .*arm.*
+
diff --git a/gas/testsuite/gas/arm/mve-vddup-bad.l b/gas/testsuite/gas/arm/mve-vddup-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..92ff9657446829f1f703d99be34384d21307e3a9
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vddup-bad.l
@@ -0,0 +1,33 @@
+[^:]*: Assembler messages:
+[^:]*:16: Error: bad type in SIMD instruction -- `vddup.s16 q0,r0,#1'
+[^:]*:17: Error: bad type in SIMD instruction -- `vddup.u64 q0,r0,#1'
+[^:]*:18: Error: immediate must be either 1, 2, 4 or 8 -- `vddup.u32 q0,r0,#3'
+[^:]*:19: Error: immediate must be either 1, 2, 4 or 8 -- `vddup.u32 q0,r0,#0'
+[^:]*:20: Error: bad type in SIMD instruction -- `vdwdup.s16 q0,r0,r1,#1'
+[^:]*:21: Error: bad type in SIMD instruction -- `vdwdup.u64 q0,r0,r1,#1'
+[^:]*:22: Error: immediate must be either 1, 2, 4 or 8 -- `vdwdup.u32 q0,r0,r1,#3'
+[^:]*:23: Error: immediate must be either 1, 2, 4 or 8 -- `vdwdup.u32 q0,r0,r1,#0'
+[^:]*:24: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:25: Error: r15 not allowed here -- `vdwdup.u32 q0,r0,pc,#1'
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Error: syntax error -- `vddupeq.u32 q0,r0,#1'
+[^:]*:30: Error: syntax error -- `vddupeq.u32 q0,r0,#1'
+[^:]*:32: Error: syntax error -- `vddupeq.u32 q0,r0,#1'
+[^:]*:33: Error: vector predicated instruction should be in VPT/VPST block -- `vddupt.u32 q0,r0,#1'
+[^:]*:35: Error: instruction missing MVE vector predication code -- `vddup.u32 q0,r0,#1'
+[^:]*:37: Error: syntax error -- `vdwdupeq.u32 q0,r0,r1,#1'
+[^:]*:38: Error: syntax error -- `vdwdupeq.u32 q0,r0,r1,#1'
+[^:]*:40: Error: syntax error -- `vdwdupeq.u32 q0,r0,r1,#1'
+[^:]*:41: Error: vector predicated instruction should be in VPT/VPST block -- `vdwdupt.u32 q0,r0,r1,#1'
+[^:]*:43: Error: instruction missing MVE vector predication code -- `vdwdup.u32 q0,r0,r1,#1'
diff --git a/gas/testsuite/gas/arm/mve-vddup-bad.s b/gas/testsuite/gas/arm/mve-vddup-bad.s
new file mode 100644
index 0000000000000000000000000000000000000000..9951e9d11843d3302823e7805bbbe20abc79d3eb
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vddup-bad.s
@@ -0,0 +1,43 @@
+.macro cond1
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vddup.u32 q0, r2, #1
+.endr
+.endm
+
+.macro cond2
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vdwdup.u32 q0, r2, r1, #1
+.endr
+.endm
+.syntax unified
+.thumb
+vddup.s16 q0, r0, #1
+vddup.u64 q0, r0, #1
+vddup.u32 q0, r0, #3
+vddup.u32 q0, r0, #0
+vdwdup.s16 q0, r0, r1, #1
+vdwdup.u64 q0, r0, r1, #1
+vdwdup.u32 q0, r0, r1, #3
+vdwdup.u32 q0, r0, r1, #0
+vdwdup.u32 q0, r0, sp, #1
+vdwdup.u32 q0, r0, pc, #1
+cond1
+cond2
+it eq
+vddupeq.u32 q0, r0, #1
+vddupeq.u32 q0, r0, #1
+vpst
+vddupeq.u32 q0, r0, #1
+vddupt.u32 q0, r0, #1
+vpst
+vddup.u32 q0, r0, #1
+it eq
+vdwdupeq.u32 q0, r0, r1, #1
+vdwdupeq.u32 q0, r0, r1, #1
+vpst
+vdwdupeq.u32 q0, r0, r1, #1
+vdwdupt.u32 q0, r0, r1, #1
+vpst
+vdwdup.u32 q0, r0, r1, #1
diff --git a/gas/testsuite/gas/arm/mve-vdup-bad.d b/gas/testsuite/gas/arm/mve-vdup-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..2ad95976135bb46535720195d17b0024cf391abc
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vdup-bad.d
@@ -0,0 +1,5 @@
+#name: bad MVE VDUP instructions
+#as: -march=armv8.1-m.main+mve
+#error_output: mve-vdup-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vdup-bad.l b/gas/testsuite/gas/arm/mve-vdup-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..08808393569f7e7a839680b001e38e9f1ca66886
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vdup-bad.l
@@ -0,0 +1,16 @@
+[^:]*: Assembler messages:
+[^:]*:11: Error: bad type in SIMD instruction -- `vdup.64 q0,r1'
+[^:]*:12: Error: selected FPU does not support instruction -- `vdup.32 q0,d0\[1\]'
+[^:]*:13: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:14: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Error: syntax error -- `vdupeq.32 q0,r2'
+[^:]*:18: Error: syntax error -- `vdupeq.32 q0,r2'
+[^:]*:20: Error: syntax error -- `vdupeq.32 q0,r2'
+[^:]*:21: Error: incorrect condition in VPT/VPST block -- `vdupt.32 q0,r2'
+[^:]*:23: Error: instruction missing MVE vector predication code -- `vdup.32 q0,r2'
diff --git a/gas/testsuite/gas/arm/mve-vdup-bad.s b/gas/testsuite/gas/arm/mve-vdup-bad.s
new file mode 100644
index 0000000000000000000000000000000000000000..c6539d860575184fcf6745d165995edf80270f6e
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vdup-bad.s
@@ -0,0 +1,23 @@
+.macro cond
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vdup.32 q0, r2
+.endr
+.endm
+
+.syntax unified
+.thumb
+vdup.f16 q0, r1
+vdup.64 q0, r1
+vdup.32 q0, d0[1]
+vdup.32 q0, sp
+vdup.32 q0, pc
+cond
+it eq
+vdupeq.32 q0, r2
+vdupeq.32 q0, r2
+vpste
+vdupeq.32 q0, r2
+vdupt.32 q0, r2
+vpst
+vdup.32 q0, r2
diff --git a/gas/testsuite/gas/arm/mve-vidup-bad.d b/gas/testsuite/gas/arm/mve-vidup-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..6a9a0384048c05c0f962130078755c6dd983e962
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vidup-bad.d
@@ -0,0 +1,5 @@
+#name: bad MVE VIDUP and VIWDUP instructions
+#as: -march=armv8.1-m.main+mve
+#error_output: mve-vidup-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vidup-bad.l b/gas/testsuite/gas/arm/mve-vidup-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..5fb742559f5bd1573aa03ea767a56112a5acb9f0
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vidup-bad.l
@@ -0,0 +1,34 @@
+[^:]*: Assembler messages:
+[^:]*:16: Error: bad type in SIMD instruction -- `vidup.s16 q0,r0,#1'
+[^:]*:17: Error: bad type in SIMD instruction -- `vidup.u64 q0,r0,#1'
+[^:]*:18: Error: immediate must be either 1, 2, 4 or 8 -- `vidup.u32 q0,r0,#3'
+[^:]*:19: Error: immediate must be either 1, 2, 4 or 8 -- `vidup.u32 q0,r0,#0'
+[^:]*:20: Error: bad type in SIMD instruction -- `viwdup.s16 q0,r0,r1,#1'
+[^:]*:21: Error: bad type in SIMD instruction -- `viwdup.u64 q0,r0,r1,#1'
+[^:]*:22: Error: immediate must be either 1, 2, 4 or 8 -- `viwdup.u32 q0,r0,r1,#3'
+[^:]*:23: Error: immediate must be either 1, 2, 4 or 8 -- `viwdup.u32 q0,r0,r1,#0'
+[^:]*:24: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:25: Error: r15 not allowed here -- `viwdup.u32 q0,r0,pc,#1'
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Error: syntax error -- `vidupeq.u32 q0,r0,#1'
+[^:]*:30: Error: syntax error -- `vidupeq.u32 q0,r0,#1'
+[^:]*:32: Error: syntax error -- `vidupeq.u32 q0,r0,#1'
+[^:]*:33: Error: vector predicated instruction should be in VPT/VPST block -- `vidupt.u32 q0,r0,#1'
+[^:]*:35: Error: instruction missing MVE vector predication code -- `vidup.u32 q0,r0,#1'
+[^:]*:37: Error: syntax error -- `viwdupeq.u32 q0,r0,r1,#1'
+[^:]*:38: Error: syntax error -- `viwdupeq.u32 q0,r0,r1,#1'
+[^:]*:40: Error: syntax error -- `viwdupeq.u32 q0,r0,r1,#1'
+[^:]*:41: Error: vector predicated instruction should be in VPT/VPST block -- `viwdupt.u32 q0,r0,r1,#1'
+[^:]*:43: Error: instruction missing MVE vector predication code -- `viwdup.u32 q0,r0,r1,#1'
+
diff --git a/gas/testsuite/gas/arm/mve-vidup-bad.s b/gas/testsuite/gas/arm/mve-vidup-bad.s
new file mode 100644
index 0000000000000000000000000000000000000000..3d3a4488d9c780123754a3243241720a513f4d3c
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vidup-bad.s
@@ -0,0 +1,43 @@
+.macro cond1
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vidup.u32 q0, r2, #1
+.endr
+.endm
+
+.macro cond2
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+viwdup.u32 q0, r2, r1, #1
+.endr
+.endm
+.syntax unified
+.thumb
+vidup.s16 q0, r0, #1
+vidup.u64 q0, r0, #1
+vidup.u32 q0, r0, #3
+vidup.u32 q0, r0, #0
+viwdup.s16 q0, r0, r1, #1
+viwdup.u64 q0, r0, r1, #1
+viwdup.u32 q0, r0, r1, #3
+viwdup.u32 q0, r0, r1, #0
+viwdup.u32 q0, r0, sp, #1
+viwdup.u32 q0, r0, pc, #1
+cond1
+cond2
+it eq
+vidupeq.u32 q0, r0, #1
+vidupeq.u32 q0, r0, #1
+vpst
+vidupeq.u32 q0, r0, #1
+vidupt.u32 q0, r0, #1
+vpst
+vidup.u32 q0, r0, #1
+it eq
+viwdupeq.u32 q0, r0, r1, #1
+viwdupeq.u32 q0, r0, r1, #1
+vpst
+viwdupeq.u32 q0, r0, r1, #1
+viwdupt.u32 q0, r0, r1, #1
+vpst
+viwdup.u32 q0, r0, r1, #1
next prev parent reply other threads:[~2019-05-01 17:09 UTC|newest]
Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-01 16:51 [PATCH 0/57][Arm][binutils]: Add support for Armv8.1-M Mainline MVE instructions Andre Vieira (lists)
2019-05-01 16:53 ` [PATCH 1/57][Arm][GAS]: Add support for +mve and +mve.fp Andre Vieira (lists)
2019-05-01 16:55 ` [PATCH 2/57][Arm][GAS] Add support for MVE instructions: vpst, vadd, vsub and vabd Andre Vieira (lists)
2019-05-02 10:56 ` Nick Clifton
2019-05-13 13:42 ` Andre Vieira (lists)
[not found] ` <98e50dc4-7b0e-d727-0c20-34711be86533@redhat.com>
[not found] ` <4e56a5f3-bcde-f4cd-21d4-35cc3f11b5e8@arm.com>
2019-05-14 16:53 ` Nick Clifton
2019-05-14 16:54 ` Nick Clifton
2019-05-01 16:56 ` [PATCH 3/57][Arm][GAS] Add support for MVE instructions: vabs and vneg Andre Vieira (lists)
2019-05-01 16:57 ` [PATCH 4/57][Arm][GAS] Add support for MVE instructions: vabav, vmladav and vmlsdav Andre Vieira (lists)
2019-05-01 16:59 ` [PATCH 5/57][Arm][GAS] Add support for MVE instructions: vmull{b,t} Andre Vieira (lists)
2019-05-01 17:00 ` [PATCH 6/57][Arm][GAS] Add support for MVE instructions: vst/vld{2,4} Andre Vieira (lists)
2019-05-01 17:01 ` [PATCH 7/57][Arm][GAS] Add support for MVE instructions: vstr/vldr Andre Vieira (lists)
2019-05-01 17:02 ` [PATCH 8/57][Arm][GAS] Add support for MVE instructions: vcvt Andre Vieira (lists)
2019-05-01 17:03 ` [PATCH 9/57][Arm][GAS] Add support for MVE instructions: vmov Andre Vieira (lists)
2019-05-01 17:03 ` [PATCH 10/57][Arm][GAS] Add support for MVE instructions: vcmp and vpt Andre Vieira (lists)
2019-05-01 17:05 ` [PATCH 11/57][Arm][GAS] Add support for MVE instructions: vadc, vsbc and vbrsr Andre Vieira (lists)
2019-05-01 17:06 ` [PATCH 12/57][Arm][GAS] Add support for MVE instructions: vaddlv and vaddv Andre Vieira (lists)
2019-05-01 17:07 ` [PATCH 13/57][Arm][GAS] Add support for MVE instructions: vand, vbic, vorr, vorn and veor Andre Vieira (lists)
2019-05-01 17:08 ` [PATCH 14/57][Arm][GAS] Add support for MVE instructions: vcadd, vcmla and vcmul Andre Vieira (lists)
2019-05-01 17:09 ` [PATCH 15/57][Arm][GAS] Add support for MVE instructions: vcls, vclz and vfmas Andre Vieira (lists)
2019-05-01 17:09 ` Andre Vieira (lists) [this message]
2019-05-01 17:11 ` [PATCH 17/57][Arm][GAS] Add support for MVE instructions: vfma and vfms Andre Vieira (lists)
2019-05-01 17:12 ` [PATCH 18/57][Arm][GAS] Add support for MVE instructions: vhcadd, vhadd, vhsub and vrhadd Andre Vieira (lists)
2019-05-01 17:12 ` [PATCH 19/57][Arm][GAS] Add support for MVE instructions: vmax[nm][a] and vmin[nm][a] Andre Vieira (lists)
2019-05-01 17:13 ` [PATCH 21/57][Arm][GAS] Add support for MVE instructions: vmaxv, vmaxav, vminv and vminav Andre Vieira (lists)
2019-05-01 17:13 ` [PATCH 20/57][Arm][GAS] Add support for MVE instructions: vmaxnmv, vmaxnmav, vminnmv and vminnmav Andre Vieira (lists)
2019-05-01 17:15 ` [PATCH 23/57][Arm][GAS] Add support for MVE instructions: vmla, vmul, vqadd and vqsub Andre Vieira (lists)
2019-05-01 17:15 ` [PATCH 22/57][Arm][GAS] Add support for MVE instructions: vmlaldav, vmlalv, vmlsldav, vrmlaldavh, vrmlalvh and vrmlsldavh Andre Vieira (lists)
2019-05-01 17:16 ` [PATCH 24/57][Arm][GAS] Add support for MVE instructions: vmlas, vmulh and vrmulh Andre Vieira (lists)
2019-05-01 17:17 ` [PATCH 26/57][Arm][GAS] Add support for MVE instructions: vpnot and vpsel Andre Vieira (lists)
2019-05-01 17:17 ` [PATCH 25/57][Arm][GAS] Add support for MVE instruction: vmvn, vqabs and vqneg Andre Vieira (lists)
2019-05-01 17:18 ` [PATCH 0/57][Arm][binutils]: Add support for Armv8.1-M Mainline MVE instructions Andre Vieira (lists)
2019-05-01 17:19 ` [PATCH 28/57][Arm][GAS] Add support for MVE instructions: vqdmlah, vqrdmlah, vqdmlash, vqrdmlash, vqdmulh and vqrdmulh Andre Vieira (lists)
2019-05-01 17:30 ` [PATCH 27/57][Arm][GAS] Add support for MVE instructions: vqdmladh, vqrdmladh, vqdmlsdh and vqrdmlsdh Andre Vieira (lists)
2019-05-01 17:31 ` [PATCH 29/57][Arm][GAS] Add support for MVE instructions: vqdmullt and vqdmullb Andre Vieira (lists)
2019-05-01 17:32 ` [PATCH 31/57][Arm][GAS] Add support for MVE instructions: vshrn[tb], vrshrn[tb], vqshrn[tb], vqshrun[tb], vqrshrn[tb] and vqrshrun[tb] Andre Vieira (lists)
2019-05-01 17:32 ` [PATCH 30/57][Arm][GAS] Add support for MVE instructions: vqmovnt, vqmovnb, vqmovunt, vqmovunb, vqrshl and vrshl Andre Vieira (lists)
2019-05-01 17:33 ` [PATCH 32/57][Arm][GAS] Add support for MVE instructions: vrintn, vrintx, vrinta, vrintz, vrintm and vrintp Andre Vieira (lists)
2019-05-01 17:34 ` [PATCH 33/57][Arm][GAS] Add support for MVE instructions: vshr, vrshr, vsli, vsri, vrev16, vrev32 and vrev64 Andre Vieira (lists)
2019-05-01 17:34 ` [PATCH 34/57][Arm][GAS] Add support for MVE instructions: vshl and vqshl Andre Vieira (lists)
2019-05-01 17:36 ` [PATCH 35/57][Arm][GAS] Add support for MVE instructions: vshlc and vshll Andre Vieira (lists)
2019-05-01 17:36 ` [PATCH 36/57][Arm][GAS] Add support for MVE instructions: wlstp, dlstp, letp and lctp Andre Vieira (lists)
2019-05-01 17:38 ` [PATCH 37/57][Arm][OBJDUMP] Add framework for MVE instructions Andre Vieira (lists)
2019-05-01 17:38 ` [PATCH 38/57][Arm][OBJDUMP] Disable the use of MVE reserved coproc numbers in coprocessor instructions Andre Vieira (lists)
2019-05-01 17:39 ` [PATCH 39/57][Arm][OBJDUMP] Add support for MVE instructions: vpt, vpst and vcmp Andre Vieira (lists)
2019-05-01 17:40 ` [PATCH 40/57][Arm][OBJDUMP] Add support for MVE instructions: vdup, veor, vfma, vfms, vhadd, vhsub and vrhadd Andre Vieira (lists)
2019-05-01 17:40 ` [PATCH 41/57][Arm][OBJDUMP] Add support for MVE instructions: vld[24] and vst[24] Andre Vieira (lists)
2019-05-01 17:41 ` [PATCH 42/57][Arm][OBJDUMP] Add support for MVE instructions: vldr[bhw] and vstr[bhw] Andre Vieira (lists)
2019-05-01 17:42 ` [PATCH 43/57][Arm][OBJDUMP] Add support for MVE instructions: scatter stores and gather loads Andre Vieira (lists)
2019-05-01 17:43 ` [PATCH 44/57][Arm][OBJDUMP] Add support for MVE instructions: vcvt and vrint Andre Vieira (lists)
2019-05-02 9:54 ` Nick Clifton
2019-05-13 13:38 ` Andre Vieira (lists)
2019-05-01 17:44 ` [PATCH 46/57][Arm][OBJDUMP] Add support for MVE instructions: vmovl, vmull, vqdmull, vqmovn, vqmovun and vmovn Andre Vieira (lists)
2019-05-01 17:44 ` [PATCH 45/57][Arm][OBJDUMP] Add support for MVE instructions: vmov, vmvn, vorr, vorn, vmovx and vbic Andre Vieira (lists)
2019-05-01 17:45 ` [PATCH 47/57][Arm][OBJDUMP] Add support for MVE instructions: vaddv, vmlaldav, vmladav, vmlas, vrmlsldavh, vmlsldav, vmlsdav, vrmlaldavh, vqdmlah, vqrdmlash, vqrdmlash, vqdmlsdh, vqrdmlsdh, vqdmulh and vqrdmulh Andre Vieira (lists)
2019-05-01 17:46 ` [PATCH 49/57][Arm][OBJDUMP] Add support for MVE complex number instructions Andre Vieira (lists)
2019-05-01 17:46 ` [PATCH 48/57][Arm][OBJDUMP] Add support for MVE instructions: vddup, vdwdup, vidup and viwdup Andre Vieira (lists)
2019-05-01 17:47 ` [PATCH 0/57][Arm][binutils]: Add support for Armv8.1-M Mainline MVE instructions Andre Vieira (lists)
2019-05-01 17:48 ` [PATCH 51/57][Arm][OBJDUMP] Add support for MVE instructions: lctp, letp, wlstp and dlstp Andre Vieira (lists)
2019-05-01 17:48 ` [PATCH 52/57][Arm][OBJDUMP] Add support for MVE instructions: vadc, vabav, vabd, vabs, vadd, vsbc and vsub Andre Vieira (lists)
2019-05-01 17:49 ` [PATCH 53/57][Arm][OBJDUMP] Add support for MVE instructions: vand, vbrsr, vcls, vclz and vctp Andre Vieira (lists)
2019-05-01 17:50 ` [PATCH 54/57][Arm][OBJDUMP] Add support for MVE instructions: vmax(a), vmax(a)v, vmaxnm(a), vmaxnm(a)v, vmin(a), vmin(a)v, vminnm(a), vminnm(a)v and vmla Andre Vieira (lists)
2019-05-01 17:50 ` [PATCH 55/57][Arm][OBJDUMP] Add support for MVE instructions: vmul, vmulh, vrmulh and vneg Andre Vieira (lists)
2019-05-01 17:51 ` [PATCH 56/57][Arm][OBJDUMP] Add support for MVE instructions: vpnot, vpsel, vqabs, vqadd, vqsub, vqneg and vrev Andre Vieira (lists)
2019-05-01 18:23 ` [PATCH 57/57][Arm][GAS] MVE Tests Andre Vieira (lists)
2019-05-01 18:24 ` Andre Vieira (lists)
2019-05-01 18:25 ` Andre Vieira (lists)
2019-05-01 18:25 ` Andre Vieira (lists)
2019-05-02 10:03 ` [PATCH 0/57][Arm][binutils]: Add support for Armv8.1-M Mainline MVE instructions Nick Clifton
2019-05-02 10:18 ` Nick Clifton
2019-05-13 13:39 ` [PATCH, binutils, Arm] Add Armv8.1-M Mainline and MVE enablement to NEWS Andre Vieira (lists)
2019-05-02 13:39 ` [PATCH 0/57][Arm][binutils]: Add support for Armv8.1-M Mainline MVE instructions Nick Clifton
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=137d8ebb-fad6-70ee-4fca-7145ab1bd83f@arm.com \
--to=andre.simoesdiasvieira@arm.com \
--cc=binutils@sourceware.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).