* [PATCH 1/2] Remove the alignment limit on AArch64.
@ 2014-02-18 18:26 Philipp Tomsich
2014-02-18 18:26 ` [PATCH 2/2] Rename 'xgene-1' to 'xgene1' Philipp Tomsich
2014-02-18 18:56 ` [PATCH 1/2] Remove the alignment limit on AArch64 Philipp Tomsich
0 siblings, 2 replies; 4+ messages in thread
From: Philipp Tomsich @ 2014-02-18 18:26 UTC (permalink / raw)
To: binutils; +Cc: philipp.tomsich, marcus.shawcroft
Updated per Marcus's review.
Remove the artificial limit on code alignment through the use of the
fixed part of a fragment for output generation only, which required
MAX_MEM_FOR_RS_ALIGN_CODE to be large enough to hold the maximum pad.
* config/tc-aarch64.h (MAX_MEM_FOR_RS_ALIGN_CODE): Define to 7.
* config/tc-aarch64.c (aarch64_handle_align): Rewrite to handle large
alignments with a constant fragment size of MAX_MEM_FOR_RS_ALIGN_CODE.
---
gas/config/tc-aarch64.c | 77 +++++++++++++++++++------------------------------
gas/config/tc-aarch64.h | 7 +++--
2 files changed, 33 insertions(+), 51 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 5578dfb..2c11cc9 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -5820,80 +5820,61 @@ md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
}
/* This is called from HANDLE_ALIGN in write.c. Fill in the contents
- of an rs_align_code fragment. */
+ of an rs_align_code fragment.
+
+ Here we fill the frag with the appropriate info for padding the
+ output stream. The resulting frag will consist of a fixed (fr_fix)
+ and of a repeating (fr_var) part.
+
+ The fixed content is always emitted before the repeating content and
+ these two parts are used as follows in constructing the output:
+ - the fixed part will be used to align to a valid instruction word
+ boundary, in case that we start at a misaligned address; as no
+ executable instruction can live at the misaligned location, we
+ simply fill with zeros;
+ - the variable part will be used to cover the remaining padding and
+ we fill using the AArch64 NOP instruction.
+
+ Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
+ enough storage space for up to 3 bytes for padding the back to a valid
+ instruction alignment and exactly 4 bytes to store the NOP pattern.
+ */
void
-aarch64_handle_align (fragS * fragP)
+aarch64_handle_align (fragS * frag)
{
/* NOP = d503201f */
- /* AArch64 instructions are always little-endian. */
+ /* AArch64 instructions are always little-endian */
static char const aarch64_noop[4] = { 0x1f, 0x20, 0x03, 0xd5 };
int bytes, fix, noop_size;
char *p;
- const char *noop;
- if (fragP->fr_type != rs_align_code)
+ if (frag->fr_type != rs_align_code)
return;
bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
p = fragP->fr_literal + fragP->fr_fix;
- fix = 0;
-
- if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
- bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
#ifdef OBJ_ELF
- gas_assert (fragP->tc_frag_data.recorded);
+ gas_assert (frag->tc_frag_data.recorded);
#endif
- noop = aarch64_noop;
noop_size = sizeof (aarch64_noop);
- fragP->fr_var = noop_size;
- if (bytes & (noop_size - 1))
+ fix = bytes & (noop_size - 1);
+ if (fix)
{
- fix = bytes & (noop_size - 1);
#ifdef OBJ_ELF
- insert_data_mapping_symbol (MAP_INSN, fragP->fr_fix, fragP, fix);
+ insert_data_mapping_symbol (MAP_INSN, frag->fr_fix, frag, fix);
#endif
memset (p, 0, fix);
p += fix;
- bytes -= fix;
+ fragP->fr_fix += fix;
}
- while (bytes >= noop_size)
- {
- memcpy (p, noop, noop_size);
- p += noop_size;
- bytes -= noop_size;
- fix += noop_size;
- }
-
- fragP->fr_fix += fix;
-}
-
-/* Called from md_do_align. Used to create an alignment
- frag in a code section. */
-
-void
-aarch64_frag_align_code (int n, int max)
-{
- char *p;
-
- /* We assume that there will never be a requirement
- to support alignments greater than x bytes. */
- if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
- as_fatal (_
- ("alignments greater than %d bytes not supported in .text sections"),
- MAX_MEM_FOR_RS_ALIGN_CODE + 1);
-
- p = frag_var (rs_align_code,
- MAX_MEM_FOR_RS_ALIGN_CODE,
- 1,
- (relax_substateT) max,
- (symbolS *) NULL, (offsetT) n, (char *) NULL);
- *p = 0;
+ memcpy (p, aarch64_noop, noop_size);
+ fragP->fr_var = noop_size;
}
/* Perform target specific initialisation of a frag.
diff --git a/gas/config/tc-aarch64.h b/gas/config/tc-aarch64.h
index c3220bf..acd4de3 100644
--- a/gas/config/tc-aarch64.h
+++ b/gas/config/tc-aarch64.h
@@ -113,8 +113,9 @@ void aarch64_copy_symbol_attributes (symbolS *, symbolS *);
#define TC_CONS_FIX_NEW cons_fix_new_aarch64
-/* Max code alignment is 32 bytes */
-#define MAX_MEM_FOR_RS_ALIGN_CODE 31
+/* Max space for a rs_align_code fragment is 3 unaligned bytes
+ (fr_fix) plus 4 bytes to contain the repeating NOP (fr_var) */
+#define MAX_MEM_FOR_RS_ALIGN_CODE 7
/* For frags in code sections we need to record whether they contain
code or data. */
@@ -143,7 +144,7 @@ extern int aarch64_relax_frag (asection *, struct frag *, long);
#define md_do_align(N, FILL, LEN, MAX, LABEL) \
if (FILL == NULL && (N) != 0 && ! need_pass_2 && subseg_text_p (now_seg)) \
{ \
- aarch64_frag_align_code (N, MAX); \
+ frag_align_code (N, MAX); \
goto LABEL; \
}
--
1.9.0
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 2/2] Rename 'xgene-1' to 'xgene1'.
2014-02-18 18:26 [PATCH 1/2] Remove the alignment limit on AArch64 Philipp Tomsich
@ 2014-02-18 18:26 ` Philipp Tomsich
2014-02-25 16:52 ` Richard Earnshaw
2014-02-18 18:56 ` [PATCH 1/2] Remove the alignment limit on AArch64 Philipp Tomsich
1 sibling, 1 reply; 4+ messages in thread
From: Philipp Tomsich @ 2014-02-18 18:26 UTC (permalink / raw)
To: binutils; +Cc: philipp.tomsich, marcus.shawcroft
This change brings the target naming back into sync with all other
documentation on the chip.
---
gas/config/tc-aarch64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 2c11cc9..c1e2b95 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -7170,7 +7170,7 @@ static const struct aarch64_cpu_option_table aarch64_cpus[] = {
{"all", AARCH64_ANY, NULL},
{"cortex-a53", AARCH64_ARCH_V8, "Cortex-A53"},
{"cortex-a57", AARCH64_ARCH_V8, "Cortex-A57"},
- {"xgene-1", AARCH64_ARCH_V8, "APM X-Gene 1"},
+ {"xgene1", AARCH64_ARCH_V8, "APM X-Gene 1"},
{"generic", AARCH64_ARCH_V8, NULL},
/* These two are example CPUs supported in GCC, once we have real
--
1.9.0
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] Rename 'xgene-1' to 'xgene1'.
2014-02-18 18:26 ` [PATCH 2/2] Rename 'xgene-1' to 'xgene1' Philipp Tomsich
@ 2014-02-25 16:52 ` Richard Earnshaw
0 siblings, 0 replies; 4+ messages in thread
From: Richard Earnshaw @ 2014-02-25 16:52 UTC (permalink / raw)
To: Philipp Tomsich; +Cc: binutils, marcus.shawcroft
On 18/02/14 18:26, Philipp Tomsich wrote:
> This change brings the target naming back into sync with all other
> documentation on the chip.
> ---
> gas/config/tc-aarch64.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
> index 2c11cc9..c1e2b95 100644
> --- a/gas/config/tc-aarch64.c
> +++ b/gas/config/tc-aarch64.c
> @@ -7170,7 +7170,7 @@ static const struct aarch64_cpu_option_table aarch64_cpus[] = {
> {"all", AARCH64_ANY, NULL},
> {"cortex-a53", AARCH64_ARCH_V8, "Cortex-A53"},
> {"cortex-a57", AARCH64_ARCH_V8, "Cortex-A57"},
> - {"xgene-1", AARCH64_ARCH_V8, "APM X-Gene 1"},
> + {"xgene1", AARCH64_ARCH_V8, "APM X-Gene 1"},
> {"generic", AARCH64_ARCH_V8, NULL},
>
> /* These two are example CPUs supported in GCC, once we have real
>
This patch needs a ChangeLog entry. It also needs an update to the
texinfo entry in the manual.
R.
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 1/2] Remove the alignment limit on AArch64.
2014-02-18 18:26 [PATCH 1/2] Remove the alignment limit on AArch64 Philipp Tomsich
2014-02-18 18:26 ` [PATCH 2/2] Rename 'xgene-1' to 'xgene1' Philipp Tomsich
@ 2014-02-18 18:56 ` Philipp Tomsich
1 sibling, 0 replies; 4+ messages in thread
From: Philipp Tomsich @ 2014-02-18 18:56 UTC (permalink / raw)
To: binutils; +Cc: philipp.tomsich, marcus.shawcroft
I had a badly edited patch-file lying around, which hadn't undone all
frag->fragP changes yet (so please disregard my earlier mail).
Sorry for the trouble.
---
Updated per Marcus's review.
Remove the artificial limit on code alignment through the use of the
fixed part of a fragment for output generation only, which required
MAX_MEM_FOR_RS_ALIGN_CODE to be large enough to hold the maximum pad.
* config/tc-aarch64.h (MAX_MEM_FOR_RS_ALIGN_CODE): Define to 7.
* config/tc-aarch64.c (aarch64_handle_align): Rewrite to handle large
alignments with a constant fragment size of MAX_MEM_FOR_RS_ALIGN_CODE.
---
gas/config/tc-aarch64.c | 69 ++++++++++++++++++-------------------------------
gas/config/tc-aarch64.h | 7 ++---
2 files changed, 29 insertions(+), 47 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 5578dfb..cd34c55 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -5820,80 +5820,61 @@ md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
}
/* This is called from HANDLE_ALIGN in write.c. Fill in the contents
- of an rs_align_code fragment. */
+ of an rs_align_code fragment.
+
+ Here we fill the frag with the appropriate info for padding the
+ output stream. The resulting frag will consist of a fixed (fr_fix)
+ and of a repeating (fr_var) part.
+
+ The fixed content is always emitted before the repeating content and
+ these two parts are used as follows in constructing the output:
+ - the fixed part will be used to align to a valid instruction word
+ boundary, in case that we start at a misaligned address; as no
+ executable instruction can live at the misaligned location, we
+ simply fill with zeros;
+ - the variable part will be used to cover the remaining padding and
+ we fill using the AArch64 NOP instruction.
+
+ Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
+ enough storage space for up to 3 bytes for padding the back to a valid
+ instruction alignment and exactly 4 bytes to store the NOP pattern.
+ */
void
aarch64_handle_align (fragS * fragP)
{
/* NOP = d503201f */
- /* AArch64 instructions are always little-endian. */
+ /* AArch64 instructions are always little-endian */
static char const aarch64_noop[4] = { 0x1f, 0x20, 0x03, 0xd5 };
int bytes, fix, noop_size;
char *p;
- const char *noop;
if (fragP->fr_type != rs_align_code)
return;
bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
p = fragP->fr_literal + fragP->fr_fix;
- fix = 0;
-
- if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
- bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
#ifdef OBJ_ELF
gas_assert (fragP->tc_frag_data.recorded);
#endif
- noop = aarch64_noop;
noop_size = sizeof (aarch64_noop);
- fragP->fr_var = noop_size;
- if (bytes & (noop_size - 1))
+ fix = bytes & (noop_size - 1);
+ if (fix)
{
- fix = bytes & (noop_size - 1);
#ifdef OBJ_ELF
insert_data_mapping_symbol (MAP_INSN, fragP->fr_fix, fragP, fix);
#endif
memset (p, 0, fix);
p += fix;
- bytes -= fix;
+ fragP->fr_fix += fix;
}
- while (bytes >= noop_size)
- {
- memcpy (p, noop, noop_size);
- p += noop_size;
- bytes -= noop_size;
- fix += noop_size;
- }
-
- fragP->fr_fix += fix;
-}
-
-/* Called from md_do_align. Used to create an alignment
- frag in a code section. */
-
-void
-aarch64_frag_align_code (int n, int max)
-{
- char *p;
-
- /* We assume that there will never be a requirement
- to support alignments greater than x bytes. */
- if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
- as_fatal (_
- ("alignments greater than %d bytes not supported in .text sections"),
- MAX_MEM_FOR_RS_ALIGN_CODE + 1);
-
- p = frag_var (rs_align_code,
- MAX_MEM_FOR_RS_ALIGN_CODE,
- 1,
- (relax_substateT) max,
- (symbolS *) NULL, (offsetT) n, (char *) NULL);
- *p = 0;
+ memcpy (p, aarch64_noop, noop_size);
+ fragP->fr_var = noop_size;
}
/* Perform target specific initialisation of a frag.
diff --git a/gas/config/tc-aarch64.h b/gas/config/tc-aarch64.h
index c3220bf..acd4de3 100644
--- a/gas/config/tc-aarch64.h
+++ b/gas/config/tc-aarch64.h
@@ -113,8 +113,9 @@ void aarch64_copy_symbol_attributes (symbolS *, symbolS *);
#define TC_CONS_FIX_NEW cons_fix_new_aarch64
-/* Max code alignment is 32 bytes */
-#define MAX_MEM_FOR_RS_ALIGN_CODE 31
+/* Max space for a rs_align_code fragment is 3 unaligned bytes
+ (fr_fix) plus 4 bytes to contain the repeating NOP (fr_var) */
+#define MAX_MEM_FOR_RS_ALIGN_CODE 7
/* For frags in code sections we need to record whether they contain
code or data. */
@@ -143,7 +144,7 @@ extern int aarch64_relax_frag (asection *, struct frag *, long);
#define md_do_align(N, FILL, LEN, MAX, LABEL) \
if (FILL == NULL && (N) != 0 && ! need_pass_2 && subseg_text_p (now_seg)) \
{ \
- aarch64_frag_align_code (N, MAX); \
+ frag_align_code (N, MAX); \
goto LABEL; \
}
--
1.9.0
^ permalink raw reply [flat|nested] 4+ messages in thread
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2014-02-18 18:26 [PATCH 1/2] Remove the alignment limit on AArch64 Philipp Tomsich
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2014-02-25 16:52 ` Richard Earnshaw
2014-02-18 18:56 ` [PATCH 1/2] Remove the alignment limit on AArch64 Philipp Tomsich
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