From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 15419 invoked by alias); 18 Jan 2018 15:38:01 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 15394 invoked by uid 89); 18 Jan 2018 15:38:00 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,KAM_LAZY_DOMAIN_SECURITY,T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=sk:complai, 015 X-HELO: foss.arm.com Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 18 Jan 2018 15:37:57 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D313E1529; Thu, 18 Jan 2018 07:37:55 -0800 (PST) Received: from [10.2.206.38] (e109742-lin.cambridge.arm.com [10.2.206.38]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E1E6D3F41F; Thu, 18 Jan 2018 07:37:52 -0800 (PST) Subject: Re: [Binutils][AARCH64][1/2]Add group relocations to create PC-relative offset. From: Renlin Li To: "binutils@sourceware.org" , Ramana Radhakrishnan , Nicholas Clifton References: <0911da78-0f25-fd2d-7edb-a791e38dc990@foss.arm.com> Message-ID: <13ca6aa7-befd-2d13-08d9-5e3513d809cb@foss.arm.com> Date: Thu, 18 Jan 2018 15:38:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.4.0 MIME-Version: 1.0 In-Reply-To: <0911da78-0f25-fd2d-7edb-a791e38dc990@foss.arm.com> Content-Type: multipart/mixed; boundary="------------6884F606CED7DB90C86A2222" X-IsSubscribed: yes X-SW-Source: 2018-01/txt/msg00276.txt.bz2 This is a multi-part message in MIME format. --------------6884F606CED7DB90C86A2222 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-length: 3156 Hi all, This is the assembler part support for the following relocations: BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC, BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC, BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC, BFD_RELOC_AARCH64_MOVW_PREL_G3 Regards, Renlin bfd/ 2018-01-18 Renlin Li * reloc.c: Add BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC, BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC, BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC, BFD_RELOC_AARCH64_MOVW_PREL_G3. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elfnn-aarch64.c (elfNN_aarch64_howto_table): Add entries for BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC, BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC, BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC, BFD_RELOC_AARCH64_MOVW_PREL_G3. gas/ 2018-01-18 Renlin Li * config/tc-aarch64.c (reloc_table): add entries for BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC, BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC, BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC, BFD_RELOC_AARCH64_MOVW_PREL_G3. (process_movw_reloc_info): Supports newly added MOVW_PREL relocations. (md_apply_fix): Likewise * testsuite/gas/aarch64/prel_g0.s: New. * testsuite/gas/aarch64/prel_g0.d: New. * testsuite/gas/aarch64/prel_g0_nc.s: New. * testsuite/gas/aarch64/prel_g0_nc.d: New. * testsuite/gas/aarch64/prel_g1.s: New. * testsuite/gas/aarch64/prel_g1.d: New. * testsuite/gas/aarch64/prel_g1_nc.s: New. * testsuite/gas/aarch64/prel_g1_nc.d: New. * testsuite/gas/aarch64/prel_g2.s: New. * testsuite/gas/aarch64/prel_g2.d: New. * testsuite/gas/aarch64/prel_g2_nc.s: New. * testsuite/gas/aarch64/prel_g2_nc.d: New. * testsuite/gas/aarch64/prel_g3.s: New. * testsuite/gas/aarch64/prel_g3.d: New. On 18/01/18 15:34, Renlin Li wrote: > Hi all, > > This is a patch to add Group relocations to create a > 16, 32, 48, or 64 bit PC-relative offset inline. > > The following relocations are added along with the test cases: > BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC, > BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC, > BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC, > BFD_RELOC_AARCH64_MOVW_PREL_G3. > > > The operations for those relocations are: S + A - P. > S is the address of the symbol. > A is the addend for the relocation. > P is the address of the place being relocated > > Those relocations are used to create PC-relative offset. For example, > The following code sequence could get the full address of _start. > > .Ltmp1: > movz    x0, :prel_g2: _start - .Ltmp1 > movk    x0, :prel_g1_nc: _start - .Ltmp1 > movk    x0, :prel_g0_nc: _start - .Ltmp1 > adr    x1, .Ltmp1 > add    x0, x0, x1 > > binutils regression test checked OK, linux kernel link checked OK. > OK to commit? > > Regards, > Renlin --------------6884F606CED7DB90C86A2222 Content-Type: text/x-patch; name="0001-GAS-AARCH64-Add-group-relocations-to-create-PC-relat.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename*0="0001-GAS-AARCH64-Add-group-relocations-to-create-PC-relat.pa"; filename*1="tch" Content-length: 21782 --- bfd/bfd-in2.h | 30 ++++++++ bfd/elfnn-aarch64.c | 108 +++++++++++++++++++++++++++ bfd/libbfd.h | 7 ++ bfd/reloc.c | 37 +++++++++ gas/config/tc-aarch64.c | 84 +++++++++++++++++++++ gas/testsuite/gas/aarch64/reloc-prel_g0.d | 13 ++++ gas/testsuite/gas/aarch64/reloc-prel_g0.s | 7 ++ gas/testsuite/gas/aarch64/reloc-prel_g0_nc.d | 15 ++++ gas/testsuite/gas/aarch64/reloc-prel_g0_nc.s | 8 ++ gas/testsuite/gas/aarch64/reloc-prel_g1.d | 13 ++++ gas/testsuite/gas/aarch64/reloc-prel_g1.s | 7 ++ gas/testsuite/gas/aarch64/reloc-prel_g1_nc.d | 15 ++++ gas/testsuite/gas/aarch64/reloc-prel_g1_nc.s | 8 ++ gas/testsuite/gas/aarch64/reloc-prel_g2.d | 15 ++++ gas/testsuite/gas/aarch64/reloc-prel_g2.s | 8 ++ gas/testsuite/gas/aarch64/reloc-prel_g2_nc.d | 15 ++++ gas/testsuite/gas/aarch64/reloc-prel_g2_nc.s | 8 ++ gas/testsuite/gas/aarch64/reloc-prel_g3.d | 15 ++++ gas/testsuite/gas/aarch64/reloc-prel_g3.s | 8 ++ 21 files changed, 459 insertions(+) create mode 100644 gas/testsuite/gas/aarch64/reloc-prel_g0.d create mode 100644 gas/testsuite/gas/aarch64/reloc-prel_g0.s create mode 100644 gas/testsuite/gas/aarch64/reloc-prel_g0_nc.d create mode 100644 gas/testsuite/gas/aarch64/reloc-prel_g0_nc.s create mode 100644 gas/testsuite/gas/aarch64/reloc-prel_g1.d create mode 100644 gas/testsuite/gas/aarch64/reloc-prel_g1.s create mode 100644 gas/testsuite/gas/aarch64/reloc-prel_g1_nc.d create mode 100644 gas/testsuite/gas/aarch64/reloc-prel_g1_nc.s create mode 100644 gas/testsuite/gas/aarch64/reloc-prel_g2.d create mode 100644 gas/testsuite/gas/aarch64/reloc-prel_g2.s create mode 100644 gas/testsuite/gas/aarch64/reloc-prel_g2_nc.d create mode 100644 gas/testsuite/gas/aarch64/reloc-prel_g2_nc.s create mode 100644 gas/testsuite/gas/aarch64/reloc-prel_g3.d create mode 100644 gas/testsuite/gas/aarch64/reloc-prel_g3.s diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index f4b3720..42991e7 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -5957,6 +5957,36 @@ of a signed value. Changes instruction to MOVZ or MOVN depending on the value's sign. */ BFD_RELOC_AARCH64_MOVW_G2_S, +/* AArch64 MOV[NZ] instruction with most significant bits 0 to 15 +of a signed value. Changes instruction to MOVZ or MOVN depending on the +value's sign. */ + BFD_RELOC_AARCH64_MOVW_PREL_G0, + +/* AArch64 MOV[NZ] instruction with most significant bits 0 to 15 +of a signed value. Changes instruction to MOVZ or MOVN depending on the +value's sign. */ + BFD_RELOC_AARCH64_MOVW_PREL_G0_NC, + +/* AArch64 MOVK instruction with most significant bits 16 to 31 +of a signed value. */ + BFD_RELOC_AARCH64_MOVW_PREL_G1, + +/* AArch64 MOVK instruction with most significant bits 16 to 31 +of a signed value. */ + BFD_RELOC_AARCH64_MOVW_PREL_G1_NC, + +/* AArch64 MOVK instruction with most significant bits 32 to 47 +of a signed value. */ + BFD_RELOC_AARCH64_MOVW_PREL_G2, + +/* AArch64 MOVK instruction with most significant bits 32 to 47 +of a signed value. */ + BFD_RELOC_AARCH64_MOVW_PREL_G2_NC, + +/* AArch64 MOVK instruction with most significant bits 47 to 63 +of a signed value. */ + BFD_RELOC_AARCH64_MOVW_PREL_G3, + /* AArch64 Load Literal instruction, holding a 19 bit pc-relative word offset. The lowest two bits must be zero and are not stored in the instruction, giving a 21 bit signed byte offset. */ diff --git a/bfd/elfnn-aarch64.c b/bfd/elfnn-aarch64.c index d5711e0..b84c8ba 100644 --- a/bfd/elfnn-aarch64.c +++ b/bfd/elfnn-aarch64.c @@ -617,6 +617,114 @@ static reloc_howto_type elfNN_aarch64_howto_table[] = 0xffff, /* dst_mask */ FALSE), /* pcrel_offset */ + /* Group relocations to create a 16, 32, 48 or 64 bit + PC relative address inline. */ + + /* MOV[NZ]: ((S+A-P) >> 0) & 0xffff */ + HOWTO64 (AARCH64_R (MOVW_PREL_G0), /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 17, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + AARCH64_R_STR (MOVW_PREL_G0), /* name */ + FALSE, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* MOVK: ((S+A-P) >> 0) & 0xffff [no overflow check] */ + HOWTO64 (AARCH64_R (MOVW_PREL_G0_NC), /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + AARCH64_R_STR (MOVW_PREL_G0_NC), /* name */ + FALSE, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* MOV[NZ]: ((S+A-P) >> 16) & 0xffff */ + HOWTO64 (AARCH64_R (MOVW_PREL_G1), /* type */ + 16, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 17, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + AARCH64_R_STR (MOVW_PREL_G1), /* name */ + FALSE, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* MOVK: ((S+A-P) >> 16) & 0xffff [no overflow check] */ + HOWTO64 (AARCH64_R (MOVW_PREL_G1_NC), /* type */ + 16, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + AARCH64_R_STR (MOVW_PREL_G1_NC), /* name */ + FALSE, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* MOV[NZ]: ((S+A-P) >> 32) & 0xffff */ + HOWTO64 (AARCH64_R (MOVW_PREL_G2), /* type */ + 32, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 17, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + AARCH64_R_STR (MOVW_PREL_G2), /* name */ + FALSE, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* MOVK: ((S+A-P) >> 32) & 0xffff [no overflow check] */ + HOWTO64 (AARCH64_R (MOVW_PREL_G2_NC), /* type */ + 32, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + AARCH64_R_STR (MOVW_PREL_G2_NC), /* name */ + FALSE, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* MOV[NZ]: ((S+A-P) >> 48) & 0xffff */ + HOWTO64 (AARCH64_R (MOVW_PREL_G3), /* type */ + 48, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + AARCH64_R_STR (MOVW_PREL_G3), /* name */ + FALSE, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + /* Relocations to generate 19, 21 and 33 bit PC-relative load/store addresses: PG(x) is (x & ~0xfff). */ diff --git a/bfd/libbfd.h b/bfd/libbfd.h index 2f5f16e..8746d9c 100644 --- a/bfd/libbfd.h +++ b/bfd/libbfd.h @@ -2887,6 +2887,13 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", "BFD_RELOC_AARCH64_MOVW_G0_S", "BFD_RELOC_AARCH64_MOVW_G1_S", "BFD_RELOC_AARCH64_MOVW_G2_S", + "BFD_RELOC_AARCH64_MOVW_PREL_G0", + "BFD_RELOC_AARCH64_MOVW_PREL_G0_NC", + "BFD_RELOC_AARCH64_MOVW_PREL_G1", + "BFD_RELOC_AARCH64_MOVW_PREL_G1_NC", + "BFD_RELOC_AARCH64_MOVW_PREL_G2", + "BFD_RELOC_AARCH64_MOVW_PREL_G2_NC", + "BFD_RELOC_AARCH64_MOVW_PREL_G3", "BFD_RELOC_AARCH64_LD_LO19_PCREL", "BFD_RELOC_AARCH64_ADR_LO21_PCREL", "BFD_RELOC_AARCH64_ADR_HI21_PCREL", diff --git a/bfd/reloc.c b/bfd/reloc.c index a1353a2..301199a 100644 --- a/bfd/reloc.c +++ b/bfd/reloc.c @@ -7071,6 +7071,43 @@ ENUMDOC of a signed value. Changes instruction to MOVZ or MOVN depending on the value's sign. ENUM + BFD_RELOC_AARCH64_MOVW_PREL_G0 +ENUMDOC + AArch64 MOV[NZ] instruction with most significant bits 0 to 15 + of a signed value. Changes instruction to MOVZ or MOVN depending on the + value's sign. +ENUM + BFD_RELOC_AARCH64_MOVW_PREL_G0_NC +ENUMDOC + AArch64 MOV[NZ] instruction with most significant bits 0 to 15 + of a signed value. Changes instruction to MOVZ or MOVN depending on the + value's sign. +ENUM + BFD_RELOC_AARCH64_MOVW_PREL_G1 +ENUMDOC + AArch64 MOVK instruction with most significant bits 16 to 31 + of a signed value. +ENUM + BFD_RELOC_AARCH64_MOVW_PREL_G1_NC +ENUMDOC + AArch64 MOVK instruction with most significant bits 16 to 31 + of a signed value. +ENUM + BFD_RELOC_AARCH64_MOVW_PREL_G2 +ENUMDOC + AArch64 MOVK instruction with most significant bits 32 to 47 + of a signed value. +ENUM + BFD_RELOC_AARCH64_MOVW_PREL_G2_NC +ENUMDOC + AArch64 MOVK instruction with most significant bits 32 to 47 + of a signed value. +ENUM + BFD_RELOC_AARCH64_MOVW_PREL_G3 +ENUMDOC + AArch64 MOVK instruction with most significant bits 47 to 63 + of a signed value. +ENUM BFD_RELOC_AARCH64_LD_LO19_PCREL ENUMDOC AArch64 Load Literal instruction, holding a 19 bit pc-relative word diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 8af3137..3a0cde9 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -2577,6 +2577,69 @@ static struct reloc_table_entry reloc_table[] = { 0, 0}, + /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */ + {"prel_g0", 1, + 0, /* adr_type */ + 0, + BFD_RELOC_AARCH64_MOVW_PREL_G0, + 0, + 0, + 0}, + + /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */ + {"prel_g0_nc", 1, + 0, /* adr_type */ + 0, + BFD_RELOC_AARCH64_MOVW_PREL_G0_NC, + 0, + 0, + 0}, + + /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */ + {"prel_g1", 1, + 0, /* adr_type */ + 0, + BFD_RELOC_AARCH64_MOVW_PREL_G1, + 0, + 0, + 0}, + + /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */ + {"prel_g1_nc", 1, + 0, /* adr_type */ + 0, + BFD_RELOC_AARCH64_MOVW_PREL_G1_NC, + 0, + 0, + 0}, + + /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */ + {"prel_g2", 1, + 0, /* adr_type */ + 0, + BFD_RELOC_AARCH64_MOVW_PREL_G2, + 0, + 0, + 0}, + + /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */ + {"prel_g2_nc", 1, + 0, /* adr_type */ + 0, + BFD_RELOC_AARCH64_MOVW_PREL_G2_NC, + 0, + 0, + 0}, + + /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */ + {"prel_g3", 1, + 0, /* adr_type */ + 0, + BFD_RELOC_AARCH64_MOVW_PREL_G3, + 0, + 0, + 0}, + /* Get to the page containing GOT entry for a symbol. */ {"got", 1, 0, /* adr_type */ @@ -5079,6 +5142,10 @@ process_movw_reloc_info (void) case BFD_RELOC_AARCH64_MOVW_G0_S: case BFD_RELOC_AARCH64_MOVW_G1_S: case BFD_RELOC_AARCH64_MOVW_G2_S: + case BFD_RELOC_AARCH64_MOVW_PREL_G0: + case BFD_RELOC_AARCH64_MOVW_PREL_G1: + case BFD_RELOC_AARCH64_MOVW_PREL_G2: + case BFD_RELOC_AARCH64_MOVW_PREL_G3: case BFD_RELOC_AARCH64_TLSGD_MOVW_G1: case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0: case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1: @@ -5096,6 +5163,8 @@ process_movw_reloc_info (void) case BFD_RELOC_AARCH64_MOVW_G0_NC: case BFD_RELOC_AARCH64_MOVW_G0_S: case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC: + case BFD_RELOC_AARCH64_MOVW_PREL_G0: + case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC: case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC: case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC: case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC: @@ -5109,6 +5178,8 @@ process_movw_reloc_info (void) case BFD_RELOC_AARCH64_MOVW_G1_NC: case BFD_RELOC_AARCH64_MOVW_G1_S: case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1: + case BFD_RELOC_AARCH64_MOVW_PREL_G1: + case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC: case BFD_RELOC_AARCH64_TLSDESC_OFF_G1: case BFD_RELOC_AARCH64_TLSGD_MOVW_G1: case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1: @@ -5121,6 +5192,8 @@ process_movw_reloc_info (void) case BFD_RELOC_AARCH64_MOVW_G2: case BFD_RELOC_AARCH64_MOVW_G2_NC: case BFD_RELOC_AARCH64_MOVW_G2_S: + case BFD_RELOC_AARCH64_MOVW_PREL_G2: + case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC: case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2: case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2: if (is32) @@ -5133,6 +5206,7 @@ process_movw_reloc_info (void) shift = 32; break; case BFD_RELOC_AARCH64_MOVW_G3: + case BFD_RELOC_AARCH64_MOVW_PREL_G3: if (is32) { set_fatal_syntax_error @@ -7608,12 +7682,16 @@ md_apply_fix (fixS * fixP, valueT * valP, segT seg) case BFD_RELOC_AARCH64_MOVW_G0_NC: case BFD_RELOC_AARCH64_MOVW_G0_S: case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC: + case BFD_RELOC_AARCH64_MOVW_PREL_G0: + case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC: scale = 0; goto movw_common; case BFD_RELOC_AARCH64_MOVW_G1: case BFD_RELOC_AARCH64_MOVW_G1_NC: case BFD_RELOC_AARCH64_MOVW_G1_S: case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1: + case BFD_RELOC_AARCH64_MOVW_PREL_G1: + case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC: scale = 16; goto movw_common; case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC: @@ -7635,9 +7713,12 @@ md_apply_fix (fixS * fixP, valueT * valP, segT seg) case BFD_RELOC_AARCH64_MOVW_G2: case BFD_RELOC_AARCH64_MOVW_G2_NC: case BFD_RELOC_AARCH64_MOVW_G2_S: + case BFD_RELOC_AARCH64_MOVW_PREL_G2: + case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC: scale = 32; goto movw_common; case BFD_RELOC_AARCH64_MOVW_G3: + case BFD_RELOC_AARCH64_MOVW_PREL_G3: scale = 48; movw_common: if (fixP->fx_done || !seg->use_rela_p) @@ -7669,6 +7750,9 @@ md_apply_fix (fixS * fixP, valueT * valP, segT seg) case BFD_RELOC_AARCH64_MOVW_G0_S: case BFD_RELOC_AARCH64_MOVW_G1_S: case BFD_RELOC_AARCH64_MOVW_G2_S: + case BFD_RELOC_AARCH64_MOVW_PREL_G0: + case BFD_RELOC_AARCH64_MOVW_PREL_G1: + case BFD_RELOC_AARCH64_MOVW_PREL_G2: /* NOTE: We can only come here with movz or movn. */ if (signed_overflow (value, scale + 16)) as_bad_where (fixP->fx_file, fixP->fx_line, diff --git a/gas/testsuite/gas/aarch64/reloc-prel_g0.d b/gas/testsuite/gas/aarch64/reloc-prel_g0.d new file mode 100644 index 0000000..9ba990e --- /dev/null +++ b/gas/testsuite/gas/aarch64/reloc-prel_g0.d @@ -0,0 +1,13 @@ +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0000000000000000 <.*>: + 0: 8a000000 and x0, x0, x0 + 4: 92400000 and x0, x0, #0x1 + 8: d2800004 mov x4, #0x0 // #0 + 8: R_AARCH64_MOVW_PREL_G0 tempy + c: d2800011 mov x17, #0x0 // #0 + c: R_AARCH64_MOVW_PREL_G0 tempy2 diff --git a/gas/testsuite/gas/aarch64/reloc-prel_g0.s b/gas/testsuite/gas/aarch64/reloc-prel_g0.s new file mode 100644 index 0000000..4cbb287 --- /dev/null +++ b/gas/testsuite/gas/aarch64/reloc-prel_g0.s @@ -0,0 +1,7 @@ +.comm gempy,4,4 +.text + + and x0,x0,x0 + and x0,x0,#0x1 + movz x4, :prel_g0:tempy + movz x17, :prel_g0:tempy2 diff --git a/gas/testsuite/gas/aarch64/reloc-prel_g0_nc.d b/gas/testsuite/gas/aarch64/reloc-prel_g0_nc.d new file mode 100644 index 0000000..4127ce7 --- /dev/null +++ b/gas/testsuite/gas/aarch64/reloc-prel_g0_nc.d @@ -0,0 +1,15 @@ +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0000000000000000 <.*>: + 0: 8a000000 and x0, x0, x0 + 4: 92400000 and x0, x0, #0x1 + 8: f2800004 movk x4, #0x0 + 8: R_AARCH64_MOVW_PREL_G0_NC tempy + c: f2800007 movk x7, #0x0 + c: R_AARCH64_MOVW_PREL_G0_NC tempy2 + 10: f2800011 movk x17, #0x0 + 10: R_AARCH64_MOVW_PREL_G0_NC tempy3 diff --git a/gas/testsuite/gas/aarch64/reloc-prel_g0_nc.s b/gas/testsuite/gas/aarch64/reloc-prel_g0_nc.s new file mode 100644 index 0000000..6b4c2e9 --- /dev/null +++ b/gas/testsuite/gas/aarch64/reloc-prel_g0_nc.s @@ -0,0 +1,8 @@ +.comm gempy,4,4 +.text + + and x0,x0,x0 + and x0,x0,#0x1 + movk x4, :prel_g0_nc:tempy + movk x7, :prel_g0_nc:tempy2 + movk x17, :prel_g0_nc:tempy3 diff --git a/gas/testsuite/gas/aarch64/reloc-prel_g1.d b/gas/testsuite/gas/aarch64/reloc-prel_g1.d new file mode 100644 index 0000000..1a161f8 --- /dev/null +++ b/gas/testsuite/gas/aarch64/reloc-prel_g1.d @@ -0,0 +1,13 @@ +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0000000000000000 <.*>: + 0: 8a000000 and x0, x0, x0 + 4: 92400000 and x0, x0, #0x1 + 8: d2a00004 movz x4, #0x0, lsl #16 + 8: R_AARCH64_MOVW_PREL_G1 tempy + c: d2a00011 movz x17, #0x0, lsl #16 + c: R_AARCH64_MOVW_PREL_G1 tempy2 diff --git a/gas/testsuite/gas/aarch64/reloc-prel_g1.s b/gas/testsuite/gas/aarch64/reloc-prel_g1.s new file mode 100644 index 0000000..fd7e216 --- /dev/null +++ b/gas/testsuite/gas/aarch64/reloc-prel_g1.s @@ -0,0 +1,7 @@ +.comm gempy,4,4 +.text + + and x0,x0,x0 + and x0,x0,#0x1 + movz x4, :prel_g1:tempy + movz x17, :prel_g1:tempy2 diff --git a/gas/testsuite/gas/aarch64/reloc-prel_g1_nc.d b/gas/testsuite/gas/aarch64/reloc-prel_g1_nc.d new file mode 100644 index 0000000..4c0a1d9 --- /dev/null +++ b/gas/testsuite/gas/aarch64/reloc-prel_g1_nc.d @@ -0,0 +1,15 @@ +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0000000000000000 <.*>: + 0: 8a000000 and x0, x0, x0 + 4: 92400000 and x0, x0, #0x1 + 8: f2a00004 movk x4, #0x0, lsl #16 + 8: R_AARCH64_MOVW_PREL_G1_NC tempy + c: f2a00007 movk x7, #0x0, lsl #16 + c: R_AARCH64_MOVW_PREL_G1_NC tempy2 + 10: f2a00011 movk x17, #0x0, lsl #16 + 10: R_AARCH64_MOVW_PREL_G1_NC tempy3 diff --git a/gas/testsuite/gas/aarch64/reloc-prel_g1_nc.s b/gas/testsuite/gas/aarch64/reloc-prel_g1_nc.s new file mode 100644 index 0000000..6c5b72f --- /dev/null +++ b/gas/testsuite/gas/aarch64/reloc-prel_g1_nc.s @@ -0,0 +1,8 @@ +.comm gempy,4,4 +.text + + and x0,x0,x0 + and x0,x0,#0x1 + movk x4, :prel_g1_nc:tempy + movk x7, :prel_g1_nc:tempy2 + movk x17, :prel_g1_nc:tempy3 diff --git a/gas/testsuite/gas/aarch64/reloc-prel_g2.d b/gas/testsuite/gas/aarch64/reloc-prel_g2.d new file mode 100644 index 0000000..80d1870 --- /dev/null +++ b/gas/testsuite/gas/aarch64/reloc-prel_g2.d @@ -0,0 +1,15 @@ +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0000000000000000 <.*>: + 0: 8a000000 and x0, x0, x0 + 4: 92400000 and x0, x0, #0x1 + 8: d2c00004 movz x4, #0x0, lsl #32 + 8: R_AARCH64_MOVW_PREL_G2 tempy + c: d2c00007 movz x7, #0x0, lsl #32 + c: R_AARCH64_MOVW_PREL_G2 tempy2 + 10: d2c00011 movz x17, #0x0, lsl #32 + 10: R_AARCH64_MOVW_PREL_G2 tempy3 diff --git a/gas/testsuite/gas/aarch64/reloc-prel_g2.s b/gas/testsuite/gas/aarch64/reloc-prel_g2.s new file mode 100644 index 0000000..716bf29 --- /dev/null +++ b/gas/testsuite/gas/aarch64/reloc-prel_g2.s @@ -0,0 +1,8 @@ +.comm gempy,4,4 +.text + + and x0,x0,x0 + and x0,x0,#0x1 + movz x4, :prel_g2:tempy + movz x7, :prel_g2:tempy2 + movz x17, :prel_g2:tempy3 diff --git a/gas/testsuite/gas/aarch64/reloc-prel_g2_nc.d b/gas/testsuite/gas/aarch64/reloc-prel_g2_nc.d new file mode 100644 index 0000000..dc3c58e --- /dev/null +++ b/gas/testsuite/gas/aarch64/reloc-prel_g2_nc.d @@ -0,0 +1,15 @@ +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0000000000000000 <.*>: + 0: 8a000000 and x0, x0, x0 + 4: 92400000 and x0, x0, #0x1 + 8: f2c00004 movk x4, #0x0, lsl #32 + 8: R_AARCH64_MOVW_PREL_G2_NC tempy + c: f2c00007 movk x7, #0x0, lsl #32 + c: R_AARCH64_MOVW_PREL_G2_NC tempy2 + 10: f2c00011 movk x17, #0x0, lsl #32 + 10: R_AARCH64_MOVW_PREL_G2_NC tempy3 diff --git a/gas/testsuite/gas/aarch64/reloc-prel_g2_nc.s b/gas/testsuite/gas/aarch64/reloc-prel_g2_nc.s new file mode 100644 index 0000000..7327faa --- /dev/null +++ b/gas/testsuite/gas/aarch64/reloc-prel_g2_nc.s @@ -0,0 +1,8 @@ +.comm gempy,4,4 +.text + + and x0,x0,x0 + and x0,x0,#0x1 + movk x4, :prel_g2_nc:tempy + movk x7, :prel_g2_nc:tempy2 + movk x17, :prel_g2_nc:tempy3 diff --git a/gas/testsuite/gas/aarch64/reloc-prel_g3.d b/gas/testsuite/gas/aarch64/reloc-prel_g3.d new file mode 100644 index 0000000..4a476ab --- /dev/null +++ b/gas/testsuite/gas/aarch64/reloc-prel_g3.d @@ -0,0 +1,15 @@ +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0000000000000000 <.*>: + 0: 8a000000 and x0, x0, x0 + 4: 92400000 and x0, x0, #0x1 + 8: d2e00004 movz x4, #0x0, lsl #48 + 8: R_AARCH64_MOVW_PREL_G3 tempy + c: d2e00007 movz x7, #0x0, lsl #48 + c: R_AARCH64_MOVW_PREL_G3 tempy2 + 10: d2e00011 movz x17, #0x0, lsl #48 + 10: R_AARCH64_MOVW_PREL_G3 tempy3 diff --git a/gas/testsuite/gas/aarch64/reloc-prel_g3.s b/gas/testsuite/gas/aarch64/reloc-prel_g3.s new file mode 100644 index 0000000..2850e49 --- /dev/null +++ b/gas/testsuite/gas/aarch64/reloc-prel_g3.s @@ -0,0 +1,8 @@ +.comm gempy,4,4 +.text + + and x0,x0,x0 + and x0,x0,#0x1 + movz x4, :prel_g3:tempy + movz x7, :prel_g3:tempy2 + movz x17, :prel_g3:tempy3 -- 1.9.1 --------------6884F606CED7DB90C86A2222--