From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 23F46385482A for ; Thu, 11 Aug 2022 07:01:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 23F46385482A Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 737D7300089; Thu, 11 Aug 2022 07:01:57 +0000 (UTC) From: Tsukasa OI To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [RFC PATCH 5/5] RISC-V: New testcases for mapping symbols w/ ISA Date: Thu, 11 Aug 2022 16:00:53 +0900 Message-Id: <1456c6147a218ac04269b56cdd59003bd134bd74.1660201178.git.research_trasio@irq.a4lg.com> In-Reply-To: References: <1659692183-5682-1-git-send-email-nelson.chu@sifive.com> Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 11 Aug 2022 07:02:05 -0000 Mapping symbols are handled per section but the "current" architecture handled by the assembler has a file scope (regardless of the section). We have to make sure that we can handle such text section changes while changing the architecture. Also, mapping symbol "$x" means that it follows the code with the default architecture (possibly guessed by the ELF attributes). So, if the assembler has the default architecture, we have to make sure that "$x" is emitted. These four new tests are meant to test such complex conditions. gas/ChangeLog: * testsuite/gas/riscv/mapping-05.s: New test for FPR switching. * testsuite/gas/riscv/mapping-05a.d: Likewise. * testsuite/gas/riscv/mapping-05b.d: Likewise. * testsuite/gas/riscv/mapping-06.s: New to test FPR switching and make sure the last mapping symbol is the default without ISA string. * testsuite/gas/riscv/mapping-06a.d: Likewise. * testsuite/gas/riscv/mapping-06b.d: Likewise. * testsuite/gas/riscv/mapping-07.s: New to test no excess mapping symbols are generated by switching between text sections. * testsuite/gas/riscv/mapping-07a.d: Likewise. * testsuite/gas/riscv/mapping-07b.d: Likewise. * testsuite/gas/riscv/mapping-08.s: New to test whether the assembler correctly keeps track of architecture changes even if text sections are changed in the process. * testsuite/gas/riscv/mapping-08a.d: Likewise. * testsuite/gas/riscv/mapping-08b.d: Likewise. --- gas/testsuite/gas/riscv/mapping-05.s | 11 +++++++++ gas/testsuite/gas/riscv/mapping-05a.d | 14 +++++++++++ gas/testsuite/gas/riscv/mapping-05b.d | 14 +++++++++++ gas/testsuite/gas/riscv/mapping-06.s | 11 +++++++++ gas/testsuite/gas/riscv/mapping-06a.d | 14 +++++++++++ gas/testsuite/gas/riscv/mapping-06b.d | 14 +++++++++++ gas/testsuite/gas/riscv/mapping-07.s | 12 ++++++++++ gas/testsuite/gas/riscv/mapping-07a.d | 14 +++++++++++ gas/testsuite/gas/riscv/mapping-07b.d | 21 +++++++++++++++++ gas/testsuite/gas/riscv/mapping-08.s | 34 +++++++++++++++++++++++++++ gas/testsuite/gas/riscv/mapping-08a.d | 18 ++++++++++++++ gas/testsuite/gas/riscv/mapping-08b.d | 23 ++++++++++++++++++ 12 files changed, 200 insertions(+) create mode 100644 gas/testsuite/gas/riscv/mapping-05.s create mode 100644 gas/testsuite/gas/riscv/mapping-05a.d create mode 100644 gas/testsuite/gas/riscv/mapping-05b.d create mode 100644 gas/testsuite/gas/riscv/mapping-06.s create mode 100644 gas/testsuite/gas/riscv/mapping-06a.d create mode 100644 gas/testsuite/gas/riscv/mapping-06b.d create mode 100644 gas/testsuite/gas/riscv/mapping-07.s create mode 100644 gas/testsuite/gas/riscv/mapping-07a.d create mode 100644 gas/testsuite/gas/riscv/mapping-07b.d create mode 100644 gas/testsuite/gas/riscv/mapping-08.s create mode 100644 gas/testsuite/gas/riscv/mapping-08a.d create mode 100644 gas/testsuite/gas/riscv/mapping-08b.d diff --git a/gas/testsuite/gas/riscv/mapping-05.s b/gas/testsuite/gas/riscv/mapping-05.s new file mode 100644 index 00000000000..e3a3da70868 --- /dev/null +++ b/gas/testsuite/gas/riscv/mapping-05.s @@ -0,0 +1,11 @@ + .text + # F + fadd.s f10, f11, f12 + .option arch, -f + .option arch, +zfinx + # Zfinx + fadd.s x10, x11, x12 + .option arch, -zfinx + .option arch, +f + # F (RV32IF -F +Zfinx -Zfinx +F) + fadd.s f10, f11, f12 diff --git a/gas/testsuite/gas/riscv/mapping-05a.d b/gas/testsuite/gas/riscv/mapping-05a.d new file mode 100644 index 00000000000..4a775707d02 --- /dev/null +++ b/gas/testsuite/gas/riscv/mapping-05a.d @@ -0,0 +1,14 @@ +#as: -march=rv32if +#source: mapping-05.s +#objdump: --syms --special-syms + +.*file format.*riscv.* + +SYMBOL TABLE: +0+00 l d .text 0+00 .text +0+00 l d .data 0+00 .data +0+00 l d .bss 0+00 .bss +0+00 l .text 0+00 \$x +0+04 l .text 0+00 \$xrv32i2p1_zicsr2p0_zfinx1p0 +0+08 l .text 0+00 \$xrv32i2p1_f2p2_zicsr2p0 +0+00 l d .riscv.attributes 0+00 .riscv.attributes diff --git a/gas/testsuite/gas/riscv/mapping-05b.d b/gas/testsuite/gas/riscv/mapping-05b.d new file mode 100644 index 00000000000..04115b5062b --- /dev/null +++ b/gas/testsuite/gas/riscv/mapping-05b.d @@ -0,0 +1,14 @@ +#as: -march=rv32if +#source: mapping-05.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <.text>: +[ ]+0:[ ]+00c5f553[ ]+fadd\.s[ ]+fa0,fa1,fa2 +[ ]+4:[ ]+00c5f553[ ]+fadd\.s[ ]+a0,a1,a2 +[ ]+8:[ ]+00c5f553[ ]+fadd\.s[ ]+fa0,fa1,fa2 +#... diff --git a/gas/testsuite/gas/riscv/mapping-06.s b/gas/testsuite/gas/riscv/mapping-06.s new file mode 100644 index 00000000000..c2a1d1689ba --- /dev/null +++ b/gas/testsuite/gas/riscv/mapping-06.s @@ -0,0 +1,11 @@ + .text + # F + fadd.s f10, f11, f12 + .option push + .option arch, -f + .option arch, +zfinx + # Zfinx + fadd.s x10, x11, x12 + .option pop + # F (reverted to default) + fadd.s f10, f11, f12 diff --git a/gas/testsuite/gas/riscv/mapping-06a.d b/gas/testsuite/gas/riscv/mapping-06a.d new file mode 100644 index 00000000000..b39d46449c9 --- /dev/null +++ b/gas/testsuite/gas/riscv/mapping-06a.d @@ -0,0 +1,14 @@ +#as: -march=rv32if +#source: mapping-06.s +#objdump: --syms --special-syms + +.*file format.*riscv.* + +SYMBOL TABLE: +0+00 l d .text 0+00 .text +0+00 l d .data 0+00 .data +0+00 l d .bss 0+00 .bss +0+00 l .text 0+00 \$x +0+04 l .text 0+00 \$xrv32i2p1_zicsr2p0_zfinx1p0 +0+08 l .text 0+00 \$x +0+00 l d .riscv.attributes 0+00 .riscv.attributes diff --git a/gas/testsuite/gas/riscv/mapping-06b.d b/gas/testsuite/gas/riscv/mapping-06b.d new file mode 100644 index 00000000000..bf4af0d4499 --- /dev/null +++ b/gas/testsuite/gas/riscv/mapping-06b.d @@ -0,0 +1,14 @@ +#as: -march=rv32if +#source: mapping-06.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <.text>: +[ ]+0:[ ]+00c5f553[ ]+fadd\.s[ ]+fa0,fa1,fa2 +[ ]+4:[ ]+00c5f553[ ]+fadd\.s[ ]+a0,a1,a2 +[ ]+8:[ ]+00c5f553[ ]+fadd\.s[ ]+fa0,fa1,fa2 +#... diff --git a/gas/testsuite/gas/riscv/mapping-07.s b/gas/testsuite/gas/riscv/mapping-07.s new file mode 100644 index 00000000000..04a0dd55a35 --- /dev/null +++ b/gas/testsuite/gas/riscv/mapping-07.s @@ -0,0 +1,12 @@ + .section .text, "ax", @progbits + add a0, a1, a2 + .section .text2, "ax", @progbits + sub a0, a1, a2 + .section .text, "ax", @progbits + add a0, a1, a2 + .section .text2, "ax", @progbits + sub a0, a1, a2 + .section .text, "ax", @progbits + add a0, a1, a2 + .section .text2, "ax", @progbits + sub a0, a1, a2 diff --git a/gas/testsuite/gas/riscv/mapping-07a.d b/gas/testsuite/gas/riscv/mapping-07a.d new file mode 100644 index 00000000000..75af5d91e71 --- /dev/null +++ b/gas/testsuite/gas/riscv/mapping-07a.d @@ -0,0 +1,14 @@ +#as: +#source: mapping-07.s +#objdump: --syms --special-syms + +.*file format.*riscv.* + +SYMBOL TABLE: +0+00 l d .text 0+00 .text +0+00 l d .data 0+00 .data +0+00 l d .bss 0+00 .bss +0+00 l .text 0+00 \$x +0+00 l d .text2 0+00 .text2 +0+00 l .text2 0+00 \$x +0+00 l d .riscv.attributes 0+00 .riscv.attributes diff --git a/gas/testsuite/gas/riscv/mapping-07b.d b/gas/testsuite/gas/riscv/mapping-07b.d new file mode 100644 index 00000000000..b18d9eea1b6 --- /dev/null +++ b/gas/testsuite/gas/riscv/mapping-07b.d @@ -0,0 +1,21 @@ +#as: +#source: mapping-07.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <.text>: +[ ]+0:[ ]+00c58533[ ]+add[ ]+a0,a1,a2 +[ ]+4:[ ]+00c58533[ ]+add[ ]+a0,a1,a2 +[ ]+8:[ ]+00c58533[ ]+add[ ]+a0,a1,a2 +#... +Disassembly of section .text2: + +0+000 <.text2>: +[ ]+0:[ ]+40c58533[ ]+sub[ ]+a0,a1,a2 +[ ]+4:[ ]+40c58533[ ]+sub[ ]+a0,a1,a2 +[ ]+8:[ ]+40c58533[ ]+sub[ ]+a0,a1,a2 +#... diff --git a/gas/testsuite/gas/riscv/mapping-08.s b/gas/testsuite/gas/riscv/mapping-08.s new file mode 100644 index 00000000000..b992d8e47fc --- /dev/null +++ b/gas/testsuite/gas/riscv/mapping-08.s @@ -0,0 +1,34 @@ + .section .text, "ax", @progbits + # (text:0x0) Arch: default + add a0, a0, a1 + .option push + .option arch, +c + + .section .text2, "ax", @progbits + # (text2:0x0) Arch: +c + sub a0, a0, a1 + .option pop + + .section .text, "ax", @progbits + # (text:0x4) Arch: default (no change) + add a0, a0, a1 + .option push + .option arch, +c + # (text:0x8) Arch: +c + add a0, a0, a1 + + .section .text2, "ax", @progbits + # (text2:0x2) Arch: +c (no change) + sub a0, a0, a1 + .option arch, -c + # (text2:0x4) Arch: +c-c (not default) + sub a0, a0, a1 + + .section .text, "ax", @progbits + # (text:0xa) Arch: +c-c (not default, changed from +c) + add a0, a0, a1 + .option pop + + .section .text2, "ax", @progbits + # (text2:0x8) Arch: Default (changed from +c-c) + sub a0, a0, a1 diff --git a/gas/testsuite/gas/riscv/mapping-08a.d b/gas/testsuite/gas/riscv/mapping-08a.d new file mode 100644 index 00000000000..7c983785471 --- /dev/null +++ b/gas/testsuite/gas/riscv/mapping-08a.d @@ -0,0 +1,18 @@ +#as: -march=rv32i +#source: mapping-08.s +#objdump: --syms --special-syms + +.*file format.*riscv.* + +SYMBOL TABLE: +0+00 l d .text 0+00 .text +0+00 l d .data 0+00 .data +0+00 l d .bss 0+00 .bss +0+00 l .text 0+00 \$x +0+00 l d .text2 0+00 .text2 +0+00 l .text2 0+00 \$xrv32i2p1_c2p0 +0+08 l .text 0+00 \$xrv32i2p1_c2p0 +0+04 l .text2 0+00 \$xrv32i2p1 +0+0a l .text 0+00 \$xrv32i2p1 +0+08 l .text2 0+00 \$x +0+00 l d .riscv.attributes 0+00 .riscv.attributes diff --git a/gas/testsuite/gas/riscv/mapping-08b.d b/gas/testsuite/gas/riscv/mapping-08b.d new file mode 100644 index 00000000000..3d9db75e544 --- /dev/null +++ b/gas/testsuite/gas/riscv/mapping-08b.d @@ -0,0 +1,23 @@ +#as: -march=rv32i +#source: mapping-08.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <.text>: +[ ]+0:[ ]+00b50533[ ]+add[ ]+a0,a0,a1 +[ ]+4:[ ]+00b50533[ ]+add[ ]+a0,a0,a1 +[ ]+8:[ ]+952e[ ]+add[ ]+a0,a0,a1 +[ ]+a:[ ]+00b50533[ ]+add[ ]+a0,a0,a1 +#... +Disassembly of section .text2: + +0+000 <.text2>: +[ ]+0:[ ]+8d0d[ ]+sub[ ]+a0,a0,a1 +[ ]+2:[ ]+8d0d[ ]+sub[ ]+a0,a0,a1 +[ ]+4:[ ]+40b50533[ ]+sub[ ]+a0,a0,a1 +[ ]+8:[ ]+40b50533[ ]+sub[ ]+a0,a0,a1 +#... -- 2.34.1