From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 1214 invoked by alias); 30 Mar 2016 17:18:07 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 1136 invoked by uid 89); 30 Mar 2016 17:18:06 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.2 spammy=Instructions X-HELO: mail-wm0-f49.google.com Received: from mail-wm0-f49.google.com (HELO mail-wm0-f49.google.com) (74.125.82.49) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Wed, 30 Mar 2016 17:17:56 +0000 Received: by mail-wm0-f49.google.com with SMTP id 191so97748388wmq.0 for ; Wed, 30 Mar 2016 10:17:56 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=WZnvK8YexyHn0ovnuTA1V3oXZmD7SNwWq7au4710k74=; b=GXIuloHJoc+6i3Usx6SfscGwz/qeC7tLeak3Hj43m6ngO+QxQGhfiu2pEah8fceA+l J7KXK6kB5+FeDZKABwYkIekao/bXvl1SX5Y9pF5BC7VKCd/bcNUD+k0VzaXJ43cVQkaZ 5wdNkO7uNwkWlTwmw4VD7emadCe28uv62eEL281q38eVn/lx6JzJ0rHUZ3v2c29YswYw bqVMuJGRClDdfx6fYd0ACqO7VvWeq2jypUtzGX3vu3pMl+cFqQALYtXiHXVfVRgq8I3L Tgno4WVQeB1lhi95yaHV6jCKVXSlwB79ZratavWWzl5loAqR8CseAqqe+b/GUToNbS0t x7Pg== X-Gm-Message-State: AD7BkJJJhFNEb36QDjd/JWdbLo4wEMETDmnoMowY+u2qmFccXLxs1dutT0yOhbL4Nc5stQ== X-Received: by 10.194.95.198 with SMTP id dm6mr11531794wjb.136.1459358273284; Wed, 30 Mar 2016 10:17:53 -0700 (PDT) Received: from localhost (host81-140-212-51.range81-140.btcentralplus.com. [81.140.212.51]) by smtp.gmail.com with ESMTPSA id hh8sm4878763wjc.42.2016.03.30.10.17.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 Mar 2016 10:17:52 -0700 (PDT) From: Andrew Burgess To: binutils@sourceware.org Cc: Andrew Burgess Subject: [PUSHED/OBV] opcodes/arc: Comment and whitespace fixes in opcode table Date: Wed, 30 Mar 2016 17:18:00 -0000 Message-Id: <1459358269-10771-1-git-send-email-andrew.burgess@embecosm.com> X-IsSubscribed: yes X-SW-Source: 2016-03/txt/msg00438.txt.bz2 Add a new comment, and clean up some whitespace issues in the instruction table. opcode/ChangeLog: * arc-nps400-tbl.h: Add a header comment, and fix some whitespace issues. No functional changes. --- opcodes/ChangeLog | 5 +++++ opcodes/arc-nps400-tbl.h | 14 ++++++++------ 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/opcodes/arc-nps400-tbl.h b/opcodes/arc-nps400-tbl.h index 4b715f9..493c5b6 100644 --- a/opcodes/arc-nps400-tbl.h +++ b/opcodes/arc-nps400-tbl.h @@ -1,11 +1,13 @@ +/**** Bit Manipulation Instructions ****/ + /* movl<.cl> */ -{ "movh", 0x48080000, 0xf81f0000, ARC_OPCODE_NPS400 , BITOP, NONE, { NPS_R_DST, NPS_R_SRC1, NPS_UIMM16 }, { 0 }}, -{ "movh", 0x48180000, 0xf81f0000, ARC_OPCODE_NPS400 , BITOP, NONE, { NPS_R_DST, NPS_UIMM16 }, { C_NPS_CL }}, +{ "movh", 0x48080000, 0xf81f0000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST, NPS_R_SRC1, NPS_UIMM16 }, { 0 }}, +{ "movh", 0x48180000, 0xf81f0000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST, NPS_UIMM16 }, { C_NPS_CL }}, /* movl<.cl> */ -{ "movl", 0x48090000, 0xf81f0000, ARC_OPCODE_NPS400 , BITOP, NONE, { NPS_R_DST, NPS_R_SRC1, NPS_UIMM16 }, { 0 }}, -{ "movl", 0x48190000, 0xf81f0000, ARC_OPCODE_NPS400 , BITOP, NONE, { NPS_R_DST, NPS_UIMM16 }, { C_NPS_CL }}, +{ "movl", 0x48090000, 0xf81f0000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST, NPS_R_SRC1, NPS_UIMM16 }, { 0 }}, +{ "movl", 0x48190000, 0xf81f0000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST, NPS_UIMM16 }, { C_NPS_CL }}, /* movb<.f><.cl> */ -{ "movb", 0x48010000, 0xf80f8000, ARC_OPCODE_NPS400 , BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }}, -{ "movb", 0x48018000, 0xf80f8000, ARC_OPCODE_NPS400 , BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F, C_NPS_CL }}, +{ "movb", 0x48010000, 0xf80f8000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }}, +{ "movb", 0x48018000, 0xf80f8000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F, C_NPS_CL }}, -- 2.6.4