* [PATCH 2/2] [ARC] Enhance enter/leave mnemonics.
2017-04-25 14:04 [PATCH 0/2] [ARC] Various updates Claudiu Zissulescu
@ 2017-04-25 14:04 ` Claudiu Zissulescu
2017-04-25 14:30 ` Nick Clifton
2017-04-25 14:04 ` [PATCH 1/2] [ARC] Prefer NOP instead of MOV 0,0 Claudiu Zissulescu
1 sibling, 1 reply; 7+ messages in thread
From: Claudiu Zissulescu @ 2017-04-25 14:04 UTC (permalink / raw)
To: binutils; +Cc: Claudiu.Zissulescu, Francois.Bedard
enter/leave mnemonics are enhanced to not only accept register ranges
but also single register (i.e., r13) or even no GPR register at all.
gas/
2017-04-03 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/leave_enter.d: Update test.
* testsuite/gas/arc/leave_enter.s: Likewise.
opcodes/
2017-04-03 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
* arc-opc.c (insert_r13el): New function.
(R13_EL): Define.
* arc-tbl.h: Add new enter/leave variants.
---
gas/testsuite/gas/arc/leave_enter.d | 41 ++++++++++++++++++++++---------------
gas/testsuite/gas/arc/leave_enter.s | 11 ++++++++++
opcodes/arc-dis.c | 19 ++++++++++++++---
opcodes/arc-opc.c | 20 +++++++++++++++++-
opcodes/arc-tbl.h | 2 ++
5 files changed, 73 insertions(+), 20 deletions(-)
diff --git a/gas/testsuite/gas/arc/leave_enter.d b/gas/testsuite/gas/arc/leave_enter.d
index 5eb1aef..821656a 100644
--- a/gas/testsuite/gas/arc/leave_enter.d
+++ b/gas/testsuite/gas/arc/leave_enter.d
@@ -1,21 +1,30 @@
-#objdump: -dr
+#objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format .*arc.*
Disassembly of section .text:
-
-[0-9a-f]+ <.text>:
- 0: c0c2 leave_s \[r13-r13\]
- 2: c4dc leave_s \[r13-gp,pcl\]
- 4: c1dc leave_s \[r13-gp,fp\]
- 6: c2dc leave_s \[r13-gp,blink\]
- 8: c3dc leave_s \[r13-gp,fp,blink\]
- a: c5dc leave_s \[r13-gp,fp,pcl\]
- c: c6dc leave_s \[r13-gp,blink,pcl\]
- e: c7dc leave_s \[r13-gp,fp,blink,pcl\]
- 10: 1100 0000 ld r0,\[r1\]
- 14: c0e2 enter_s \[r13-r13\]
- 16: c1fc enter_s \[r13-gp,fp\]
- 18: c2fc enter_s \[r13-gp,blink\]
- 1a: c3fc enter_s \[r13-gp,fp,blink\]
+0x[0-9a-f]+\s+c0c2\s+leave_s \[r13\]
+0x[0-9a-f]+\s+c0c2\s+leave_s \[r13\]
+0x[0-9a-f]+\s+c4dc\s+leave_s \[r13-gp,pcl\]
+0x[0-9a-f]+\s+c1dc\s+leave_s \[r13-gp,fp\]
+0x[0-9a-f]+\s+c2dc\s+leave_s \[r13-gp,blink\]
+0x[0-9a-f]+\s+c3dc\s+leave_s \[r13-gp,fp,blink\]
+0x[0-9a-f]+\s+c5dc\s+leave_s \[r13-gp,fp,pcl\]
+0x[0-9a-f]+\s+c6dc\s+leave_s \[r13-gp,blink,pcl\]
+0x[0-9a-f]+\s+c7dc\s+leave_s \[r13-gp,fp,blink,pcl\]
+0x[0-9a-f]+\s+c6c2\s+leave_s \[r13,blink,pcl\]
+0x[0-9a-f]+\s+c6c0\s+leave_s \[blink,pcl\]
+0x[0-9a-f]+\s+c1c0\s+leave_s \[fp\]
+0x[0-9a-f]+\s+c2c0\s+leave_s \[blink\]
+0x[0-9a-f]+\s+c4c0\s+leave_s \[pcl\]
+0x[0-9a-f]+\s+1100 0000\s+ld r0,\[r1\]
+0x[0-9a-f]+\s+c0e2\s+enter_s \[r13\]
+0x[0-9a-f]+\s+c0e2\s+enter_s \[r13\]
+0x[0-9a-f]+\s+c1fc\s+enter_s \[r13-gp,fp\]
+0x[0-9a-f]+\s+c2fc\s+enter_s \[r13-gp,blink\]
+0x[0-9a-f]+\s+c3fc\s+enter_s \[r13-gp,fp,blink\]
+0x[0-9a-f]+\s+c2e2\s+enter_s \[r13,blink]
+0x[0-9a-f]+\s+c2e0\s+enter_s \[blink\]
+0x[0-9a-f]+\s+c3e0\s+enter_s \[fp,blink\]
+0x[0-9a-f]+\s+c1e0\s+enter_s \[fp\]
diff --git a/gas/testsuite/gas/arc/leave_enter.s b/gas/testsuite/gas/arc/leave_enter.s
index 1bdcc06..75cf913 100644
--- a/gas/testsuite/gas/arc/leave_enter.s
+++ b/gas/testsuite/gas/arc/leave_enter.s
@@ -1,4 +1,5 @@
.cpu HS
+ leave_s {r13}
leave_s {r13-r13}
leave_s {r13-r26,pcl}
leave_s {r13-r26,fp}
@@ -7,10 +8,20 @@
leave_s {r13-r26,fp,pcl}
leave_s {r13-r26,blink,pcl}
leave_s {r13-r26,fp,blink,pcl}
+ leave_s {r13,blink,pcl}
+ leave_s {blink,pcl}
+ leave_s {fp}
+ leave_s {blink}
+ leave_s {pcl}
ld r0,[r1]
+ enter_s {r13}
enter_s {r13-r13}
enter_s {r13-r26,fp}
enter_s {r13-r26,blink}
enter_s {r13-r26,fp,blink}
+ enter_s {r13,blink}
+ enter_s {blink}
+ enter_s {fp, blink}
+ enter_s {fp}
diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
index 4beca68..6fb030e 100644
--- a/opcodes/arc-dis.c
+++ b/opcodes/arc-dis.c
@@ -1208,9 +1208,22 @@ print_insn_arc (bfd_vma memaddr,
if (operand->flags & ARC_OPERAND_TRUNCATE
&& !(operand->flags & ARC_OPERAND_ALIGNED32)
&& !(operand->flags & ARC_OPERAND_ALIGNED16)
- && value > 0 && value <= 14)
- (*info->fprintf_func) (info->stream, "r13-%s",
- regnames[13 + value - 1]);
+ && value >= 0 && value <= 14)
+ {
+ switch (value)
+ {
+ case 0:
+ need_comma = FALSE;
+ break;
+ case 1:
+ (*info->fprintf_func) (info->stream, "r13");
+ break;
+ default:
+ (*info->fprintf_func) (info->stream, "r13-%s",
+ regnames[13 + value - 1]);
+ break;
+ }
+ }
else
{
const char *rname = get_auxreg (opcode, value, isa_mask);
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index 41cd037..c266f4f 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -546,6 +546,21 @@ extract_rrange (unsigned long long insn,
}
static unsigned long long
+insert_r13el (unsigned long long insn,
+ long long int value,
+ const char **errmsg)
+{
+ if (value != 13)
+ {
+ *errmsg = _("Invalid register number, should be fp");
+ return insn;
+ }
+
+ insn |= 0x02;
+ return insn;
+}
+
+static unsigned long long
insert_fpel (unsigned long long insn,
long long value,
const char ** errmsg)
@@ -1876,7 +1891,10 @@ const struct arc_operand arc_operands[] =
#define RRANGE_EL (ZA + 1)
{ 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE,
insert_rrange, extract_rrange},
-#define FP_EL (RRANGE_EL + 1)
+#define R13_EL (RRANGE_EL + 1)
+ { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
+ insert_r13el, extract_rrange },
+#define FP_EL (R13_EL + 1)
{ 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
insert_fpel, extract_fpel },
#define BLINK_EL (FP_EL + 1)
diff --git a/opcodes/arc-tbl.h b/opcodes/arc-tbl.h
index 6b8a589..826b2ce 100644
--- a/opcodes/arc-tbl.h
+++ b/opcodes/arc-tbl.h
@@ -6192,6 +6192,7 @@
/* enter_s u6 110000UU111uuuu0. */
{ "enter_s", 0x0000C0E0, 0x0000FCE1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ENTER, CD1, { BRAKET, RRANGE_EL, FP_EL, BLINK_EL, BRAKETdup }, { 0 }},
+{ "enter_s", 0x0000C0E0, 0x0000FCE1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ENTER, CD1, { BRAKET, R13_EL, FP_EL, BLINK_EL, BRAKETdup }, { 0 }},
{ "enter_s", 0x0000C0E0, 0x0000FCE1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ENTER, CD1, { UIMM6_11_S }, { 0 }},
/* ex<.di> b,c 00100bbb00101111DBBBCCCCCC001100. */
@@ -8230,6 +8231,7 @@
/* leave_s u7 11000UUU110uuuu0. */
{ "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LEAVE, CD1, { BRAKET, RRANGE_EL, FP_EL, BLINK_EL, PCL_EL, BRAKETdup }, { 0 }},
+{ "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LEAVE, CD1, { BRAKET, R13_EL, FP_EL, BLINK_EL, PCL_EL, BRAKETdup }, { 0 }},
{ "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LEAVE, CD1, { UIMM7_11_S }, { 0 }},
/* llock<.di> b,c 00100bbb00101111DBBBCCCCCC010000. */
--
1.9.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 0/2] [ARC] Various updates
@ 2017-04-25 14:04 Claudiu Zissulescu
2017-04-25 14:04 ` [PATCH 2/2] [ARC] Enhance enter/leave mnemonics Claudiu Zissulescu
2017-04-25 14:04 ` [PATCH 1/2] [ARC] Prefer NOP instead of MOV 0,0 Claudiu Zissulescu
0 siblings, 2 replies; 7+ messages in thread
From: Claudiu Zissulescu @ 2017-04-25 14:04 UTC (permalink / raw)
To: binutils; +Cc: Claudiu.Zissulescu, Francois.Bedard
From: claziss <claziss@synopsys.com>
Hi,
First patch is a "cosmetic" one, by printing NOP instead of MOV 0,0 (NOP instruction is actually a MOV 0,0). More details in the patch itself.
Second patch is updating the enter/leave mnemonics as a result, these instructions can also accept an empty register range.
Tests are provided/updated.
Ok to apply?
Claudiu
Claudiu Zissulescu (2):
Prefer NOP instead of MOV 0,0
Enhance enter/leave mnemonics.
gas/testsuite/gas/arc/b.d | 8 ++++----
gas/testsuite/gas/arc/leave_enter.d | 41 ++++++++++++++++++++++---------------
gas/testsuite/gas/arc/leave_enter.s | 11 ++++++++++
gas/testsuite/gas/arc/noargs_hs.d | 2 +-
opcodes/arc-dis.c | 19 ++++++++++++++---
opcodes/arc-opc.c | 20 +++++++++++++++++-
opcodes/arc-tbl.h | 8 +++++---
7 files changed, 81 insertions(+), 28 deletions(-)
--
1.9.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/2] [ARC] Prefer NOP instead of MOV 0,0
2017-04-25 14:04 [PATCH 0/2] [ARC] Various updates Claudiu Zissulescu
2017-04-25 14:04 ` [PATCH 2/2] [ARC] Enhance enter/leave mnemonics Claudiu Zissulescu
@ 2017-04-25 14:04 ` Claudiu Zissulescu
2017-04-25 14:28 ` Nick Clifton
1 sibling, 1 reply; 7+ messages in thread
From: Claudiu Zissulescu @ 2017-04-25 14:04 UTC (permalink / raw)
To: binutils; +Cc: Claudiu.Zissulescu, Francois.Bedard
NOP and MOV 0,0 are having the same encoding. As MOV mnemonic is
located before NOP in the instruction table, the disassembler prints
MOV 0,0 for NOP. Reorder the instructions such that NOP is first.
gas/
2017-03-30 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/b.d: Update test.
* testsuite/gas/arc/noargs_hs.d: Likewise.
opcode/
2017-03-30 Claudiu Zissulescu <claziss@synopsys.com>
* arc-tbl.h: Reorder NOP entry to be before MOV instructions.
---
gas/testsuite/gas/arc/b.d | 8 ++++----
gas/testsuite/gas/arc/noargs_hs.d | 2 +-
opcodes/arc-tbl.h | 6 +++---
3 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/gas/testsuite/gas/arc/b.d b/gas/testsuite/gas/arc/b.d
index 50bc305..8f121cd 100644
--- a/gas/testsuite/gas/arc/b.d
+++ b/gas/testsuite/gas/arc/b.d
@@ -35,12 +35,12 @@ Disassembly of section .text:
68: 0798 ffce bls -104
6c: 0794 ffcf bpnz -108
70: 0791 ffef b.d 0 <text_label>
- 74: 264a 7000 mov 0,0
+ 74: 264a 7000 nop
78: 0789 ffcf b 0 <text_label>
7c: 0785 ffef b.d 0 <text_label>
- 80: 264a 7000 mov 0,0
+ 80: 264a 7000 nop
84: 077c ffe1 beq.d -132
- 88: 264a 7000 mov 0,0
+ 88: 264a 7000 nop
8c: 0774 ffc2 bne -140
90: 0770 ffe6 bnc.d -144
- 94: 264a 7000 mov 0,0
+ 94: 264a 7000 nop
diff --git a/gas/testsuite/gas/arc/noargs_hs.d b/gas/testsuite/gas/arc/noargs_hs.d
index 14f97aa..7adef57 100644
--- a/gas/testsuite/gas/arc/noargs_hs.d
+++ b/gas/testsuite/gas/arc/noargs_hs.d
@@ -14,7 +14,7 @@ Disassembly of section .text:
e: 246f 003f rtie
12: 216f 003f sleep 0
16: 226f 103f dsync
- 1a: 264a 7000 mov 0,0
+ 1a: 264a 7000 nop
1e: 78e0 nop_s
20: 256f 003f brk
24: 236f 003f sync
diff --git a/opcodes/arc-tbl.h b/opcodes/arc-tbl.h
index c7d5c34..6b8a589 100644
--- a/opcodes/arc-tbl.h
+++ b/opcodes/arc-tbl.h
@@ -10113,6 +10113,9 @@
/* minidl<.f><.cc> 0,limm,limm 0010111011001001F1111111100QQQQQ. */
{ "minidl", 0x2EC97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+/* nop 00100110010010100111000000000000. */
+{ "nop", 0x264A7000, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
+
/* mov<.f> b,c 00100bbb00001010FBBBCCCCCCRRRRRR. */
{ "mov", 0x200A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { RB, RC }, { C_F }},
@@ -12702,9 +12705,6 @@
/* neg_s b,c 01111bbbccc10011. */
{ "neg_s", 0x00007813, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RC_S }, { 0 }},
-/* nop 00100110010010100111000000000000. */
-{ "nop", 0x264A7000, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
-
/* nop_s 0111100011100000. */
{ "nop_s", 0x000078E0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
--
1.9.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] [ARC] Prefer NOP instead of MOV 0,0
2017-04-25 14:04 ` [PATCH 1/2] [ARC] Prefer NOP instead of MOV 0,0 Claudiu Zissulescu
@ 2017-04-25 14:28 ` Nick Clifton
2017-04-25 14:58 ` Claudiu Zissulescu
0 siblings, 1 reply; 7+ messages in thread
From: Nick Clifton @ 2017-04-25 14:28 UTC (permalink / raw)
To: Claudiu Zissulescu, binutils; +Cc: Francois.Bedard
Hi Claudiu,
> gas/
> 2017-03-30 Claudiu Zissulescu <claziss@synopsys.com>
>
> * testsuite/gas/arc/b.d: Update test.
> * testsuite/gas/arc/noargs_hs.d: Likewise.
>
> opcode/
> 2017-03-30 Claudiu Zissulescu <claziss@synopsys.com>
>
> * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
Approved - please apply.
Cheers
Nick
PS. FYI: Some other targets show the true disassembly of a NOP instruction
as a comment at the end of the line. Just in case a user complains that their
"mov 0,0" instruction was not disassembled correctly, I guess.
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] [ARC] Enhance enter/leave mnemonics.
2017-04-25 14:04 ` [PATCH 2/2] [ARC] Enhance enter/leave mnemonics Claudiu Zissulescu
@ 2017-04-25 14:30 ` Nick Clifton
2017-04-25 15:11 ` Claudiu Zissulescu
0 siblings, 1 reply; 7+ messages in thread
From: Nick Clifton @ 2017-04-25 14:30 UTC (permalink / raw)
To: Claudiu Zissulescu, binutils; +Cc: Francois.Bedard
Hi Claudiu,
> gas/
> 2017-04-03 Claudiu Zissulescu <claziss@synopsys.com>
>
> * testsuite/gas/arc/leave_enter.d: Update test.
> * testsuite/gas/arc/leave_enter.s: Likewise.
>
> opcodes/
> 2017-04-03 Claudiu Zissulescu <claziss@synopsys.com>
>
> * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
> * arc-opc.c (insert_r13el): New function.
> (R13_EL): Define.
> * arc-tbl.h: Add new enter/leave variants.
Approved - please apply.
Cheers
Nick
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH 1/2] [ARC] Prefer NOP instead of MOV 0,0
2017-04-25 14:28 ` Nick Clifton
@ 2017-04-25 14:58 ` Claudiu Zissulescu
0 siblings, 0 replies; 7+ messages in thread
From: Claudiu Zissulescu @ 2017-04-25 14:58 UTC (permalink / raw)
To: Nick Clifton, binutils; +Cc: Francois.Bedard
> PS. FYI: Some other targets show the true disassembly of a NOP instruction
> as a comment at the end of the line. Just in case a user complains that their
> "mov 0,0" instruction was not disassembled correctly, I guess.
Good point, though until now I've got the complains that we do show only mov 0,0 :)
I'll make a note to come back to you with an extra patch on the subject.
Thank you,
Claudiu
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH 2/2] [ARC] Enhance enter/leave mnemonics.
2017-04-25 14:30 ` Nick Clifton
@ 2017-04-25 15:11 ` Claudiu Zissulescu
0 siblings, 0 replies; 7+ messages in thread
From: Claudiu Zissulescu @ 2017-04-25 15:11 UTC (permalink / raw)
To: Nick Clifton, binutils; +Cc: Francois.Bedard
> Approved - please apply.
>
Both patches committed. Thank you for your review,
Claudiu
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2017-04-25 15:11 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
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2017-04-25 14:04 [PATCH 0/2] [ARC] Various updates Claudiu Zissulescu
2017-04-25 14:04 ` [PATCH 2/2] [ARC] Enhance enter/leave mnemonics Claudiu Zissulescu
2017-04-25 14:30 ` Nick Clifton
2017-04-25 15:11 ` Claudiu Zissulescu
2017-04-25 14:04 ` [PATCH 1/2] [ARC] Prefer NOP instead of MOV 0,0 Claudiu Zissulescu
2017-04-25 14:28 ` Nick Clifton
2017-04-25 14:58 ` Claudiu Zissulescu
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