* [Committed] S/390: arch13: Adjust to recent changes
2019-03-12 13:28 [Committed] S/390: arch13: Add instruction descriptions Andreas Krebbel
@ 2019-03-12 13:28 ` Andreas Krebbel
0 siblings, 0 replies; 2+ messages in thread
From: Andreas Krebbel @ 2019-03-12 13:28 UTC (permalink / raw)
To: binutils
This adjusts the assembler/disassembler to some last minute changes.
In order to work with the arch13 instruction set only this version of
Binutils should be used.
Applied to mainline and 2.32 branch.
opcodes/ChangeLog:
2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
* s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
from vstrszb, vstrszh, and vstrszf.
gas/ChangeLog:
2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
* testsuite/gas/s390/zarch-arch13.s: Adjust testcase to optable changes.
* testsuite/gas/s390/zarch-arch13.d: Likewise.
---
gas/testsuite/gas/s390/zarch-arch13.d | 46 +++++++++++++++++------------------
gas/testsuite/gas/s390/zarch-arch13.s | 45 ++++++++++++++++------------------
opcodes/s390-opc.txt | 10 ++++----
3 files changed, 48 insertions(+), 53 deletions(-)
diff --git a/gas/testsuite/gas/s390/zarch-arch13.d b/gas/testsuite/gas/s390/zarch-arch13.d
index 2530be6..fecbeb5 100644
--- a/gas/testsuite/gas/s390/zarch-arch13.d
+++ b/gas/testsuite/gas/s390/zarch-arch13.d
@@ -61,27 +61,27 @@ Disassembly of section .text:
.*: b9 e3 bd 69 [ ]*selgrnh %r6,%r9,%r11
.*: b9 e3 bd 69 [ ]*selgrnh %r6,%r9,%r11
.*: b9 e3 be 69 [ ]*selgrno %r6,%r9,%r11
-.*: b9 c0 bd 69 [ ]*selhhhrnh %r6,%r9,%r11
-.*: b9 c0 b1 69 [ ]*selhhhro %r6,%r9,%r11
-.*: b9 c0 b2 69 [ ]*selhhhrh %r6,%r9,%r11
-.*: b9 c0 b2 69 [ ]*selhhhrh %r6,%r9,%r11
-.*: b9 c0 b3 69 [ ]*selhhhrnle %r6,%r9,%r11
-.*: b9 c0 b4 69 [ ]*selhhhrl %r6,%r9,%r11
-.*: b9 c0 b4 69 [ ]*selhhhrl %r6,%r9,%r11
-.*: b9 c0 b5 69 [ ]*selhhhrnhe %r6,%r9,%r11
-.*: b9 c0 b6 69 [ ]*selhhhrlh %r6,%r9,%r11
-.*: b9 c0 b7 69 [ ]*selhhhrne %r6,%r9,%r11
-.*: b9 c0 b7 69 [ ]*selhhhrne %r6,%r9,%r11
-.*: b9 c0 b8 69 [ ]*selhhhre %r6,%r9,%r11
-.*: b9 c0 b8 69 [ ]*selhhhre %r6,%r9,%r11
-.*: b9 c0 b9 69 [ ]*selhhhrnlh %r6,%r9,%r11
-.*: b9 c0 ba 69 [ ]*selhhhrhe %r6,%r9,%r11
-.*: b9 c0 bb 69 [ ]*selhhhrnl %r6,%r9,%r11
-.*: b9 c0 bb 69 [ ]*selhhhrnl %r6,%r9,%r11
-.*: b9 c0 bc 69 [ ]*selhhhrle %r6,%r9,%r11
-.*: b9 c0 bd 69 [ ]*selhhhrnh %r6,%r9,%r11
-.*: b9 c0 bd 69 [ ]*selhhhrnh %r6,%r9,%r11
-.*: b9 c0 be 69 [ ]*selhhhrno %r6,%r9,%r11
+.*: b9 c0 bd 69 [ ]*selfhrnh %r6,%r9,%r11
+.*: b9 c0 b1 69 [ ]*selfhro %r6,%r9,%r11
+.*: b9 c0 b2 69 [ ]*selfhrh %r6,%r9,%r11
+.*: b9 c0 b2 69 [ ]*selfhrh %r6,%r9,%r11
+.*: b9 c0 b3 69 [ ]*selfhrnle %r6,%r9,%r11
+.*: b9 c0 b4 69 [ ]*selfhrl %r6,%r9,%r11
+.*: b9 c0 b4 69 [ ]*selfhrl %r6,%r9,%r11
+.*: b9 c0 b5 69 [ ]*selfhrnhe %r6,%r9,%r11
+.*: b9 c0 b6 69 [ ]*selfhrlh %r6,%r9,%r11
+.*: b9 c0 b7 69 [ ]*selfhrne %r6,%r9,%r11
+.*: b9 c0 b7 69 [ ]*selfhrne %r6,%r9,%r11
+.*: b9 c0 b8 69 [ ]*selfhre %r6,%r9,%r11
+.*: b9 c0 b8 69 [ ]*selfhre %r6,%r9,%r11
+.*: b9 c0 b9 69 [ ]*selfhrnlh %r6,%r9,%r11
+.*: b9 c0 ba 69 [ ]*selfhrhe %r6,%r9,%r11
+.*: b9 c0 bb 69 [ ]*selfhrnl %r6,%r9,%r11
+.*: b9 c0 bb 69 [ ]*selfhrnl %r6,%r9,%r11
+.*: b9 c0 bc 69 [ ]*selfhrle %r6,%r9,%r11
+.*: b9 c0 bd 69 [ ]*selfhrnh %r6,%r9,%r11
+.*: b9 c0 bd 69 [ ]*selfhrnh %r6,%r9,%r11
+.*: b9 c0 be 69 [ ]*selfhrno %r6,%r9,%r11
.*: e6 f6 9f a0 d0 06 [ ]*vlbr %v15,4000\(%r6,%r9\),13
.*: e6 f6 9f a0 10 06 [ ]*vlbrh %v15,4000\(%r6,%r9\)
.*: e6 f6 9f a0 20 06 [ ]*vlbrf %v15,4000\(%r6,%r9\)
@@ -130,11 +130,8 @@ Disassembly of section .text:
.*: e7 f1 42 00 87 8b [ ]*vstrsf %v15,%v17,%v20,%v24
.*: e7 f1 42 d0 87 8b [ ]*vstrsf %v15,%v17,%v20,%v24,13
.*: e7 f1 40 20 87 8b [ ]*vstrszb %v15,%v17,%v20,%v24
-.*: e7 f1 40 f0 87 8b [ ]*vstrszb %v15,%v17,%v20,%v24,13
.*: e7 f1 41 20 87 8b [ ]*vstrszh %v15,%v17,%v20,%v24
-.*: e7 f1 41 f0 87 8b [ ]*vstrszh %v15,%v17,%v20,%v24,13
.*: e7 f1 42 20 87 8b [ ]*vstrszf %v15,%v17,%v20,%v24
-.*: e7 f1 42 f0 87 8b [ ]*vstrszf %v15,%v17,%v20,%v24,13
.*: e7 f1 00 bc d4 c3 [ ]*vcfps %v15,%v17,13,12,11
.*: e7 f1 00 cd 24 c3 [ ]*wcefb %v15,%v17,5,12
.*: e7 f1 00 cd 24 c3 [ ]*wcefb %v15,%v17,5,12
@@ -154,3 +151,4 @@ Disassembly of section .text:
.*: e6 6f 00 d0 00 52 [ ]*vcvbg %r6,%v15,13
.*: e6 6f 00 dc 00 52 [ ]*vcvbg %r6,%v15,13,12
.*: b9 3a 00 69 [ ]*kdsa %r6,%r9
+.*: 07 07 [ ]*nopr %r7
diff --git a/gas/testsuite/gas/s390/zarch-arch13.s b/gas/testsuite/gas/s390/zarch-arch13.s
index 2dbbafb..9563a1b 100644
--- a/gas/testsuite/gas/s390/zarch-arch13.s
+++ b/gas/testsuite/gas/s390/zarch-arch13.s
@@ -55,27 +55,27 @@ foo:
selgrnh %r6,%r9,%r11
selgrnp %r6,%r9,%r11
selgrno %r6,%r9,%r11
- selhhhr %r6,%r9,%r11,13
- selhhhro %r6,%r9,%r11
- selhhhrh %r6,%r9,%r11
- selhhhrp %r6,%r9,%r11
- selhhhrnle %r6,%r9,%r11
- selhhhrl %r6,%r9,%r11
- selhhhrm %r6,%r9,%r11
- selhhhrnhe %r6,%r9,%r11
- selhhhrlh %r6,%r9,%r11
- selhhhrne %r6,%r9,%r11
- selhhhrnz %r6,%r9,%r11
- selhhhre %r6,%r9,%r11
- selhhhrz %r6,%r9,%r11
- selhhhrnlh %r6,%r9,%r11
- selhhhrhe %r6,%r9,%r11
- selhhhrnl %r6,%r9,%r11
- selhhhrnm %r6,%r9,%r11
- selhhhrle %r6,%r9,%r11
- selhhhrnh %r6,%r9,%r11
- selhhhrnp %r6,%r9,%r11
- selhhhrno %r6,%r9,%r11
+ selfhr %r6,%r9,%r11,13
+ selfhro %r6,%r9,%r11
+ selfhrh %r6,%r9,%r11
+ selfhrp %r6,%r9,%r11
+ selfhrnle %r6,%r9,%r11
+ selfhrl %r6,%r9,%r11
+ selfhrm %r6,%r9,%r11
+ selfhrnhe %r6,%r9,%r11
+ selfhrlh %r6,%r9,%r11
+ selfhrne %r6,%r9,%r11
+ selfhrnz %r6,%r9,%r11
+ selfhre %r6,%r9,%r11
+ selfhrz %r6,%r9,%r11
+ selfhrnlh %r6,%r9,%r11
+ selfhrhe %r6,%r9,%r11
+ selfhrnl %r6,%r9,%r11
+ selfhrnm %r6,%r9,%r11
+ selfhrle %r6,%r9,%r11
+ selfhrnh %r6,%r9,%r11
+ selfhrnp %r6,%r9,%r11
+ selfhrno %r6,%r9,%r11
vlbr %v15,4000(%r6,%r9),13
vlbrh %v15,4000(%r6,%r9)
vlbrf %v15,4000(%r6,%r9)
@@ -124,11 +124,8 @@ foo:
vstrsf %v15,%v17,%v20,%v24
vstrsf %v15,%v17,%v20,%v24,13
vstrszb %v15,%v17,%v20,%v24
- vstrszb %v15,%v17,%v20,%v24,13
vstrszh %v15,%v17,%v20,%v24
- vstrszh %v15,%v17,%v20,%v24,13
vstrszf %v15,%v17,%v20,%v24
- vstrszf %v15,%v17,%v20,%v24,13
vcfps %v15,%v17,13,12,11
vcefb %v15,%v17,13,12
wcefb %v15,%v17,13,12
diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
index 58a2490..7569a56 100644
--- a/opcodes/s390-opc.txt
+++ b/opcodes/s390-opc.txt
@@ -1910,8 +1910,8 @@ b9f0 selr RRF_RURR "select 32 bit" arch13 zarch
b9f00000 selr*20 RRF_R0RR3 "select 32 bit" arch13 zarch
b9e3 selgr RRF_RURR "select 64 bit" arch13 zarch
b9e30000 selgr*20 RRF_R0RR3 "select 64 bit" arch13 zarch
-b9c0 selhhhr RRF_RURR "select high" arch13 zarch
-b9c00000 selhhhr*20 RRF_R0RR3 "select high" arch13 zarch
+b9c0 selfhr RRF_RURR "select high" arch13 zarch
+b9c00000 selfhr*20 RRF_R0RR3 "select high" arch13 zarch
# Vector Enhancements Facility 2
@@ -1969,9 +1969,9 @@ e7000000008b vstrsb VRR_VVVU0VB "vector string search byte" arch13 zarch optparm
e7000100008b vstrsh VRR_VVVU0VB "vector string search halfword" arch13 zarch optparm
e7000200008b vstrsf VRR_VVVU0VB "vector string search word" arch13 zarch optparm
-e7000020008b vstrszb VRR_VVVU0VB2 "vector string search byte zero" arch13 zarch optparm
-e7000120008b vstrszh VRR_VVVU0VB2 "vector string search halfword zero" arch13 zarch optparm
-e7000220008b vstrszf VRR_VVVU0VB2 "vector string search word zero" arch13 zarch optparm
+e7000020008b vstrszb VRR_VVV0V "vector string search byte zero" arch13 zarch
+e7000120008b vstrszh VRR_VVV0V "vector string search halfword zero" arch13 zarch
+e7000220008b vstrszf VRR_VVV0V "vector string search word zero" arch13 zarch
e700000000c3 vcfps VRR_VV0UUU "vector fp convert from fixed" arch13 zarch
e700000020c3 vcefb VRR_VV0UU "vector fp convert from fixed 32 bit" arch13 zarch
--
2.7.4
^ permalink raw reply [flat|nested] 2+ messages in thread
* [Committed] S/390: arch13: Add instruction descriptions
@ 2019-03-12 13:28 Andreas Krebbel
2019-03-12 13:28 ` [Committed] S/390: arch13: Adjust to recent changes Andreas Krebbel
0 siblings, 1 reply; 2+ messages in thread
From: Andreas Krebbel @ 2019-03-12 13:28 UTC (permalink / raw)
To: binutils
Applied to mainline and 2.32 branch.
opcodes/ChangeLog:
2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
* s390-opc.txt: Add instruction descriptions.
---
opcodes/s390-opc.txt | 216 +++++++++++++++++++++++++++------------------------
1 file changed, 115 insertions(+), 101 deletions(-)
diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
index be4c97d..58a2490 100644
--- a/opcodes/s390-opc.txt
+++ b/opcodes/s390-opc.txt
@@ -1888,106 +1888,120 @@ e70000000036 vlm VRS_VVRDU "vector load multiple" arch12 zarch optparm
e7000000000e vst VRX_VRRDU "vector store" arch12 zarch optparm
e7000000003e vstm VRS_VVRDU "vector store multiple" arch12 zarch optparm
+
# arch13 instructions
-b9f5 ncrk RRF_R0RR2 " " arch13 zarch
-b9e5 ncgrk RRF_R0RR2 " " arch13 zarch
-e50a mvcrl SSE_RDRD " " arch13 zarch
-b974 nnrk RRF_R0RR2 " " arch13 zarch
-b964 nngrk RRF_R0RR2 " " arch13 zarch
-b976 nork RRF_R0RR2 " " arch13 zarch
-b966 nogrk RRF_R0RR2 " " arch13 zarch
-b977 nxrk RRF_R0RR2 " " arch13 zarch
-b967 nxgrk RRF_R0RR2 " " arch13 zarch
-b975 ocrk RRF_R0RR2 " " arch13 zarch
-b965 ocgrk RRF_R0RR2 " " arch13 zarch
-b9e1 popcnt RRF_U0RR " " arch13 zarch optparm
-b9f0 selr RRF_RURR " " arch13 zarch
-b9f00000 selr*20 RRF_R0RR3 " " arch13 zarch
-b9e3 selgr RRF_RURR " " arch13 zarch
-b9e30000 selgr*20 RRF_R0RR3 " " arch13 zarch
-b9c0 selhhhr RRF_RURR " " arch13 zarch
-b9c00000 selhhhr*20 RRF_R0RR3 " " arch13 zarch
-
-e60000000006 vlbr VRX_VRRDU " " arch13 zarch
-e60000001006 vlbrh VRX_VRRD " " arch13 zarch
-e60000002006 vlbrf VRX_VRRD " " arch13 zarch
-e60000003006 vlbrg VRX_VRRD " " arch13 zarch
-e60000004006 vlbrq VRX_VRRD " " arch13 zarch
-
-e60000000007 vler VRX_VRRDU " " arch13 zarch
-e60000001007 vlerh VRX_VRRD " " arch13 zarch
-e60000002007 vlerf VRX_VRRD " " arch13 zarch
-e60000003007 vlerg VRX_VRRD " " arch13 zarch
-
-e60000000004 vllebrz VRX_VRRDU " " arch13 zarch
-e60000001004 vllebrzh VRX_VRRD " " arch13 zarch
-e60000002004 vllebrzf VRX_VRRD " " arch13 zarch
-e60000003004 ldrv VRX_VRRD " " arch13 zarch
-e60000003004 vllebrzg VRX_VRRD " " arch13 zarch
-e60000006004 lerv VRX_VRRD " " arch13 zarch
-e60000006004 vllebrze VRX_VRRD " " arch13 zarch
-
-e60000000001 vlebrh VRX_VRRDU " " arch13 zarch
-e60000000003 vlebrf VRX_VRRDU " " arch13 zarch
-e60000000002 vlebrg VRX_VRRDU " " arch13 zarch
-
-e60000000005 vlbrrep VRX_VRRDU " " arch13 zarch
-e60000001005 vlbrreph VRX_VRRD " " arch13 zarch
-e60000002005 vlbrrepf VRX_VRRD " " arch13 zarch
-e60000003005 vlbrrepg VRX_VRRD " " arch13 zarch
-
-e6000000000e vstbr VRX_VRRDU " " arch13 zarch
-e6000000100e vstbrh VRX_VRRD " " arch13 zarch
-e6000000200e vstbrf VRX_VRRD " " arch13 zarch
-e6000000300e vstbrg VRX_VRRD " " arch13 zarch
-e6000000400e vstbrq VRX_VRRD " " arch13 zarch
-
-e6000000000f vster VRX_VRRDU " " arch13 zarch
-e6000000100f vsterh VRX_VRRD " " arch13 zarch
-e6000000200f vsterf VRX_VRRD " " arch13 zarch
-e6000000300f vsterg VRX_VRRD " " arch13 zarch
-
-e60000000009 vstebrh VRX_VRRDU " " arch13 zarch
-e6000000000b vstebrf VRX_VRRDU " " arch13 zarch
-e6000000000b sterv VRX_VRRD " " arch13 zarch
-e6000000000a vstebrg VRX_VRRDU " " arch13 zarch
-e6000000000a stdrv VRX_VRRD " " arch13 zarch
-
-e70000000086 vsld VRI_VVV0U " " arch13 zarch
-e70000000087 vsrd VRI_VVV0U " " arch13 zarch
-
-e7000000008b vstrs VRR_VVVUU0V " " arch13 zarch optparm
-
-e7000000008b vstrsb VRR_VVVU0VB " " arch13 zarch optparm
-e7000100008b vstrsh VRR_VVVU0VB " " arch13 zarch optparm
-e7000200008b vstrsf VRR_VVVU0VB " " arch13 zarch optparm
-
-e7000020008b vstrszb VRR_VVVU0VB2 " " arch13 zarch optparm
-e7000120008b vstrszh VRR_VVVU0VB2 " " arch13 zarch optparm
-e7000220008b vstrszf VRR_VVVU0VB2 " " arch13 zarch optparm
-
-e700000000c3 vcfps VRR_VV0UUU " " arch13 zarch
-e700000020c3 vcefb VRR_VV0UU " " arch13 zarch
-e700000820c3 wcefb VRR_VV0UU8 " " arch13 zarch
-
-e700000000c1 vcfpl VRR_VV0UUU " " arch13 zarch
-e700000020c1 vcelfb VRR_VV0UU " " arch13 zarch
-e700000820c1 wcelfb VRR_VV0UU8 " " arch13 zarch
-
-e700000000c2 vcsfp VRR_VV0UUU " " arch13 zarch
-e700000020c2 vcfeb VRR_VV0UU " " arch13 zarch
-e700000820c2 wcfeb VRR_VV0UU8 " " arch13 zarch
-
-e700000000c0 vclfp VRR_VV0UUU " " arch13 zarch
-e700000020c0 vclfeb VRR_VV0UU " " arch13 zarch
-e700000820c0 wclfeb VRR_VV0UU8 " " arch13 zarch
-
-b939 dfltcc RRF_R0RR2 " " arch13 zarch
-
-b938 sortl RRE_RR " " arch13 zarch
-
-e60000000050 vcvb VRR_RV0UU " " arch13 zarch optparm
-e60000000052 vcvbg VRR_RV0UU " " arch13 zarch optparm
-
-b93a kdsa RRE_RR " " arch13 zarch
+
+# Miscellaneous Instruction Extensions Facility 2
+
+b9f5 ncrk RRF_R0RR2 "and with complement 32 bit" arch13 zarch
+b9e5 ncgrk RRF_R0RR2 "and with complement 64 bit" arch13 zarch
+e50a mvcrl SSE_RDRD "move right to left" arch13 zarch
+b974 nnrk RRF_R0RR2 "nand 32 bit" arch13 zarch
+b964 nngrk RRF_R0RR2 "nand 64 bit" arch13 zarch
+b976 nork RRF_R0RR2 "nor 32 bit" arch13 zarch
+b966 nogrk RRF_R0RR2 "nor 64 bit" arch13 zarch
+b977 nxrk RRF_R0RR2 "not exclusive or 32 bit" arch13 zarch
+b967 nxgrk RRF_R0RR2 "not exclusive or 64 bit" arch13 zarch
+b975 ocrk RRF_R0RR2 "or with complement 32 bit" arch13 zarch
+b965 ocgrk RRF_R0RR2 "or with complement 64 bit" arch13 zarch
+b9e1 popcnt RRF_U0RR "population count arch13" arch13 zarch optparm
+b9f0 selr RRF_RURR "select 32 bit" arch13 zarch
+b9f00000 selr*20 RRF_R0RR3 "select 32 bit" arch13 zarch
+b9e3 selgr RRF_RURR "select 64 bit" arch13 zarch
+b9e30000 selgr*20 RRF_R0RR3 "select 64 bit" arch13 zarch
+b9c0 selhhhr RRF_RURR "select high" arch13 zarch
+b9c00000 selhhhr*20 RRF_R0RR3 "select high" arch13 zarch
+
+# Vector Enhancements Facility 2
+
+e60000000006 vlbr VRX_VRRDU "vector load byte reversed elements" arch13 zarch
+e60000001006 vlbrh VRX_VRRD "vector load byte reversed halfword elements" arch13 zarch
+e60000002006 vlbrf VRX_VRRD "vector load byte reversed word elements" arch13 zarch
+e60000003006 vlbrg VRX_VRRD "vector load byte reversed doubleword elements" arch13 zarch
+e60000004006 vlbrq VRX_VRRD "vector load byte reversed quadword elements" arch13 zarch
+
+e60000000007 vler VRX_VRRDU "vector load elements reversed" arch13 zarch
+e60000001007 vlerh VRX_VRRD "vector load halfword elements reversed" arch13 zarch
+e60000002007 vlerf VRX_VRRD "vector load word elements reversed" arch13 zarch
+e60000003007 vlerg VRX_VRRD "vector load doubleword elements reversed" arch13 zarch
+
+e60000000004 vllebrz VRX_VRRDU "vector load byte reversed element and zero" arch13 zarch
+e60000001004 vllebrzh VRX_VRRD "vector load byte reversed halfword element and zero" arch13 zarch
+e60000002004 vllebrzf VRX_VRRD "vector load byte reversed word element and zero" arch13 zarch
+e60000003004 ldrv VRX_VRRD "load byte reversed doubleword" arch13 zarch
+e60000003004 vllebrzg VRX_VRRD "vector load byte reversed doubleword element and zero" arch13 zarch
+e60000006004 lerv VRX_VRRD "load byte reversed word" arch13 zarch
+e60000006004 vllebrze VRX_VRRD "vector load byte reversed word element left-aligned and zero" arch13 zarch
+
+e60000000001 vlebrh VRX_VRRDU "vector load byte reversed halfword element" arch13 zarch
+e60000000003 vlebrf VRX_VRRDU "vector load byte reversed word element" arch13 zarch
+e60000000002 vlebrg VRX_VRRDU "vector load byte reversed doubleword element" arch13 zarch
+
+e60000000005 vlbrrep VRX_VRRDU "vector load byte reversed element and replicate" arch13 zarch
+e60000001005 vlbrreph VRX_VRRD "vector load byte reversed halfword element and replicate" arch13 zarch
+e60000002005 vlbrrepf VRX_VRRD "vector load byte reversed word element and replicate" arch13 zarch
+e60000003005 vlbrrepg VRX_VRRD "vector load byte reversed doubleword element and replicate" arch13 zarch
+
+e6000000000e vstbr VRX_VRRDU "vector store byte reversed elements" arch13 zarch
+e6000000100e vstbrh VRX_VRRD "vector store byte reversed halfword elements" arch13 zarch
+e6000000200e vstbrf VRX_VRRD "vector store byte reversed word elements" arch13 zarch
+e6000000300e vstbrg VRX_VRRD "vector store byte reversed doubleword elements" arch13 zarch
+e6000000400e vstbrq VRX_VRRD "vector store byte reversed quadword elements" arch13 zarch
+
+e6000000000f vster VRX_VRRDU "vector store elements reversed" arch13 zarch
+e6000000100f vsterh VRX_VRRD "vector store halfword elements reversed" arch13 zarch
+e6000000200f vsterf VRX_VRRD "vector store word elements reversed" arch13 zarch
+e6000000300f vsterg VRX_VRRD "vector store doubleword elements reversed" arch13 zarch
+
+e60000000009 vstebrh VRX_VRRDU "vector store byte reversed halfword element" arch13 zarch
+e6000000000b vstebrf VRX_VRRDU "vector store byte reversed word element" arch13 zarch
+e6000000000b sterv VRX_VRRD "store byte reversed word" arch13 zarch
+e6000000000a vstebrg VRX_VRRDU "vector store byte reversed doubleword element" arch13 zarch
+e6000000000a stdrv VRX_VRRD "store byte reversed doubleword" arch13 zarch
+
+e70000000086 vsld VRI_VVV0U "vector shift left double by bit" arch13 zarch
+e70000000087 vsrd VRI_VVV0U "vector shift right double by bit" arch13 zarch
+
+e7000000008b vstrs VRR_VVVUU0V "vector string search" arch13 zarch optparm
+
+e7000000008b vstrsb VRR_VVVU0VB "vector string search byte" arch13 zarch optparm
+e7000100008b vstrsh VRR_VVVU0VB "vector string search halfword" arch13 zarch optparm
+e7000200008b vstrsf VRR_VVVU0VB "vector string search word" arch13 zarch optparm
+
+e7000020008b vstrszb VRR_VVVU0VB2 "vector string search byte zero" arch13 zarch optparm
+e7000120008b vstrszh VRR_VVVU0VB2 "vector string search halfword zero" arch13 zarch optparm
+e7000220008b vstrszf VRR_VVVU0VB2 "vector string search word zero" arch13 zarch optparm
+
+e700000000c3 vcfps VRR_VV0UUU "vector fp convert from fixed" arch13 zarch
+e700000020c3 vcefb VRR_VV0UU "vector fp convert from fixed 32 bit" arch13 zarch
+e700000820c3 wcefb VRR_VV0UU8 "vector fp convert from fixed 32 bit" arch13 zarch
+
+e700000000c1 vcfpl VRR_VV0UUU "vector fp convert from logical" arch13 zarch
+e700000020c1 vcelfb VRR_VV0UU "vector fp convert from logical 32 bit" arch13 zarch
+e700000820c1 wcelfb VRR_VV0UU8 "vector fp convert from logical 32 bit" arch13 zarch
+
+e700000000c2 vcsfp VRR_VV0UUU "vector fp convert to fixed" arch13 zarch
+e700000020c2 vcfeb VRR_VV0UU "vector fp convert to fixed 32 bit" arch13 zarch
+e700000820c2 wcfeb VRR_VV0UU8 "vector fp convert to fixed 32 bit" arch13 zarch
+
+e700000000c0 vclfp VRR_VV0UUU "vector fp convert to logical" arch13 zarch
+e700000020c0 vclfeb VRR_VV0UU "vector fp convert to logical 32 bit" arch13 zarch
+e700000820c0 wclfeb VRR_VV0UU8 "vector fp convert to logical 32 bit" arch13 zarch
+
+# Deflate conversion facility
+
+b939 dfltcc RRF_R0RR2 "deflate conversion call" arch13 zarch
+
+# Enhanced-Sort Facility
+
+b938 sortl RRE_RR "sort lists" arch13 zarch
+
+# Vector packed decimal enhancement facility
+
+e60000000050 vcvb VRR_RV0UU "vector convert to binary 32 bit" arch13 zarch optparm
+e60000000052 vcvbg VRR_RV0UU "vector convert to binary 64 bit" arch13 zarch optparm
+
+# Message Security Assist Extension 9
+
+b93a kdsa RRE_RR "compute digital signature authentication" arch13 zarch
--
2.7.4
^ permalink raw reply [flat|nested] 2+ messages in thread
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2019-03-12 13:28 [Committed] S/390: arch13: Add instruction descriptions Andreas Krebbel
2019-03-12 13:28 ` [Committed] S/390: arch13: Adjust to recent changes Andreas Krebbel
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