From: Matthew Malcomson <Matthew.Malcomson@arm.com>
To: "binutils@sourceware.org" <binutils@sourceware.org>
Cc: nd <nd@arm.com>, Matthew Malcomson <Matthew.Malcomson@arm.com>
Subject: [PATCH 01/16] [binutils][aarch64] SVE2 feature extension flags.
Date: Wed, 01 May 2019 14:44:00 -0000 [thread overview]
Message-ID: <1556721866-21052-2-git-send-email-matthew.malcomson@arm.com> (raw)
In-Reply-To: <1556721866-21052-1-git-send-email-matthew.malcomson@arm.com>
Include all feature flag macros.
The "sve2" extension that enables the core sve2 instructions.
This also enables the sve extension, since sve is a requirement of sve2.
Extra optional sve2 features are the bitperm, sm4, aes, and sha3 extensions.
These are all given extra feature flags, "bitperm", "sve2-sm4",
"sve2-aes", and "sve2-sha3" respectively.
The sm4, aes, and sha3 extensions are explicitly marked as sve2
extensions to distinguish them from the corresponding NEON extensions.
Rather than continue extending the current feature flag numbers, I used
some bits that have been skipped.
gas/ChangeLog:
2019-04-02 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c: Add command line architecture feature flags
"sve2", "sve2-sm4", "sve2-aes", "sve2-sha3", "bitperm".
* doc/c-aarch64.texi: Document new architecture feature flags.
include/ChangeLog:
2019-04-02 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_SVE2
AARCH64_FEATURE_SVE2_AES, AARCH64_FEATURE_SVE2_BITPERM,
AARCH64_FEATURE_SVE2_SM4, AARCH64_FEATURE_SVE2_SHA3): New
feature macros.
opcodes/ChangeLog:
2019-04-02 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-tbl.h
(aarch64_feature_sve2, aarch64_feature_sve2aes,
aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
aarch64_feature_sve2bitperm): New feature sets.
(SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
for feature set addresses.
(SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
---
gas/config/tc-aarch64.c | 13 +++++++++++++
gas/doc/c-aarch64.texi | 10 ++++++++++
include/opcode/aarch64.h | 6 ++++++
opcodes/aarch64-tbl.h | 36 ++++++++++++++++++++++++++++++++++++
4 files changed, 65 insertions(+)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index d04e9a1..f8d5b56 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -8866,6 +8866,19 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
AARCH64_ARCH_NONE},
{"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG, 0),
AARCH64_ARCH_NONE},
+ {"sve2", AARCH64_FEATURE (AARCH64_FEATURE_SVE2, 0),
+ AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0)},
+ {"sve2-sm4", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SM4, 0),
+ AARCH64_FEATURE (AARCH64_FEATURE_SVE2
+ | AARCH64_FEATURE_SM4, 0)},
+ {"sve2-aes", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_AES, 0),
+ AARCH64_FEATURE (AARCH64_FEATURE_SVE2
+ | AARCH64_FEATURE_AES, 0)},
+ {"sve2-sha3", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3, 0),
+ AARCH64_FEATURE (AARCH64_FEATURE_SVE2
+ | AARCH64_FEATURE_SHA3, 0)},
+ {"bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM, 0),
+ AARCH64_FEATURE (AARCH64_FEATURE_SVE2, 0)},
{NULL, AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
};
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 445fb2f..0f80852 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -194,6 +194,16 @@ automatically cause those extensions to be disabled.
@tab Enable Speculative Store Bypassing Safe state read and write.
@item @code{memtag} @tab ARMv8.5-A @tab No
@tab Enable ARMv8.5-A Memory Tagging Extensions.
+@item @code{sve2} @tab ARMv8-A @tab No
+ @tab Enable the SVE2 Extension.
+@item @code{bitperm} @tab ARMv8-A @tab No
+ @tab Enable SVE2 BITPERM Extension.
+@item @code{sve2-sm4} @tab ARMv8-A @tab No
+ @tab Enable SVE2 SM4 Extension.
+@item @code{sve2-aes} @tab ARMv8-A @tab No
+ @tab Enable SVE2 AES Extension.
+@item @code{sve2-sha3} @tab ARMv8-A @tab No
+ @tab Enable SVE2 SHA3 Extension.
@end multitable
@node AArch64 Syntax
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 0c0234a..ecd57cb 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -87,6 +87,12 @@ typedef uint32_t aarch64_insn;
/* Memory Tagging Extension. */
#define AARCH64_FEATURE_MEMTAG 0x1000000000000ULL
+/* SVE2 instructions. */
+#define AARCH64_FEATURE_SVE2 0x000000010
+#define AARCH64_FEATURE_SVE2_AES 0x000000080
+#define AARCH64_FEATURE_SVE2_BITPERM 0x000000100
+#define AARCH64_FEATURE_SVE2_SM4 0x000000200
+#define AARCH64_FEATURE_SVE2_SHA3 0x000000400
/* Architectures are the sum of the base and extensions. */
#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index e0c3903..07b6d62 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2197,6 +2197,16 @@ static const aarch64_feature_set aarch64_feature_bti =
AARCH64_FEATURE (AARCH64_FEATURE_BTI, 0);
static const aarch64_feature_set aarch64_feature_memtag =
AARCH64_FEATURE (AARCH64_FEATURE_V8_5 | AARCH64_FEATURE_MEMTAG, 0);
+static const aarch64_feature_set aarch64_feature_sve2 =
+ AARCH64_FEATURE (AARCH64_FEATURE_SVE2, 0);
+static const aarch64_feature_set aarch64_feature_sve2aes =
+ AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_AES, 0);
+static const aarch64_feature_set aarch64_feature_sve2sha3 =
+ AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_SHA3, 0);
+static const aarch64_feature_set aarch64_feature_sve2sm4 =
+ AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_SM4, 0);
+static const aarch64_feature_set aarch64_feature_sve2bitperm =
+ AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_BITPERM, 0);
#define CORE &aarch64_feature_v8
@@ -2232,6 +2242,11 @@ static const aarch64_feature_set aarch64_feature_memtag =
#define PREDRES &aarch64_feature_predres
#define BTI &aarch64_feature_bti
#define MEMTAG &aarch64_feature_memtag
+#define SVE2 &aarch64_feature_sve2
+#define SVE2_AES &aarch64_feature_sve2aes
+#define SVE2_SHA3 &aarch64_feature_sve2sha3
+#define SVE2_SM4 &aarch64_feature_sve2sm4
+#define SVE2_BITPERM &aarch64_feature_sve2bitperm
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@@ -2299,6 +2314,27 @@ static const aarch64_feature_set aarch64_feature_memtag =
{ NAME, OPCODE, MASK, CLASS, 0, BTI, OPS, QUALS, FLAGS, 0, 0, NULL }
#define MEMTAG_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, MEMTAG, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
+ { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
+ FLAGS | F_STRICT, 0, TIED, NULL }
+#define SVE2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
+ { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
+ FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
+#define SVE2AES_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
+ { NAME, OPCODE, MASK, CLASS, OP, SVE2_AES, OPS, QUALS, \
+ FLAGS | F_STRICT, 0, TIED, NULL }
+#define SVE2SHA3_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
+ { NAME, OPCODE, MASK, CLASS, OP, SVE2_SHA3, OPS, QUALS, \
+ FLAGS | F_STRICT, 0, TIED, NULL }
+#define SVE2SM4_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
+ { NAME, OPCODE, MASK, CLASS, OP, SVE2_SM4, OPS, QUALS, \
+ FLAGS | F_STRICT, 0, TIED, NULL }
+#define SVE2SM4_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
+ { NAME, OPCODE, MASK, CLASS, OP, SVE2_SM4, OPS, QUALS, \
+ FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
+#define SVE2BITPERM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
+ { NAME, OPCODE, MASK, CLASS, OP, SVE2_BITPERM, OPS, QUALS, \
+ FLAGS | F_STRICT, 0, TIED, NULL }
struct aarch64_opcode aarch64_opcode_table[] =
{
--
2.7.4
next prev parent reply other threads:[~2019-05-01 14:44 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-01 14:44 [Patch 00/16] [gas][aarch64] SVE2 binutils instructions for aarch64 Matthew Malcomson
2019-05-01 14:44 ` [PATCH 03/16] [binutils][aarch64] Introduce SVE_IMM_ROT3 operand Matthew Malcomson
2019-05-01 14:44 ` [PATCH 05/16] [binutils][aarch64] New SVE_Zm3_11_INDEX operand Matthew Malcomson
2019-05-01 14:44 ` Matthew Malcomson [this message]
2019-05-01 14:44 ` [PATCH 08/16] [binutils][aarch64] New sve_size_bh iclass Matthew Malcomson
2019-05-01 14:44 ` [PATCH 04/16] [binutils][aarch64] New iclass sve_size_hsd2 Matthew Malcomson
2019-05-01 14:44 ` [PATCH 09/16] [binutils][aarch64] New sve_size_013 iclass Matthew Malcomson
2019-05-01 14:44 ` [PATCH 07/16] [binutils][aarch64] New sve_size_sd2 iclass Matthew Malcomson
2019-05-01 14:44 ` [PATCH 02/16] [binutils][aarch64] Allow movprfx for SVE2 instructions Matthew Malcomson
2019-05-01 14:45 ` [PATCH 12/16] [binutils][aarch64] New SVE_Zm4_11_INDEX operand Matthew Malcomson
2019-05-01 14:45 ` [PATCH 14/16] [binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand Matthew Malcomson
2019-05-01 14:45 ` [PATCH 13/16] [binutils][aarch64] New sve_size_tsz_bhs iclass Matthew Malcomson
2019-05-01 14:45 ` [PATCH 06/16] [binutils][aarch64] New SVE_ADDR_ZX operand Matthew Malcomson
2019-05-01 14:45 ` [PATCH 11/16] [binutils][aarch64] New sve_shift_tsz_bhsd iclass Matthew Malcomson
2019-05-01 14:45 ` [PATCH 10/16] [binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand Matthew Malcomson
2019-05-01 14:55 ` [Patch 15/16] [binutils][aarch64] Add SVE2 instructions Matthew Malcomson
2019-05-01 15:02 ` [Patch 16/16] [binutils][aarch64] Add SVE2 tests Matthew Malcomson
2019-05-02 15:25 ` [Patch 00/16] [gas][aarch64] SVE2 binutils instructions for aarch64 Joseph Myers
2019-05-02 15:34 ` Matthew Malcomson
2019-05-03 11:21 ` Nick Clifton
2019-05-03 14:56 ` Matthew Malcomson
2019-05-08 10:08 ` Nick Clifton
2019-05-09 13:30 ` Christophe Lyon
2019-05-09 14:04 ` Matthew Malcomson
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