From: Matthew Malcomson <Matthew.Malcomson@arm.com>
To: "binutils@sourceware.org" <binutils@sourceware.org>
Cc: nd <nd@arm.com>, Matthew Malcomson <Matthew.Malcomson@arm.com>
Subject: [PATCH 03/16] [binutils][aarch64] Introduce SVE_IMM_ROT3 operand.
Date: Wed, 01 May 2019 14:44:00 -0000 [thread overview]
Message-ID: <1556721866-21052-4-git-send-email-matthew.malcomson@arm.com> (raw)
In-Reply-To: <1556721866-21052-1-git-send-email-matthew.malcomson@arm.com>
New operand AARCH64_OPND_SVE_IMM_ROT3 handles a single bit rotate
operand encoded at bit position 10.
gas/ChangeLog:
2019-04-04 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_IMM_ROT3 operand.
include/ChangeLog:
2019-04-04 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_IMM_ROT3 operand.
opcodes/ChangeLog:
2019-04-04 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_IMM_ROT3.
(aarch64_print_operand): Add printing for SVE_IMM_ROT3.
(fields): Handle SVE_rot3 field.
* aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
---
gas/config/tc-aarch64.c | 1 +
include/opcode/aarch64.h | 1 +
opcodes/aarch64-asm-2.c | 37 +++++++++++++++++++------------------
opcodes/aarch64-dis-2.c | 37 +++++++++++++++++++------------------
opcodes/aarch64-opc-2.c | 1 +
opcodes/aarch64-opc.c | 3 +++
opcodes/aarch64-opc.h | 1 +
opcodes/aarch64-tbl.h | 2 ++
8 files changed, 47 insertions(+), 36 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index f8d5b56..407ffee 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -5779,6 +5779,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_IMM_ROT3:
case AARCH64_OPND_SVE_IMM_ROT1:
case AARCH64_OPND_SVE_IMM_ROT2:
+ case AARCH64_OPND_SVE_IMM_ROT3:
po_imm_nc_or_fail ();
info->imm.value = val;
break;
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index ecd57cb..8f629b9 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -369,6 +369,7 @@ enum aarch64_opnd
AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */
AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */
+ AARCH64_OPND_SVE_IMM_ROT3, /* SVE cadd 1-bit rotate (90 or 270). */
AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 2587093..b89d677 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -627,7 +627,6 @@ aarch64_insert_operand (const aarch64_operand *self,
case 27:
case 28:
case 29:
- case 159:
case 160:
case 161:
case 162:
@@ -637,7 +636,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 166:
case 167:
case 168:
- case 181:
+ case 169:
case 182:
case 183:
case 184:
@@ -646,8 +645,9 @@ aarch64_insert_operand (const aarch64_operand *self,
case 187:
case 188:
case 189:
- case 193:
- case 196:
+ case 190:
+ case 194:
+ case 197:
return aarch64_ins_regno (self, info, code, inst, errors);
case 13:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -659,7 +659,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 31:
case 32:
case 33:
- case 198:
+ case 199:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 34:
return aarch64_ins_reglist (self, info, code, inst, errors);
@@ -693,9 +693,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 79:
case 80:
case 81:
- case 156:
- case 158:
- case 173:
+ case 157:
+ case 159:
case 174:
case 175:
case 176:
@@ -703,6 +702,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 178:
case 179:
case 180:
+ case 181:
return aarch64_ins_imm (self, info, code, inst, errors);
case 42:
case 43:
@@ -715,7 +715,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 147:
return aarch64_ins_fpimm (self, info, code, inst, errors);
case 67:
- case 154:
+ case 155:
return aarch64_ins_limm (self, info, code, inst, errors);
case 68:
return aarch64_ins_aimm (self, info, code, inst, errors);
@@ -729,6 +729,7 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
case 74:
case 151:
+ case 153:
return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
case 75:
case 76:
@@ -830,26 +831,26 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
case 150:
return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
- case 153:
+ case 154:
return aarch64_ins_inv_limm (self, info, code, inst, errors);
- case 155:
+ case 156:
return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
- case 157:
+ case 158:
return aarch64_ins_sve_scale (self, info, code, inst, errors);
- case 169:
case 170:
- return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 171:
+ return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 172:
+ case 173:
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
- case 190:
case 191:
case 192:
+ case 193:
return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
- case 194:
- return aarch64_ins_sve_index (self, info, code, inst, errors);
case 195:
- case 197:
+ return aarch64_ins_sve_index (self, info, code, inst, errors);
+ case 196:
+ case 198:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index a5b7f45..f7dddef 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -20022,7 +20022,6 @@ aarch64_extract_operand (const aarch64_operand *self,
case 27:
case 28:
case 29:
- case 159:
case 160:
case 161:
case 162:
@@ -20032,7 +20031,7 @@ aarch64_extract_operand (const aarch64_operand *self,
case 166:
case 167:
case 168:
- case 181:
+ case 169:
case 182:
case 183:
case 184:
@@ -20041,8 +20040,9 @@ aarch64_extract_operand (const aarch64_operand *self,
case 187:
case 188:
case 189:
- case 193:
- case 196:
+ case 190:
+ case 194:
+ case 197:
return aarch64_ext_regno (self, info, code, inst, errors);
case 8:
return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
@@ -20058,7 +20058,7 @@ aarch64_extract_operand (const aarch64_operand *self,
case 31:
case 32:
case 33:
- case 198:
+ case 199:
return aarch64_ext_reglane (self, info, code, inst, errors);
case 34:
return aarch64_ext_reglist (self, info, code, inst, errors);
@@ -20093,9 +20093,8 @@ aarch64_extract_operand (const aarch64_operand *self,
case 79:
case 80:
case 81:
- case 156:
- case 158:
- case 173:
+ case 157:
+ case 159:
case 174:
case 175:
case 176:
@@ -20103,6 +20102,7 @@ aarch64_extract_operand (const aarch64_operand *self,
case 178:
case 179:
case 180:
+ case 181:
return aarch64_ext_imm (self, info, code, inst, errors);
case 42:
case 43:
@@ -20117,7 +20117,7 @@ aarch64_extract_operand (const aarch64_operand *self,
case 147:
return aarch64_ext_fpimm (self, info, code, inst, errors);
case 67:
- case 154:
+ case 155:
return aarch64_ext_limm (self, info, code, inst, errors);
case 68:
return aarch64_ext_aimm (self, info, code, inst, errors);
@@ -20131,6 +20131,7 @@ aarch64_extract_operand (const aarch64_operand *self,
return aarch64_ext_imm_rotate2 (self, info, code, inst, errors);
case 74:
case 151:
+ case 153:
return aarch64_ext_imm_rotate1 (self, info, code, inst, errors);
case 75:
case 76:
@@ -20232,26 +20233,26 @@ aarch64_extract_operand (const aarch64_operand *self,
return aarch64_ext_sve_float_half_two (self, info, code, inst, errors);
case 150:
return aarch64_ext_sve_float_zero_one (self, info, code, inst, errors);
- case 153:
+ case 154:
return aarch64_ext_inv_limm (self, info, code, inst, errors);
- case 155:
+ case 156:
return aarch64_ext_sve_limm_mov (self, info, code, inst, errors);
- case 157:
+ case 158:
return aarch64_ext_sve_scale (self, info, code, inst, errors);
- case 169:
case 170:
- return aarch64_ext_sve_shlimm (self, info, code, inst, errors);
case 171:
+ return aarch64_ext_sve_shlimm (self, info, code, inst, errors);
case 172:
+ case 173:
return aarch64_ext_sve_shrimm (self, info, code, inst, errors);
- case 190:
case 191:
case 192:
+ case 193:
return aarch64_ext_sve_quad_index (self, info, code, inst, errors);
- case 194:
- return aarch64_ext_sve_index (self, info, code, inst, errors);
case 195:
- case 197:
+ return aarch64_ext_sve_index (self, info, code, inst, errors);
+ case 196:
+ case 198:
return aarch64_ext_sve_reglist (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 15f2b9f..90e9654 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -177,6 +177,7 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_ZERO_ONE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i1}, "either 0.0 or 1.0"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_rot1}, "a 1-bit rotation specifier for complex arithmetic operations"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_rot2}, "a 2-bit rotation specifier for complex arithmetic operations"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_rot3}, "a 1-bit rotation specifier for complex arithmetic operations"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_INV_LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms}, "an inverted 13-bit logical immediate"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms}, "a 13-bit logical immediate"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_LIMM_MOV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms}, "a 13-bit logical move immediate"},
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 33e4af6..5a381d6 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -309,6 +309,7 @@ const aarch64_field fields[] =
{ 0, 4 }, /* SVE_prfop: prefetch operation for SVE PRF[BHWD]. */
{ 16, 1 }, /* SVE_rot1: 1-bit rotation amount. */
{ 10, 2 }, /* SVE_rot2: 2-bit rotation amount. */
+ { 10, 1 }, /* SVE_rot3: 1-bit rotation amount at bit 10. */
{ 22, 1 }, /* SVE_sz: 1-bit element size select. */
{ 16, 4 }, /* SVE_tsz: triangular size select. */
{ 22, 2 }, /* SVE_tszh: triangular size select high, bits [23,22]. */
@@ -2230,6 +2231,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
case AARCH64_OPND_IMM_ROT3:
case AARCH64_OPND_SVE_IMM_ROT1:
+ case AARCH64_OPND_SVE_IMM_ROT3:
if (opnd->imm.value != 90 && opnd->imm.value != 270)
{
set_other_error (mismatch_detail, idx,
@@ -3343,6 +3345,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_IMM_ROT3:
case AARCH64_OPND_SVE_IMM_ROT1:
case AARCH64_OPND_SVE_IMM_ROT2:
+ case AARCH64_OPND_SVE_IMM_ROT3:
snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
break;
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index f6c506d..b1060d4 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -136,6 +136,7 @@ enum aarch64_field_kind
FLD_SVE_prfop,
FLD_SVE_rot1,
FLD_SVE_rot2,
+ FLD_SVE_rot3,
FLD_SVE_sz,
FLD_SVE_tsz,
FLD_SVE_tszh,
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 07b6d62..980d8fa 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -4858,6 +4858,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
"a 1-bit rotation specifier for complex arithmetic operations") \
Y(IMMEDIATE, imm_rotate2, "SVE_IMM_ROT2", 0, F(FLD_SVE_rot2), \
"a 2-bit rotation specifier for complex arithmetic operations") \
+ Y(IMMEDIATE, imm_rotate1, "SVE_IMM_ROT3", 0, F(FLD_SVE_rot3), \
+ "a 1-bit rotation specifier for complex arithmetic operations") \
Y(IMMEDIATE, inv_limm, "SVE_INV_LIMM", 0, \
F(FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms), \
"an inverted 13-bit logical immediate") \
--
2.7.4
next prev parent reply other threads:[~2019-05-01 14:44 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-01 14:44 [Patch 00/16] [gas][aarch64] SVE2 binutils instructions for aarch64 Matthew Malcomson
2019-05-01 14:44 ` Matthew Malcomson [this message]
2019-05-01 14:44 ` [PATCH 05/16] [binutils][aarch64] New SVE_Zm3_11_INDEX operand Matthew Malcomson
2019-05-01 14:44 ` [PATCH 01/16] [binutils][aarch64] SVE2 feature extension flags Matthew Malcomson
2019-05-01 14:44 ` [PATCH 08/16] [binutils][aarch64] New sve_size_bh iclass Matthew Malcomson
2019-05-01 14:44 ` [PATCH 04/16] [binutils][aarch64] New iclass sve_size_hsd2 Matthew Malcomson
2019-05-01 14:44 ` [PATCH 07/16] [binutils][aarch64] New sve_size_sd2 iclass Matthew Malcomson
2019-05-01 14:44 ` [PATCH 09/16] [binutils][aarch64] New sve_size_013 iclass Matthew Malcomson
2019-05-01 14:44 ` [PATCH 02/16] [binutils][aarch64] Allow movprfx for SVE2 instructions Matthew Malcomson
2019-05-01 14:45 ` [PATCH 12/16] [binutils][aarch64] New SVE_Zm4_11_INDEX operand Matthew Malcomson
2019-05-01 14:45 ` [PATCH 14/16] [binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand Matthew Malcomson
2019-05-01 14:45 ` [PATCH 13/16] [binutils][aarch64] New sve_size_tsz_bhs iclass Matthew Malcomson
2019-05-01 14:45 ` [PATCH 06/16] [binutils][aarch64] New SVE_ADDR_ZX operand Matthew Malcomson
2019-05-01 14:45 ` [PATCH 11/16] [binutils][aarch64] New sve_shift_tsz_bhsd iclass Matthew Malcomson
2019-05-01 14:45 ` [PATCH 10/16] [binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand Matthew Malcomson
2019-05-01 14:55 ` [Patch 15/16] [binutils][aarch64] Add SVE2 instructions Matthew Malcomson
2019-05-01 15:02 ` [Patch 16/16] [binutils][aarch64] Add SVE2 tests Matthew Malcomson
2019-05-02 15:25 ` [Patch 00/16] [gas][aarch64] SVE2 binutils instructions for aarch64 Joseph Myers
2019-05-02 15:34 ` Matthew Malcomson
2019-05-03 11:21 ` Nick Clifton
2019-05-03 14:56 ` Matthew Malcomson
2019-05-08 10:08 ` Nick Clifton
2019-05-09 13:30 ` Christophe Lyon
2019-05-09 14:04 ` Matthew Malcomson
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