From: Matthew Malcomson <Matthew.Malcomson@arm.com>
To: "binutils@sourceware.org" <binutils@sourceware.org>
Cc: nd <nd@arm.com>, Matthew Malcomson <Matthew.Malcomson@arm.com>
Subject: [PATCH 05/16] [binutils][aarch64] New SVE_Zm3_11_INDEX operand.
Date: Wed, 01 May 2019 14:44:00 -0000 [thread overview]
Message-ID: <1556721866-21052-6-git-send-email-matthew.malcomson@arm.com> (raw)
In-Reply-To: <1556721866-21052-1-git-send-email-matthew.malcomson@arm.com>
Introduce new operand SVE_Zm3_11_INDEX that indicates a register between
z0-z7 stored in bits 18-16 and an index stored in bits 20-19:11.
gas/ChangeLog:
2019-04-04 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_Zm3_11_INDEX operand.
include/ChangeLog:
2019-04-04 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm3_11_INDEX operand.
opcodes/ChangeLog:
2019-04-04 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_Zm3_11_INDEX.
(aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
(fields): Handle SVE_i3l and SVE_i3h2 fields.
* aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
fields.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
---
gas/config/tc-aarch64.c | 1 +
include/opcode/aarch64.h | 1 +
opcodes/aarch64-asm-2.c | 13 +++++++------
opcodes/aarch64-dis-2.c | 13 +++++++------
opcodes/aarch64-opc-2.c | 1 +
opcodes/aarch64-opc.c | 4 ++++
opcodes/aarch64-opc.h | 2 ++
opcodes/aarch64-tbl.h | 3 +++
8 files changed, 26 insertions(+), 12 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 407ffee..612febd 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -5635,6 +5635,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SVE_Zm3_INDEX:
case AARCH64_OPND_SVE_Zm3_22_INDEX:
+ case AARCH64_OPND_SVE_Zm3_11_INDEX:
case AARCH64_OPND_SVE_Zm4_INDEX:
case AARCH64_OPND_SVE_Zn_INDEX:
reg_type = REG_TYPE_ZN;
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 10541d8..1c3f126 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -409,6 +409,7 @@ enum aarch64_opnd
AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */
AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
+ AARCH64_OPND_SVE_Zm3_11_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 11. */
AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */
AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index b89d677..0b67ceb 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -646,8 +646,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 188:
case 189:
case 190:
- case 194:
- case 197:
+ case 195:
+ case 198:
return aarch64_ins_regno (self, info, code, inst, errors);
case 13:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -659,7 +659,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 31:
case 32:
case 33:
- case 199:
+ case 200:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 34:
return aarch64_ins_reglist (self, info, code, inst, errors);
@@ -846,11 +846,12 @@ aarch64_insert_operand (const aarch64_operand *self,
case 191:
case 192:
case 193:
+ case 194:
return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
- case 195:
- return aarch64_ins_sve_index (self, info, code, inst, errors);
case 196:
- case 198:
+ return aarch64_ins_sve_index (self, info, code, inst, errors);
+ case 197:
+ case 199:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index f7dddef..630ef20 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -20041,8 +20041,8 @@ aarch64_extract_operand (const aarch64_operand *self,
case 188:
case 189:
case 190:
- case 194:
- case 197:
+ case 195:
+ case 198:
return aarch64_ext_regno (self, info, code, inst, errors);
case 8:
return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
@@ -20058,7 +20058,7 @@ aarch64_extract_operand (const aarch64_operand *self,
case 31:
case 32:
case 33:
- case 199:
+ case 200:
return aarch64_ext_reglane (self, info, code, inst, errors);
case 34:
return aarch64_ext_reglist (self, info, code, inst, errors);
@@ -20248,11 +20248,12 @@ aarch64_extract_operand (const aarch64_operand *self,
case 191:
case 192:
case 193:
+ case 194:
return aarch64_ext_sve_quad_index (self, info, code, inst, errors);
- case 195:
- return aarch64_ext_sve_index (self, info, code, inst, errors);
case 196:
- case 198:
+ return aarch64_ext_sve_index (self, info, code, inst, errors);
+ case 197:
+ case 199:
return aarch64_ext_sve_reglist (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 90e9654..db2fc37 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -217,6 +217,7 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_22_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h, FLD_SVE_Zm_16}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_11_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h2, FLD_SVE_i3l, FLD_SVE_imm3}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an indexed SVE vector register"},
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index c133c1d..695146f 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -294,6 +294,8 @@ const aarch64_field fields[] =
{ 0, 5 }, /* SVE_Zt: SVE vector register, bits [4,0]. */
{ 5, 1 }, /* SVE_i1: single-bit immediate. */
{ 22, 1 }, /* SVE_i3h: high bit of 3-bit immediate. */
+ { 11, 1 }, /* SVE_i3l: low bit of 3-bit immediate. */
+ { 19, 2 }, /* SVE_i3h2: two high bits of 3bit immediate, bits [20,19]. */
{ 16, 3 }, /* SVE_imm3: 3-bit immediate field. */
{ 16, 4 }, /* SVE_imm4: 4-bit immediate field. */
{ 5, 5 }, /* SVE_imm5: 5-bit immediate field. */
@@ -1515,6 +1517,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
{
case AARCH64_OPND_SVE_Zm3_INDEX:
case AARCH64_OPND_SVE_Zm3_22_INDEX:
+ case AARCH64_OPND_SVE_Zm3_11_INDEX:
case AARCH64_OPND_SVE_Zm4_INDEX:
size = get_operand_fields_width (get_operand_from_code (type));
shift = get_operand_specific_data (&aarch64_operands[type]);
@@ -3301,6 +3304,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_SVE_Zm3_INDEX:
case AARCH64_OPND_SVE_Zm3_22_INDEX:
+ case AARCH64_OPND_SVE_Zm3_11_INDEX:
case AARCH64_OPND_SVE_Zm4_INDEX:
case AARCH64_OPND_SVE_Zn_INDEX:
snprintf (buf, size, "z%d.%s[%" PRIi64 "]", opnd->reglane.regno,
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index 942fa58..8803bca 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -121,6 +121,8 @@ enum aarch64_field_kind
FLD_SVE_Zt,
FLD_SVE_i1,
FLD_SVE_i3h,
+ FLD_SVE_i3l,
+ FLD_SVE_i3h2,
FLD_SVE_imm3,
FLD_SVE_imm4,
FLD_SVE_imm5,
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 980d8fa..826b4df 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -4939,6 +4939,9 @@ struct aarch64_opcode aarch64_opcode_table[] =
Y(SVE_REG, sve_quad_index, "SVE_Zm3_22_INDEX", \
3 << OPD_F_OD_LSB, F(FLD_SVE_i3h, FLD_SVE_Zm_16), \
"an indexed SVE vector register") \
+ Y(SVE_REG, sve_quad_index, "SVE_Zm3_11_INDEX", \
+ 3 << OPD_F_OD_LSB, F(FLD_SVE_i3h2, FLD_SVE_i3l, FLD_SVE_imm3), \
+ "an indexed SVE vector register") \
Y(SVE_REG, sve_quad_index, "SVE_Zm4_INDEX", \
4 << OPD_F_OD_LSB, F(FLD_SVE_Zm_16), \
"an indexed SVE vector register") \
--
2.7.4
next prev parent reply other threads:[~2019-05-01 14:44 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-01 14:44 [Patch 00/16] [gas][aarch64] SVE2 binutils instructions for aarch64 Matthew Malcomson
2019-05-01 14:44 ` [PATCH 09/16] [binutils][aarch64] New sve_size_013 iclass Matthew Malcomson
2019-05-01 14:44 ` [PATCH 07/16] [binutils][aarch64] New sve_size_sd2 iclass Matthew Malcomson
2019-05-01 14:44 ` [PATCH 04/16] [binutils][aarch64] New iclass sve_size_hsd2 Matthew Malcomson
2019-05-01 14:44 ` [PATCH 02/16] [binutils][aarch64] Allow movprfx for SVE2 instructions Matthew Malcomson
2019-05-01 14:44 ` [PATCH 08/16] [binutils][aarch64] New sve_size_bh iclass Matthew Malcomson
2019-05-01 14:44 ` [PATCH 01/16] [binutils][aarch64] SVE2 feature extension flags Matthew Malcomson
2019-05-01 14:44 ` [PATCH 03/16] [binutils][aarch64] Introduce SVE_IMM_ROT3 operand Matthew Malcomson
2019-05-01 14:44 ` Matthew Malcomson [this message]
2019-05-01 14:45 ` [PATCH 11/16] [binutils][aarch64] New sve_shift_tsz_bhsd iclass Matthew Malcomson
2019-05-01 14:45 ` [PATCH 10/16] [binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand Matthew Malcomson
2019-05-01 14:45 ` [PATCH 06/16] [binutils][aarch64] New SVE_ADDR_ZX operand Matthew Malcomson
2019-05-01 14:45 ` [PATCH 12/16] [binutils][aarch64] New SVE_Zm4_11_INDEX operand Matthew Malcomson
2019-05-01 14:45 ` [PATCH 14/16] [binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand Matthew Malcomson
2019-05-01 14:45 ` [PATCH 13/16] [binutils][aarch64] New sve_size_tsz_bhs iclass Matthew Malcomson
2019-05-01 14:55 ` [Patch 15/16] [binutils][aarch64] Add SVE2 instructions Matthew Malcomson
2019-05-01 15:02 ` [Patch 16/16] [binutils][aarch64] Add SVE2 tests Matthew Malcomson
2019-05-02 15:25 ` [Patch 00/16] [gas][aarch64] SVE2 binutils instructions for aarch64 Joseph Myers
2019-05-02 15:34 ` Matthew Malcomson
2019-05-03 11:21 ` Nick Clifton
2019-05-03 14:56 ` Matthew Malcomson
2019-05-08 10:08 ` Nick Clifton
2019-05-09 13:30 ` Christophe Lyon
2019-05-09 14:04 ` Matthew Malcomson
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